Sequential Circuits

OU TLI N E OF CH APTER
5

Sequenti Latche Flip- Analysis State

al s flop ofClocked Reduction
and
Circuits Assignment Sequential
Circuits

Design
Procedure
 4

SEQU EN TI AL
CI RCU I TS
• Every digital system is likely to have combinational
circuits.
• Most systems encountered in practice also include
storage elements, which require that the system be
described in
terms
Inputs of sequential logic.
Combinational Outputs
Circuit
Memory

Elements
 5

SEQU EN TI AL
CI RCU I TS
• The storage elements are devices capable of storing
binary
information.
• The binary information stored in these elements at
any given time defines the state of the sequential
circuit at that time.
• The sequential circuit receives binary information
from external
inputs.
• These inputs, together with the present state of the
 6

SEQU EN TI AL
CI RCU I TS
• They also determine the condition for changing the
state in the
storage elements.
• A sequential circuit is specified by a time sequence of
inputs, output, and internal states.
 7

SEQU EN TI AL
CI RCU I TS
• There are two main types of sequential circuits.

• Their classification depends on the timing of their

signals.

Synchronou Asynchrono
s us

Sequenti
al
Circuit
 8

SEQU EN TI AL
CI RCU I TS
• Asynchronous Sequential
Circuit
Inputs Outputs
Combinationa
l Circuit
Memory

Elements

– The behaviour of the circuit depends upon the input

signals at any instant of time and the order in which the
inputs change.
 9

SEQU EN TI AL
CI RCU I TS
• Asynchronous Sequential Circuit
– In gate – type asynchronous systems, the storage
elements consist of logic gates whose propagation delay
provides the required storage.
– Thus, an asynchronous sequential circuit may be
regarded as a combinational circuit with feedback.
– Because of the feedback among logic gates, an
asynchronous sequential circuit may become
unstable at times.
 10

SEQU EN TI AL
CI RCU I TS
• Synchronous Sequential
Circuit
Inputs Outputs
Combinationa
l Circuit
Flip-flops
Clock

– The behaviour can be defined from the knowledge of its

signals at discrete instants of time.
 11

SEQU EN TI AL
CI RCU I TS
• Synchronous Sequential Circuit
– Employs signals that affect the storage elements only at
discrete instants of time.
– Synchronisation is achieved by a timing device called
a clock generator.
• Provides a periodic train of clock pulses.

• Clock pulses are distributed throughout the system in such a

way that storage elements are affected only with the arrival
of each pulse.
 12

SEQU EN TI AL
CI RCU I TS
• Synchronous Sequential Circuit
• In practice, the clock pulses are applied with other signals
that specify the required change in the storage elements.

– Circuits that use clock pulses in the inputs of storage

elements are
called clocked sequential circuits.
– The storage elements used in clocked sequential circuits
are called
flip – flops.
– A flip – flop is a binary storage device capable of storing
one bit of information.
 14

LATCH E
S
• Latches are the basic circuits from which all flip – flops
are
constructed.
• Although latches are useful for storing binary
information and for the design of asynchronous
sequential circuits.
• They are not practical for use in synchronous
sequential circuits.
 15

LATCH E
S
• SR
Latch

Reset 1 1
0 Q
(R) 0

Set Q
1 0
(S) 0
 16

LATCH E
S
• SR
Latch SR Q
R 0 0 Q0 No change
Q
0 1 0 Reset
1 0 1 Set
Q 1 1 Q=Q’=0 Invalid
S

S SR Q
Q
0 0 Q=Q’=1 Invalid
0 1 1 Set
Q 1 0 0
R Reset
1 1 Q0 No
chang
e
 17

LATCH E
S
• SR Latch with Control
Input S
R R S
Q Q

C C
R Q
S Q R
S
C S R Q
0 X X HOLD No
1 0 0 HOLD change
1 0 1 Q=0 No
1 1 0 Q=1 change

1 1 1 Q= Reset
Q’ Set
Invalid
 18

LATCH E
S
• D Latch (D = Data)
– One way to eliminate the undesirable condition of the
indeterminate state in the SR latch is to ensure that inputs
S and R are never equal to 1 at the same time.
– D latch has two inputs
• D (data) - directly goes to the S input and its complement is
applied to the R input.
• C (control)
 19

LATCH E
S
• D Latch (D =
Data) S
D
Q
C
R Q

C D Q
0 X HOLD No
1 0 Q=0 change
1 1 Q=1 Reset
Set
 20

LATCH E
S
• D Latch (D =
Data) S
D
Q
C
R Q

C D Q
0 X HOLD No
1 0 Q=0 change
1 1 Q=1 Reset
Set
 21

LATCH E
S
• D Latch (D = Data)
– The D latch has an ability to hold data in its internal
storage.
– It is suited for use as a temporary storage for binary
information.
– This circuit is often called transparent latch.
• The output follow changes in the data input as long as the
control input is enabled.
 23

FLI P – FLOPS
• Flip – flops are constructed in such a way to make D latches
operate properly when they are part of a sequential
circuit that employs a common clock.
• The problem with the latch is that
– It responds to a change in the level of a clock pulse.
• Positive level response in the control input allows changes, in
the output when the D input changes while the control pulse
stays at logic 1.

• The key to the proper operation of a flip – flop is

– to trigger it only during a signal transition.
 24

FLI P – FLOPS
• Controlled latches are level –
triggered

• Flip-Flops are edge –

triggered
CL Positive Edge
K

CL Negative Edge
K
 25

FLI P – FLOPS
• There are two ways that a latch can be modified to form
a flip –
flop.
1. Employ two latches in a special configuration that
• isolates the output of the flip – flop from being affected while
its input is changing.

2. Produce a flip – flop that triggers only during a signal

transition.
• From 0 to 1 or from 1 to 0 only.
• Disabled during the rest of the clock pulse duration.
 26

FLI P – FLOPS
• Master – Slave D flip –
flopsD D
D D Latch Q D Latch Q Q
(Master) (Slave)
C C
M aster Slave
CL
K CL
Looks like it is negative K
edge-triggered
D

QMaster
 27

FLI P – FLOPS
• Edge-Triggered D Flip – • Two latches respond to the
Flop
external D (data) and CLK
(clock inputs).
S
Q • Third latch provides the
CL outputs
K for the flip – flop.
Q

D R
 28

FLI P – FLOPS
• Edge-Triggered D Flip – I. When CLK = 0, S = 1 and
Flop R=
1.Output = present state.

S II. If D = 0, when CLK  1

Q 1. R changes to 0
CL 2. Flip – flop goes to the
K
Q RESET state.

3. Q = 0.

D R
 29

FLI P – FLOPS
• Edge-Triggered D Flip – III. If D changes when CLK = 1
Flop then
1. R remains at 0.
2. Flip – flop is locked out

S 3. Unresponsive to further
Q changes in the input.
CL
K IV. When CLK 
0,
Q 1. R  1
2. Placing the output latch in
the quiescent condition.
D R
3. No change in the output.
 30

FLI P – FLOPS
• Edge-Triggered D Flip – V. If D = 1 when CLK = 0
Flop  1,
1. S changes to 0.

2. Circuit goes to SET state

S
Q 3. Q = 1.
CL 4. Any change in D while CLK
K
Q = 1 does not affect the
output.

D R
 31

FLI P – FLOPS
• Edge-Triggered D Flip – • When CLK in the positive-
Flop edge-
triggered flip – flop

S – Makes positive
• The value of D is
Q transition
transferred
CL
to Q.
K
Q – Makes
negative
transition
D R • Does not
affect the
output.
– Steady CLK 1
 32

FLI P – FLOPS
• Edge-Triggered D Flip – Flop
– The timing of the response of a flip – flop to input
data and clock must be taken into consideration when
using edge – triggered flip - flops.
• There is a minimum time, called setup time, for which the D
input must be maintained at a constant value prior to the
occurrence of the clock transition.
• There is a minimum time, called hold time, for which the D
input must not change after the application of the positive
transition of the clock.
 33

FLI P – FLOPS
• Edge-Triggered D Flip –
Flop D Q

Q
Q Positive Edge
CL Dynamic
K input
Q D Q

Q
D
Negative Edge
 34

FLI P – FLOPS
• The most economical and effi cient flip – flop constructed
is the
edge – triggered D flip – flop.
– It requires smallest number of gates.

• Other types of flip – flops can be constructed by using

the D flip – flop and external logic.
– JK flip – flops

– T flip - flops
 35

FLI P – FLOPS
• There are three operations that can be performed
with a flip –
flop:
– Set it to 1

– Reset it to 0

– Complement its output

 36

FLI P – FLOPS
• JK Flip – Flop • When J = 1, sets the flip –
flop
– Performs all three
operations. to 1.

J • When K = 1, resets the

D Q Q
K
CLK Q
flip – flop to 0.
Q

D = JQ’ +
K’Q
 37

FLI P – FLOPS
• JK Flip – Operation 1
Flop
• When J = 1 and K
= 0,
– D = 1.Q’ + 1.Q (Post2
J
b)
D Q Q – D = Q’ + Q
K (Post5a
CLK Q Q – D=1 )
– Next clock edge sets the

D = JQ’ + output to 1.
K’Q
 38

FLI P – FLOPS
• JK Flip – Operation 2
Flop
• When J = 0 and K
= 1,
– D = 0.Q’ + 0.Q (Theo2b
J
)
D Q Q – D=0+0
K
CLK Q Q – D=0

– Next clock edge sets the

D = JQ’ + output to 0.
K’Q
 39

FLI P – FLOPS
• JK Flip – Operation 3
Flop
• When J = 1 and K
= 1,
– D = 1.Q’ + 0.Q (Post2b)
J
D Q Q – D = Q’ + 0 .Q (Theo2
K
CLK Q Q – D = Q’ + 0 b)
– D = Q’ (Post2a)

D = JQ’ + – Next clock edge

K’Q complements the output.
 40

FLI P – FLOPS
• JK Flip – • When J = 0 and K
Flop = 0,
– D = 0.Q’ + (Theo2b
1.Q )

– D=0+ (Post2b)
J
D Q Q
1 .Q
K (Post2a)
CLK Q
– D=0+Q
Q
–– Next
D = Qclock edge the
output is unchanged.
D = JQ’ +
K’Q
 41

FLI P – FLOPS
• JK Flip –
Flop

J
J Q
D Q Q
K
CLK Q Q
K Q

D = JQ’ +
K’Q
 42

FLI P – FLOPS
• T (toggle) Flip – Flop
– Complementing flip –
flop.
T J Q
– Can be obtained from
C
a JK flip – flop.
K
– When inputs J and K
are tied
together. Q
– Useful for designing
binary counters. D = JQ’ + K’Q
 43

FLI P – FLOPS
• T (toggle) Flip – Flop
– When T = 0 (J = K = 0)

– A clock edge does T J Q

not change the C
output.
K
– When T = 1 (J = K
= 1)
Q
– A clock edge
complements
the output. D = JQ’ + K’Q
 44

FLI P – FLOPS
• T (toggle) Flip – Flop
– Can be constructed with
a D flip – flop and an
D Q
XOR gate. T
– When T = 0 then D = Q
C Q
• No change in the
output.

– When T = 1 then D = D = TQ’ + T’Q = T 

Q’ Q

• Output complements
 45

FLI P – FLOPS
• T (toggle) Flip –
Flop

T J Q
T Q
T D Q
C
C Q
K Q C Q

(a) From JK Flip – (b) From D Flip – (c) Graphic

Flop Flop Symbol
 46

FLI P – FLOPS
• Flip – Flop Characteristics
Table

D Q D Q (t+1)
0 0 Reset
1 1 Set
Q

Q(t+1) = D
 47

FLI P – FLOPS
• Flip – Flop Characteristics
Table
J K Q (t+1)
J Q 0 0 Q(t) No change
0 1 0 Reset
1 0 1 Set
K Q
1 1 Q’(t) Toggl
e
Q(t+1) = JQ’ +
K’Q
 48

FLI P – FLOPS
• Flip – Flop Characteristics
Table

T Q T Q (t+1)
0 Q(t) No change
1 Q’(t) Toggle
Q

Q(t+1) = T Q
 49

FLI P – FLOPS
• Some flip – flops have asynchronous inputs that are
used to force the flip – flop to a particular state
independent of the clock.
• The input that sets the flip – flop to 1 is called preset.
• The input that clears the flip – flop to 0 is called clear
or direct
reset.
• When power is on in a digital system, the state of the
flip flop is unknown.
 50

FLI P – FLOPS
• When power is on in a digital system, the state of the
flip flop is
unknown.
• The direct inputs are useful for bringing all flip – flops
in the system to a known starting state prior to the
clocked operation.
 51

FLI P – FLOPS
• Asynchronous
Reset
R’ D CLK Q(t+1)
D Q 0 x x 0

Q
R
Reset
 52

FLI P – FLOPS
• Asynchronous
Reset
R’ D CLK Q(t+1)
D Q 0 x x 0
1 0 ↑ 0
1 1 ↑ 1

Q
R
Reset
 53

FLI P – FLOPS
• Asynchronous Preset and
Clear
Preset
PR’ CLR’ D CLK Q(t+1)
PR
D 1 0 x x 0
Q
Q
CLR
Reset
23 Decem b er , 20
16
 54

FLI P – FLOPS
• Asynchronous Preset and
Clear
Preset
PR’ CLR’ D CLK Q(t+1)
PR
1 0 x x 0
D
Q 0 1 x x 1
Q
CLR
Reset
 55

FLI P – FLOPS
• Asynchronous Preset and
Clear
Preset
PR’ CLR’ D CLK Q(t+1)
PR
1 0 x x 0
D
Q 0 1 x x 1
1 1 0 ↑ 0
CL Q 1 1 1 ↑ 1
R
Reset
2
 57

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
• The behaviour of a clocked sequential circuit is
determined from:
– The inputs

– The outputs

– The state of its flip – flops

• The outputs and the next state are both a function of

– The inputs

– The present state

 58

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
• The analysis of sequential circuit consists of:
– Obtaining a table or a diagram for the time sequence
of
• Inputs

• Outputs

• Internal states

– It is also possible to write Boolean expression that

describe the behaviour of the sequential circuit.
 59

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
State Equations
• The behaviour of a clocked sequential circuit can be
described algebraically by means of state equations
(transition equations).
• A state equation specifies the next state as a function of
– The present state

– Inputs
 60

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
Consider: • Circuit consists
of: – Two D flip – flops A and
x B.
D Q A
– An input x.
Q
– An output y.

D Q B
– It is possible to write a
set of equations for the
CL Q
K circuit.
y
 61

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
Conside • A(t+1) = A(t) . x(t) + B(t) .
r: x(t)
x
D Q A • B(t+1) = A’(t) . x(t)
– (t+1)  next state of the flip
Q A’
flop
– Right side of the equation
D Q B is a Boolean expression
• Specifies the present state
CL Q B’ • Input conditions that
K
make the next state = 1.
y
 62

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
Conside • A(t+1) = A(t) . x(t) +
r: B(t) . x(t)
x
D Q A • B(t+1) = A’(t) . x(t)
– Since all the variables in
Q A’ the Boolean expression
are a function of the
D Q B present state
CL Q B’ – We can omit the
K • A(t+1) =A.x+B.
designation (t)
y x
• B(t+1) = A’ . x
 63

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
Conside • Similarly,
r:
• y(t) = [A(t) + B(t)]
x
D Q A x’(t)
Q A’ • y = (A + B) x’

D Q B

CL Q B’
K

y
 64

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
Conside • A(t+1) = A . x + B .
r: x
x
D Q A • B(t+1) = A’ . x
Q A’ • y = (A + B) x’

D Q B

CL Q B’
K

y
 65

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
State Table
• The time sequence of inputs, outputs and flip – flop can be
enumerated in state table (transition table).
• In general, a sequential circuit with m flip – flops and n
inputs needs 2m+n rows in the state table.
 66

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
State Table • A(t+1) = A . x + B .
Present Input Next State
Output
x
State (t) (t) (t+1)
A B x A B y • B(t+1) = A’ . x
0 0 0 0 0 0
0 0 1 0 1 0
• y = (A + B) x’
x
0 1 0 0 0 1 D Q A

0 1 1 0 1 0 Q A’

1 0 0 0 0 1
D Q B
1 0 1 1 0 0
CLK Q B’
1 1 0 0 0 1
y
1 1 1 1 0 0
 67

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
State Table 2 • A(t+1) = A . x + B .
Present Next State
Output
x
State (t+1)
(t) x=0 x=1 x=0 x=1 • B(t+1) = A’ . x

• y = (A + B) x’
AB AB AB y y x
D Q A
00 00 01 0 0
Q A’
01 00 11 1 0

10 00 10 1 0 D Q B

CLK Q B’
11 00 10 1 0
y
 68

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
State Diagram
• The information available in a state table can be represented
graphically in the form of a state diagram.
• State is represented by a circle

• Transition between states are indicated by directed lines

connecting the
circles.
 69

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
State Diagram 0/ 0 1/ 0
Present Next State
Output
State (t+1) 0/ 1
(t) x=0 x=1 x=0 x=1
00 10
AB AB AB y y
0/ 1
00 00 01 0 0
1/ 0 0/ 1 1/ 0
01 00 11 1 0

10 00 10 1 0

11 00 10 1 0
01 11
AB input/output
1/ 0
 70

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
Analysis with D Flip – Present Next
Flops Inputs
state state

x A x y A
D Q A
y 0 0 0 0
CL Q 0 0 1 1
K 0 1 0 1
• A(t+1) = DA = A  x  y 0 1 1 0
1 0 0 1
01,10
1 0 1 0
1 1 0 0
00,11 0 1 00,11
1 1 1 1

01,10
 71

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
Analysis with JK Flip – • JA = B KA = B . x’
Flops
• JB = KB = A  x
J Q A
x’
x K Q • A(t+1) = JA Q’A + K’A QA
= A’B + AB’ +
J Q B Ax

K Q • B(t+1) = JB Q’B + K’B QB

CL = B’x’ + ABx +
K A’Bx’
 72

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
Analysis with JK Flip –
Present Next Flip –
Flops State
I/P
Flop
State Inputs
• JA = B KA = A B x A B JA KA JB KB
B x’
0 0 0 0 1 0 1 0
• JB = x’ KB = A  x
0
0 0 1 0 0 0 0 1
• A(t+1) = JA Q’A + K’A QA
0
= A’B + AB’ + Ax 0 1 0 1 1 1 1 0

1
• B(t+1) = JB Q’B + K’B QB 0 1 1 1 0 1 0 1
= B’x’ + ABx + A’Bx’ 0
 73

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
Analysis with JK Flip – Present Next Flip –
I/P
Flops State Flop
State Inputs
x=1 x=0 x=1 A B x A B JA KA JB KB

11 0 0 0 0 1 0 1 0
00
0
x=0 0 0 1 0 0 0 0 1
x =0 x=0
0
0 1 0 1 1 1 1 0
01 10
1
x=1
0 1 1 1 0 1 0 1
x=1
0
 74

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
Analysis with T Flip – • TA = B.x TB = x
x Flops T • y=A.B
Q y
A • Q(t+1) = T Q = T’Q + TQ’
• A(t+1) = TA A = TA’ A + TA
R Q
= (Bx)’A’
A + BxA’
= (B’ + x’)A +
T A’Bx
Q B
• B(t+1) == AB’
TB + Ax’B+ = TB’ B +
TB B’ A’Bx
R Q
= x’B
x + xB’
CLK B
Reset
 75

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
Analysis with T Flip –
Present Next FF
Flops
• TA = B.x TB = x State
I/P
Inputs
Output
State
A B x A B TA TB y
• y=A.B
0 0 0 0 0 0 0 0
• Q(t+1) = T Q = T’Q + TQ’
0 0 1 0 1 0 1 0
• A(t+1) = TA A = TA’ A + TA
0 1 0 0 1 0 0 0
= (Bx)’ A’
A + BxA’
0 1 1 1 0 1 1 0
= (B’ + x’)A +
A’Bx 1 0 0 1 0 0 0 0
• B(t+1) ==AB’
TB + B
Ax’
= T+B’ B + TB B’ 1 0 1 1 1 0 1 0
A’Bx
= x’B xB’ 1 0 1 0 0 1
+ 1 1
=x 1 1 1 0 0 1 1 1
B
 76

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
Analysis with T Flip – Flops Present Next FF
I/P Output
State Inputs
x=0 State
A B x A B TA TB y
x=0
0 0 0 0 0 0 0 0
00/0 x=1 01/0
0 0 1 0 1 0 1 0
0 1 0 0 1 0 0 0
x=1 x=1
0 1 1 1 0 1 1 0
1 0 0 1 0 0 0 0
11/1 10/0 1 0 1 1 1 0 1 0
x=0 x=0 1 1 0
x=1 1 1 0 0 1
1 1 1 0 0 1 1 1
 77

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
Mealy and Moore Models
• The most general model of a sequential circuit has:
– Inputs
– Outputs
– Internal states.

• Sequential circuits are divided into two (they diff er in the way
output is
generated:
– Mealy model
– Moore model
 78

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
Mealy and Moore Models
• Mealy model:
– The output is a function of both the present state and input.

– The outputs may change if the inputs change during the clock
pulse period.
• The outputs may have momentary false values unless the
inputs are synchronized with the clocks.
– Example of Sequential Circuit
 79

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
Mealy and Moore Models
• Moore model:
– The output is function of the present
state only.
– The outputs are synchronous with the
clocks.
– Example of Sequential Circuit
 80

A N A LYS I S O F CLO CK ED S EQ U
EN T I A L CI R CU I T S
Mealy and Moore Models
Mealy Machine

Inputs Next State State Output

Outputs
Combinational Register Combinational
(Mealy – type)
Logic Logic
clock

Moore Machine

Inputs Next State State Output

Outputs
Combinational Register Combinational
(Moore –
Logic Logic
type)
clock
 81

A N A LYS I S O F CLO CK ED S EQ U
EN T I A LM ealy
CI R CU I T S M oore
Present Next Present Next
I/P O/P I/P O/P
State State
A B x A B
State y State
0 0 0 0 0 0 A B x A B y
0 0 1 0 1 0 0 0 0 0 0 0
0 1 0 0 0 1 0 0 1 0 1 0
0 1 1 1 1 0 0 1 0 0 1 0
1 0 0 0 0 1 0 1 1 1 0 0
1 0 1 1 0 0 1 0 0 1 0 0
1 1 0 0 0 1 1 0 1 1 1 0
1 1 1 1 0 0 1 1 0 1 1 1
1 1 1 0 0 1
For the same state, For the same state,
the output changes with the input the output does not change with the input
 83

STATE REDUCTION AND ASSIGNMENT

• The analysis of sequential
circuits
– starts from a circuit diagram
and
– culminates in a state table
or diagram.

• The design of a sequential

circuits
– starts from a set of
specifications and
– culminates in a logic diagram.
 84

STATE REDUCTION AND ASSIGNMENT

• State – reduction algorithms are concerned with
procedures for reducing the number of states in a state
table, while keeping the external input – output
requirements unchanged.
• Since m flip – flops produce 2 m states,
– a reduction in the number of states may (or may not) result in a
reduction in the number of flip – flops.

• An unpredictable effect in reducing the number of flip –

flops is that sometimes the equivalent circuit (with fewer
flip – flops) may require more combinational gates.
 85

STATE REDUCTION AND ASSIGNMENT

• Consider a sequential 0/ 0

circuit whose a
0/ 0 0/ 0
specification is given in 1/ 0

0/ 0 0/ 0
the state diagram. b c

1/ 0 1/0
• There are infinite
0/ 0
number of input g d e
1/ 1 1/ 1
sequence that may be
0/ 0 1/ 1
applied to the circuit; f
1/ 1
– Each results in a unique
output sequence.
 86

STATE REDUCTION AND ASSIGNMENT

• Consider input sequence 0/ 0

– 01010110100 a
0/ 0 0/ 0
– Starting from the initial 1/ 0
state a. 0/ 0 0/ 0
b c
– Each input of 0/1 produces 1/0
1/ 0
an
to go to the next 0/ 0
output of 0/1 and causes g d e
state.
circuit 1/ 1 1/ 1
0/ 0 1/ 1
f
1/ 1
 87

STATE REDUCTION AND ASSIGNMENT

• Consider input 0/0
sequence a
0/0 0/0
– 01010110100 1/0

0/0
state

a a b c d e f f g f g a 0/0 b c
1/0
1/ 0
input

0 1 0 1 0 1 1 0 1 0 0 0/0
g d e
1/1 1/1
output

0 0 0 0 0 1 1 0 1 0 0 0/0 1/1
f
1/ 1
 88

STATE REDUCTION AND ASSIGNMENT

• Two circuits are equivalent
– Have identical outputs for all input sequences;

– The number of states is not important.

• The problem of state reduction is

– To fi nd ways of reducing the number of states in a
sequential circuit
without altering the input – output relationships.
 89

STATE REDUCTION AND ASSIGNMENT

• Equivalent States
– Two states are said to be equivalent if,
• For each member of the set of inputs,

• they give exactly the same output and

• send the circuit to the same state or to an equivalent

state.

– When two states are equivalent, one of them can be

removed without altering the input – output
relationships.
 90

STATE REDUCTION AND ASSIGNMENT

• Reduce the number of states 0/0

a
– Draw a state table 0/0 0/0
1/0
Next state Output
Present state x=0 x=1 x=0 x=1 0/0 0/0
b c
a a b 0 0 1/0
1/0
b c d 0 0
0/0
c a d 0 0 g d e
d 1/1 1/1
e f 0 1
e 0/0 1/1
a f 0 1
f
f g f 0 1
1/1
g a f 0 1
 91

STATE REDUCTION AND ASSIGNMENT

• Reduce the number of
states
Present Next state Output
– e = g (remove g)
state x=0 x=1 x=0 x=1
– The row g is removed.
a a b 0 0
– State g is replaced by
b c d 0 0
state e each time it c a d 0 0

occurs in the next – d e f 0 1

e a f 0 1
state columns.
f g f 0 1
g a f 0 1
 92

STATE REDUCTION AND ASSIGNMENT

• Reduce the number of
states
Present Next state Output
– Present state f has now
state x=0 x=1 x=0 x=1
next states e and f and
a a b 0 0
outputs 0 and 1 for x =
b c d 0 0
0 and x = 1.
c a d 0 0
– Then, d = f (remove f) d e f 0 1
e a f 0 1
– The row f is removed.
f e f 0 1
– The state f is replaced
by state d.
 93

STATE REDUCTION AND ASSIGNMENT

• Reduce the number of
states
Present Next state Output
– Final table
state x=0 x=1 x=0 x=1
– This table satisfies the
a a b 0 0
original input – output
b c d 0 0
specifications and will c a d 0 0
produce the required d e d 0 1
e a d 0 1
output sequence for any
given input sequence.
 94

STATE REDUCTION AND ASSIGNMENT

• Reduce the number of states
0/0

Present Next state Output a

state x=0 x=1 x=0 x=1
0/ 0 1/ 0 0/ 0

a 0/ 0
a b 0 0 g b c
b c d 0 0 1/ 1
1/ 0
c a d 0 0 0/ 0 1/ 0
d e d 0 1 d
e a d 0 1 1/ 1
 95

STATE REDUCTION AND ASSIGNMENT

• Reduce the number of states
– The checking of each pair of states for possible
equivalence can be done systematically using Implication
Table.

– The unused states are treated as don't-care condition

 fewer combinational gates.
 96

STATE REDUCTION AND ASSIGNMENT

• Implication Table (extra reading)
– The state-reduction procedure for completely specified state tables
is based on the algorithm that two states in a state table can be
combined into one if they can be shown to be equivalent. There
are occasions when a pair of states do not have the same next
states, but, nonetheless, go to equivalent next states. Consider
the following state table:
 97

STATE REDUCTION AND ASSIGNMENT

• Implication Table (extra
reading) Next state Output
Present
– Consider the following state x=0 x=1 x=0 x=1

state table:
a c b 0 1
– (a, b) imply (c, d) and (c, d)
b d a 0 1
imply (a, b). Both pairs of c a d 1 0
states are equivalent; i.e., a d b d 1 0
and b are equivalent as
well as c and d.
 98

STATE REDUCTION AND ASSIGNMENT

• Implication Table (extra reading)
– The checking of each pair of states for possible equivalence in a
table with a large number of states can be done systematically by
means of an implication table. This a chart that consists of
squares, one for every possible pair of states, that provide spaces
for listing any possible implied states. Consider the following
state table:
 99

STATE REDUCTION AND ASSIGNMENT

• Implication Table (extra reading)

– Consider the following state table: Implication

table: Next state Output

Present state x=0 x=1 x=0 x=1
a d b 0 0
b e a 0 0
c g f 0 1
d a d 1 0
e a d 1 0
f c b 0 0
g a e 1 0
 100

STATE REDUCTION AND ASSIGNMENT

• Implication Table (extra reading)
– On the left side along the vertical are listed all the states defined in
the state table except the last, and across the bottom horizontally
are listed all the states except the last.
– The states that are not equivalent are marked with a ‘x’ in the
corresponding square, whereas their equivalence is recorded with a
‘√’.
 101

STATE REDUCTION AND ASSIGNMENT

• Implication Table (extra reading)
– Some of the squares have entries of implied states that must
be further
investigated to determine whether they are equivalent or not.
– The step-by-step procedure of filling in the squares is as follows:
1. Place a cross in any square corresponding to a pair of states whose outputs
are not equal for every input.

2. Enter in the remaining squares the pairs of states that are implied by the
pair of states representing the squares. We do that by starting from the
top square in the left column and going down and then proceeding with
the next column to the right.
 102

STATE REDUCTION AND ASSIGNMENT

• Implication Table (extra reading)
3.Make successive passes through the table to determine whether
any additional squares should be marked with a ‘x’. A square in the
table is crossed out if it contains at least one implied pair that is not
equivalent.

4.Finally, all the squares that have no crosses are recorded with check
marks. The equivalent states are: (a, b), (d, e), (d, g), (e, g).
 103

STATE REDUCTION AND ASSIGNMENT

• Implication Table (extra reading)
– We now combine pairs of states into larger groups of
equivalent states. The last three pairs can be combined
into a set of three equivalent states (d, e,g) because each
one of the states in the group is equivalent to the other
two. The final partition of these states consists of the
equivalent states found from the implication table,
together with all the remaining states in the state table
that are not equivalent to any other state:
– (a, b) (c) (d, e, g) (f)
 104

STATE REDUCTION AND ASSIGNMENT

• State Assignment
– In order to design a sequential circuit with physical
components, it is necessary to assign coded binary values
to the states.
– To minimize the cost of the combinational circuits.

– For a circuit with m states, the codes must contain n bits

where 2n =
≥ m.
– Ex: with 3 bits it is possible to assign codes to 8 states
denoted by binary numbers 000 trough 111.
 105

STATE REDUCTION AND ASSIGNMENT

• State Assignment
– If the state table1 is used, we must assign binary values to 7
states.
• Remaining state is unused.

– If the state table2 is used, only five states need binary

assignment.
• Remaining 3 state is unused.
• Unused states treated as don’t care conditions.
• Since don’t care conditions usually help in obtaining a simpler
circuit, it is more likely that the circuit with five states will
require fewer combinational gates than the one with seven
 106

STATE REDUCTION AND ASSIGNMENT

• State
Assignment
Present Assignment 1 Assignment 2 Assignment 3
state Binary Gray Code One-hot
a 000 000 00001
b 001 001 00010
c 010 011 00100
d 011 010 01000
e 100 110 10000
 10
7

STATE REDUCTION AND ASSIGNMENT

• State Assignment
Present Next state Output
– Any binary number state x=0 x=1 x=0 x=1
assignment is
000 000 001 0 0
satisfactory as long as
001 010 011 0 0
each state is assigned a 010 000 011 0 0
unique number. 011 100 011 0 1
100 000 011 0 1
– Use binary assignment 1.
 109

D ESI GN PROCED U RE
• The design of a clocked sequential circuit starts from
– a set of specifications and
– culminates in a logic diagram or

– a list of Boolean functions from which the logic

diagram can be obtained.
 110

D ESI GN PROCED U RE
1. Derive a state diagram for the circuit from the word
description.

2. Reduce the number of states if necessary.

3. Assign binary values to the states.

4. Obtain the binary-coded state table.

5. Choose the type of flip-flops.

6. Derive the simplified flip-flop input equations and output

equations.

7. Draw the logic diagram.

 111

D ESI GN PROCED U RE
• Example: We wish to design a circuit that detects three
or more
consecutive 1’s in a string of0 bits coming through
1
an
• State
input line.
diagram:
S0 / 0 S1 / 0
0

0 1
0

S3 / 1 S2 / 0
1
1
 112

D ESI GN PROCED U RE
• This is a Moore model
0 1
sequential circuit since
S0 / 0 S1 / 0
the output is 1 when the
0
circuit
in is and 0
State3
0 1
0 otherwise.
State A B
S0 0 0
S3 / 1 S2 / 0 S1 0 1
1
1 S2 1 0
S3 1 1
 113

D ESI GN PROCED U RE
Present Next
I/P O/P
State State
0 1
A B x A B y
S0 / 0 S1 / 0 0 0 0 0 0 0

0 0 0 1 0 1 0
0 1 0 0 0 0
0 1
0 0 1 1 1 0 0
1 0 0 0 0 0
S3 / 1 S2 / 0 1 0 1 1 1 0
1
1 1 1 0 0 0 1
1 1 1 1 1 1
 114

D ESI GN PROCED U RE
• To implement the circuit,
– Two D flip-flops are chosen to represent the four states
and label their outputs A and B.
– There is one input x.

– There is one output y.

– The characteristic equation of the D flip – flop is

• Q(t+1) = DQ.
 11
5

D ESI GN PROCED U RE
Present Next
• To implement the circuit, State
I/P
State
O/P

– The flip – flop input A B x A B y

equations can be obtained 0 0 0 0 0 0

directly from the next – 0 0 1 0 1 0

0 1 0 0 0 0
state columns of A and B
0 1 1 1 0 0
and expressed in sum of
1 0 0 0 0 0
minterms.
1 0 1 1 1 0
– A(t+1) = DA(A,B,x) = ∑ 1 1 0 0 0 1
(3, 5, 7)
1 1 1 1 1 1
– B(t+1) = DB(A,B,x) = ∑
(1, 5, 7)
 11
6

D ESI GN PROCED U RE
• Synthesis using D Flip - • DA’s K -
flops Map
– A(t+1) = DA(A,B,x) = B B
∑ (3, 5, 7) A x 0 0 1 1
m0 m1 m1 M0
– B(t+1) = DB(A,B,x) = 0 1 3 2

0
∑ (1, 5, 7) 1
m4 m5 m7 M6
– y(A,B,x) = ∑ A 1 1
(6, 7) 1

DA = Ax + Bx
 11
7

D ESI GN PROCED U RE
• Synthesis using D Flip – • DB’s K -
flops Map
– A(t+1) = DA(A,B,x) = B B
∑ (3, 5, 7) A x 0 0 1 1
m0 m1 m1 M0
– B(t+1) = DB(A,B,x) = 0 1 3 2

0
∑ (1, 5, 7) 1
m4 m5 m7 M6
– y(A,B,x) = ∑ A 1 1
(6, 7) 1

DA = Ax + B’x
 11
8

D ESI GN PROCED U RE
• Synthesis using D Flip – • y’s K -
flops Map
– A(t+1) = DA(A,B,x) = B B
∑ (3, 5, 7) A x 0 0 1 1
m0 m1 m1 M0
– B(t+1) = DB(A,B,x) = 0 1 3 2

0
∑ (1, 5, 7)
m4 m5 m7 M6
– y(A,B,x) = ∑ A 1 1 1
(6, 7)

y = AB
 11
9

D ESI GN PROCED U RE
• Synthesis using D Flip – • Logic Diagram of
flops Sequence
– DA = Ax + Bx Detector
x D Q A
– DB = Ax + B’x

– y = AB Q
y

D Q B

CL Q
K
 120

D ESI GN PROCED U RE
• When – D type flip-flops are employed, the input equations are
obtained
directly from the next state.
• This is not the case for the JK and T types of flip-flops. In
order to determine the input equations for these flip flops,
it is necessary to derive a functional relationship between
the state table and the input equations.
 121

D ESI GN PROCED U RE
• During the design process we usually know the transition
from present state to the next state and wish to fi nd the flip
– flop input conditions that will cause the required
transition.
• For this reason, we need a table that lists the required inputs
for a given
change of state. Such table is called an excitation table.
 122

D ESI GN PROCED U RE
• D Flip – Flop Excitation
table
Present Next F.F.
State Input
D Flip – Flop Characteristic Table State
D Q (t+1)
Q(t) Q(t+1) D
0 0
0 0 0
1 1 0 1 1

Q(t+1) = D 1 0 0

1 1 1
 123

D ESI GN PROCED U RE
• JK Flip – Flop Excitation
table
Present Next F.F.
State Input
JK Flip J– Flop Characteristic
K Q (t+1) Table State
0 0 (No change)
Q(t) Q(t+1) J K
0 0 Q(t) 1 1 (Reset)
0 0 0 X 2 0 (Set)
0 1 0 1 1 (Toggle)
0 1 1 X
1 0 1 3 1 (Reset)
1 0 X 1 4 1 (Toggle)
1 1 Q’(t) 5 0 (No change)
1 1 X 0
6 0 (Set)
Q(t+1) = JQ’ +
K’Q
 124

D ESI GN PROCED U RE
• T Flip – Flop Excitation
table
Present Next F.F.
State Input
T Flip – Flop Characteristic Table State
T Q (t+1)
Q(t) Q(t+1) T
0 Q(t)
0 0 0
1 Q’(t) 0 1 1
1 0 1
Q(t+1) = T Q
1 1 0
 125

D ESI GN PROCED U RE
• Synthesis Using JK Flip – Flops: Detect 3 or more
consecutive 1’s
0 1

S0 / 0 S1 / 0
0

0 1
0

S3 / 1 S2 / 0
1
1
 126

D ESI GN PROCED U RE
• Synthesis Using JK Flip – Flops: Detect 3 or more
consecutive 1’s
Present Next Flip-Flop
Input
State Inputs
State
A B x A B JA KA JB KB
JA (A, B, x) = ∑ (3, 4, 5, 6,
0 0 0 0 0 0 X 0 X
7)
K (A, B, x) = ∑ (0, 1, 2, 3, 4,
0 0 1 0 1 0 X 1 X A
6)
0 1 0 0 0 0 X X 1 JB (A, B, x) = ∑ (1, 2, 3, 5, 6, 7)
0 1 1 1 0 1 X X 1 KB (A, B, x) = ∑ (0, 1, 2, 3, 4, 5,
1 0 0 0 0 X 1 0 X 6)
1 0 1 1 1 X 0 1 X
1 1 0 0 0 X 1 X 1
1 1 1 1 1 X 0 X 0
 12
7

D ESI GN PROCED U RE
• Synthesis Using JK Flip – • JA’s K-
Flops: Map
Detect 3 or more B B
consecutive 1’s A x 0 0 1 1
– JA (A, B, x) = ∑ (3, 4, 5, 6, m0
0 m1
1
m1
3 m0
2

–7) JB (A, B, x) = ∑ (1, 2, 3, 5, 6, 0 1

7) m4 m5 m7 m6
– KB (A,KAB,(A,x)B,=x)
∑ (0,
=∑ 1,(0,
2, 3,
1, 4,
2, 5,
3, 6)
A X X X X
4, 6)
1
x

JA = Bx
 12
8

D ESI GN PROCED U RE
• Synthesis Using JK Flip – • KA’s K-
Flops: Map
Detect 3 or more B B
consecutive 1’s A x 0 0 1 1
– JA (A, B, x) = ∑ (3, 4, 5, 6, m0
0 m1
1 m1
3 m0
2

–7) JB (A, B, x) = ∑ (1, 2, 3, 5, 6, 0

X X X X
7)
m4 m5 m7 M6
– KB (A,KAB,(A,x)B,=x)
∑ (0,
=∑ 1,(0,
2, 3,
1, 4,
2, 5,
3, 6)
A 1 1
4, 6)
1
x

KA = x’
 12
9

D ESI GN PROCED U RE
• Synthesis Using JK Flip – • JB’s K-
Flops: Map
Detect 3 or more B B
consecutive 1’s A x 0 0 1 1
– JA (A, B, x) = ∑ (3, 4, 5, 6, m0
0 m1
1 m1
3 m0
2

–7) JB (A, B, x) = ∑ (1, 2, 3, 5, 6, 0

1 X X
7)
m4 m5 m7 M6
– KB (A,KAB,(A,x)B,=x)
∑ (0,
=∑ 1,(0,
2, 3,
1, 4,
2, 5,
3, 6)
A 1 X X
4, 6)
1
x

JB = x
 13
0

D ESI GN PROCED U RE
• Synthesis Using JK Flip – • KB’s K-
Flops: Map
Detect 3 or more B B
consecutive 1’s A x 0 0 1 1
– JA (A, B, x) = ∑ (3, 4, 5, 6, m0
0 m1
1 m1
3 m0
2

–7) JB (A, B, x) = ∑ (1, 2, 3, 5, 6, 0

X X 1 1
7) m4 m5 m7 m6
– KB (A,KAB,(A,x)B,=x)
∑ (0,
=∑ 1,(0,
2, 3,
1, 4,
2, 5,
3, 6)
A X X 1
4, 6)
1
x

KB = A’ + x’
 13
1

D ESI GN PROCED U RE
• Synthesis Using JK Flip – • Logic Diagram of
Flops: Sequence
Detect 3 or more Detector
consecutive 1’s
J Q A
– JA = Bx
– KA = x’ x K Q y

– JB = x
J Q B
– KB = A’ + x’

CLK
 132

D ESI GN PROCED U RE
• Synthesis Using T Flip – Flops: 3-bit Counter. An n-bit
binary
counter consists of n flip – flops that can count in
to 2n – 000
binary from 0
1. 111 001

110 010

101 011
100
 133

D ESI GN PROCED U RE
• Synthesis Using T Flip – Flops: 3-bit
Counter.
Present Next Flip-Flop
State Inputs
State
A2 A1 A0 A2 A1 A0 TA2 TA1 TA0
TA2 (A2, A1, A0) = ∑ (3, 7)
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1 TA1 (A2, A1, A0) = ∑ (1, 3, 5, 7)
0 1 0 0 1 1 0 0 1 TA0 (A2, A1, A0) = ∑ (0, 1, 2, 3, 4, 5, 6, 7)
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
 13
4

D ESI GN PROCED U RE
• Synthesis Using T Flip – • TA2’s
K-
Flops: 3-
Map
bit Counter. A1A0 A1
– TA2 (A2, A1, A0) = ∑ (3, 7) A2 0 0 1 1
m0
0 m1
1
m1
3 m0
2
–– T (ATA1 (A2, A1, A0) = ∑ (1, 3, 0
A0 2 , A1 , A0 ) = ∑ (0, 1, 2, 3, 1
5, 7)
4, 5,
6, 7) m4 m5 m7 m6
A 1
1

A0

TA2 = A1A0
 13
5

D ESI GN PROCED U RE
• Synthesis Using T Flip – • TA1’s
K-
Flops: 3-
Map
bit Counter. A1A0 A1
– TA2 (A2, A1, A0) = ∑ (3, 7) A2 0 0 1 1
m0
0 m1
1 m1
3 m0
2
–– T (ATA1 (A2, A1, A0) = ∑ (1, 3, 0
A0 2 , A1 , A0 ) = ∑ (0, 1, 2, 3, 1 1
5, 7)
4, 5,
6, 7) m4 m5 m7 m6
A
1 1
1

A0

TA1 = A0
 13
6

D ESI GN PROCED U RE
• Synthesis Using T Flip – • TA0’s
K-
Flops: 3-
Map
bit Counter. A1A0 A1
– TA2 (A2, A1, A0) = ∑ (3, 7) A2 0 0 1 1
m0
0 m1
1 m1
3 m0
2
–– T (ATA1 (A2, A1, A0) = ∑ (1, 3, 0
A0 2 , A1 , A0 ) = ∑ (0, 1, 2, 3, 1 1 1 1
5, 7)
4, 5,
6, 7) m4 m5 m7 m6
A
1 1 1 1
1

A0

TA0 = 1
 13
7

D ESI GN PROCED U RE
• Synthesis Using T Flip – • Logic Diagram of 3-bit
Flops: 3- Binary
bit Counter. Counter
– TA2 = A1A0 T

Q
– TA1 = A0
A2
T Q A1
– TA0 = 1
Q
Q

1 T Q A0

CLK