Digital System Design

Chapter 5
Flip-Flops and Related Devices
Thái Truyển Đại Chấn
 Introduction
• The logic circuit consider so far
has no memory
• Depending on only current
statuses
• Flip-flop is the most important
memory element
• A logic gate cannot store info.
• Several gates are used to form a
flip-flop
 Introduction
Basic Structure
• is the most common
designations for FF’s outputs
•
• States
• FF is in the HIGH (1) state ↔Q = 1
• FF is in the LOW (0) state ↔Q = 0
• Q is always the inverse of Q
 Introduction
• Flip-flop
• Several inputs
• Switch back and forth
• Momentarily activated (pulsed)
• Other names
• Latch
• Bistable multivibrator
 Introduction

A
A
Y
B B

Set

Set Q
Reset
Reset
Q

• Momentarily activated (pulsed)

 NAND Gate Latch
• Most basic FF
• Two NAND gates or
• Two NOR gates
• The SET and RESET of NAND gate latch
• Normally in the HIGH state NAND flip-flop
• LOW pulse
 NAND Gate Latch
• SET = RESET = 1
• First possibility

• Second possibility

• Two possibilities for the same combination of

states of inputs
• Which possibility occurs depends on what
happened previously
 NAND Gate Latch
• Setting the latch
•Q=0 •Q=1
• A LOW pulse on SET always causes Q = 1
 NAND Gate Latch
• Resetting the latch
•Q=0 •Q=1
• A LOW pulse on RESET always causes Q = 0
 NAND Gate Latch
• Simultaneous setting and resetting
• , an undesired condition
• When SET and RESET pulse LOW, the condition depends on which
input turn HIGH first
• If they turn HIGH the same time, the result is unpredicted

• SET = RESET = 0 is normally not used

 NAND Gate Latch
• Summary
 NAND Gate Latch
• Alternative representations

Active-LOW
 NAND Gate Latch
• Example
• Given SET and RESET waveforms and initial Q, determine
the waveform of Q
• It “remembers” the last input that was activated and will not
change until the opposite input is activated
 NAND Gate Latch
• Example
• Already left contact 1 but bouncing on contact 2
 NAND Gate Latch
At set 1 R=0 because the current
• Example connect to 5v and to ground
 NOR Gate Latch
• Similar to NAND gate latch except
• Q and Q have reversed positions
• SET and RESET are active-HIGH, normally at 0, set/reset by
a HIGH pulse
 NOR Gate Latch
• Simplified block symbol

NOR Gate Latch NAND Gate Latch

 NOR Gate Latch
• Example
• Given SET and RESET waveforms and initial Q, determine
the waveform of Q
 NOR Gate Latch
• Example
• Detect the interruption of a light
beam
• Normally S = R = 0
• Light beam is interrupted even just
a very short time, Q = 1 to alarm
• Push SW1 to turn off the alarm
 NOR Gate Latch
• Flip-flop state on power-up
• When power is applied to a circuit, it is not possible to predict
the starting state of a flip-flop’s output
• May depend on
• Internal propagation delays, parasitic capacitance, and external loading

• Or must start off in a particular state to ensure the proper

operation of a circuit
• Must be placed in that state by momentarily activating the SET or RESET input
 Troubleshooting Study Case
• Using the latch to produce a
clear bounce-free signal at Q
and
• The switch is at A  Z2 passes
the 1-kHz pulse to XA
• Switching the pulse can be
conducted with a simpler
circuit but not bounce-free
 Troubleshooting Study Case
• The same circuit with the
observation shown as follows
• When the switch is at B,
correctly
• When the switch is at A, Q is
not at HIGH
 Troubleshooting Study Case
• Possibilities
• An internal open connection at Z1-1, which
would prevent Q from responding to the SET
input.
• An internal component failure in NAND gate
Z1 that prevents it from responding properly.
• The Q output is stuck LOW, which could be
caused by:
• Z1-3, Z1-4, or Z2-2 internally shorted to ground
• The Q node externally shorted to ground
• Checking:
• An ohmmeter check from Q to ground will determine if any
of these conditions are present.
• A visual check should reveal any external short.
 Troubleshooting Study Case
• Possibilities
• is not internally or externally
short to HIGH because if so, Q
should go HIGH when the latch is
SET
 Digital Pulses
• A signal switches from a inactive state to an active
state, causing sth to happen
• That signal returns to inactive state but its effect
remains
• The signals are called pulses
• Positive pulses: active state = HIGH
• Negative pulses
Digital Pulses
 Digital Pulses
• Example
• A microcontroller wants to access data in its external memory,
• It activates an active-LOW output pin called (read)
• Pulse width of 50 ns, a rise time of 15 ns, a fall time of 10 ns
 Clock Signals and Clocked Flip-Flops
• Digital systems can operate either asynchronously or
synchronously
• In asynchronous systems, the outputs change state
any time the inputs change
• An asynchronous system is generally more difficult to
design and troubleshoot
• Most digital systems are principally synchronous
 Clock Signals and Clocked Flip-Flops
• Synchronous systems:
• Outputs can change state only when the clock makes a
transition
• The clock signal
• Distributed to all parts of the system
• Generally a rectangular pulse train or a square wave
 Clock Signals and Clocked Flip-Flops
• Synchronous systems:
• The speed of a synchronous digital system depends on
how often the clock cycles occur
• The number of cycles in 1s = Frequency (F)
 Clock Signals and Clocked Flip-Flops
• Clocked Flip-Flops
• A clock input that is typically labeled CLK, CK, or CP
• In most clocked FFs, the CLK input is edge-triggered
(Latches are level-triggered)
 Clock Signals and Clocked Flip-Flops
• Clocked Flip-Flops
• Control inputs
• No effect on Q until the active clock transition occurs
• Called synchronous control inputs
• The control inputs control the WHAT (i.e., what state the
output will go to); the CLK input determines the WHEN
 Clock Signals and Clocked Flip-Flops
• Setup and hold Times
• Two timing requirements must be met if a clocked FF is to
respond to its control inputs and CLK transition
 Clock Signals and Clocked Flip-Flops
• Setup and hold Times
• The control inputs must be stable (unchanging) for at least
tS prior to the clock transition, and for at least tH after the
clock transition
• These times are measured between the 50% points on the
transitions.
 Clocked S-R Flip-Flop
• A clocked S-R flip-flop similar to a NOR latch but
required a ↑
 Clocked S-R Flip-Flop

• Assume that the setup and

hold time requirements
are met
 Clocked S-R Flip-Flop
• Internal circuitry of the edge-triggered S-R flip-flop
• Although our main interest is the FF’s external operation,
• A simplified version of the FF’s internal circuitry will aid
• Note: NAND latch with NAND pulse-steering circuit
• Active-LOW SET, RESET
• Active-HIGH S, R
 Clocked S-R Flip-Flop
• Internal circuitry of the edge-triggered S-R flip-flop
• The edge detector produces a narrow positive going spike
(CLK*)
 Clocked J-K Flip-Flop
• The same ways as for the clocked S-R flip-
flop
• J = K = 1 does not result in an ambiguous
output
Clocked J-K Flip-Flop
 Clocked J-K Flip-Flop
• Internal circuitry of the
edge-triggered J-K flip-
flop
• The CLK* pulse must be
very narrow,
• It must return to 0
before Q output a new
value,
• Otherwise the latch
toggles again
 Clocked D Flip-Flop
• Only one synchronous control input
• Q will go to the same state that is present on the D input
when a PGT occurs at CLK
 Clocked D Flip-Flop
• Waveforms
 Clocked D Flip-Flop
• Implementation of the D flip-flop
 D Latch (Transparent Latch)
• The D latch is not edge-triggered
 D Latch (Transparent Latch)
• Determine the Q waveform for a D latch with the EN
and D inputs given. Assume that Q = 0 initially
 Asynchronous Inputs
• Asynchronous Inputs (AIs) operate independently of
the synchronous inputs and clock input
• AIs can be used to set or clear the FF at any time,
regardless of the conditions at the other inputs
• AIs are override inputs
 Asynchronous Inputs
• Not used in all applications  permanently held at
inactive states
 Asynchronous Inputs
• Example
• Draw the waveform of Q for
given CLK, PRE, and CLR’s
• Provided long and short active-
LOW segments of PRE and CLR
 IEEE/ANSI Symbols
A single edge-triggered J-K flip-flop An actual IC (74LS112 dual negative edge- triggered J-K
flip-flop).
 IEEE/ANSI Symbols
A single edge-triggered D flip-flop An actual IC (74HC175 quad flip-flop with common
clock and clear)
 Flip-Flop Timing Considerations
• Manufacturers specify timing parameters and characteristics
• Setup and hold times
 Flip-Flop Timing Considerations
• Propagation delays
 Flip-Flop Timing Considerations
• Propagation delays
• Range from a few ns to 100 ns
• tPLH and tPHL are generally not the same
• Increase w/ the no. of loads driven by the Q output
 Flip-Flop Timing Considerations
• Maximum clocking frequency, fMAX
• The highest frequency that may be applied to the CLK input of a FF and still
have it trigger reliably
• Clock pulse HIGH and LOW times
• The min time duration that the CLK must remain LOW before it goes HIGH =
tW(L)
• The min time duration that the CLK must remain HIGH before it goes LOW =
tW(H)
 Flip-Flop Timing Considerations
• Asynchronous active pulse width
• tW(L) for active-LOW asynchronous inputs.

• Clock transition times

• Should be kept very short
• Generally should be ≤ 50 ns for TTL and ≤ 200 ns for CMOS
 Flip-Flop Timing Considerations
• Actual ICs
 Potential Timing Problem in FF Circuits
• If tPHLis not greater than tH, the response of Q2 is
unpredictable
• The FF output will go to a state determined by the logic
levels present at its synchronous control inputs just prior to
the active clock transition
 Flip-Flop Applications
• Applications including
• Counting,
• Storing of binary data,
• Transferring binary data from one location to another,
• Many more
• Almost utilize clocked operation
• A sequential circuit:
• Outputs follow a predetermined sequence of states
• A new state occurring each time a clock pulse occurs
 Flip-Flop Synchronization
• Most signals change states synchronously with the
clock transitions
• External signals may be not synchronized to the clock
• As a result of human’s actuating
• This randomness can produce unpredictable and
undesirable results
 Flip-Flop Synchronization
• Example
 Flip-Flop Synchronization
• Example
 Detecting an Input Sequence
Certain combination of inputs Activate something

Certain combination and sequence of inputs Activate something

A must go HIGH prior to B by at least the setup time

 Data Storage and Transfer
• Synchronous transfer

• Value stored in FF A is transferred to FF B upon the NGT of the

TRANSFER pulse

• Synchronous transfer: the synchronous control and CLK inputs

are used
 Data Storage and Transfer
• Asynchronous transfer

• Also called jammed transfer

 Data Storage and Transfer
• Parallel data transfer
• Does not change the contents of the
register that is the source of data
 Serial Data Transfer: Shift Registers
• Shift registers
• A group of FFs arranged so that the binary numbers stored in the
FFs are shifted from one FF to the next for every clock pulse
 Serial Data Transfer: Shift Registers
• Shift registers
• The waveforms
• Hold time requirements
CLK

Data in

X3
Hold time
X2

CLK-to-output propagation delay

 Serial Data Transfer: Shift Registers
• Remind
• The hold time is the interval following the active transition of
the CLK signal during which the synchronous control input must
be maintained at the proper level
 Serial Data Transfer: Shift Registers
• Serial transfer between registers
Serial Data Transfer: Shift Registers
 Serial Data Transfer: Shift Registers
• Parallel versus serial transfer

• Single pulse • N clock pulses

• The last FF in reg. X to the first
FF in Y
• Speed • Economy and simplicity

• When the transmission distance is long

• When there are a great no. of bits to be transmitted
Frequency Division and Counting
Frequency Division and Counting
 Frequency Division and Counting
• Frequency division
• Each FF divides the freq. of its input by 2
• Using N flip-flop produce an output freq. = 1/2N of the
input freq.
• Example: quartz watch, the “second” display (1Hz) is
produced by divided a much higher freq. signal from the
crystal
 Frequency Division and Counting
• Counting operation
• State table
• State transition diagram
 Frequency Division and Counting
• MOD number
• Indicates the number of states in the counting sequence
• N flip-flops  MOD-2N counter

• Example:
• Assume that the MOD-8 counter in
the 011 state. What will be the state
(count) after 21 pulses have been
applied?
 Frequency Division and Counting

• Example:
• Consider a counter circuit that contains 5 FFs similar to the above (i.e., Q4, Q3, Q2, Q1,
Q0).
• (a) Determine the counter’s MOD number.
• (b) Determine the frequency at the output of the last FF (Q4) when the input clock
frequency is 1 MHz.
• (c) What is the range of counting states for this counter?
• (d) Assume a starting state (count) of 00000. What will be the counter’s state after 129
pulses?
 Microcomputer Application
• A microprocessor unit (MPU) is the central processing unit of a
microcomputer
• Execute a program stored in memory

• E.g., On/Off devices

such as relays,
motors, …
• The data determines
which device
 Schmitt-Trigger Devices
• A Schmitt-trigger circuit
• Is not classified as a flip-flop
• Exhibit a type of memory characteristic
• Slow transition times
• Produce oscillations
• Erratic triggering of FFs
Schmitt-Trigger Devices
 Schmitt-Trigger Devices
• Positive-going
threshold voltage, VT+
• Negative-going
threshold voltage, VT-
 One-Shot (Monostable Multivibrator)
• One-shot
• Has only one stable state (normally, Q = 0)
• Once triggered, switch to and remain in quasi-stable state for a fixed
period of time,
• tp (few ns – few tens s), is determined by the values of external
components RT and CT.
One-Shot (Monostable Multivibrator)
 One-Shot (Monostable Multivibrator)
• Nonretriggerable one-Shot vs. Retriggerable one-Shot
 One-Shot (Monostable Multivibrator)
• Example: standard symbol and IEEE/ANSI symbol
Nonretriggerable
 Troubleshooting Flip-Flop Circuits
• Same problems with combinational circuits + timing
problems
• The most common types
• Open inputs
• Shorted outputs
• Clock skew
 Troubleshooting Flip-Flop Circuits
• Open inputs
• Picking up noise
• In combinational circuits, the output returns to the case when
the noise has not appeared
• In FFs, the output remains in its new state  more critical
 Troubleshooting Flip-Flop Circuits
• Open inputs
• Example
• X0 toggle after the 2nd
• Probably, a break between
and K0
 Troubleshooting Flip-Flop Circuits
• Shorted outputs
• Example
 Troubleshooting Flip-Flop Circuits
• Shorted outputs
• Possibilities
• 1. Z2-5 is internally shorted to
• 2. Z1-4 is internally shorted to VCC
• 3. Z2-5 or Z1-4 is externally shorted to
• 4. Z2-4 is internally or externally shorted to
GROUND. This would keep activated and
would override the CLK input.
• 5. There is an internal failure in Z2 that
prevents Q from responding properly to its
inputs.
 Troubleshooting Flip-Flop Circuits
• Shorted outputs
• Story
• Check with ohmmeter and finds no fault
• Replace Z2, not OK
• Replace Z1, not OK
• Finally, bridge solder between Z2-6 and Z2-
7
• Solution
• is stuck LOW. Q and are cross-coupled
• Both outputs should be checked, even not
connected to other devices
 Troubleshooting Flip-Flop Circuits
• Clock skew
• Example
• X is HIGH
• Initially, Q1 = Q2 = 0
 Troubleshooting Flip-Flop Circuits
• Clock skew
• Example
 Troubleshooting Flip-Flop Circuits
• Clock skew
• Not always easy to detect because the response of the affected
FF may be intermittent
• Sometimes it works correctly, sometimes it doesn’t
• Sometimes adding and removing an oscilloscope probe gives
different results
• Solution:
• Equalizing the delays in the various paths