SEQUENTIAL CIRCUITS

A sequential circuit is a digital logic circuit that includes memory elements to store the history of past operations.
Its output depends not only on the present inputs but also on the past outputs stored in its memory. This enables
sequential circuits to perform time-dependent operations.
LATCHES
Latches are level-sensitive, meaning they are transparent (allow data to pass through) when the control signal
(e.g., enable) is active, and they hold their state when the control signal is inactive.
SR Latch (Set-Reset)
SR latch is a circuit with two cross-coupled NOR gates or two cross coupled NAND gates, and two inputs labeled S
for set, and R for reset.

Hold
Reset
Set
Invalid

** Invalid or race condition arises then both Q and Q’ both are equal at a time, action produces an undefined next state,
because the state that results from the input transitions depends on the order in which they return to 0. So both input should
not be same at a time which is handle by using D LATCH OR JK LATCH OR T LATCH.

D Latch (Transparent) JK LATCH

**Race Around Condition In JK latchs – For J-K latches, if J=K=1, and if clock is enable for a long
period of time, then Q output will toggle as long as CLK is high, which makes the output of the flip-
flop unstable or uncertain. This problem is called race around condition in J-K flip-flop.
Solutions-
MASTER SLAVE OR EDGE TRIGGER FLIP FLOP
 SR LATCHE D LATCHE T LATCHE JK LATCHE
module SR_Latch ( module D_Latch ( module T_Latch (
input S, // Set input D, // Data input T, En, module JK_Latch (
input R, // Reset input En, // Enable output reg Q // Output); input J , K,EN,
output Q, // Output output reg Q ); always @(*) begin
output reg Q // Output
output Qn // Inverted always @(*) begin if (En) begin
); if (T)
);
if (En)
assign Q = ~(R | Qn); Q = D; // Q = ~Q; // Toggle always @(*) begin
assign Qn = ~(S | Q); Transparent end if (En)
endmodule end end begin
endmodule endmodule case ({J, K})
2'b00: Q = Q; //
MASTER SLAVE Hold
module MasterSlave_FlipFlop ( input clk, input reset, input D, output reg Q ); 2'b01: Q = 0; //
reg master; Reset
always @(posedge clk or posedge reset) 2'b10: Q = 1; //
begin if (reset) master <= 1'b0; // Reset master to 0
Set
else master <= D; // Capture input into master
end 2'b11: Q = ~Q; //
// Slave flip-flop (negative edge of the clock) Toggle
always @(negedge clk or posedge reset) endcase
begin if (reset) Q <= 1'b0; // Reset slave to 0 end
else
end
Q <= master; // Transfer master data to slave
end endmodule
endmodule

Common Issues with Latches- Applications of

• Timing Hazards: Latches can introduce glitches in asynchronous designs. Latches:
• Simulation vs. Synthesis Mismatch: Improperly inferred latches may behave
• TEMPORARY
differently in hardware.
STORAGE.
• Unintentional Latch Inference: Occurs when all possible conditions are not
specified combinational logic. • MEMORY
a. Missing else Statement ELEMENTS.
always @* begin • SYNCHRONIZA -
if (A) TION
Y = 1; // No `else` -> latch inferred • GATING SIGNAL
end
b. Partial Case Statement:
always @* begin
case (sel)
2'b00: Y = A;
2'b01: Y = B;
// Missing cases -> latch inferred also DEFAULT
endcase
end
c. Missing sensitive elements
always @(A) begin
Y = B;
else if (A)
Y = 0; // B not included in the sensitivity list
end
 FLIP FLOP
A flip-flop is a basic memory element in digital electronics that can store one bit of data. It
has two stable states, 0 and 1, and changes its state on the active edge of a triggering
clock signal or control input

SR FLIP FLOP D-FLIP FLOP

NAND BASED NOR BASED CHARACTERSTIC EQUATION: Qn+1 = D

S R QN+1
0 0 QN(HOLD)
0 1 0 (RESET)
1 0 1(SET)
1 1 X(INVALID)
CHARACTERSTIC EQUATION: Qn+1= S+ R’Qn JK FLIP FLOP

T FLIP FLOP

CHARACTERSTIC EQUATION: Qn+1 = JQ’ +K’Q

CHARACTERSTIC EQUATION: Qn+1 =

EXITATION TABLE:
 JK-FF SR -FF D-FF
module jk(q,qb,j ,k,reset ,clk); module srff (S,R,clk,reset ,q,qb); module dff(q,reset ,clk,d);
1 output reg q; input reset ,d,clk;
output reg q,qb; output reg q , qb ;
input j ,k,clk,reset; input S,R,clk,reset; initial
initial initial begin
begin begin q=1’b0;
q = 1’b0; q=1’b0; end
qb = 1’b1; qb =1’b1; always @ (posedge clk)
end end if (reset) q <= 1’b0; else q<=d;
always @ (posedge clk) always @ (posedge clk) endmodule
if(reset) if (reset)
begin begin
q = 1’b0; q <= 0;
qb = 1’b1; qb <= 1; T-FF
end end module tff(q,reset ,clk,t);
else else output reg q; input T,reset ,clk;
case({j ,k}) begin initial
if (S!=R) begin
{1’b0,1’b0}: begin begin q=1’b0;
q=q; qb=qb; q <=S; end
end qb <=R; always @ (posedge clk)
{1’b0,1’b1}: begin end if (reset)
q=1’b0; qb=1’b1; else q <= 1’b0;
end if (S==1 && R==1) else if (T) q= ∼q;
{1’b1,1’b0}: begin begin else q = q;
q=1’b1; qb=1’b0; q <= 1’bZ; endmodule
end qb <= 1’bZ; OR
{1’b1,1’b1}: begin end always @ (posedge clk)
q=~q; qb=~qb; end if (reset)
end endmodule q <= 1’b0;
endcase else q <= q ^t;
endmodule endmodule

Feature Latch Flip-Flop

Level-sensitive (triggered by input level or enable Edge-sensitive (triggered on clock edge, either rising
Sensitivity
signal). or falling).

Does not depend on the clock directly; uses

Clock Dependency Depends on clock edges (positive or negative).
enable signals.

Behaviour Continuously follows input when enabled. Changes state only at specific clock edges.
Operates at discrete intervals, ensuring more stable
Timing Control Transparent while enabled, can cause glitches.
operation.
Faster but less reliable due to continuous
Speed Slower due to clock dependency, but more reliable.
transparency.
Design Complexity Simple design. More complex design due to clock synchronization.
Sequential circuits, registers, and synchronous
Usage Temporary storage or small data path designs.
designs.
Power Lower power consumption as they do not require Higher power consumption due to the clocking
Consumption a clock. mechanism.
Better metastability handling due to clock
Metastability More prone to metastability issues.
synchronization.
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