Service Manual: PC-1211, CE-121

----SHARP----
SERVICE MANUAL
MODEL PC-1211, CE-121
CONTENTS
1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. LSI signal description 12
4. About servicing 17
5. Cassette operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6. Check program · · · · 25
7. Circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8. PC-1211 parts list & guide · · 32
9. CE-121 parts list & guide . . . . . . . . . . . . . . . . . . . . . . · · · · . · · · · · · · · · · · 34
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1. SPECIFICATIONS
~~POWER
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RESERVABLE KEYS
1-1 . Display
• Displaytube: LF8017JE
• Display method: 5 x 7 dot matrix liquid crystal
• Display capacity: 24 coulumns (alphanumerics and symbols)
1-2. Basic functions

• Computational capacity: 12 digits of mantissa and 2 digits of exponent.
• Computational method: According to mathematical formula (with priority consideration
and judge function)
• Capacities: Program memory; 1424 steps, max (PC1211)
Data memory; Fixed memory
26 memories
Flexible memory (commonly usable with the
program memory)
178 memories, max (PC1211)
Reserve program; 18 kinds, 48 steps, max
Input buffer; 80 steps
• Buffers: Data buffer; 8 stages
Functional buffer; 16 stages (but 15 stages for parenthesis)
Subroutine buffer; 4 stages
"FOR NEXT" stagement buffer: 4 stages
1-3. Arithmeticfunctions
Add (+),Subtract(-), Multiply (+),Divide(/), Power raising (A)
Trigonometric functions: SIN (sine), COS (cosine), TAN (tangent)
Inverse trigonometric functions: ASN (sine" ), ACS (cosine-1 ), ATN (tangent-1)
Logarithmic functions: LOG (common logarithm), LN (natural logarithm [ln])
·Exponential functions: EXP (exponential)
Angular transformations: DMS (decimal notation to sexagesimalnotation),
DEG (sexagesimalnotation to decimal notation)
Square root extraction: r
Signum function. SGN
Absolute value: ABS (IX I)
In terization: INT
Execution of arithmetic operation is commanded by the ENTER key.

1-4. Editorial functions
Cursor shift: .... (right), ~(left)
Insertion. INS
Deletion: DEL
Line control: +(down), t (up)
1-5. Programming language

BASIC (Beginner's All purpose Symbolic Instruction Code)
1-6. Power source

Battery: Four MR44 (mercury batteries)
Battery life: 300 hours
Power consumption: 0.01 iw
Automatic power shut off: About 6 minutes
1-7. Others
Data protection: Program memory, data memory, reserve program memory
Peripheral unit: Audio cassette unit (recording/reading of the program memory,
data memory and reserve program memory)
Physical dimensions: 175(W) x 70(D) x 44(H) mm
3
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4
System configuration (see the system block diagram)
System of this unit consists of the following components:
1) CPU I (SC43157) x 1
2) CPU II (SC43178) x 1
3) 4K-bit RAM (TC5514P x 3)
4) Display chip (SC43125 x 3, with built-in RAM)
5) 2AND gate (TC401 l UBP x 1)
6) 2AND 20R (TC4019BP x 1)
7) Inverter (TC4069BP x 1)
8) Quard Analog Switch Multiplexer (TC4066BP)
9) LCD (24-digit FEM dot LCD)
10) Key
11) Crystal (CSB2560)
2-1. CPU I, CPU II

These CPUs are provided with internal ROM, and each of CPUs shares the following assignments:
CPUI CPU II
8 Key input routine Display processing routine
>
Acknowledgement of the remaining Input buffer
program Computational result
Error
One instruction to one program step
incorporation Arithmetic routine
Interpreter: Character generator
Program execute statement Cassette routine
Cassette control statement Print routine
Command statement
Printer control Buzzer
Execution of manual operation Recognition of printer
I Power shut off control I Power off
Clock stop control Clock stop
• The CPU I functions to read key-in data or read the instruction to be executed from the RAM,
and decides what is to be done for the control of arithmetical operation (i.e. control of
arithmetic sequence, memorizing of arithmetical data, and its readout), or interprete the syntax
of the BASIC instruction for deciding what is to be executed, or determines and prepares the
information to be displayed, but the CPU I does not perform any execution by itself. It only
arranges the data and information in proper sequence and acts to provide instruction code to the
CPU II via the buffer. On the other hand, the CPU II constantly receives execution instructions
from the CPU I via the transfer buffer and executes operation against each of instructions or
sometimes performs to exchange data depending on the situation. Although it shares major part
of execution in term of execution, it performs some kinds of auxiliary CPU when looked in the
view that it does not perform any decision by itself.
5
Ex: Actions of CPU I and CPU II at the time of key data entry.
CPU Il
In the case of manual operation of the pocket computer, the instruction code (key code) is written
into the RAM in the display chip (input buffer) after information is put through the keyboard and
converted into the instruction code by the CPU I, then this instruction code (display, at this case)
is transfered to the CPU II via the transfer buffer. As the CPU II receives this instruction, the CPU II
then decodes this instruction (display, at this case) and executes display processing. Upon the
completion of this processing, it is then notified to the CPU I, then the CPU I confirms the comple-
tion of the task by the CPU II before terminating their jobs.
6
2-2. RAM
A certain number of C-MOS RAM (1 - 3 chips, 4K bits each) and another RAM incorporated inside
the display chip are used in this pocket computer, having varieties of configurations as described
below:
• Map of 4K-bit RAM
1536 Bytes
001
Reserve program
048
en
nd
;e)
II
------- - - - - - --
he
le-
Program
or
flexible memory
~------ -------
1472
Fixed memories (W - Z) Although RAM area is mainly shared by the program, data
Subroutine
stack
I FOR NEXT
statement
1504
and reserve program memories, it is also used for the sub-
stack 1536
routine stack, FOR NEXT statement stack and fixed
memories (W, X, Y, Z).
(PC1211)
7
• Map of the RAM incorporated in the display chip
There are three lK-bit RAMs (128 bytes each) incorporated in each of display chips (SC43125),
having the following configurations:
DISPLAY CHIP 1 DISPLAY CHIP 2 DISPLAY CHIP 3

000
8-digit display buffer 8-digit display buffer 8-digit display buffer
040
Transfer buffer
048
Fixed memories Fixed memories

80 step input buffer (A-K, 11 memories) (L-V, 11 memories)
128
• 8-digit display buffer

40 bytes of 8-digit display buffer is used as a display data buffer during displaying and also used
as a buffer memory for arithmetical result during the arithmetical operation.
• Fixed memory
The total memory of 176 bytes from the display chip 2 and 3 is used as a fixed memories, A-V
(22 memories).
1 memory
----1}4bit
16 bits
• Transfer buffer
8 bytes (1 memory equivalent) of the display chip 1 is used as a transfer buffer which is used in
the transaction of instruction between the CPU I and the CPU II.
• Input buffer
Remaining 80 bytes (10 memories equivalent) of the display chip 1 is used for the input buffer,
which is used in the following functions:
1. Any information entered through the keyboard is stored once in this buffer, thus allowing up
to 80 steps.
2. The display contents is stored by the CPU I and the CPU II makes selection out of this data.
3. When an arithmetical instruction is entered, its procedure is stored in this buffer by the CPU I
and the CPU II performs operation according to this procedure.
4. When program or reserve program is to be recorded or read out during the execution of the
cassette control instruction, action takes place through this input buffer.
8
2-3. Display
The contents of display indicated by the CPU I is received by the CPU II via the input buffer and
makes converted into respective character codes, then they are carried over to the display buffer in
the display chip through the address data bus.
• Designation of the display data
The following structure is observed in the display buffer in the display chip.
There are 8 x 40=320 bits ( 40 bytes)

of area in the display buffer in the
Counter/
HA decoder display chip.
Ex: Displaying numerical figure "4"

Al
I
A8 A7 A6 A4 H8 H7 H6 H5 H4 H3 H2 Hl
d 0 XOOl 1000 1 Hl DDD•D

1 XOOl 0100 S2 H2
oo••o
H3
o•o•o
0 0 0
) H4
•oo•o
v
F
0
Sl6
Sl7
H5
•••••
H6 ooo•o
H7 ooo•o
1 Sl8 Sl S2 S3 S4 S5
0 0 1
) Display buffer
F
S32
0 S33
1 S34
.in
0 1 0
~
fer, F S40
Address
up
ata. DI04 DI02 DI04 DI02

'U I '--------..,..-~
A5=1 A5=0
the Fig 2-3-1
The numerica figure "4", to be displayed by the CPU II, is converted into the relevant character
code and carried through on the address data bus. First of all, the segment Sl is selected with the
address A8-Al "00000000" to store the data DI04-DI01 "1000" in the display buffer (see Fig.
2-3-1 ). To store second half 4 bits of the data, only AS in the address in turned "1" to make the
address "00010000" to store data "0001 ". In the same manner, the address "00000001" is selected
for storing the first half 4-bit data "O 100" for he segment S2 and the second half 4-bit data "000 I"
is stored with the address "00010001 ".
9
DI SP 0.5ms
~
HA
----------- ----------- GND
----- VA
Hl --------.-----------Vs
-------- Vn1SP
H2
H3
H4
LJ
H5
H6 LJl....____flJ
H7 L I
Sl
S2
Fig 2-3-2
HA: Clock frequency for the counter. This signal is counted and decoded to perform synchroni-
zation with the comman signal, Hl-H7, generated from the CPU II.
DSIP: With high level of this signal, processing of display operation is indicated (RAM data
designated by Hl-H8 is sent out on SI -S40).
The data stored in the display buffer is carried through SI-S40 (Fig. 2-3-2) to be fed to the LCD.
(To indicate "4" on the display, H4 and HS are engaged for SI, H3 and HS for S2, etc., all the same
throughout S6-S40.)
10
2-4. Power source
ioo»
MOS FET
Relation between ternperture and VDISP

Yoo
C PUil
oo 20°
o The liquid crystal reference voltage VDISP is generated in the above circuitry in order to avoid
occurrence of such unpleasant phenomena as blurred character or contrast variation that might
degrade display performance, which is caused by a slight voltage variation in the liquid crystal
reference voltage VDISP, since the 5 x 7 dot matrix liquid crystal is used in the display of this
pocket computer.
A) VDD is generated in the CPU II on the basis of VGG.
B) The gate voltage of MOS FET is controlled by the 250KS1pot to regurate the voltage for VDISP.
Furthermore, the voltage of VDISP is changed by the thermistor to meet with temperature varia-
tion, so as to maintain proper display performance.
C) Line between the reference voltage VDISP and GND is divided by resistor to make out VA, VM
and VB.
VDISP: Low side voltage of common signals (Hl-H7) for LCD.
mi- VA: High side voltage for segment signals (Sl - S40)
VM: Intermediate voltage of the common and segment signals
ata VB: Low side voltage of segment signals.
NOTE: VA, VM and VB become pulses in an amplitude of several volts owing to influence
:D. caused from the LSI.
o Adjustments of reference voltage VDISP
The VDISP had been precisely adjusted to become -3.74V at an 30° Eye position
ambient temperature of 20°C and -4.29V at 0°C. In case there is a
need of readjusting the voltage after servicingthe LCD or exchanging
some of power source components, be sure to look on the LCD from
30° of angle from the vertical line while adjusting the pot.
-- --- ov
VA ....___ - - - --- -I.8V
6.8ms----
-------IV
VM ....___ - - - --- - 2.8V
------ -2.lV
VB L_ - - - --- -3.9V
VDISP - ----- -3.9V

11
3. LSI SIGNAL DESCRIPTIONS
3-1. SC43157 (CPU I)
Pin No. Signal name In/Out Description
1 F4a Out Chip Enable signal (RAM3 select signal)

4 Fla Out Chip Enable signal (Display chip 1 select signal, for input
buffer and transfer buffer usage)
During display: Low / ---- ---
During read-in: turns momentarily high
6 VGG In Source voltage("-" voltage of battery)

7 VGG In
8 Xin In Basic clock (pulse signal in 256KHz)
9 TESTl
Connected with GND
10 TEST2
11 RESET In All reset switch input

Normally high but turns low when the all reset switch is
depressed.
12 R/Wa Out RAM Data Read/Write signal

During display: High ________
Depression of the key causes it momentary low!
13 DIOl In/Out Data Bus (for address designation of the input buffer and
14 DI02 In/Out transfer buffer in RAM and display chip 1 ).
15 DI03 In/Out During display: High
16 DI03 In/Out During read-in: Low \_\_\_\_\_\_\_
17 B8a Out Address Bus (for address designation of the input buffer and
18 B7a Out transfer buffer in RAM and display chip 1 ).
19 B6a Out
20 BS a Out During display: ___ Mementary generation
21 B4a Out
22
23
B3a
B2a
Out
Out
During read-in:
lllllllllllllllllllllll l
24 Bla Out
30 GND In Source voltage (OV)
40 S16a Out Busy signal to the CPU II (High during the execution in the
CPU I)
During display: Low
During read-in: turns momentarily high
12
-
41 Sn Out Key Strobe signal, RAM Address signal
42 Si Out Key Strobe signal, RAM Address signal
43 Sl3 Out Key Strobe signal

44 Sl2 Out
45 Sll Out During display: High
46 SlO Out Depression of the key causes it momentary low
47 S9 Out
48 S8 Out
49 S7 Out
50 S6 Out
51 SS Out
52 S4 Out
53 S3 Out
54 S2 Out
55 Kil In Key input signal

56 Ki2 In
57 Ki3 In During display: Low
58 Ki4 In Depression of the key causes it momentary high
59 S16b
(Ki5)
In
CPU II)
During display: Low
I
Busy signal of the CPU II (high during the execution of the
Depression of the key causes it momentary high'.
3-2. SC43178 (CPU II)

1 F4 Out Buzzer signal

When the buzzer is off: Low ----i 0. 2 5msl--
When the buzzer is on: LS1___J
2 F3 Out Chip Enable signal (Display chip 3 select signal)
3 F2 Out Chip Enable signal (Display chip 2 select signal)
n 4 Fl Out Chip Enable signal (Display chip 1 select signal)
During display: Low ----- ______
During read-in: Turns mementarily high
5 VDD Out For liquid crystal drive voltage preparation (VDD :; V GG)
6 VGG In Source voltage("-" voltage of the battery)

7 VGG In
-
8 Xin In Basic clock (Pulse signal in 256KHz)
11 RESET In All reset switch input
13
12 R/VI Out RAM Data Read/Write signal

During display: High
During read-in: Turns momentarily low-- - - -- - -
13 DI04 In/Out Data Bus (for data transaction between RAM and display chip)
14 DI03 In/Out During display: High
lS DI02 In/Out During read-in: Turns low--l[lllll
16 DIOl In/Out
17 B8b Out Address Bus (for address designation of the display chip)
18 B7b Out During display: Bl b=high, B2B=low, B3b=low, B4b=low,
19 B6b Out BSb=high, B6b=high, B7b=low, B8b=low
20 BSb Out During read-in: Turns momentarily high
21
22
23
B4b
B3b
B2b
Out
Out
Out
. ______ /
24 Blb Out
2S HA Out Display signal (Common signal counting pulse)

Being generated during displaying
.ruu --10.Smst--
26 DISP Out Display command signal

During display: High
During execution: Low
27 VM In LCD display voltage (Intermediate voltage of the segment

signal)
28 VA In LCD display voltage (High side voltage of the segment signal)
29 GND In Supply voltage (OV)
30 H4 Out LCD common signals (backplate)

31 H7 Out
32 H3 Out
33 H6 Out
34 H2 Out
3S HS Out
36 Hl Out
37 VDISP In LCD display voltage (Low side voltage of the common signal)
38 VB In LCD display voltage (Low side voltage of the segment signal)
39 Sl6 Out Busy signal to the CPU I (High during the execution in the
CPU II)
During display: Low /
Depression of key causes it momentarily high.
40 SIS Out Record signal to the cassette tape and print data.
41 Sl4 Out Remote signal to the MT.
14
42 Sl3 Out Busy signal to the printer.
43 Sl2 Out Expansion signal

During display: Low
-~
) Depression of the CA (ON) key causes an instant pulse
generation.
49 S6 Out For DEF symbol display (engaged: low, not engaged: high)
54 Sl Out For symbol display (SHIFT, DGE, RAD, GRAD, RESERVE,

PRO, RUN)
Same waveform as the segment signal.
55 Kil In CPU I Busy signal (High during the execution in CPU I)

(Sl6a)
56 K.i2 In Expansion signal

To be connected to Sl 2 (CPU II) for PC-1211.
57 K.i3 In Printer Busy signal

Low when the priner is not operated.
58 K.i4 In Printer connection identifying signal.

Low when the printer is not connected.
59 l~5 In Cassette reproduct signal.
60 K.i6 In ON key input signal
1)
)
15
3-3 IC
TC4011UBP TC4069P
(Quad 2- input positive NAND gate ) ( HEX inverter
Vnn 14 13 12 11 10 9 8 Vno 14 13 12 11 10 9 8
2 3 4 5 6 7 2 3 4 5 6 7 GND
GND
TC4019BP TC4066BP
(Quad AND-OR select gate) ( Quad bilateral switch )
14 13
CIN
15
13 1 IN/ouT OUf/IN 2
1
5
2
12 CIN
4 IN/ouT our /IN 3
3
4 6
11
CIN
5
8 IN/ouT OUT/IN 9
6 12
10
7 CJN
11 IN/our OUT/IN 10
9
16

4. ABOUT SERVICING
~--Screw(b)
• Disassembly procedure
1) Remove the 2 screws (a) and
2 screws (b ).
2) Separate the upper cabinet
from the lower cabinet from
the screw side, as they are
latched together at three
points, A, B, and C.
• Repairing procedure
1) As the back of the arithmetic
printed board comes into
sight after the removal of the
Lach Fig 4- 1
lower cabinet, the arithmetic
printed board can be checked from the back side.
2) Replacement of the CPU II is possible.
3) If the key printed board is to be checked, the arithmetic printed board has to be bent in right
angle after removing the screws ( d) and (e ). Inspection of the CPU I is possible if the buzzer is
removed after removing the screw (c).
4) The key printed board can be dismounted from the upper cabinet when the 9 screws (f) and
2 screws (g) are removed. But, care must be exercised in dismounting the printed board, as
key tops may come falling down one after another.
• Replacement of the LSI
1) It will be much convenient if the LSI use soldering pencil (UKOG-0078CSZZ) is used for
replacing the LSI.
2) Be sure to remove the key printed board from the upper cabinet first, if the LSI on the key
printed board is to be removed. If the LSI was removed with the key printed board being
fitted on the upper cabinet, there is a possibility of deforming the key rubber by the heat of
the soldering pencil.
3) Be sure to cut the legs of IC, if IC was removed.
• Measuring current consumption
Power source voltage. 4.72V
Current consumption:
After depress the ON key: Under 850µA
After depress the OFF key: Under 12µA
Screw(el
Screw(c)
Fig 4 - 2
17
5. CASSETTE OPERATION
5-1. Recording
Recording method
4
1+1
80 steps
Contents of program or reserve program
Recording format of program or reserve program
Data memory recording format
1 = Check sun code (after every 8 steps or one data memory.)

2= 8 steps of program or reserve program
3= End code of recording.
4= This gap, composed of all "l ",is inserted at each step the recording exceeds 80 steps, during
which teime the next 80 steps of data to be input is prepared in the input buffer.
5 = All "l" is recorded for a period of about 6 seconds in order to avoid non-recordable area
located at the top of the tape and is also used for the cueing of the recording head.
6 = With this program or reserve program name is indicated. 5
7 = File name
8 = Data memory is indicated with this code.
9 = Area for one data memory.
Recording method
Data "O" and "l" are identified by changing the frequency of the recording signal (F4").
DATA"O" 2KHz
DATA" i " 4KHz
1 bit
18
Recording signal (F4") generation circuit
., ~ F<"---+ To CE121 cassette rnodulation circuit
Sl5 ~
s 15
HA
F4
Recording signal
11)
(F 4
Signal waveform at the time of recording
When recording signal "1" is to be recorded, Sl 5 is turned low level and the signal F4 (clock
pulse of'..;'. 4KHz) is output during that period. When recording signal "O" is to be recorded, SI 5
is turned high level and the F4 output is inhibited during that period, at which duration the
reverse signal of HA (clock pulse of::: 2KHz) is carried on the recording signal.
ring
Then, this signal is supplied to the MIC terminal of the tape recorder via the modulation circuit
of the CE121.
area
5-2. Reproduction
Output signal from the EAR PHONE jack of the tape recorder is amplified and shaped in the
Schmitt circuit, to be input to the CPU II through the KiS terminal of the CPU II.
KI 5
CPU 11
Schmitt circuit Amplifier circuit
19
5-3. Remote control
The CEl 21 will control the REMOTE terminal in automatic manner against the record, playback
and check commands.
0.04.:7PF 470Kn
100
2 Kn
4 6
ru_
Ain Q 2SA733 NR-5711
A
-----..,
MT
5 7
REMOTO Bin QA 74'W
TC4528BP 33n 5
(Sl4)
3
0.047µF
VGG 100
8 14 Kn
8 in QB 10 2SA733
83 B
I
11 9
GND Bin QB 14w L------~
330
13 TC4528BP
The TC 4528P is a mono-stable multivibrator which can perform trigger operation and reset
operation and two circuits are contained in the same chip.
"A" outputs a pulse which is dependable on the time constant of CR at the falling edge of the input
signal, and "B" outputs a pulse which is dependable on the time constant of CR at the rising edge of
the input signal. The relay operates ON and OFF according to the current flow to the coil, and it is
activated when "A" is active and deactivated when "B" is active.
~Startup of the cassette operation ~ Termination of the cassette operation
TI
Sl4----i--~~~~~~~~~__.r--
QA-u
\ Activation of the relay
(cassette to start running)
Lr
\ Deactivation of the· relay
(cassette to stop running)
20

5-4. Testing the CE121
1. Writing test data to PC-1211
;k
First of all, test data must be entered to PC1211 for checking CE121.
No. Read in Display Remarks
1 lMODEI - lMODE) > RESERVE Make the RESERVE

symbol indicated on
the display after
d1f essinf the
IE TER key.
I
I
I 2 NEW NEW_ RESERVE
I
I 3 IENTERI > RESERVE
I
4 lSHFTI z Z:_ RESERVE
~
RESERVE
µ__ 5 P.# lSHFTlf Af lSHF'rj; A(204) Z: P.#YA'; A(204)
I 6 !ENTER! Z: PRINT #fAf; A(204)RESERVE
7 lsHFTI X X:_ RESERVE
8 1.# !SHFTlfAY lSHFTl; A(76) X: I. #YAT; A(204)_ RESERVE
9 !ENTER! X: INPUT #JAY; A(204)RESERVE
10 I SHFTI ISP.CI . - RESERVE
11 A(76) : A(204) RESERVE
12 IENTERI : A(204)
13 IMODEI > DEF
14 !MODEi > RUN
15 I SHFTI ISPC I = 100 A(204)=100_ RUN
16 !ENTER! RUN 100
The test data have to be written into PC-1211 in the above manner.
2. Checking CE121
Assumes that the step 1 has already been executed
1 loFFI
2 Connect the CE121 with the

tape recorder.
3 Connect the PC 1211 with the

CE121.
4 loNI > RUN Make sure that the symbol

RUN is on the display.
Otherwise, let the symbol
Rillf :Jo8iEJlayed using
the key.
21
5 > RUN Make sureof the tape
recording location.
6 > RUN Depress the [REC] and

[PLAY] buttons. Then, the
cassette will come to halt.
7 lsHFTI Z PRINT #TA'; A(204)_RUN
8 !ENTER! RUN The cassette starts to run
generating sound.
9 > RUN The cassette comes to stop
quitting sound generation.
10 > RUN Depress the (PLAY)
button. But, the fassette
is still at halt.
11 > RUN Return the cassette tape

until the beginning of th"
recording.
12 lsHFTI X INPUT #'A'; A(204)_RUN
13 IENTERI RUN The cassette starts to run
generating reproducing
sound.
14 > RUN The cassette comes to stop
quitting sound generation.
15 lsHFTI lsPcl A(204)_ RUN
16 IENTERJ RUN 100.
17 RUN 100. Push the [STOP] button.
18 lOFFI
19 Disconnect PCl 211
from CE121.
20 Disconnect CE121 from the
cassette recorder unit.
I. It requires inspection if one of following conditions is recognized.

1. When the cassette starts to run at Step 6.
2. When the cassette fails to run or no sound is heard at Step 8.
3. When the cassette does not stop at Step 9.
4. When reproducing sound is not heard at Step 13.
II. Repeat the procedure in the following case.
1. When "5 " is displayed at Step 13, repeat operation from Step 10. If the same indica-
tion is still on the display, repeat the procedure from Step 5 after entering "A(204)=100". If
the same indication is to remain on the display even after this, it requires detailed inspection.
2. When "100." is not displayed at Step 16, repeat operation from Step 10. If the specific
indication does not appear on the display, repeat the procedure from Step 5 after entering
"A(204)=100". If the specific indication is not to appear on the display even after this, it
requires detailed inspection.
NOTE:
• When next CE121 check is to be performed in executing secondary test, be sure to enter
"A(204)=100".
• Repeat once again from the "l. Writing test data to PCl 211 ", if the contents of PCl 211
happens to change.
22
5-5. About repairing of CE121
Program
0 P R I N T # 'f D 'f A(201) PAUSE 1
O:GOTO 10
The CE 121 is in proper operation if the following procedures are ended successfully.
Plug Tape recorder

EAR REM
PHOE MIC OTE PLAY REC STOP
1 ( loFFI) Connect PC 1211
with CE121.
2
[QH]. > RUN 0 0 Determine the
location of the
tape to be recorded.
3 > RUN 0 0 0 0 0 Make sure that the
cassette tape does
not run.
4 cs. jsHIFTl'A CS. ,A_ RUN 0 0 0 0 0
5 !ENTER! RUN 0 0 0 0 0 The cassette tape
starts to run and
the recording sound
is heard.
6 > RUN 0 0 0 0 The sound is inter-
rupted and the
cassette tape comes
to halt with">"
indicated on the
display.
7 > RUN 0 0 Return the tape to
the beginning of
the recording.
8 > RUN 0 0 0 0
9 CLO.? lsHFTI'A CLO.?YA_ RUN 0 0 0 0
10 jENTERj RUN 0 0 0 0 The display con-
tents comes to dis-
appear from the
display and the
cassette tape starts
to run generating
the reproducing
sound.
11 > RUN 0 0 0 0 Sound generation
is interrupted and
the cassette tape
comes to halt with
">" indicated on
the display.
12 RUN
13 IOFFI
23
[Cautions]
1. Check the machine with the check procedure provided separately, if the cassette tape happens to
keep running at Step 3, the cassette tape fails to run at Step 5, or the cassette tape fails to stop
at Step 6.
2. Check the recording circuit of the CE121 if no recording sound is audible at Step 5.
3. In case no reproducing sound is audible at Step 10, proceed to playback another recorded tape to
check if reproducing sound is audible with that tape. If reproducing sound is not audible with
that tape, proceed to check the reproducing circuit of the CE121 as it may be not functioning
properly. If the reproducing sound is audible with the second tape, check the recording circuit
of the CE 121 as no proper recording may not have been carried out.
1 RUN RUN_ RUN No need of running the tape recorder.
2 IENTE~-- RUN Recording sound is audible.
3 RUN Recording sound goes out and "1 O." is displayed on

the display for a period of about 1 second.
4 - RUN
#5 and 12 pins of
TC4528BP (or equivalent) L
•In display~ . .,,4 .,14 In . ~4 · ..j4 In ~---.j+ ~~cording
recording In display recording In display recording In display
#6 pin of TC4528 and
--~,
#5 terminal of the relay
~
_J L__
1msec,min
Activation of the relay

(cassettetape to start running)
n n rt_
#10 pin of TC4528 and
-----,
#3 terminal of the relay
--Jl+---
~ L 1 msec, min n. . . . ._ ___.n. . . .__
Deactivation of the relay
(cassettetape to stop)
Cassette operation ON/OFF control must be properly executed when the above signals are observed
during the execution of program.
24
6. CHECK PROGF.
-
DISPLAY
READ I N
1 I 213141516 I 1l s I 9 l1oln l12ll3lul15!16!11i1al19I
l [1lliJ >
I
-
2 IALL RESET! > '
I I
3 5/9 !ENTER! 5 5 5 5 5 5 I 5 5 5
-
4 IMODEI >,
5 I p · lsHFTI w o K lsHFTI w IENTERI l : p R I N T
"' 0
'
K
"' l~
6 2 lSHFTI w z lsHFTI w P 2
"' z "'. p
I I
7 I SHFTI w s ISHFTI
3 B E E p 2 IENTERI
w !ENTER! 2 :
:
"' "'
z
B E E P
p R
2
I N T
" s "' I
8 3
~, I•
9 IMODEI > I
'
I
10 G R A D iENTERl >,
11 I SHFTI ISPCI 0 I 4 7 IENTERI :
I
0 l 4 7
I
·l
12 IMODEI >, '
I
13 ISHFTI z s
14 IMODEI lsHFTllsPcl 0 I 4 7
I
15 @RAD IENTERI >
I6
17
R
I ENTERI
· lENTERl 0 K
s
I I
T
'r T 'r
1
.:
I
18 IENTERI > '

-
I
19 !OFFI -
20
21 I
'
'r
T
' 'r
' I I
22
23 I
-
24
25
I T l
26
' ' I ' ;
27 -
I
28
29
30
I
I .I
I
31
I
32 ' ' ' I
33
I I
' ' ' l l
' "l
l
34
I I
' ' '
I' l
35 ' l I
I
v
B
I
36 I
' ' ' I '
37
'
I
38
39
I
' ' '
40 '

!HECK PROGRAM
DISPLAY SYMBOL Cassete

Smm
11 I 12 I 13 lu I 15 I !6 I 11 I is I 19 I 20 I 21I22 I 23 I 24 SHFT DEG RAD GRAD DEF RUN PRO ~ PLA) REC STOP REMJT]
I 0 0
I
5 5 5 5 5 5 5 5 5 E - 0 1 0 0
I 0 0
K 'f (0) 0 0
I
(0) 0 0
T' s T'
I
(0)
I
0 0
0 0
I
0 0
0 0
(0) 0 0
I
0 0
(0) 0 0
(0) 0 0
I I
0 0
0 0
0 0
I
0 0 0
I I
I
I I I
I
I
I I
I
I I
I I I I
I I
·' I I
I
I I
25

7. CIRCUIT DIAGRAM PARTS
7-1. Operation Circuit Diagram
~~~C!_l~!_,CCZZ J
I Opt ion: I/0 connect signal

I
Ki4
I VGG
Op tion
Co ntrol
JoI
I
51 3
l
I
I
D ATAI
I
515
I
I
cMT I
I
514
REM OTO
-
Signet I IA3
12 I
I l
:· ioxo r µ_,.-,
•B2a~~~:
I
'- ,_
--
I
S4" ' 3~1-1- I t:-:t--'A_2
__ -J..__
CMT ' lOKn"\....___,.~lt-t---t-+-t---~-l--1-LJJ'k/1..,/e -
Recording
Signe q TC4011 UBP .,,,..._]
[rc4-059 p
- - '--------!lrt--++-----i· ill I 5
1 I
:
I ~ I
I
I
D-7-GND
--ir-+-+--+-l--1...J""-/C-H-+-L---'''
5 6 l~O~P;;;Ft---f-+-H----1J •Bla~-~I
I T.Q''~A=l~--r------=i-
I
50WV
---r-tt-t---++----+'~D I 7 ·101 I
lOOKn
nl 'Q'" ";, - - _J
~VGG
I
I
L..----....J
SUB PWB
--D Q~
H ~~Hn
..... nn
0000
1 2 3 4
VGG* s
16
a
DF/F
K' CP GL PR
1 1 ,
i
l
HA S 16L
26

GRAM PARTS & SIGNALS POSITION
F2a F 3a F4a BP
13 11 9
TC4069P
12 ID 8 [~J_ ,____ _
VM
1:::
iTC4019P(2)
-
·-v.
D515BBL1
-
- -
L:
~
BP
56'
56'
VM
BP §= ~
>--'-
._~
'----- VnrsP Vnrsi ~
1AS
i2 i2
113 I gi ~~
0 TC4066P
I lM
I
I
I (RAM)
A7 TC 5514PX 3
-
12 I
~
I ,___
I ,___
-
---
I
IA6 (3)
111 '-'-
I -~ '-'- 150Kn
L- F4a1 GKD Tbermi stor
I -
h~ ~tJ
GND
I
I
IA5 VA_
10 l > <R
I
I "~:~ ~,!~- "'~
VM~ ~-H
....J ~,___
--,TC4019P(IJ
IA4
I --
- --
,. '-
>
=z~
~ .._ ~=-
~- r---- IOOKn ~ i!OWV
Vg - JOQµF
13 I '-'- -
(21 i.lf
I
I
I
'-
-- >-'-'-
'-'-
.._ F3a 1
Vmsr - -'
i~~ ~.--'
} 2~Kn
I
'-
~ ::;J 1
Von
IA3
L-~
'-
12 I
VGG"
I
I
111
I
!A2
~
A7
A6
A5
GND
AB>--
Si-r-
- I
I
I
I
I A4
'-Al
A2 (I)
Sn
DIOl
DI02
~
- -
I A3 DI03
•Al F2a1 DI04 ,.

10 I -vGG RA''
.
1~PF ·~
I IOOKn ~
_J
"
-
r=n -- .,,
PWB ' ~
AAAAAAA A S Sn R/Wb Xin
7654321 8 i
516L

7-3. Key Circuit
FUNCTION
28

~rJ~ 1: ~rJ~ ~ I~=
\
-6±M I
=s
I J =-=-=-. .
::::
I I I
!
=-_, .,.-_-
=-= ~~ 'O.': -~ =-~ l"t - =~ ~~ ~l
-==- ;:::~ ~~=J)~
I
-=-~~~1--:
Io I
I ,\ +++
~l* I
\
~li:~
~ ~ fij•~
~r r ~r r rrr
~ S27~~~~~~:;~~~~~~;;~~~)_ ~ t•••"''~"~"'~"~·~~,
,,_
s-
,,_ '--s2s se-
'--$2']VlVlUlVlVl'JlUllJlU'IVlVlllll.fl00Vl<ntl)S~~
'--sza snl----"
,._ ---- 529
'---53-0
S5---"
S•-
-s2s
,...____ 580
ss~
54 ___,;
ss- ...---GND SC43125 ss- --cw SC43125 ss-'
I'--- 531 52 - I'- 581 52 ____,
C---532 DlSPLAY CH]P(2) SI- r--s32 DJSPLAY CH!P(3) SI~
i'-- S33 A5 _......, ['--- Sas AS _......,
t"-- 534
~~s
I'-- 534 A7--+. A7 ---+.
~ 585~ ~~~~ ~~~~~ ~~~~<~<AB~ bM 535~* *~~~~~~~ ~~<~AS~
~J ~J J J
J
Ht
))) )
f"" ~H MR44X4
..... •..... •• DODOO

D
D
DO
DODOO
0 D
DO DODOO
D 0
ODD
D
ODD
D D D
qoo
D
...• •••••
D D D ODDO D D D D D D D D
DOD D 0 D ODDO D DOD DODD D O DOD
D DODOO D D D D D 0 D D D
• D 0 0 0 DD D D D 0 0 D D , D
~ !5~t~~f~
0000 0 ODD OD DOD D DOD DO DOD DODOO
~ ? ~ ••
.• D
D
D
D DOD
0
D D D
0
D
D D
0
00000 DODOO
DODOO
DODOO
DD
DD
DODOO
•• D
D D D 0
0 D
D D
D
DODOO DD
DD
• D DODOO
.•......•
•••
0000
D
D
ODD
O
0
D
D
0
0
0
D
DOD DODO
0 D
DODOO
D D
D 0 0
0
0
D
D
DODD
D
DODOO
0
D
DODO
0
D
D
D
D
ODDO
DD
D
D
D
D
D
0
00000
D 0
0 ODO
0
0
D
D
ODD
D
0
0
D
0
B
00
0 D
D~
D D
D
D
D
D
D D
DD OD
D D D
D D D
D D
•• •• D
0000
D D
ODO
0 0
DODO
0 0
DODOO
0
D
D
ODO
D D
D
D
0
D
ODD
D
DO
0 D
0
D
0
D
DODOO
D
0
D
D
•. .• ODD ODDO ODD ODDO ODD 00000 D D D O DODOO
•...
D 0 0 D 0 0
. • ••.
D D 0 0 D D o o o o D D D o o D 0 0 D D D 0
•• D
0
D
O 0
D DODO
0 0
0 0
D
D D
D 0000
D D D o o
0 o
000
o
D
D
D
O
D
D
D D
O
O
D D
D D
0 D D
D 0 D
D D 0
0
0
0
D
D
0
0
0
0
D
0
0
D 0 0 O D o o o o D D D D DD 00 o o o 0
ODO 0 DD D o o DOD D ODD D D D D 0 D DODOO
D D DODOO 0 DOD
D D o o o D
D o o o o
o o o D
o o o D D
o o DD
D 0 O D
00000 DD
0 0 OD
DD OD
OD DO
0 0 0 D
DODOO 0 D

i-------
~
(' MSM401 3RS
~ _____ ..;

7-5. CE-121 Circuit Diagram
2SA 733
RECORD input 0.(

470Kn 25
( F4")
lOOKn
DS1588Ll
CMT
LOAD output
6
(KI 5 )
DS1588Ll TC4069P
50WV
0. 047 )lF 470 Kn
lOOKn
r
4
CMT
REMOTE Y4W
(s
14) 5 33!1
3
50WV
0.047 FF 470Kn
VGG lOOKn
e 16WV 15 14
Ef> lO)lF QB 2 SA733
12 10
BQB 9
GND %W
11 TC4528
BP 33!1
13
,__-1•1•
AAX3
30

2 SA 733
O.OlµF 2SC458KS
25WV MIC
lOOK.n i uo
.~,~~.
.,.
I
EAR
12 PHONE
0. 047J1- F/50WV..,t ..
I
2 SC458KS
NR 5711
r---- --- --- -.,
5 I
'--~~~~~~+---<~>-----.-.. :
I
Y4W
33.n
4
RE.YOTE
1
1
%W ,3 :
33.n L------------J
'----1•1•
AAX3

8. PC-1211 PARTS LIST & GUIDE
NEW PARTS
NO. PARTS CODE DESCRIPTION MARK RANK PRICE RANK NO. PART
1 LX-BZ I I 02CCZZ Screw N c A B TMANEI
2 LX-BZI032CCZZ Screw c A A 5PAKCE
3 HDECAl705CCZZ Bottom cabinet N D A N TiN5E2
4 PZETLl323CCZZ Insulator sheet N c A B LPLTPI
5 PTPEHI062CCZZ Tap for chassis c A A TLABZI
6 LCH551078CCZZ Chassis N c A c RR-DZI
7 GFTAAl231CCZZ Lid N D A B RR-DZI
8 XBP5D20P09000 Screw c A A RR-DZI
9 RALMBl006CCZZ Buzzer B A H RVR-ME
10 LX-BZI060CCZZ Screw X9 o A A VCEAAL
11 XTP5D20P05000 Screw c A A VCKYPL
12 QCNTMI036CCZZ All reset switch o A B VHDD51
13 PCU551081CCZZ Cushion c A A VHHl54
14 QCNW-1 I 35CCZZ Flexible wire (22pin) N B A o VHi5C4
15 QCNCWl259CCOi Connector (9pin) N B A H VH i 5C4
16 PGUM5 I I 90CCZZ Rubber connector c A F VHi5C4
17 VVLLF8017..JE-I LCD N B B A VHiTC4
18 PTPEHl033CCZZ Tape for LCD c A A VHiTC4
19 LANGK1290CCZZ Angle for LCD c A D VHiTC4
20 PFiLWl230CCZZ Filter c A H VHiTC4
21 HDECAl527CCZZ Display mask c A c VH i TCE
22 PFiLWl228CCZZ Display filter . c A c VRC-M1
23 PGUMMl254CCZZ Key rubber B A K VRD-51
24 M5PRCI098CCZZ Earth spring c A A VRD-51
25 ..JKNBZ1515CC04 Key top (18key) N c A F VRD-51
26 ..JKNBZl515CC05 Keyt op (17key) N c A F VRD-51
27 ..JKNBZl516CC02 Keyt op (SHIFT) X20pcs N c A E VRD-51
28 ..JKNBZ1566CCOI Keyt op (ENT ER) X 1 0 pcs N c A G VRD-51
29 ..JKNBZ1492CC02 Keyt op (Numeral) N c A E VRD-51
30 ..JKNBZl567CCOI Keyt op (CL) X20pcs N c A E V525C4
31 QTANZl287CCZZ "Battery terminal (+, -) c A B V525..J4
32 QTANZ1292CCZZ Battery terminal (+) c A B RC-5ZI
33 QTANZl250CCZZ Battery terminal (-) c A B RCR5PI
34 XU55D20P04000 Screw c A A VCKYPL
35 LANGTl336CCZZ Angle for bottom cabinet N c A B VCTYPL
36 CCABB2299CC02 Top cabinet N D A s RC-5ZI
37 GFTAA1232CCZZ Lid for connector N D A B VRD-51
38 QCNW-1 I 37CCZZ Flexible wire N B A c VCKYPL
39 QTANZl293CCZZ Battery terminal (+.-) N c A B
UBAGZ I 2 I I CCZZ Hard case N D A M DKiT-1
SPAKA5108CCZZ Packing cushion N D A F
TiNSE3137CCZZ Instruction book (U.S. A) N D A p
PC-1211-[j] PC-1211-[gj
32

NEW PARTS PRICE ::r,;.
NO. PARTS CODE DESCRIPTION MARK RANK
TMANEIOIOCCZZ Program library N D A z
SPAKC5012CCZZ Packing case N D A G
TiNSE2826CCZZ Basic text N D A K
LPLTPl070CCZZ Tenplate N D A 8
TLABZl295CCZZ Name lavel D A A
RR-DZI006CCZZ Resistor 1/BW 143Kohm ±2% c A B
RR-DZl007CCZZ Resistor 1 /BW 12. 7Kohm ±2% c A B
RR-DZI008CCZZ Resistor 1 /BW 21.0Kohm ±2% c A B
RVR-MB510QCZZ Valiable resistor 250Kohm c A D
VCEAAUIAW107Q Capacitor lµF 50V c A E
VCKYPUIHB221K Capacitor 220PF 50V c A 8
VHDDSl588Ll-I Diode DS1588L1 8 A D
VHHl54KD-5/-I Thermistor 150Kohm B A c
VHiSC43125/-I L. S. i (Display chip) B A x
VHiSC43157/-I L. S. I (CPU- I) N B B F
VHiSC43178/-I L. S. i (CPU- II) N 8 8 D
VH i TC40 I I UBP I i. C. 8 A F
VHiTC4019P/-I i. C. B A K
VHiTC4066P/-I i. C. 8 A K
VHiTC4069P/-I i. C. B A H
VHiTC5514P/-I L. S. i (RAM) 8 B D
VRC-MT2BGl65J Resistor 1/BW 1.6Mohm ±5% c A 8
VRD-ST2BYIOIJ Resistor 1/BW 100ohm ±5% c A A
VRD-ST2BY223J
VRD-ST2BYl03J
Resistor
Resistor 1/BW
1/BW 22Kohm ±5%
10Kohm ±5%
c
c
A
A
A
A
1
33
VRD-ST2BY104J Resistor 1/BW 100Kohm ±5% c A A
VRD-ST2BYl05J Resistor 1/BW 1Mohm ±5% I c A A
VRD-ST2BY472J Resistor 1/BW 4.7Kohm ±5% I c A A
VRD-ST2BY474J Resistor 1/BW 470Kohm ±5% I B A A
VS2SC458KS/-I Transistor 2SC458KS B A c
VS2SJ40-///-I MOS FET 2SJ40 c A G
RC-SZl005CCZZ Capacitor 0.1µF lOV c A c
RCRSPl024CCZZ Crystal N c A H
VCKYPUIHBIOIK Capacitor lOOPF 50V c A A
VCTYPUIEXI03M Capacitor lOOOOPF 25V c A B
RC-SZl007CCZZ Capacitor lµF lOV I c A F
VRD-ST2BY224J Resistor 1 /BW 220Kohm ± 5% c A A
VCKYPUIHBI02K Capacitor 1 OOOPF 50V c A A
DKiT-IOOICCZZ SUB-PWB Kit N
•
PC-1211-[g]

l/.iii
33
9. CE-121 PARTS LIST & GUIDE
NEW PARTS PRICE RANK
NO. PARTS CODE DESCRIPTION MARK RANK
1 GCABA2315CCZZ Bottom cabinet N D A G
2 LX-BZl038CCZZ Screw c A A
3 GLEGGIOl2CCZZ Rubber foot c A A
4 GFTABl235CCZZ Battery lid N D A c
5 XTBSD20P06000 Screw c A A
6 QPLG..JI008CCZZ Plug N B A Q
7 QCNCMl260CCOI Connector (9pin) N B A G
8 XTBSD20P05000 Screw c A A
9 LANGTl334CCZZ Angle N c A c
10 QTANZl266CCZZ Battery terminal 9 c A A
11 QTANZl072CCZZ Battery terminal EB c A A
12 HDECAl684CCZZ Dec. panel A N D A c
13 HDECAl685CCZZ Dec. panel B N D A D
14 GCABB2316CCZZ Top cabinet N D A G
SPAKA5097CCZZ Packing case N D A D
SPAKC5 I I I CCZZ Packing case N D A D
SPAKA5109CCZZ Packing cushion N D A E
VCEAAUICWI06Q Capacitor 10µF 16V c A B
VCQYKUIHM472K Capacitor 0.0047µF 50V c A B
VCQYKUIHM473K Capacitor 0.047µF 50V c A B
VCTYPUIEXI03M Capacitor 0.01µF 25V c A B
VCTYPUINXI04M Capacitor 0.1µF 12V c A B
VHDDSl588Ll-I Diode DS1588L1 B A B
VH i NR57 I I/ /-1 Relay NR5711 N B A w
VHiTC4069P/-I I. C. TC4069P B A H
VHiTC4528BP-I I. C. TC4528BP N B A p
VRD-ST2BYI03..J Resistor 1/8W 10Kohm ±5% c A A
VRD-ST2BYl04..J Resistor 1/8W 100Kohm ±5% c A A
J VRD-ST2BYl05..J Resistor 1/8W 1Mohm ±5% c A A
VRD-ST2BYl83..J Resistor 1/8W 18Kohm ±5% c A A
VRD-ST2BY223..J Resistor 1/BW 22Kohm ±5% c A A
VRD-ST2BY271..J Resistor 1/8W 270ohm ±5% c A A
VRD-ST2BY474..J Resistor 1/8W 470Kohm ±5% c A A
VRD-ST2BY564..J Resistor 1/BW 560Kohm ±5% c A A
VRD-ST2EY330..J Resistor 1/4W 33ohm ±5% c A A
VS2SA733-//-I Transistor 2SA733 B A D
VS2SC458KS/-I Transistor 2SC458KS B A c
34
4 ~5
10 7 .~
~/
35
•
SHARP CORPORATION
Industrial Instruments Group
Reliability & Quality Control Department
Yamatokoriyama, Nara 639-11, Japan
1 981 March Printed in Japan

Service Manual: PC-1211, CE-121

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Service Manual: PC-1211, CE-121

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----SHARP----

MODEL PC-1211, CE-121

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0 [}] 0 0 0 0 0 IT] [TI~ OJ ITJ []] El G

1-2. Basic functions

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1-5. Programming language

1-6. Power source

A.. f :;;: '., ,___

(/) ::il tOia-!OJG rn

:E '- L'lZO 0..

2-1. CPU I, CPU II

DISPLAY CHIP 1 DISPLAY CHIP 2 DISPLAY CHIP 3

Fixed memories Fixed memories

• 8-digit display buffer

There are 8 x 40=320 bits ( 40 bytes)

Ex: Displaying numerical figure "4"

d 0 XOOl 1000 1 Hl DDD•D

ata. DI04 DI02 DI04 DI02

Relation between ternperture and VDISP

VDISP - ----- -3.9V

1 F4a Out Chip Enable signal (RAM3 select signal)

6 VGG In Source voltage("-" voltage of battery)

8 Xin In Basic clock (pulse signal in 256KHz)

11 RESET In All reset switch input

12 R/Wa Out RAM Data Read/Write signal

30 GND In Source voltage (OV)

43 Sl3 Out Key Strobe signal

55 Kil In Key input signal

Depression of the key causes it momentary high'.

3-2. SC43178 (CPU II)

1 F4 Out Buzzer signal

6 VGG In Source voltage("-" voltage of the battery)

11 RESET In All reset switch input

12 R/VI Out RAM Data Read/Write signal

2S HA Out Display signal (Common signal counting pulse)

26 DISP Out Display command signal

27 VM In LCD display voltage (Intermediate voltage of the segment

30 H4 Out LCD common signals (backplate)

41 Sl4 Out Remote signal to the MT.

42 Sl3 Out Busy signal to the printer.

43 Sl2 Out Expansion signal

54 Sl Out For symbol display (SHIFT, DGE, RAD, GRAD, RESERVE,

55 Kil In CPU I Busy signal (High during the execution in CPU I)

56 K.i2 In Expansion signal

57 K.i3 In Printer Busy signal

58 K.i4 In Printer connection identifying signal.

59 l~5 In Cassette reproduct signal.

60 K.i6 In ON key input signal

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Contents of program or reserve program

Recording format of program or reserve program

Data memory recording format

1 = Check sun code (after every 8 steps or one data memory.)

DATA" i " 4KHz

., ~ F<"---+ To CE121 cassette rnodulation circuit

Schmitt circuit Amplifier circuit

~Startup of the cassette operation ~ Termination of the cassette operation

~ 585~ ~~ ~ ~~<~<AB~ bM 535~* *~~~~~ <~AS~