UNIT 1:

Microprocessors and microcontroller.

Introduction, Microprocessors and Microcontrollers, RISC &
CISC CPU Architectures, Harvard & Von- Neumann CPU
architecture, Computer software.
The 8051 Architecture: Introduction, Architecture of 8051,
Pin diagram of 8051, Memory organization, External Memory
interfacing, Stacks. 6 Hrs
 Introduction
• Computer: A multipurpose programmable machine.
• Microprocessor
What is a microcontroller?
• It is a small chip used for processing
information
• The microcontroller has a CPU, memory,
timers, input and output ports on a single
chip
• Microcontrollers are mainly used for
specific purposes.
• Inside a Microcontroller
 Uses of microcontroller
• Cell phones
• Remote Controls
• Camera
• Washing Machine
• Microwave oven
• Printers
• Fax machines
• TV etc.
 History of Microcontrollers
• Intel produced its first microprocessor the 4-
bit 4004 in 1971.
• Then came the 8-bit processor 8008. A little
change in core and features was brought out
in 8008.
• Using this core, Intel produced the first
microcontroller 8048. It’s successor in 1980
was the 8051, which was perfected and
resulted in a huge success.
 Other Microcontrollers
• Major 8-bit microcontrollers that followed
Intel were
Freescale -6811
Zilog-Z80
Microchip-PIC
The code of these microcontrollers is not
compatible with Intel’s 8051. Code written for
one will not work for others.
 RISC vs CISC
• RISC- Reduced Instruction Set Computers
• CISC- Complex Instruction Set Computers

CISC RISC
MULT 2:3, 5:2 LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3, A
 CISC RISC

Emphasis on hardware Emphasis on software

Includes multi-clock Single-clock,

complex instructions reduced instruction only

Memory-to-memory: Register to register:

"LOAD" and "STORE" "LOAD" and "STORE"
incorporated in instructions are independent instructions

Small code sizes

large code sizes

Transistors used for storing Spends more transistors

complex instructions on memory registers
 Architecture
• The features of a controller are best learned
by studying the internal hardware design
known as the architecture.
• Vonneumann (Princeton) Architecture
• Harvard Architecture
Introduction to 8051 microcontroller
Made by Intel in 1981

An 8-bit, single-chip microcontroller optimized

for control applications

128 bytes RAM, 4096 bytes (4KB) ROM, 2

timers, 1 serial port, 4 I/O ports

40 pins in a dual in-line package (DIP) layout

 General Physical Features

4KB ROM
128 bytes internal RAM
4 register banks of 8 bytes each (R0-R7)
16 bytes of bit-addressable area
80 bytes of general purpose memory
Four 8-bit I/O ports (P0-P3)
Two 16-bit timers (Timer0 & Timer1)
One serial receiver-transmitter interface
Five interrupt sources (2 external & 3 internal)
One oscillator (generates clock signal)
 Hardware Description
1. Oscillator circuit
2. Program counter (PC)
3. Data pointer (DPTR)
4. Accumulator (“A”) register
5. B register
6. Flags
7. Program status word (PSW)
8. Internal memory (ROM, RAM, additional
memory)
9. Stack & stack pointer (SP)
10. Special function register (SFR)
 Oscillator Circuit
A single machine cycle
consists of 12 crystal pulses !
The heart of the 8051
Produces clock pulses
Synchronize all 8051’s internal operations
 Machine Cycle

 Machine cycle is the basic repetitive process that the

CPU performs once it is powered on. A machine cycle
consists of a fixed number of clock cycles (pulses). It is
different for different kinds of CPU.
 The 8051 family needs 12 clock cycles for a machine
cycle.
 The CPU takes one or more machine cycles to complete
an instruction. More complex instructions require
more number of machine cycles to complete the
instruction. The number of machine cycles of the 8051
instructions are ranging from 1 to 4.
• Find the elapse time of the machine cycle for:
XTAL = 11.0592 MHz
XTAL = 16 MHz
XTAL = 20 MHz

Solution:
(a)11.0592 MHz / 12 = 921.6 kHz
Machine cycle = 1 / 921.6 kHz = 1.085 s
(b)16 MHz / 12 = 1.333 MHz
Machine cycle = 1 / 1.333 MHz = 0.75 s
(c)20 MHz / 12 = 1.667 MHz
Machine cycle = 1 / 1.667 MHz = 0.60 s
Program Counter (PC)
PC is a 16-bit register
PC is the only register that does not have an internal
address
Holds the address of the memory location to fetch the
program instruction
Program ROM may be on the chip at addresses 0000H to
0FFFH (4Kbytes), external to the chip for addresses that
exceed 0FFFH
Program ROM may be totally external for all addresses
from 0000H to FFFFH
PC is automatically incremented (+1) after every
instruction byte is fetched
• Find the elapse time of the machine cycle for:
XTAL = 11.0592 MHz
XTAL = 16 MHz
XTAL = 20 MHz

Solution:
(a)11.0592 MHz / 12 = 921.6 kHz
Machine cycle = 1 / 921.6 kHz = 1.085 s
(b)16 MHz / 12 = 1.333 MHz
Machine cycle = 1 / 1.333 MHz = 0.75 s
(c)20 MHz / 12 = 1.667 MHz
Machine cycle = 1 / 1.667 MHz = 0.60 s
Data Pointer (DPTR)
DPTR is a 16-bit register
DPTR is made up of two 8-bit registers: DPH and DPL
DPTR holds the memory addresses for internal and
external code access and external data access
(eg. MOVC A,@A+DPTR MOVX A,@DPTR MOVX @DPTR,A )
DPTR is under the control of program instructions and can
be specified by its 16-bit name, or by each individual byte
name, DPH and DPL
DPTR does not have a single internal address; DPH and
DPL are each assigned an address (83H and 82H)
Accumulator (A Register)

Most versatile CPU register and is used for many

operations, including addition, integer multiplication
and division, and Boolean bit manipulations
A register is also used for all data transfer between
the 8051 and any external memory
B Register

B register is used with the A register for

multiplication and division operations
(eg. MUL AB DIV AB)
No other special function other than as a location
where data may be stored
Flags
Flags are 1-bit registers provided to store the results of
certain program instructions
Other instructions can test the condition of the flags
and make decisions based on the flag states
Flags are grouped inside the program status word
(PSW) and the power control (PCON) registers for
convenient addressing
Math flags(conditional flags): respond automatically to
the outcomes of math operations (CY, AC, OV, P)
User flags: general-purpose flags that may be used by
the programmer to record some event in the program
(F0, GF0, GF1)
Program Status Word (PSW)

PSW contains the math flags, user program flag F0,

and the register select bits (RS1, RS0) that identify
which of the four general-purpose register banks is
currently in use by the program

7 6 5 4 3 2 1 0
CY AC F0 RS1 RS0 OV -- P
Program Status Word (PSW)
Bit Symbol Function
7 CY Carry Flag; used in arithmetic, JUMP, ROTATE,
and BOOLEAN instruction
6 AC Auxiliary carry flag; used for BCD arithmetic
5 F0 User flag 0
4 RS1 Register bank select bit 1
3 RS0 Register bank select bit 0
2 OV Overflow flag; used in arithmetic instructions
1 -- Reserved for future use
0 P Parity flag; shows parity of register A: 1 = Odd
Parity
Instruction that Affect Flag Bits
Instruction CY OV AC Instruction CY OV AC
ADD X X X SETB C 1
ADDC X X X CLR C 0
SUBB X X X CPL C X
MUL 0 X ANL C, bit X
DIV 0 X ANL C, /bit X
DA X ORL C, bit X
RRC X ORL C, /bit X
RLC X CJNE X
MOV C, bit X Note: X can be 0 or 1
Internal Memory
A functioning computer must have memory for program
code bytes, commonly in ROM, and RAM memory for
variable data that can be altered as the program runs
8051 has internal RAM (128 bytes) and ROM (4Kbytes)
8051 uses the same address but in different memories for
code and data
Internal circuitry access the correct memory based on the
nature of the operation in progress
Can add memory externally if needed
8051 Internal RAM Organisation
1F R7
1E R6 7F
1D R5
Bank 3

1C R4
1B R3
1A R2
19 R1
18 R0
17 R7
16 R6
15 R5
Bank 2

14 R4
13 R3
12 R2
11 R1
10 R0
0F R7 2F 7F 78
0E R6 2E 77 70
Bank 1

0D R5 2D 6F 68
0C R4 2C 67 60
0B R3 2B 5F 58
0A R2 2A 57 50
09 R1 29 4F 48
08 R0 28 47 40
07 R7 27 3F 38
06 R6 26 37 30
05 R5 25 2F 28
Bank 0

04 R4 24 27 20
03 R3 23 1F 18
02 R2 22 17 10
01 R1 21 0F 08
00 R0 20 07 00 30

Working Registers Bit Addressable General Purpose

Program Status Word (PSW)
Bank Select Bits, RS1, & RS0 to select 1 of 4 register bank

PSW
State the contents of RAM locations after the following program:
SETB PSW.4
MOV R0, #99H
MOV R1, #85H
MOV R2, #3FH
MOV R7, #63H
MOV R5, #12H

7 6 5 4 3 2 1 0

CY AC F0 RS1 RS0 OV -- P

PSW 1 0
• By default, PSW.3=0 and PSW.4=0; therefore, the
instruction “SETB PSW.4” sets RS1=1 and RS0=0,
thereby selecting register bank 2. Register bank 2
uses RAM locations 10H – 17H. After the
execution of the above program we have the
following
• RAM location 10 has value 99H
• RAM location 11 has value 85H
• RAM location 12 has value 3FH
• RAM location 17 has value 63H
• RAM location 15 has value 12H
Stack and Stack Pointer (SP)
SP is a 8-bit register used to hold an internal RAM
address that is called the “top of the stack”
Stack refers to an area of internal RAM that is
used in conjunction with certain opcodes to store
and retrieve data quickly
SP holds the internal RAM address where the last
byte of data was stored by a stack operation
When data is to be placed on the stack, the SP
increments before storing data on the stack so
that the stack grows up as data is stored
As data is retrieved from the stack, the byte is read
from the stack, and then the SP decrements to
point to the next available byte of stored data
SP = 07H after reset
Show the stack and stack pointer for the following.

MOV SP, #5FH

MOV R2, #25H
MOV R1, #12H
MOV R4, #0F3H
PUSH R2
PUSH R1
PUSH R4
Special Function Registers (SFR)
8051 has 21 SFRs which occupy the addresses from 80H to FFH (128bytes)
Not all of the addresses from 80H to FFH are used for SFRs
Attempt to use the “empty” addresses may get unpredictable result
8051 PIN Diagram
Accessing external RAM
Accessing external ROM
Timing Diagram of Accessing External RAM and ROM
 Computer Software
• Machine level
• Assembly level
• High level