Datasheet

R9A02G021 R01DS0422EJ0110
Rev.1.10
32-Bit MCU based on RISC-V Feb 29, 2024
Ultra low power 48 MHz Renesas RISC-V core with 128-KB code flash memory, 16 KB SRAM, 12-bit A/D Converter, and
Safety features.

Features
■ RISC-V Core – 32-pin HWQFN (5 mm × 5 mm, 0.5 mm pitch)
● Renesas RISC-V instruction-set architecture (RV32I [MACB]) – 24-pin HWQFN (4 mm × 4 mm, 0.5 mm pitch)
● Maximum operating frequency: 48 MHz – 16-pin WLCSP(1.99 mm × 1.99 mm, 0.4 mm pitch)
● Debug and Trace: RISC-V External Debug Support
● Debug Port: cJTAG

■ Memory
● 128-KB code flash memory
● 4 KB data flash
● 16 KB SRAM
● 128-bit unique ID

■ Connectivity
● Serial Array Unit (SAU) × 2
– Simplified SPI × 6
– UART × 3
– Simplified I2C × 6
● I2C Bus Interface (IICA) × 2
● Serial Interface UARTA (UARTA) × 2
● Remote Control Signal Receiver (REMC)

■ Analog
● 12-bit A/D Converter (ADC12)
● Comparator (CMP) × 2
● 8-bit D/A Converter (DAC8) × 2
● Temperature Sensor (TSN)

■ Timers
● Watchdog Timer (WDT)
● Realtime Clock (RTC)
● Timer Array Unit (TAU) × 8
● 32-bit Interval Timer (TML32)

■ Safety
● SRAM parity and ECC error check
● Flash area protection
● ADC test function
● Clock Frequency Accuracy Measurement Circuit (CAC)
● Cyclic Redundancy Check (CRC) calculator
● Data Operation Circuit (DOC)
● Independent Watchdog Timer (IWDT)
● GPIO readback level detection
● Register write protection
● Illegal memory access detection
● True Random Number Generator (TRNG)

■ System and Power Management

● Low power modes
● Event Link Controller (ELC)
● Data Transfer Controller (DTC)
● Key Interrupt Function (KINT)
● Power-on reset
● Low Voltage Detection (LVD) with voltage settings

■ Multiple Clock Sources

● External clock input (EXTAL) (1 to 20 MHz)
● Sub-clock oscillator (SOSC) (32.768 kHz)
● High-speed on-chip oscillator (HOCO) (24/32/48 MHz)
● Middle-speed on-chip oscillator (MOCO) (8 MHz)
● Low-speed on-chip oscillator (LOCO) (32.768 kHz)
● Clock trim function for HOCO/MOCO/LOCO
● IWDT-dedicated on-chip oscillator (15 kHz)
● Clock out support

■ Up to 42 pins for general I/O ports

● Open drain, input pull-up

■ Operating Voltage
● VCC: 1.6 to 5.5 V

■ Operating Temperature and Packages

● Ta = -40℃ to +125℃
– 48-pin HWQFN (7 mm × 7 mm, 0.5 mm pitch)

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R9A02G021 Datasheet 1. Overview

1. Overview
The MCU in this series incorporates an energy-efficient Renesas RISC-V 32-bit core, that is particularly well suited for
cost-sensitive and low-power applications, with the following features:
● 128-KB code flash memory
● 4 KB data flash
● 16 KB SRAM
● 12-bit A/D Converter (ADC12)
● Analog peripherals

1.1 Function Outline

Table 1.1 RISC-V core
Feature Functional description

RISC-V core ● Maximum operating frequency: up to 48 MHz

● Instruction-set architecture (ISA)
– RISC-V RV32I base integer instruction set
– RISC-V C standard extension for compressed instructions
– RISC-V M standard extension for integer multiplication and division
– RISC-V A standard extension for atomic instructions
– RISC-V Ziscr, Control and Status Register (CSR) instructions
– RISC-V Zifencei Instruction-Fetch Fence
– RISC-V B standard extension for bit manipulation (Zba, Zbb, Zbs)
– Performance monitors, cycle and instruction count Control and Status Registers
(CSRs)
● Dynamic branch prediction
● Privilege mode: Machine mode
● Machine timer
● RISC-V external debug support
– Debug module (DM)
• 4 hardware breakpoint/watchpoint registers
– Debug transport module (DTM)
– Debug port: cJTAG

Table 1.2 Memory

Feature Functional description

Code flash memory 128-KB of code flash memory.

Data flash memory 4-KB of data flash memory
Option-setting memory The option-setting memory determines the state of the MCU after a reset.
SRAM 16-KB On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC).

Table 1.3 System (1 of 2)

Feature Functional description

Operating modes Two operating modes:

● Single-chip mode
● UART (SAU) boot mode
Resets The MCU provides 12 resets (RES pin reset, power-on reset, independent watchdog timer reset,
watchdog timer reset, voltage monitor 0/1/2 resets, SRAM parity error reset, SRAM ECC error
reset, bus error reset, debug reset, software reset).
Low Voltage Detection (LVD) The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin. The
detection level can be selected by register settings. The LVD module consists of three separate
voltage level detectors (LVD0, LVD1, LVD2). LVD0, LVD1, and LVD2 measure the voltage level
input to the VCC pin. LVD registers allow your application to configure detection of VCC changes
at various voltage thresholds.

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Table 1.3 System (2 of 2)

Feature Functional description

Clocks ● External clock input (EXTAL)

● Sub-clock oscillator (SOSC)
● High-speed on-chip oscillator (HOCO)
● Middle-speed on-chip oscillator (MOCO)
● Low-speed on-chip oscillator (LOCO)
● IWDT-dedicated on-chip oscillator
● Clock out support
Clock Frequency Accuracy The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to
Measurement Circuit (CAC) be measured (measurement target clock) within the time generated by the clock selected
as the measurement reference (measurement reference clock), and determines the accuracy
depending on whether the number of pulses is within the allowable range. When measurement
is complete or the number of pulses within the time generated by the measurement reference
clock is not within the allowable range, an interrupt request is generated.
Interrupt Controller Unit (ICU) The Interrupt Controller Unit (ICU) controls which event signals are linked to the Core-Local
Interrupt Controller (CLIC), and the Data Transfer Controller (DTC) modules. The ICU also
controls non-maskable interrupts.
Key Interrupt Function (KINT) The key interrupt function (KINT) generates the key interrupt by detecting rising or falling edge
on the key interrupt input pins.
Low power modes Power consumption can be reduced in multiple ways, including setting clock dividers, stopping
modules, selecting power control mode in normal operation, and transitioning to low power
modes.
Register write protection The register write protection function protects important registers from being overwritten due to
software errors. The registers to be protected are set with the Protect Register (PRCR).
Watchdog Timer (WDT) The Watchdog Timer (WDT) is a 14-bit down counter that can be used to reset the MCU when
the counter underflows because the system has run out of control and is unable to refresh the
WDT. In addition, the WDT can be used to generate a non-maskable interrupt or an underflow
interrupt.
Independent Watchdog Timer (IWDT) The Independent Watchdog Timer (IWDT) consists of a 14-bit down counter that must be
serviced periodically to prevent counter underflow. The IWDT provides functionality to reset
the MCU or to generate a non-maskable interrupt or an underflow interrupt. Because the timer
operates with an independent, dedicated clock source, it is particularly useful in returning the
MCU to a known state as a fail-safe mechanism when the system runs out of control. The IWDT
can be triggered automatically by a reset, underflow, refresh error, or a refresh of the count value
in the registers.

Table 1.4 Event link

Feature Functional description

Event Link Controller (ELC) The Event Link Controller (ELC) uses the event requests generated by various peripheral
modules as source signals to connect them to different modules, allowing direct link between
the modules without CPU intervention.

Table 1.5 Direct memory access

Feature Functional description

Data Transfer Controller (DTC) A Data Transfer Controller (DTC) module is provided for transferring data when activated by an
interrupt request.

Table 1.6 Timers (1 of 2)

Feature Functional description

Realtime Clock (RTC) The realtime clock has the following features:
● Capable of counting years, months, days of the week, dates, hours, minutes, and seconds,
for up to 99 years
● Fixed-cycle interrupt (with period selectable from among 0.5 of a second, 1 second, 1
minute, 1 hour, 1 day, or 1 month)
● Alarm interrupt (alarm set by day of week, hour, and minute)
● Pin output function of 1 Hz

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Table 1.6 Timers (2 of 2)

Feature Functional description

Timer Array Unit (TAU) The timer array unit has eight 16-bit timers.
Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two
or more channels can be used to create a high-accuracy timer.
32-bit Interval Timer (TML32) The 32-bit interval timer is made up of four 8-bit interval timers (reference as channels 0 to 3).
Each is capable of operating independently and in that case, they all have the same functions.
Two 8-bit interval timer channels can be connected to operate as a 16-bit interval timer. Four
8-bit interval timer channels can be connected to operate as a 32-bit interval timer.

Table 1.7 Communication interfaces

Feature Functional description

Serial Array Unit (SAU) A single serial array unit has up to four serial channels. Each channel can achieve 3-wire serial
(simplified SPI), UART, and simplified I2C communication.

I2C Bus Interface (IICA) The I2C bus interface has the following three modes:
● Operation stop mode
● I2C bus mode (multi-master supported)
● Wakeup mode
Serial Interface UARTA (UARTA) The serial interface UARTA supports the following two modes:
● Operation stop mode
● UART mode
Remote Control Signal Receiver The remote control signal receiver can receive data by checking the width and period of an
(REMC) external pulse input signal.

Table 1.8 Analog

Feature Functional description

12-bit A/D Converter (ADC12) A 12-bit successive approximation A/D converter is provided. Up to 10 analog input channels
are selectable. Temperature sensor output and internal reference voltage are selectable for
conversion.
Comparator (CMP) The Comparator (CMP) compares a test voltage with a reference voltage and provides a digital
output based on the comparison result. The test voltages can be provided to the comparator
from an external. The reference voltages can be provided to the comparator from internal
DAC8 output and an external source. Such flexibility is useful in applications that require go/no-
go comparisons to be performed between analog signals without necessarily requiring A/D
conversion.
8-bit D/A Converter (DAC8) Two channels of 8-bit D/A Converter (DAC8) can be used as comparator reference voltage and
can be output externally.
Temperature Sensor (TSN) The on-chip Temperature Sensor (TSN) determines and monitors the die temperature for
reliable operation of the device. The sensor outputs a voltage directly proportional to the die
temperature, and the relationship between the die temperature and the output voltage is fairly
linear. The output voltage is provided to the ADC12 for conversion and can be further used by
the end application.

Table 1.9 Data processing

Feature Functional description

Cyclic Redundancy Check (CRC) The Cyclic Redundancy Check (CRC) generates CRC codes to detect errors in the data. The
calculator bit order of CRC calculation results can be switched for LSB-first or MSB-first communication.
Additionally, various CRC-generation polynomials are available. The snoop function allows to
monitor the access to specific addresses. This function is useful in applications that require CRC
code to be generated automatically in certain events, such as monitoring writes to the serial
transmit buffer and reads from the serial receive buffer.
Data Operation Circuit (DOC) The data operation circuit (DOC) is used to compare, add, and subtract 16 or 32-bit data. An
interrupt can be generated when the following conditions apply:
● When the 16 or 32-bit compared values match the detection condition
● When the result of 16 or 32-bit data addition overflows
● When the result of 16 or 32-bit data subtraction underflows
True Random Number Generator The true random number generator generates 32-bit random number seeds (which are true
(TRNG) random numbers).

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1.2 Block Diagram

Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the
features.

Memory Renesas RISC-V core System

128 KB code flash CLIC POR/LVD Clocks

EXTAL/SOSC
4 KB data flash
Machine timer Reset
(H/M/L) OCO
16 KB SRAM

Test and DBG interface Mode control

Power control CAC

DMA
Register write
ICU
protection
DTC

KINT

Timers Communication interfaces Data processing Analog

WDT/IWDT SAU × 2 UARTA × 2 CRC ADC12

RTC IICA × 2 REMC DOC DAC8 × 2

TAU × 8 TRNG TSN

TML32 Event link CMP × 2

ELC

Note: Not available on all parts

Figure 1.1 Block diagram

1.3 Part Numbering

Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.10 shows a
list of products.

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R9A02G021 4 CNK #AA0

Production identification code

Packaging, Terminal material (Pb-free)

[HWQFN]
＃AA：Tray/Sn (Tin) only
＃BA：Tray, full carton/Sn (Tin) only
＃UA：Tray, bulk/Sn (Tin) only
[WLCSP]
＃HC：Embossed Tape/others

Package Type
NK: HWQFN 24 pins 0.5 mm pitch
NH: HWQFN 32 pins 0.5 mm pitch
NE: HWQFN 48 pins 0.5 mm pitch
BY: WLCSP 16 pins 0.4 mm pitch

Quality ID
C: Industrial applications

Operating Temperature
4: -40°C to +125°C
Product No.

Process Generation No.

Device Type
A: Single Chip
RENESAS SOC unit

RENESAS

Figure 1.2 Part numbering scheme

Table 1.10 Product list

Operating
Product part number Package code Code flash Data flash SRAM temperature

R9A02G0214CNE PWQN0048KC-A 128 KB 4 KB 16 KB -40 to +125°C

R9A02G0214CNH PWQN0032KE-A
R9A02G0214CNK PWQN0024KG-A
R9A02G0214CBY SUBG0016LC-A

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1.4 Function Comparison

Table 1.11 Function comparison

R9A02G0214CNH

R9A02G0214CNK
R9A02G0214CNE

R9A02G0214CBY
Part number

Pin count 48 32 24 16
Package HWQFN HWQFN HWQFN WLCSP
Code flash memory 128 KB 128 KB 128 KB 128 KB
Data flash memory 4 KB 4 KB 4 KB 4 KB
SRAM (Parity) 12 KB 12 KB 12 KB 12 KB
SRAM (ECC) 4 KB 4 KB 4 KB 4 KB
System CPU clock 48 MHz 48 MHz 48 MHz 48 MHz
Sub-clock Yes Yes Yes No
oscillator
ICU Yes Yes Yes Yes
CAC Yes Yes Yes Yes
KINT 6 2 No No
ELC control ELC Yes Yes Yes Yes
DMA DTC Yes Yes Yes Yes
Timers WDT/IWDT Yes Yes Yes Yes
RTC Yes Yes Yes Yes
TAU 8 8 8 6
TML32 Yes Yes Yes Yes
Communication SAU 6 (Simplified SPI) 3 (Simplified SPI) 3 (Simplified SPI) 1 (Simplified SPI)
3 (UART) 3 (UART) 3 (UART) 2 (UART)

6 (Simplified I2C) 3 (Simplified I2C) 3 (Simplified I2C) 1 (Simplified I2C)

IICA 2 1 1 1
UARTA 2 No No No
REMC Yes Yes No No
Analog ADC12 10 8 6 4
CMP 2 2 2 1
DAC8 2 2 2 2
TSN Yes Yes Yes Yes
Data processing CRC Yes Yes Yes Yes
DOC Yes Yes Yes Yes
TRNG Yes Yes Yes Yes
I/O port General-purpose 42 26 18 12
I/O
Output current 3 3 3 3
control port

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1.5 Pin Functions

Table 1.12 Pin functions (1 of 2)
Function Signal I/O Description

Power supply VCC Input Power supply pin. Connect it to the system power supply. Connect
this pin to VSS by a 0.1-µF capacitor. Place the capacitor close to
the pin.
VCL I/O Connect this pin to the VSS pin by the smoothing capacitor used to
stabilize the internal power supply. Place the capacitor close to the
pin.
VSS Input Ground pin. Connect it to the system power supply (0 V).
Clock EXTAL Input An external clock signal can be input
XT1 Input Input/output pins for the sub-clock oscillator
Connect a crystal resonator between XT1 and XT2
XT2 Output
CLKOUT Output Clock output pin
Operating mode control MD Input Pin for setting the operating mode. The signal level on this pin must
not be changed during operation mode transition on release from
the reset state.
System control RES Input Reset signal input pin. The MCU enters the reset state when this
signal goes low.
CAC CACREF Input Measurement reference clock input pin
On-chip debug TMSC I/O On-chip emulator pins
TCKC Input
Interrupt NMI Input Non-maskable interrupt request pin
IRQ0 to IRQ7 Input Maskable interrupt request pins
KINT KR00 to KR05 Input A key interrupt can be generated by inputting a falling edge to the
key interrupt input pins
RTC RTC1HZ Output Realtime clock correction clock (1 Hz) output
TAU TI00 to TI07 Input The pins for inputting an external count clock/capture trigger to 16-
bit timers 00 to 07
TO00 to TO07 Output Timer output pins of 16-bit timers 00 to 07
SAU RxD0 to RxD2 Input Serial data input pins of serial interfaces UART0, UART1, and
UART2
TxD0 to TxD2 Output Serial data output pins of serial interfaces UART0, UART1, and
UART2
SCK00, SCK01, SCK10, I/O Serial clock I/O pins of serial interfaces SPI00, SPI01, SPI10, SPI11,
SCK11,SCK20, SCK21 SPI20, and SPI21
SCL00, SCL01, SCL10, Output Serial clock output pins of serial interfaces IIC00, IIC01, IIC10,
SCL11, SCL20, SCL21 IIC11, IIC20, and IIC21
SDA00, SDA01, SDA10, I/O Serial data I/O pins of serial interfaces IIC00, IIC01, IIC10, IIC11,
SDA11, SDA20, SDA21 IIC20, and IIC21
SI00, SI01, SI10, SI11, Input Serial data input pins of serial interfaces SPI00, SPI01, SPI10,
SI20, SI21 SPI11, SPI20, and SPI21
SO00, SO01, SO10, Output Serial data output pins of serial interfaces SPI00, SPI01, SPI10,
SO11, SO20, SO21 SPI11, SPI20, and SPI21
IICA SCLA0, SCLA1 I/O Clock I/O pins of I2C bus interfaces IICA0 and IICA1
SDAA0, SDAA1 I/O Serial data I/O pins of I2C bus interfaces IICA0 and IICA1
UARTA RxDA0, RxDA1 Input Serial data input pins of serial interfaces UARTA0 and UARTA1
TxDA0, TxDA1 Output Serial data output pins of serial interfaces UARTA0 and UARTA1
CLKA0, CLKA1 Output Clock output pins of serial interfaces UARTA0 and UARTA1

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Table 1.12 Pin functions (2 of 2)

Function Signal I/O Description

REMC RIN0 Input External pulse signal input pin for the remote control signal reception
circuit
Analog power supply AVREFP Input Analog reference voltage supply pin for the ADC12. Connect this pin
to VCC when not using the ADC12.
AVREFM Input Analog reference ground pin for the ADC12. Connect this pin to VSS
when not using the ADC12.
ADC12 ANI0 to ANI5, ANI16 to Input Input pins for the analog signals to be processed by the ADC12.
ANI19
CMP IVREF0, IVREF1 Input Reference voltage input pins for comparator
IVCMP0, IVCMP1 Input Analog voltage input pins for comparator
VCOUT0, VCOUT1 Output Comparator detection result output pins.
DAC8 DACOUT0, DACOUT1 Output Output pins for the analog signals to be processed by the DAC8.
I/O ports P000 to P003 , P006 to I/O General-purpose input/output pins
P011
P100 to P111 I/O General-purpose input/output pins
P200 Input General-purpose input pin
P201 to P207 I/O General-purpose input/output pins
P300 to P307 I/O General-purpose input/output pins
P400 to P403 I/O General-purpose input/output pins

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1.6 Pin Assignments

Figure 1.3 to Figure 1.6 show the pin assignments from the top view.

P105/ANI18
P104
P008
P009
P010

P103
P102

P101
P100
P011

P110
P111
36
35
34
33

32
31
30
29
28
27
26
25
P106/ANI19/IVCMP0 37 24 P109
P107/IVCMP1 38 23 P108
P403 39 22 P306
P402 40 21 P207
P001/ANI17/DACOUT1 41 20 P305
P000/ANI16/DACOUT0/IVREF0 42 19 P304
P007/ANI5 43 18 P303
P006/ANI4 44 17 P302
P401/ANI3 45 16 P301/TMSC
P400/ANI2 46 15 P300/EXTAL/TCKC
AVREFM/P003/ANI1 47 14 RES
AVREFP/P002/ANI0 48 13 MD/P203
10
11
12
1
2
3
4

5
6
7
8
9
VCL
XT2
XT1
VSS
VCC
NMI/P200
P201
P202
P204
P205
P206
P307

Figure 1.3 Pin assignment for HWQFN 48-pin (top view)

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P105/ANI18

P104

P102

P101

P100
P103

P110
P111
23

21
24

20
22

19

18

17
P106/ANI19/IVCMP0 25 16 P109

P107/IVCMP1 26 15 P108

P001/ANI17/DACOUT1 27 14 P303

P000/ANI16/DACOUT0/IVREF0 28 13 P302

12 P301/TMSC
P007/ANI5 29

11 P300/EXTAL/TCKC
P006/ANI4 30

10 RES
AVREFM/P003/ANI1 31

9 MD/P203
AVREFP/P002/ANI0 32
1

5
2

8
VCC
XT1
VCL

VSS
XT2

NMI/P200

P201

P202

Figure 1.4 Pin assignment for HWQFN 32-pin (top view)

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P105/ANI18

P104

P103

P102

P101

P100
18

15

14
17

13
16
P106/ANI19/IVCMP0 19 12 P303

P107/IVCMP1 20 11 P302

P001/ANI17/DACOUT1 21 10 P301/TMSC

P000/ANI16/DACOUT0/IVREF0 22 9 P300/EXTAL/TCKC

AVREFM/P003/ANI1 23 8 RES

AVREFP/P002/ANI0 24 7 MD/P203
2

6
1

NMI/P200
VCL

XT2

XT1

VSS

VCC

Figure 1.5 Pin assignment for HWQFN 24-pin (top view)

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A B C D

P107/ P000/ P003/

4 IVCMP1/ ANI16/ AVREFM/ VCL 4
CACREF DACOUT0 ANI1

P001/ P002/
3 P100 ANI17/ AVREFP/ VSS 3
DACOUT1 ANI0

P301/
2 P302 P200/NMI VCC 2
TMSC

P300/ RES
1 P303 P203/MD 1
EXTAL/TCKC

A B C D

Figure 1.6 Pin assignment for WLCSP 16-pin (top view, pad side down)

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1.7 Pin Lists

Table 1.13 Pin list (1 of 2)

Pin number Timers Communication interfaces Analogs

REMC, IICA, UARTA

ADC12, DAC8, CMP

Power, System,

Interrupt, KINT
WLCSP 16-pin

Clock, Debug,
QFN 48-pin

QFN 32-pin

QFN 24-pin

TAU, RTC
I/O ports
CAC

SAU
1 1 1 D4 VCL — — — — — —

2 2 2 — XT2 — — — — — —

3 3 3 — XT1 — — — — — —

4 4 4 D3 VSS/AVSS — — — — — —

5 5 5 D2 VCC/AVCC — — — — — —

6 6 6 C2 NMI P200 — — — — NMI

7 7 — — — P201 — — — — IRQ3_C

8 8 — — CLKOUT_B P202 — RIN0 — — IRQ2_C

9 — — — — P204 — — SCK21/SCL21 — —

10 — — — — P205 — — SI21/SDA21 — —

11 — — — — P206 — — SO21 — —

12 — — — — P307 — — — — —

13 9 7 D1 MD P203 — — — — —

14 10 8 C1 RES# — — — — — —

15 11 9 B1 EXTAL/TCKC P300 TI07_A/TO07_A — SCK00/SCL00 — IRQ0_A

16 12 10 B2 TMSC P301 TI06/TO06 — SI00/SDA00/ — IRQ1_A

RxD0_A

17 13 11 A2 — P302 TI03_B/TO03_B SCLA0_A TxD0_B VCOUT1 IRQ3_B

18 14 12 A1 CLKOUT_A P303 TI04/TO04 SDAA0_A RxD0_B — IRQ2_B

19 — — — — P304 — — SO01 — KR00

20 — — — — P305 — — SI01/SDA01 — KR01

21 — — — — P207 — — SCK01/SCL01 — KR02

22 — — — — P306 — — — — KR03

23 15 — — — P108 — — — — IRQ4_B/KR04

24 16 — — — P109 — — — — IRQ5_B/KR05

25 17 13 A3 — P100 TI05/TO05 — SO00/TxD0_A — IRQ6_C

26 18 14 — — P101 TI02_B/TO02_B — SCK20/SCL20 — IRQ7_C

27 19 — — — P110 — — — — IRQ7_B

28 20 — — — P111 — — — — IRQ6_B

29 21 15 — — P102 TI01/TO01 SCLA0_B SI20/SDA20/ — IRQ2_A

RxD2

30 22 16 — — P103 TI02_A/TO02_A SDAA0_B SO20/TxD2 — —

31 — — — — P011 TI07_B/TO07_B SCLA1/CLKA0 — — —

32 — — — — P010 — SDAA1/RxDA0 — — —

33 — — — — P009 — TxDA0 SCK10/SCL10 — —

34 — — — — P008 — RxDA1 SI10/SDA10 — —

35 23 17 — — P104 — — SCK11/SCL11 IVREF1 —

36 24 18 — — P105 RTC1HZ — SI11/SDA11 ANI18/VCOUT0 —

37 25 19 — — P106 — — SO11 ANI19/IVCMP0 —

38 26 20 A4 CACREF P107 TI03_A/TO03_A — — IVCMP1 —

39 — — — — P403 — TxDA1 SO10 — —

40 — — — — P402 — CLKA1 — — —

41 27 21 B3 — P001 TI00 — TxD1 ANI17/DACOUT1 IRQ5_A

42 28 22 B4 — P000 TO00 — RxD1 ANI16/ IRQ6_A

DACOUT0/
IVREF0*1

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R9A02G021 Datasheet 1. Overview

Table 1.13 Pin list (2 of 2)

Pin number Timers Communication interfaces Analogs

REMC, IICA, UARTA

ADC12, DAC8, CMP

Power, System,

Interrupt, KINT
WLCSP 16-pin

Clock, Debug,
QFN 48-pin

QFN 32-pin

QFN 24-pin

TAU, RTC
I/O ports
CAC

SAU
43 29 — — — P007 — — — ANI5 IRQ3_A

44 30 — — — P006 — — — ANI4 IRQ4_A

45 — — — — P401 — — — ANI3 —

46 — — — — P400 — — — ANI2 —

47 31 23 C4 AVREFM P003 — — — ANI1 IRQ7_A

48 32 24 C3 AVREFP P002 — — — ANI0 —

Note: Several pin names have the added suffix of _A, _B, and _C. The suffix can be ignored when assigning functionality.
Note 1. IVREF0 is not supported in WLCSP 16-pin

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R9A02G021 Datasheet 2. Electrical Characteristics

2. Electrical Characteristics
Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:
VCC = 1.6 to 5.5 V
VSS = 0 V, Ta = Topr
Figure 2.1 shows the timing conditions.

For example, P300

VOH = VCC × 0.7, VOL = VCC × 0.3

VIH = VCC × 0.7, VIL = VCC × 0.3
Load capacitance C = 30 pF

Figure 2.1 Input or output timing measurement conditions

The measurement conditions of the timing specifications for each peripheral are recommended for the best peripheral
operation. However, make sure to adjust driving abilities for each pin to meet the conditions of your system.
Each function pin used for the same function must select the same drive ability. If the I/O drive ability of each function pin
is mixed, the AC characteristics of each function are not guaranteed.

2.1 Absolute Maximum Ratings

Table 2.1 Absolute maximum ratings
Parameter Symbol Value Unit

Power supply voltage VCC -0.5 to +6.5 V

Input voltage Vin -0.3 to VCC + 0.3 V

Analog input voltage VAN -0.3 to VCC + 0.3 V

Operating temperature*1 Topr -40 to +125 °C

Storage temperature Tstg -55 to +140 °C

Note 1. See section 2.2.1. Tj/Ta Definition.

Caution: Permanent damage to the MCU may result if absolute maximum ratings are exceeded.
To preclude any malfunctions due to noise interference, insert capacitors with high frequency
characteristics between the VCC and VSS pins, and between the AVREFP and AVREFM pins when
AVREFP is selected as the high potential reference voltage for the ADC12. Place capacitors of the
following value as close as possible to every power supply pin and use the shortest and heaviest
possible traces:
● VCC and VSS: about 0.1 µF
● AVREFP and AVREFM: about 0.1 µF

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R9A02G021 Datasheet 2. Electrical Characteristics

Also, connect capacitors as stabilization capacitance.

Connect the VCL pin to a VSS pin by a 4.7 µF capacitor. Each capacitor must be placed close to the pin.

Table 2.2 Recommended operating conditions

Parameter Symbol Min Typ Max Unit

Power supply voltages VCC 1.6 — 5.5 V

VSS — 0 — V

2.2 DC Characteristics

2.2.1 Tj/Ta Definition

Table 2.3 DC characteristics
Conditions: Products with operating temperature (Ta) -40 to +105°C
Parameter Symbol Typ Max Unit Test conditions

Permissible junction temperature Tj — 140 °C High-speed mode

Middle-speed mode
Low-speed mode
Subosc-speed mode
Note: Make sure that Tj = Ta + θja × total power consumption (W), where total power consumption = (VCC - VOH) × ΣIOH + VOL × ΣIOL +
ICCmax × VCC.

2.2.2 I/O VIH, VIL

Table 2.4 I/O VIH, VIL
Conditions: VCC = 1.6 to 5.5 V
Test
Parameter Symbol Min Typ Max Unit Conditions

Schmitt trigger input 5V-tolerant ports VIH VCC × 0.7 — 5.8 V —

voltage (P010, P011, P101, P102, P103)
VIL — — VCC × 0.3

RES, NMI VIH VCC × 0.8 — — —

Other peripheral input pins
VIL — — VCC × 0.2 —

2.2.3 I/O IOH, IOL

Table 2.5 I/O IOH, IOL (1 of 2)
Conditions: VCC = 1.6 to 5.5 V
Parameter Symbol Min Typ Max Unit Test conditions

Permissible output current ANI0-5 ports IOH — — -4.0 mA —

(average value per pin) (P002 to P003, P006 to P007,
P400 to P401) IOL — — 8.0 mA

5V-tolerant ports IOH — — -4.0 mA —

(P010 to P011, P101 to P103)
IOL — — 8.0 mA

Other output pins*1 IOH — — -4.0 mA —

IOL — — 20.0 mA

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R9A02G021 Datasheet 2. Electrical Characteristics

Table 2.5 I/O IOH, IOL (2 of 2)

Conditions: VCC = 1.6 to 5.5 V
Parameter Symbol Min Typ Max Unit Test conditions

Permissible output current Total of ANI0-5 ports ΣIOH (max) — — -24.0 mA VCC = 2.7 to 5.5 V
(max value total pins)*1 (P002 to P003, P006 to P007,
P400 to P401) — — -6.0 mA VCC = 1.8 to 2.7 V
— — -3.0 mA VCC = 1.6 to 1.8 V
ΣIOL (max) — — 48.0 mA VCC = 2.7 to 5.5V
— — 3.6 mA VCC = 1.8 to 2.7 V
— — 1.8 mA VCC = 1.6 to 1.8 V
5V-tolerant ports ΣIOH (max) — — -20.0 mA VCC = 2.7 to 5.5V
(P010 to P011, P101 to P103)
— — -5.0 mA VCC = 1.8 to 2.7 V
— — -2.0 mA VCC = 1.6 to 1.8 V
ΣIOL (max) — — 40.0 mA VCC = 2.7 to 5.5 V
— — 3.0 mA VCC = 1.8 to 2.7 V
— — 1.5 mA VCC = 1.6 to 1.8 V
Total of other output ports ΣIOH (max) — — -30.0 mA VCC = 2.7 to 5.5 V
— — -12.0 mA VCC = 1.8 to 2.7 V
— — -6.0 mA VCC = 1.6 to 1.8 V
ΣIOL (max) — — 50.0 mA VCC = 2.7 to 5.5 V
— — 9.0 mA VCC = 1.8 to 2.7 V
— — 4.5 mA VCC = 1.6 to 1.8 V
Total of all output pin ΣIOH (max) — — -50.0 mA —

ΣIOL (max) — — 95.0 mA

Note 1. Specification under conditions where the duty factor ≤ 70%.

The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression
(when changing the duty factor from 70% to n%).
Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOH = −30.0 mA
Total output current of pins = (−30.0 × 0.7)/(80 × 0.01) ≅ −26.2 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.

Caution: To protect the reliability of the MCU, the output current values should not exceed the values in Table 2.5.

2.2.4 I/O VOH, VOL, and Other Characteristics

Table 2.6 I/O VOH, VOL (1)
Conditions: VCC = 4.0 to 5.5 V
Parameter Symbol Min Typ Max Unit Test conditions

Output Output pins*1 VOH VCC - 0.8 — — V IOH = -4.0 mA

voltage
P002 to P003, P006 to P007, P400 to P401 VOL — 0.8 IOL = 8.0 mA

P010 to P011, P101 to P103 VOL — — 0.8 IOL = 8.0 mA

Other output pins*1 VOL — — 1.2 IOL = 20.0 mA

Note 1. Except for Ports P200, which are input ports, and XT1 and XT2, which are SOSC ports.

Table 2.7 I/O VOH, VOL (2)

Conditions: VCC = 2.7 to 4.0 V
Parameter Symbol Min Typ Max Unit Test conditions

Output Output pins*1 VOH VCC - 0.8 — — V IOH = -4.0 mA

voltage
Output pins*1 VOL — — 0.8 IOL = 8.0 mA

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R9A02G021 Datasheet 2. Electrical Characteristics

Note 1. Except for Ports P200, which are input ports, and XT1 and XT2, which are SOSC ports.

Table 2.8 I/O VOH, VOL (3)

Conditions: VCC = 1.6 to 2.7 V
Parameter Symbol Min Typ Max Unit Test Conditions

Output voltage Output pins*1 VOH VCC - 0.5 — — V IOH = -1.0 mA

VCC = 1.8 to 2.7 V
VCC - 0.5 — — IOH = -0.5 mA
VCC = 1.6 to 1.8 V

Output pins*1 VOL — — 0.4 IOL = 0.6 mA

VCC = 1.8 to 2.7 V
— — 0.4 IOL = 0.3 mA
VCC = 1.6 to 1.8 V
Note 1. Except for Ports P200, which are input ports, and XT1 and XT2, which are SOSC ports.

Table 2.9 I/O other characteristics

Conditions: VCC = 1.6 to 5.5 V
Parameter Symbol Min Typ Max Unit Test conditions

Constant low-level P100, P302, P303 CCDIOL 1.15 2 2.87 mA PmnPFS.DSCR

current output*1 = b00, VCC =
4.0 V to 5.5 V
0.97 1.7 2.59 mA PmnPFS.DSCR
= b00, VCC =
2.7 V to 4.0 V
2.95 5 6.97 mA PmnPFS.DSCR
= b01, VCC =
4.0 V to 5.5 V
2.64 4.2 6.38 mA PmnPFS.DSCR
= b01, VCC =
3.0 V to 4.0 V
5.97 10 13.48 mA PmnPFS.DSCR
= b1x, VCC =
4.0 V to 5.5 V
5.6 8.5 12.38 mA PmnPFS.DSCR
= b1x, VCC =
3.3 V to 4.0 V
Input leakage current RES, P200, XT1, XT2 | Iin | — — 1.0 µA Vin = 0 V
Vin = VCC

Three-state leakage 5V-tolerant ports | ITSI | — — 1.0 µA Vin = 0 V

current (off state) (P010 to P011, P101 to P103) Vin = 5.8 V

Other ports — — 1.0 µA Vin = 0 V

(except for P200, XT1, XT2 and Vin = VCC
5V-tolerant ports)
Input pull-up resistor All ports RU 10 20 100 kΩ Vin = 0 V
(except for P200, XT1, XT2)
Input capacitance P200 Cin — — 30 pF Vin = 0 V
f = 1 MHz
Other input pins — — 15
Ta = 25°C

Note 1. The listed currents apply when the output current control function is enabled.

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R9A02G021 Datasheet 2. Electrical Characteristics

2.2.5 Operating and Standby Current

Table 2.10 Operating and standby current (1) (1 of 2)
Conditions *1 *2: VCC = 1.6 to 5.5 V
Test
Parameter Symbol Typ*11 Max Unit Conditions

Supply High- Normal All peripheral clocks ICLK = 48 MHz ICC 7.80 — mA *9 *12
current*3 speed mode disabled, CoreMark
mode*4 code executing from ICLK = 32 MHz 6.45 — *9

flash*7 ICLK = 16 MHz 4.00 —

ICLK = 8 MHz 2.70 —
All peripheral clocks ICLK = 48 MHz — 17.4 *12
enabled, code
executing from flash*7
Sleep All peripheral clocks ICLK = 48 MHz 1.80 — *9
mode disabled*7
ICLK = 32 MHz 1.40 —
ICLK = 16 MHz 1.00 —
ICLK = 8 MHz 0.80 —
All peripheral clocks ICLK = 48 MHz 3.70 — *10
enabled*7
ICLK = 32 MHz 2.60 —
ICLK = 16 MHz 1.65 —
ICLK = 8 MHz 1.10 —

Increase during BGO operation*8 1.95 — —

Middle- Normal All peripheral clocks ICLK = 24 MHz ICC 4.80 — mA *9

speed mode disabled, CoreMark
code executing from ICLK = 4 MHz 1.35 —
mode*4
flash*7
All peripheral clocks ICLK = 24 MHz — 10.1 *10
enabled, code
executing from flash*7
Sleep All peripheral clocks ICLK = 24 MHz 1.20 — *9
mode disabled*7
ICLK = 4 MHz 0.70 —
All peripheral clocks ICLK = 24 MHz 2.20 — *10
enabled*7

Increase during BGO operation*8 2.05 — —

Low- Normal All peripheral clocks ICLK = 1 MHz ICC 0.35 — mA *9

speed mode disabled, CoreMark
mode*5 code executing from
flash*7
All peripheral clocks ICLK = 1 MHz — 2.8 *10
enabled, code
executing from flash*7
Sleep All peripheral clocks ICLK = 1 MHz 0.20 — *9
mode disabled*7
All peripheral clocks ICLK = 1 MHz 0.25 — *10
enabled*7

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R9A02G021 Datasheet 2. Electrical Characteristics

Table 2.10 Operating and standby current (1) (2 of 2)

Conditions *1 *2: VCC = 1.6 to 5.5 V
Test
Parameter Symbol Typ*11 Max Unit Conditions

Supply Subosc- Normal All peripheral clocks ICLK = 32.768 kHz ICC — 1.6 mA *10
current*3 speed mode enabled, code
mode*6 executing from flash*7
Sleep All peripheral clocks ICLK = 32.768 kHz 2.30 — µA *10
mode disabled*7
All peripheral clocks ICLK = 32.768 kHz 3.65 — *10
enabled*7
Note 1. Conditions for high-speed mode are VCC = 1.8 to 5.5 V.
Note 2. Conditions for middle-speed mode are VCC = 1.8 to 5.5 V when ICLK = 24 MHz.
Note 3. Supply current is the total current flowing into VCC, including analog power supply current. Supply current values apply when
internal pull-up MOSs are in the off state and these values do not include output charge/discharge current from any of the pins.
Note 4. The clock source is HOCO.
Note 5. The clock source is MOCO.
Note 6. The clock source is the sub-clock oscillator.
Note 7. This does not include BGO operation.
Note 8. This is the increase for programming or erasure of the flash memory for data storage during program execution.
Note 9. PCLKB is set to be divided by 64.
Note 10. PCLKB is the same frequency as that of ICLK.
Note 11. VCC = 3.3 V.
Note 12. The prefetch is operating.

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R9A02G021 Datasheet 2. Electrical Characteristics

Table 2.11 Operating and standby current (2)

Conditions: VCC = 1.6 to 5.5 V
Parameter Symbol Typ*3 Max Unit Test conditions

Supply Software Peripheral All SRAM Ta = 25°C ICC 0.30 1.8 µA —

current Standby modules stop (0x2000_0000 to
*1 mode*2 0x2000_0FFF and Ta = 55°C 0.45 5.1
0x2000_4000 to
Ta = 85°C 1.15 20
0x2000_6FFF) is on
Ta = 105°C 2.75 48

Ta = 125°C 6.95 112

8KB SRAM Ta = 25°C 0.30 1.8

(0x2000_0000 to
0x2000_0FFF and Ta = 55°C 0.45 4.8
0x2000_4000 to
Ta = 85°C 1.15 19
0x2000_4FFF) is on
Ta = 105°C 2.75 47

Ta = 125°C 6.95 108

Increment for RTC operation with low-speed on-chip*4 0.65 — —

Increment for RTC operation in normal operation 0.23 — SOMCR.SODRV[

mode with sub-clock oscillator*4 1:0] are 11b (Low
power mode 3)
RTCC0.RTC128E
N is 0 (RTC
operation in
normal operation
mode)
0.97 — SOMCR.SODRV[
1:0] are 00b
(normal mode)
RTCC0.RTC128E
N is 0 (RTC
operation in
normal operation
mode)
Increment for RTC operation in low-consumption 0.22 — SOMCR.SODRV[
clock mode with sub-clock oscillator*4 1:0] are 11b (Low
power mode 3)
RTCC0.RTC128E
N is 1 (RTC
operation in low-
consumption
clock mode)
0.95 — SOMCR.SODRV[
1:0] are 00b
(normal mode)
RTCC0.RTC128E
N is 1 (RTC
operation in low-
consumption
clock mode)
Note 1. Supply current is the total current flowing into VCC, including analog power supply current. Supply current values apply when
internal pull-up MOSs are in the off state and these values do not include output charge/discharge current from any of the pins.
Note 2. The IWDT and LVD are not operating.
Note 3. VCC = 3.3 V.
Note 4. Includes the low-speed on-chip oscillator or sub-oscillation circuit current.

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R9A02G021 Datasheet 2. Electrical Characteristics

Table 2.12 Operating and standby current (3)

Conditions *1, *2: VCC = 1.6 to 5.5 V
Parameter Symbol Min Typ Max Unit Test conditions

Analog power During 12-bit A/D conversion (at high-speed IVCCADC — — 1.44 mA —
supply current conversion)
During 12-bit A/D conversion (at low-power — — 0.78 mA —
conversion)
CMP enabled (at high-speed mode, per IVCCCMP — 6.0 — µA —
channel)
CMP enabled (at low-speed mode, per — 2.0 — µA —
channel)

DAC8 enabled (per channel)*1 IVCCDAC — — 0.5 mA —

Reference During 12-bit A/D conversion IREFH — — 0.15 mA —

power supply
current

Temperature Sensor (TSN) operating current*2 ITSN — 0.13 — mA —

12-bit A/D converter internal reference voltage current*2 IADREF — 0.13 — mA —

Output current control operating current CCDE register is ICCDA — 120*3 — µA —

not 0x00
Per single output ICCDP — 30 — Setting of the
current control low-level output
port*4 current: Hi-Z
— 200 — Setting of the
low-level output
current: 2 to 15
mA
Note 1. Conditions for DAC8 use are VCC = 2.7 to 5.5 V
Note 2. Conditions for TSN and internal reference voltage use are VCC = 1.8 to 5.5 V
Note 3. This current is added to the supply current when the output voltage control port is set at CCDIOL typical current CCTRM.IADJ
setting if VCC = 4 V
Note 4. This current does not include the current flowing into the I/O port pins

2.2.6 VCC Rise and Fall Gradient and Ripple Frequency

Table 2.13 Rise and fall gradient characteristics
Conditions: VCC = 0 to 5.5 V
Parameter Symbol Min Typ Max Unit Test conditions

Power-on VCC Voltage monitor 0 reset disabled at startup SrVCC 0.02 — 2 ms/V —
rising gradient
Voltage monitor 0 reset enabled at startup*1 —

Note 1. When OFS1.LVDAS = 0.

Table 2.14 Rising and falling gradient and ripple frequency characteristics
Conditions: VCC = 1.6 to 5.5 V
The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (5.5 V) and lower limit (1.6
V).
When the VCC change exceeds VCC ± 10%, the allowable voltage change rising and falling gradient dt/dVCC must be met.
Parameter Symbol Min Typ Max Unit Test conditions

Allowable ripple frequency fr(VCC) — — 10 kHz Figure 2.2

Vr (VCC) ≤ VCC × 0.2

— — 1 MHz Figure 2.2

Vr (VCC) ≤ VCC × 0.08

— — 10 MHz Figure 2.2

Vr (VCC) ≤ VCC × 0.06

Allowable voltage change rising and dt/dVCC 1.0 — — ms/V When VCC change exceeds VCC ± 10%
falling gradient

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R9A02G021 Datasheet 2. Electrical Characteristics

1 / fr(VCC)

VCC Vr(VCC)

Figure 2.2 Ripple waveform

2.3 AC Characteristics

2.3.1 Frequency
Table 2.15 Operation frequency in high-speed mode
Conditions: VCC = 1.8 to 5.5 V
Parameter Symbol Min Typ Max*3 Unit

Operation System clock (ICLK)*1 *2 1.8 to 5.5 V f 0.032768 — 48 MHz

frequency
Peripheral module clock (PCLKB) 1.8 to 5.5 V — — 48
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for programming or
erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as
1.5 MHz cannot be set.
Note 2. The frequency accuracy of ICLK must be ± 1.5% during programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.
Note 3. The maximum value of operation frequency does not include internal oscillator errors. For details on the range for guaranteed
operation, see Table 2.19.

Table 2.16 Operation frequency in middle-speed mode

Conditions: VCC = 1.6 to 5.5 V
Parameter Symbol Min Typ Max*3 Unit

Operation System clock (ICLK)*1 *2 1.8 to 5.5 V f 0.032768 — 24 MHz

frequency
1.6 to 1.8 V 0.032768 — 4
Peripheral module clock (PCLKB) 1.8 to 5.5 V — — 24
1.6 to 1.8 V — — 4
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for programming or
erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as
1.5 MHz cannot be set.
Note 2. The frequency accuracy of ICLK must be ± 1.5% while programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.
Note 3. The maximum value of operation frequency does not include internal oscillator errors. For details on the range for guaranteed
operation, see Table 2.19.

Table 2.17 Operation frequency in low-speed mode

Conditions: VCC = 1.6 to 5.5 V

Parameter Symbol Min Typ Max*3 Unit

Operation System clock (ICLK)*1 *2 1.6 to 5.5 V f 0.032768 — 1 MHz

frequency
Peripheral module clock (PCLKB) 1.6 to 5.5 V — — 1
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory.
Note 2. The frequency accuracy of ICLK must be ± 1.5% while programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.

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R9A02G021 Datasheet 2. Electrical Characteristics

Note 3. The maximum value of operation frequency does not include internal oscillator errors. For details on the range for guaranteed
operation, see Table 2.19.

Table 2.18 Operation frequency in Subosc-speed mode

Parameter Symbol Min Typ Max Unit

Operation System clock (ICLK)*1 1.6 to 5.5 V f 27.8528 32.768 37.6832 kHz
frequency
Peripheral module clock 1.6 to 5.5 V — — 37.6832
(PCLKB)
Note 1. Programming and erasing the flash memory is not possible.

2.3.2 Clock Timing

Table 2.19 Clock timing
Parameter Symbol Min Typ Max Unit Test conditions

EXTAL external clock input cycle time tXcyc 50 — — ns Figure 2.3

EXTAL external clock input high pulse width tXH 20 — — ns —

EXTAL external clock input low pulse width tXL 20 — — ns —

EXTAL external clock rising time tXr — — 5 ns —

EXTAL external clock falling time tXf — — 5 ns —

EXTAL external clock input wait time*1 tEXWT 0.3 — — µs —

EXTAL external clock input frequency fEXTAL — — 20 MHz 1.8 ≤ VCC ≤ 5.5
— — 4 MHz 1.6 ≤ VCC < 1.8
LOCO clock oscillation frequency fLOCO 27.8528 32.768 37.6832 kHz —

LOCO clock oscillation stabilization time tLOCO — — 100 µs Figure 2.4

IWDT-dedicated clock oscillation frequency fILOCO 12.75 15 17.25 kHz —

MOCO clock oscillation frequency fMOCO 6.8 8 9.2 MHz —

MOCO clock oscillation stabilization time tMOCO — — 1 µs —

HOCO clock oscillation frequency*5 fHOCO24 23.64 24 24.36 MHz Ta = -40 to 125°C
1.6 ≤ VCC ≤ 5.5
fHOCO32 31.52 32 32.48 Ta = -40 to 125°C
1.6 ≤ VCC ≤ 5.5
fHOCO48 47.28 48 48.72 Ta = -40 to 125°C
1.6 ≤ VCC ≤ 5.5

HOCO clock oscillation stabilization time*3 *4 tHOCO24 — 6.7 7.7 µs Figure 2.5
tHOCO32
tHOCO48

Sub-clock oscillator oscillation frequency fSUB — 32.768 — kHz —

Sub-clock oscillation stabilization time*2 tSUBOSC — 0.5 — s Figure 2.6

Note 1. Time until the clock can be used after the external clock input stop bit (MOSCCR.MOSTP) is set to 0 (operating) when the external
clock is stable.
Note 2. After changing the setting of the SOSCCR.SOSTP bit to start sub-clock oscillator operation, only start using the sub-clock oscillator
after the sub-clock oscillation stabilization wait time elapsed. Use the oscillator wait time value recommended by the oscillator
manufacturer.
Note 3. This is a characteristic when the HOCOCR.HCSTP bit is set to 0 (oscillation) in the MOCO stop state. When the HOCOCR.HCSTP
bit is set to 0 (oscillation) during MOCO oscillation, this specification is shortened by 1 µs.
Note 4. Check OSCSF.HOCOSF to confirm whether stabilization time has elapsed.
Note 5. Accuracy at production test.

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R9A02G021 Datasheet 2. Electrical Characteristics

tXcyc
tXH tXL

EXTAL external clock input VCC × 0.5

tXr tXf

Figure 2.3 EXTAL external clock input timing

LOCOCR.LCSTP

tLOCO

LOCO clock oscillator output

Figure 2.4 LOCO clock oscillation start timing

HOCOCR.HCSTP

tHOCOx*1

HOCO clock

Note: x = 24, 32, 48

Figure 2.5 HOCO clock oscillation start timing (started by setting the HOCOCR.HCSTP bit)

SOSCCR.SOSTP

tSUBOSC

Sub-clock oscillator output

Figure 2.6 Sub-clock oscillation start timing

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2.3.3 Reset Timing

Table 2.20 Reset timing
Test
Parameter Symbol Min Typ Max Unit conditions

RES pulse width At power-on tRESWP 10 — — ms Figure 2.7

Not at power-on tRESW 30 — — µs Figure 2.8

Wait time after RES cancellation (at LVD0 enabled*1 tRESWT — 0.9 — ms Figure 2.7
power-on)
LVD0 disabled*2 — 0.2 —

Wait time after RES cancellation (during LVD0 enabled*1 tRESWT2 — 0.9 — ms Figure 2.8
powered-on state)
LVD0 disabled*2 — 0.2 —

Wait time after internal reset LVD0 enabled*1 tRESWT3 — 0.9 — ms Figure 2.9
cancellation (Watchdog timer reset,
SRAM parity error reset, SRAM ECC LVD0 disabled*2 — 0.2 —
error reset, bus error reset, debug
reset, software reset)
Note 1. When OFS1.LVDAS = 0.
Note 2. When OFS1.LVDAS = 1.

VCC

RES

tRESWP

Internal reset

tRESWT

Figure 2.7 Reset input timing at power-on

tRESW

RES

Internal reset

tRESWT2

Figure 2.8 Reset input timing (1)

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Independent watchdog timer reset

Software reset

Internal reset

tRESWT3

Figure 2.9 Reset input timing (2)

2.3.4 Wakeup Time

Table 2.21 Timing of recovery from low power modes (1)
Parameter Symbol Min Typ Max Unit Test conditions

Recovery High- External clock input System tSBYEX — 2.4 3.1 µs Figure 2.10
time from speed clock
Software mode source
Standby is
mode*1 external
clock
input
(20
MHz)
System clock source is HOCO (HOCO tSBYHO — 7.4 9.1 µs
clock is 32 MHz)*2
System clock source is HOCO (HOCO 7.2 8.9 µs
clock is 48 MHz)*3
System clock source is MOCO (8 MHz) tSBYMO — 4 5 µs

Note 1. The division ratio of ICLK and PCLKx is the minimum division ratio within the allowable frequency range. The recovery time is
determined by the system clock source.
Note 2. The system clock is 32 MHz.
Note 3. The system clock is 48 MHz.

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Table 2.22 Timing of recovery from low power modes (2)

Parameter Symbol Min Typ Max Unit Test conditions

Recovery Middle- External clock System clock tSBYEX — 2.4 3.1 µs Figure 2.10
time from speed input source is external
Software mode clock input (20
Standby MHz)
mode*1 VCC = 1.8 V to 5.5
V
System clock — 11.7 13
source is external
clock input (20
MHz)
VCC = 1.6 V to 1.8
V
System clock VCC = 1.8 V to 5.5 tSBYHO — 7.7 9.4 µs
source is V
HOCO*2
VCC = 1.6 V to 1.8 — 15.7 17.9
V
System clock VCC = 1.8 V to 5.5 tSBYMO — 4 5 µs
source is V
MOCO (8
MHz) VCC = 1.6 V to 1.8 — 7.2 9
V
Note 1. The division ratio of ICLK and PCLKx is the minimum division ratio within the allowable frequency range. The recovery time is
determined by the system clock source.
Note 2. The system clock is 24 MHz.

Table 2.23 Timing of recovery from low power modes (3)

Parameter Symbol Min Typ Max Unit Test conditions

Recovery Low- External clock input System tSBYEX — 25 40 µs Figure 2.10

time from speed clock
Software mode source
Standby is
mode*1 external
clock
input (1
MHz)
System clock source is MOCO (1 MHz) tSBYMO — 26 40 µs

Note 1. The division ratio of ICLK and PCLKx is the minimum division ratio within the allowable frequency range. The recovery time is
determined by the system clock source.

Table 2.24 Timing of recovery from low power modes (4)

Test
Parameter Symbol Min Typ Max Unit conditions

Recovery Subosc- System clock tSBYSC — 0.85 1 ms Figure 2.10

time from speed mode source is
Software sub-clock
Standby oscillator
mode*1 (32.768 kHz)
System clock tSBYLO — 0.85 1.2 ms
source is
LOCO
(32.768 kHz)
Note 1. The sub-clock oscillator or LOCO itself continues oscillating in Software Standby mode during Subosc-speed mode.

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R9A02G021 Datasheet 2. Electrical Characteristics

Oscillator

ICLK

IRQ

Software Standby mode

tSBYEX,
tSBYMO, tSBYHO

Oscillator

ICLK

IRQ

Software Standby mode

tSBYSC, tSBYLO

Figure 2.10 Software Standby mode cancellation timing

Table 2.25 Timing of recovery from low power modes (5)

Test
Parameter Symbol Min Typ Max Unit conditions

Recovery time High-speed tSNZ — 6.6 8.1 µs Figure 2.11

from Software mode
Standby mode System clock
to Snooze source is
mode HOCO
Middle-speed tSNZ — 6.7 8.2 µs
mode
System clock
source is
HOCO (24
MHz)
VCC = 1.8 V to
5.5 V
Middle-speed tSNZ — 10.8 12.9 µs
mode
System clock
source is
HOCO (24
MHz)
VCC = 1.6 V to
1.8 V
Low-speed tSNZ — 9.2 16 µs
mode
System clock
source is
MOCO (1 MHz)

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Oscillator

ICLK (except DTC, SRAM)

ICLK (to DTC, SRAM)*1 PCLK

IRQ

Software Standby mode Snooze mode

tSNZ

Note 1. When SNZCR.SNZDTCEN bit is set to 1, ICLK is supplied to DTC and SRAM.

Figure 2.11 Recovery time from Software Standby mode to Snooze mode

2.3.5 NMI and IRQ Noise Filter

Table 2.26 NMI and IRQ noise filter
Parameter Symbol Min Typ Max Unit Test conditions

NMI pulse tNMIW 200 — — ns NMI digital filter disabled tPcyc × 2 ≤ 200 ns
width
tPcyc × 2*1 — — tPcyc × 2 > 200 ns

200 — — NMI digital filter enabled tNMICK × 3 ≤ 200 ns

tNMICK × — — tNMICK × 3 > 200 ns

3.5*2
IRQ pulse tIRQW 200 — — ns IRQ digital filter disabled tPcyc × 2 ≤ 200 ns
width
tPcyc × 2*1 — — tPcyc × 2 > 200 ns

200 — — IRQ digital filter enabled tIRQCK × 3 ≤ 200 ns

tIRQCK × — — tIRQCK × 3 > 200 ns

3.5*3
Note: 200 ns minimum in Software Standby mode.
Note: If the clock source is being switched it is needed to add 4 clock cycle of switched source.
Note 1. tPcyc indicates the PCLKB cycle.
Note 2. tNMICK indicates the cycle of the NMI digital filter sampling clock.
Note 3. tIRQCK indicates the cycle of the IRQi digital filter sampling clock (i = 0 to 7).

NMI

tNMIW

Figure 2.12 NMI interrupt input timing

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IRQ

tIRQW

Figure 2.13 IRQ interrupt input timing

2.3.6 I/O Ports, KINT and ADC12 Trigger Timing

Table 2.27 I/O Ports, KINT and ADC12 trigger timing
Test
Parameter Symbol Min Max Unit*1 conditions

I/O Ports Input data pulse width 1.6 V ≤ VCC ≤ 5.5 V tPRW 2 — tPcyc Figure 2.14

KINT KRn (n = 00 to 05) pulse width tKR 250 — ns Figure 2.15

Note: If the clock source is being switched, add 4 clock cycles to the switched source.
Note 1. tPcyc: PCLKB cycle

Port

tPRW

Figure 2.14 I/O ports input timing

KR00 to KR05

tKR

Figure 2.15 KINT input timing

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2.3.7 TAU Timing

Table 2.28 TAU timing
Conditions: Ta = -40 to +125°C, VCC = 1.6 to 5.5 V
Parameter Symbol Min Typ Max Unit Test conditions

TI00 to TI07 input high-level width tTIH 1/fMCK + 10 — — ns Figure 2.16

TI00 to TI07 input low-level width tTIL — —

TO00 to TO07 output High-speed mode 2.7 V ≤ VCC ≤ 5.5 V fTO — — 24 MHz
frequency
2.4 V ≤ VCC ≤ 2.7 V — — 12
1.8 V ≤ VCC ≤ 2.4 V — — 6
Middle-speed mode 2.7 V ≤ VCC ≤ 5.5 V — — 24
2.4 V ≤ VCC ≤ 2.7 V — — 12
1.8 V ≤ VCC ≤ 2.4 V — — 6
1.6 V ≤ VCC ≤ 1.8 V — — 2
Low-speed mode 1.6 V ≤ VCC ≤ 5.5 V — — 1
Note: fMCK: Timer array unit operating clock frequency.

tTIL tTIH

TI00 to TI07

1/fTO

TO00 to TO07

Figure 2.16 TAU input/output timing

2.3.8 CAC Timing

Table 2.29 CAC timing
Conditions: VCC = 1.6 to 5.5 V
Parameter Symbol Min Typ Max Unit Test conditions

CAC CACREF input pulse tPcyc*1 ≤ tCAC*2 tCACREF 4.5 × tCAC + 3 × tPcyc — — ns —
width
tPcyc*1 > tCAC*2 5 × tCAC + 6.5 × tPcyc — — ns

Note 1. tPcyc: PCLKB cycle.

Note 2. tCAC: CAC count clock source cycle.

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2.3.9 CLKOUT Timing

Table 2.30 CLKOUT timing
Parameter Symbol Min Max Unit Test conditions

CLKOUT CLKOUT pin output cycle*1 2.7 V ≤ VCC ≤ 5.5 V tCcyc 62.5 — ns Figure 2.17
1.8 V ≤ VCC < 2.7 V 125 —
1.6 V ≤ VCC < 1.8 V 250 —
CLKOUT pin high pulse 2.7 V ≤ VCC ≤ 5.5 V tCH 15 — ns
width*2
1.8 V ≤ VCC < 2.7 V 30 —
1.6 V ≤ VCC < 1.8 V 150 —
CLKOUT pin low pulse 2.7 V ≤ VCC ≤ 5.5 V tCL 15 — ns
width*2
1.8 V ≤ VCC < 2.7 V 30 —
1.6 V ≤ VCC < 1.8 V 150 —
CLKOUT pin output rise time 2.7 V ≤ VCC ≤ 5.5 V tCr — 12 ns
1.8 V ≤ VCC < 2.7 V — 25
1.6 V ≤ VCC < 1.8 V — 50
CLKOUT pin output fall time 2.7 V ≤ VCC ≤ 5.5 V tCf — 12 ns
1.8 V ≤ VCC < 2.7 V — 25
1.6 V ≤ VCC < 1.8 V — 50
Note 1. When the EXTAL external clock input is used with division by 1 (the CKOCR.CKOSEL[2:0] bits are 011b and the
CKOCR.CKODIV[2:0] bits are 000b) to output from CLKOUT, specifications in Table 2.30 should be satisfied with 45% to 55%
of input duty cycle.
Note 2. When MOCO is selected as the clock output source (the CKOCR.CKOSEL[2:0] bits are 001b), set the clock output division ratio to
be divided by 2 (the CKOCR.CKODIV[2:0] bits are 001b).

tCcyc

tCH
tCf

CLKOUT

tCr
tCL
Test conditions: VOH = VCC × 0.7, VOL = VCC × 0.3, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF

Figure 2.17 CLKOUT output timing

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2.3.10 Serial Array Unit (SAU)

Table 2.31 UART communication
Conditions: Ta = -40 to +125°C, VCC = 1.6 to 5.5 V, VSS = 0 V
Parameter Symbol High-speed Middle-speed Low-speed Unit Test
mode mode mode conditions
Min. Max. Min. Max. Min. Max.

Transfer rate*1 1.6 V ≤ VCC — — fMCK/6 — fMCK/6 — fMCK/6 bps Figure 2.18
≤ 5.5 V Figure 2.19
Theoretical — 5.3 — 4 — 0.16 Mbps
value of the
maximum
transfer rate
fMCK =
PCLKB*2
Note: Select the CMOS output for the TxDq pin by using NCODR bit in Port gh Pin Function Select Register (PghPFS).
Note: ● q: UART number (q = 0 to 2), gh: Port number (g = 0 to 4, h = 00 to 15)
● fMCK: Serial array unit operation clock frequency
Note 1. The transfer rate in the Snooze mode is within the range from 4800 to 9600 bps.
Note 2. The maximum operating frequencies of PCLKB are as follows:
High-speed mode: 32 MHz (1.8 V ≤ VCC ≤ 5.5 V)
Middle-speed mode: 24 MHz (1.8 V ≤ VCC ≤ 5.5 V), 4 MHz (1.6 V ≤ VCC ≤ 5.5 V)
Low-speed mode: 1 MHz (1.6 V ≤ VCC ≤ 5.5 V)

TxDq Rx

MCU User device

RxDq Tx

Note: q: UART number (q = 0 to 2)

Figure 2.18 Connection in the UART communications

1/Transfer rate
High-/low-bit width
Baud rate error tolerance

TxDq
RxDq

Note: q: UART number (q = 0 to 2)

Figure 2.19 Bit width in the UART communications

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Table 2.32 Simplified SPI communication in master mode (only for SPI00)
Conditions: Ta = -40 to +125°C, VCC = 2.7 to 5.5 V, VSS = 0 V
Parameter Symbol High-speed Middle-speed Low-speed Unit Test
mode mode mode conditions
Min. Max. Min. Max. Min. Max.

SCKp cycle time tKCY1 ≥ 2/ 4.0 V ≤ VCC tKCY1 62.5 — 83.3 — 1000 — ns Figure 2.21
PCLKB ≤ 5.5 V Figure 2.22
2.7 V ≤ VCC 83.3 — 125 — 1000 — ns
≤ 5.5 V
SCKp high-/low- 4.0 V ≤ VCC ≤ 5.5 V tKH1, tKL1 tKCY1/2 — tKCY1/2 — tKCY1/2 — ns
level width -7 - 10 - 50
2.7 V ≤ VCC ≤ 5.5 V tKCY1/2 — tKCY1/2 — tKCY1/2 — ns
- 10 - 15 - 50
SIp setup time 4.0 V ≤ VCC ≤ 5.5 V tSIK1 23 — 33 — 110 — ns
(to SCKp↑)*1
2.7 V ≤ VCC ≤ 5.5 V 33 — 50 — 110 — ns
SIp hold time 2.7 V ≤ VCC ≤ 5.5 V tKSI1 10 — 10 — 10 — ns
(from SCKp↑)*1
Delay time from C = 20 pF*3 tKSO1 — 10 — 10 — 10 ns
SCKp↓ to SOp
output*2
Note: Select the CMOS output for the SOp pin and SCKp pin by using NCODR bit in Port gh Pin Function Select Register (PghPFS).
Note: p: SPI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), gh: Port number (g = 0 to 4, h = 00 to 15).
Note 1. The setting applies when SCRmn.DCP[1:0] = 00b or 11b. The setting for the SIp setup time changes to SCKp↓ and that for the SIp
hold time changes from SCKp↓ when SCRmn.DCP[1:0] = 01b or 10b.
Note 2. This setting applies when SCRmn.DCP[1:0] = 00b or 11b. The setting for the delay time to SOp output changes from SCKp↑ when
SCRmn.DCP[1:0] = 01b or 10b.
Note 3. C is the load capacitance of the SCKp and SOp output lines.

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Table 2.33 Simplified SPI communication in master mode (except for SPI00)
Conditions: Ta = -40 to +125°C, VCC = 1.6 to 5.5 V, VSS = 0 V
Parameter Symbol High-speed Middle-speed Low-speed Unit Test
mode*1 mode mode conditions

Min. Max. Min. Max. Min. Max.

SCKp cycle time tKCY1 ≥ 4/ 2.7 V ≤ VCC tKCY1 125 — 166 — 2000 — ns Figure 2.21
PCLKB ≤ 5.5 V Figure 2.22
2.4 V ≤ VCC 250 — 250 — 2000 — ns
≤ 5.5 V
1.8 V ≤ VCC 500 — 500 — 2000 — ns
≤ 5.5 V
1.6 V ≤ VCC — — 1000 — 2000 — ns
≤ 5.5 V
SCKp high-/low- 4.0 V ≤ VCC ≤ 5.5 V tKH1, tKL1 tKCY1/2 — tKCY1/2 — tKCY1/2 — ns
level width - 12 - 21 - 50
2.7 V ≤ VCC ≤ 5.5 V tKCY1/2 — tKCY1/2 — tKCY1/2 — ns
- 18 - 25 - 50
2.4 V ≤ VCC ≤ 5.5 V tKCY1/2 — tKCY1/2 — tKCY1/2 — ns
- 38 - 38 - 50
1.8 V ≤ VCC ≤ 5.5 V tKCY1/2 — tKCY1/2 — tKCY1/2 — ns
- 50 - 50 - 50
1.6 V ≤ VCC ≤ 5.5 V — — tKCY1/2 — tKCY1/2 — ns
- 100 - 100
SIp setup time 4.0 V ≤ VCC ≤ 5.5 V tSIK1 44 — 54 — 110 — ns
(to SCKp↑)*2
2.7 V ≤ VCC ≤ 5.5 V 44 — 54 — 110 — ns
2.4 V ≤ VCC ≤ 5.5 V 75 — 75 — 110 — ns
1.8 V ≤ VCC ≤ 5.5 V 110 — 110 — 110 — ns
1.6 V ≤ VCC ≤ 5.5 V — — 220 — 220 — ns
SIp hold time 1.6 V ≤ VCC ≤ 5.5 V tKSI1 19 — 19 — 19 — ns
(from SCKp↑)*2
Delay time from 1.6 V ≤ VCC ≤ 5.5 V tKSO1 — 25 — 25 — 25 ns
SCKp↓ to SOp C = 30 pF*4
output*3
Note: Select the CMOS output for the SOp pin and SCKp pin by using NCODR bit in Port gh Pin Function Select Register (PghPFS).
Note: p: SPI number (p = 00, 01, 10, 11, 20, 21), m: Unit number, n: Channel number (mn = 00 to 03, 10 to 11), gh: Port number (g = 0 to
4, h = 00 to 15).
Note 1. Operating voltages in high-speed mode are 1.8 V ≤ VCC ≤ 5.5 V.
Note 2. This setting applies when SCRmn.DCP[1:0] = 00b or 11b. The setting for the SIp setup time changes to SCKp↓ and that for the SIp
hold time changes from SCKp↓ when SCRmn.DCP[1:0] = 01b or 10b.
Note 3. This setting applies when SCRmn.DCP[1:0] = 00b or 11b. The setting for the delay time to SOp output changes from SCKp↑ when
SCRmn.DCP[1:0] = 01b or 10b.
Note 4. C is the load capacitance of the SCKp and SOp output lines.

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Table 2.34 Simplified SPI communication in slave mode

Conditions: Ta = -40 to +125°C, VCC = 1.6 to 5.5 V, VSS = 0 V
Parameter Symbol High-speed Middle-speed Low-speed Unit Test
mode*1 mode mode conditions

Min. Max. Min. Max. Min. Max.

SCKp cycle 4.0 V ≤ VCC 20 MHz < tKCY2 8/fMCK — 8/fMCK — — — ns Figure 2.21
time*2 ≤ 5.5 V fMCK Figure 2.22

fMCK ≤ 20 6/fMCK — 6/fMCK — 6/fMCK — ns

MHz
2.7 V ≤ VCC 16 MHz < 8/fMCK — 8/fMCK — — — ns
≤ 5.5 V fMCK

fMCK ≤ 16 6/fMCK — 6/fMCK — 6/fMCK — ns

MHz
2.4 V ≤ VCC ≤ 5.5 V 6/fMCK — 6/fMCK — 6/fMCK — ns
+ 500 + 500 + 500
1.8 V ≤ VCC ≤ 5.5 V 6/fMCK — 6/fMCK — 6/fMCK — ns
+ 750 + 750 + 750
1.6 V ≤ VCC ≤ 5.5 V — — 6/fMCK — 6/fMCK — ns
+ 1500 + 1500
SCKp high-/low- 4.0 V ≤ VCC ≤ 5.5 V tKH2, tKL2 tKCY2/2 — tKCY2/2 — tKCY2/2 — ns
level width -7 -7 -7
2.7 V ≤ VCC ≤ 5.5 V tKCY2/2 — tKCY2/2 — tKCY2/2 — ns
-8 -8 -8
1.8 V ≤ VCC ≤ 5.5 V tKCY2/2 — tKCY2/2 — tKCY2/2 — ns
- 18 - 18 - 18
1.6 V ≤ VCC ≤ 5.5 V — — tKCY2/2 — tKCY2/2 — ns
- 66 - 66
SIp setup time 2.7 V ≤ VCC ≤ 5.5 V tSIK2 1/fMCK — 1/fMCK — 1/fMCK — ns
(to SCKp↑)*3 + 20 + 30 + 30
1.8 V ≤ VCC ≤ 5.5 V 1/fMCK — 1/fMCK — 1/fMCK — ns
+ 30 + 30 + 30
1.6 V ≤ VCC ≤ 5.5 V — — 1/fMCK — 1/fMCK — ns
+ 40 + 40
SIp hold time 1.8 V ≤ VCC ≤ 5.5 V tKSI2 1/fMCK — 1/fMCK — 1/fMCK — ns
(from SCKp↑)*3 + 31 + 31 + 31
1.6 V ≤ VCC ≤ 5.5 V — — 1/fMCK — 1/fMCK — ns
+ 250 + 250
Delay time from C = 30 pF*5 2.7 V ≤ VCC tKSO2 — 2/fMCK — 2/fMCK — 2/fMCK ns
SCKp↓ to SOp ≤ 5.5 V + 44 + 110 + 110
output*4
2.4 V ≤ VCC — 2/fMCK — 2/fMCK — 2/fMCK ns
≤ 5.5 V + 75 + 110 + 110
1.8 V ≤ VCC — 2/fMCK — 2/fMCK — 2/fMCK ns
≤ 5.5 V + 110 + 110 + 110
1.6 V ≤ VCC — — — 2/fMCK — 2/fMCK ns
≤ 5.5 V + 220 + 220
Note: Select the CMOS output for the SOp pin by using NCODR bit in Port gh Pin Function Select Register (PghPFS).
Note: ● p: SPI number (p = 00, 01, 10, 11, 20, 21), m: Unit number, n: Channel number (mn = 00 to 03, 10 to 11), gh: Port number (g =
0 to 4, h = 00 to 15)
● fMCK: Serial array unit operation clock frequency
Note 1. Operating voltages in high-speed mode are 1.8 V ≤ VCC ≤ 5.5 V.
Note 2. Transfer rate in the Snooze mode is 0.5 Mbps at the maximum.
Note 3. This setting applies when SCRmn.DCP[1:0] = 00b or 11b. The setting for the SIp setup time changes to SCKp↓ and that for the SIp
hold time changes from SCKp↓ when SCRmn.DCP[1:0] = 01b or 10b.

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Note 4. This setting applies when SCRmn.DCP[1:0] = 00b or 11b. The setting for the delay time to SOp output changes from SCKp↑ when
SCRmn.DCP[1:0] = 01b or 10b.
Note 5. C is the load capacitance of the SOp output line.

SCKp SCK

MCU SIp SO User device

SOp SI

Note: p: SPI number (p = 00, 01, 10, 11, 20, 21)

Figure 2.20 Connection in the simplified SPI communications

tKCY1, 2

tKL1, 2 tKH1, 2

SCKp

tSIK1, 2 tKSI1, 2

SIp Input data

tKSO1, 2

SOp Output data

Note: ● p: SPI number (p = 00, 01, 10, 11, 20, 21)

● m: Unit number, n: Channel number (mn = 00 to 03, 10 to 11)

Figure 2.21 Timing of serial transfer in the simplified SPI communications when SCRmn.DCP[1:0] = 00b or
11b

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tKCY1, 2

tKH1, 2 tKL1, 2

SCKp

tSIK1, 2 tKSI1, 2

SIp Input data

tKSO1, 2

SOp Output data

Note: ● p: SPI number (p = 00, 01, 10, 11, 20, 21)

● m: Unit number, n: Channel number (mn = 00 to 03, 10 to 11)

Figure 2.22 Timing of serial transfer in the simplified SPI communications when SCRmn.DCP[1:0] = 01b or
10b

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Table 2.35 Simplified I2C communication

Conditions: Ta = -40 to +125°C, VCC = 1.6 to 5.5 V, VSS = 0 V
Parameter Symbol High-speed Middle-speed Low-speed Unit Test
mode*1 mode mode conditions

Min. Max. Min. Max. Min. Max.

SCLr clock 2.7 V ≤ VCC ≤ 5.5 V, fSCL — 1000*2 — 1000*2 — 400*2 kHz Figure 2.23
frequency Cb = 50 pF, Rb = 2.7 kΩ Figure 2.24
1.8 V ≤ VCC ≤ 5.5 V, — 400*2 — 400*2 — 400*2 kHz
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ VCC < 2.7 V, — 300*2 — 300*2 — 300*2 kHz
Cb = 100 pF, Rb = 5 kΩ
1.6 V ≤ VCC < 1.8 V, — — — 250*2 — 250*2 kHz
Cb = 100 pF, Rb = 5 kΩ
Hold time when 2.7 V ≤ VCC ≤ 5.5 V, tLOW 475 — 475 — 1150 — ns
SCLr is low Cb = 50 pF, Rb = 2.7 kΩ
1.8 V ≤ VCC ≤ 5.5 V, 1150 — 1150 — 1150 — ns
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ VCC < 2.7 V, 1550 — 1550 — 1550 — ns
Cb = 100 pF, Rb = 5 kΩ
1.6 V ≤ VCC < 1.8 V, — — 1850 — 1850 — ns
Cb = 100 pF, Rb = 5 kΩ
Hold time when 2.7 V ≤ VCC ≤ 5.5 V, tHIGH 475 — 475 — 1150 — ns
SCLr is high Cb = 50 pF, Rb = 2.7 kΩ
1.8 V ≤ VCC ≤ 5.5 V, 1150 — 1150 — 1150 — ns
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ VCC < 2.7 V, 1550 — 1550 — 1550 — ns
Cb = 100 pF, Rb = 5 kΩ
1.6 V ≤ VCC < 1.8 V, — — 1850 — 1850 — ns
Cb = 100 pF, Rb = 5 kΩ
Data setup time 2.7 V ≤ VCC ≤ 5.5 V, tSU:DAT 1/fMCK + — 1/fMCK — 1/fMCK — ns
(reception) Cb = 50 pF, Rb = 2.7 kΩ 85*3 +85*3 +145*3
1.8 V ≤ VCC ≤ 5.5 V, 1/fMCK + — 1/fMCK + — 1/fMCK — ns
Cb = 100 pF, Rb = 3 kΩ 145*3 145*3 +145*3
1.8 V ≤ VCC < 2.7 V, 1/fMCK + — 1/fMCK + — 1/fMCK + — ns
Cb = 100 pF, Rb = 5 kΩ 230*3 230*3 230*3
1.6 V ≤ VCC < 1.8 V, — — 1/fMCK + — 1/fMCK + — ns
Cb = 100 pF, Rb = 5 kΩ 290*3 290*3
Data hold time 2.7 V ≤ VCC ≤ 5.5 V, tHD:DAT 0 305 0 305 0 305 ns
(transmission) Cb = 50 pF, Rb = 2.7 kΩ
1.8 V ≤ VCC ≤ 5.5 V, 0 355 0 355 0 355 ns
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ VCC < 2.7 V, 0 405 0 405 0 405 ns
Cb = 100 pF, Rb = 5 kΩ
1.6 V ≤ VCC < 1.8 V, — — 0 405 0 405 ns
Cb = 100 pF, Rb = 5 kΩ
Note: Select the NMOS open-drain output for the SDAr pin and the CMOS output for the SCLr pin by using NCODR bit in Port gh Pin
Function Select Register (PghPFS).
Note: ● r: IIC number (r = 00, 01, 10, 11, 20, 21), gh: Port number (g = 0 to 4, h = 00 to 15)
● fMCK: Serial array unit operation clock frequency
● Rb[Ω]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance
Note 1. Operating voltages in high-speed mode are 1.8 V ≤ VCC ≤ 5.5 V.
Note 2. The listed times must be no greater than fMCK/4.
Note 3. Set fMCK so that it will not exceed the hold time when SCLr is low or high.

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R9A02G021 Datasheet 2. Electrical Characteristics

VCC

Rb
SDAr SDA

MCU User device

SCLr SCL

Note: r: IIC number (r = 00, 01, 10, 11, 20, 21)

Figure 2.23 Connection in the simplified I2C communications

1/fSCL

tLOW tHIGH

SCLr

SDAr

tHD:DAT tSU:DAT

Note: r: IIC number (r = 00, 01, 10, 11, 20, 21)

Figure 2.24 Timing of serial transfer in the simplified I2C communications

2.3.11 Serial Interface UARTA (UARTA)

Table 2.36 UARTA communications
Conditions: Ta = -40 to +125°C, VCC = 1.6 to 5.5 V, VSS = 0 V
Parameter Symbol Min. Typ. Max. Unit Test conditions

Transfer rate — 200 — 153600 bps —

Note: Select the CMOS output for the TxDAn pin by using NCODR bit in Port gh Pin Function Select Register (PghPFS).
Note: n: Unit number (n = 0, 1), gh: Port number (g = 0 to 4, h = 00 to 15).

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2.3.12 I2C Bus Interface (IICA)

Table 2.37 I2C standard mode
Conditions: Ta = -40 to +125°C, VCC = 1.6 to 5.5 V, VSS = 0 V
Parameter Symbol Min. Typ. Max. Unit Test
conditions

SCLAn clock frequency Standard mode: fSCL 0 — 100 kHz Figure 2.25
PCLKB ≥ 1 MHz
Setup time of restart condition — tSU:STA 4.7 — — µs

Hold time*1 — tHD:STA 4 — — µs

Hold time when SCLAn is low — tLOW 4.7 — — µs

Hold time when SCLAn is high — tHIGH 4 — — µs

Data setup time (reception) — tSU:DAT 250 — — ns

Data hold time (transmission)*2 — tHD:DAT 0 — 3.45 µs

Setup time of stop condition — tSU:STO 4 — — µs

Bus-free time — tBUF 4.7 — — µs

Note: n = 0, 1
Note: The maximum value of communication line capacitance (Cb) and communication line pull-up resistor (Rb) are as follows.
Cb = 400 pF, Rb = 2.7 kΩ
Note 1. The first clock pulse is generated after this period when the start or restart condition is detected.
Note 2. The maximum value of tHD:DAT applies to normal transfer. The clock stretching is inserted on reception of an acknowledgment
(ACK) signal.

Table 2.38 I2C fast mode

Conditions: Ta = -40 to +125°C, VCC = 1.8 to 5.5 V, VSS = 0 V
Parameter Symbol Min. Typ. Max. Unit Test
conditions

SCLAn clock frequency Fast mode: PCLKB fSCL 0 — 400 kHz Figure 2.25
≥ 3.5 MHz
Setup time of restart condition — tSU:STA 0.6 — — µs

Hold time*1 — tHD:STA 0.6 — — µs

Hold time when SCLAn is low — tLOW 1.3 — — µs

Hold time when SCLAn is high — tHIGH 0.6 — — µs

Data setup time (reception) — tSU:DAT 100 — — ns

Data hold time (transmission)*2 — tHD:DAT 0 — 0.9 µs

Setup time of stop condition — tSU:STO 0.6 — — µs

Bus-free time — tBUF 1.3 — — µs

Note: n = 0, 1
Note: The maximum value of communication line capacitance (Cb) and communication line pull-up resistor (Rb) are as follows.
Cb = 320 pF, Rb = 1.1 kΩ
Note 1. The first clock pulse is generated after this period when the start or restart condition is detected.
Note 2. The maximum value of tHD:DAT applies to normal transfer. The clock stretching is inserted on reception of an acknowledgment
(ACK) signal.

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Table 2.39 I2C fast mode plus

Conditions: Ta = -40 to +125°C, VCC = 2.7 to 5.5 V, VSS = 0 V
Parameter Symbol Min. Typ. Max. Unit Test
conditions

SCLAn clock frequency Fast mode plus: fSCL 0 — 1000 kHz Figure 2.25
PCLKB ≥ 10 MHz
Setup time of restart condition — tSU:STA 0.26 — — µs

Hold time*1 — tHD:STA 0.26 — — µs

Hold time when SCLAn is low — tLOW 0.5 — — µs

Hold time when SCLAn is high — tHIGH 0.26 — — µs

Data setup time (reception) — tSU:DAT 50 — — ns

Data hold time (transmission)*2 — tHD:DAT 0 — 0.45 µs

Setup time of stop condition — tSU:STO 0.26 — — µs

Bus-free time — tBUF 0.5 — — µs

Note: n = 0, 1
Note: The maximum value of communication line capacitance (Cb) and communication line pull-up resistor (Rb) are as follows.
Cb = 120 pF, Rb = 1.1 kΩ
Note 1. The first clock pulse is generated after this period when the start or restart condition is detected.
Note 2. The maximum value of tHD:DAT applies to normal transfer. The clock stretching is inserted on reception of an acknowledgment
(ACK) signal.

tLOW tR

SCLAn

tHD:DAT tHIGH tF tSU:STA tHD:STA tSU:STO

tHD:STA tSU:DAT

SDAAn
tBUF

Stop Start Restart Stop

condition condition condition condition

Note: n = 0, 1

Figure 2.25 I2C serial transfer timing

2.4 ADC12 Characteristics

Table 2.40 A/D conversion characteristics (1) in normal modes 1 and 2 (1 of 2)
Conditions: VCC = AVREFP = 4.5 to 5.5 V, VSS = AVREFM = 0 V
Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM
Target pins for conversion: ANI2 to ANI5, internal reference voltage, and temperature sensor output voltage
Parameter Min Typ Max Unit Test conditions

Resolution — — 12 Bit —
Conversion clock (fAD) 1 — 48 MHz —

Conversion time*4 1.33 — — µs —

Offset error*1 *2 *3 — — ±7.0 LSB —

Full-scale error*1 *2 *3 — — ±7.0 LSB —

Absolute accuracy*1 *2 *3 — — ±7.5 LSB —

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Table 2.40 A/D conversion characteristics (1) in normal modes 1 and 2 (2 of 2)

Conditions: VCC = AVREFP = 4.5 to 5.5 V, VSS = AVREFM = 0 V
Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM
Target pins for conversion: ANI2 to ANI5, internal reference voltage, and temperature sensor output voltage
Parameter Min Typ Max Unit Test conditions

DNL differential nonlinearity error*1 — ±1.0 — LSB —

INL integral nonlinearity error*1 *3 *3 — — ±3.0 LSB —

Analog input voltage range 0 — AVREFP V —

Note: These specification values apply during A/D conversion operation, while CPU is in Sleep mode and peripheral modules other than
A/D in module standby.
If CPU is running or peripheral modules other than A/D are running during A/D conversion, values might not fall within the indicated
ranges.
Note 1. This value does not include the quantization error (± 1/2 LSB).
Note 2. When pins ANI16 to ANI19 are selected as the target pins for conversion, the maximum values are as follows:
Absolute accuracy: Add ± 3 LSB to the maximum value.
Offset/full-scale error: Add ± 2 LSB to the maximum value.
Note 3. When AVREFP < VCC, the maximum values are as follows:
Absolute accuracy/Offset error/full-scale error: Add (± 0.75 LSB × (VCC voltage (V) - AVREFP voltage (V)) to the maximum value.
INL integral nonlinearity error: Add (± 0.2 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum value.
Note 4. When the internal reference voltage or the temperature sensor output voltage is selected as the target for conversion, the sampling
time must be at least 5 µs. Accordingly, use normal mode 2 and fAD = 32 MHz or less with the longer sampling time.

Table 2.41 A/D conversion characteristics (2) in normal modes 1 and 2

Conditions: VCC = AVREFP = 2.7 to 5.5 V, VSS = AVREFM = 0 V
Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM
Target pins for conversions: ANI2 to ANI5, internal reference voltage, and temperature sensor output voltage
Parameter Min Typ Max Unit Test conditions

Resolution — — 12 Bit —
Conversion clock (fAD) 1 — 48 MHz —

Conversion time*4 1.33 — — µs —

Offset error*1 *2 *3 — — ±8.5 LSB —

Full-scale error *1 *2 *3 — — ±8.5 LSB —

Absolute accuracy*1 *2 *3 — — ±9.0 LSB —

DNL differential nonlinearity error*1 — ±1.0 — LSB —

INL integral nonlinearity error*1 *3 — — ±3.0 LSB —

Analog input voltage range 0 — AVREFP V —

Note: These specification values apply during A/D conversion operation, while CPU is in Sleep mode and peripheral modules other than
A/D in module standby.
If CPU is running or peripheral modules other than A/D are running during A/D conversion, values might not fall within the indicated
ranges.
Note 1. This value does not include the quantization error (± 1/2 LSB).
Note 2. When pins ANI16 to ANI19 are selected as the target pins for conversion, the maximum values are as follows:
Absolute accuracy: Add ± 3 LSB to the maximum value.
Offset/full-scale error: Add ± 2 LSB to the maximum value.
Note 3. When AVREFP < VCC, the maximum values are as follows:
Absolute accuracy/Offset error/full-scale error: Add (± 0.75 LSB × (VCC voltage (V) - AVREFP voltage (V)) to the maximum value.
INL integral nonlinearity error: Add (± 0.2 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum value.
Note 4. When the internal reference voltage or the temperature sensor output voltage is selected as the target for conversion, the sampling
time must be at least 5 µs. Accordingly, use normal mode 2 and fAD = 32 MHz or less with the longer sampling time.

Table 2.42 A/D conversion characteristics (3) in normal modes 1 and 2 (1 of 2)

Conditions: VCC = AVREFP = 2.4 to 5.5 V, VSS = AVREFM = 0 V
Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM
Target pins for conversions: ANI2 to ANI5, internal reference voltage, and temperature sensor output voltage
Parameter Min Typ Max Unit Test conditions

Resolution — — 12 Bit —
Conversion clock (PCLKB) 1 — 32 MHz —

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Table 2.42 A/D conversion characteristics (3) in normal modes 1 and 2 (2 of 2)

Conditions: VCC = AVREFP = 2.4 to 5.5 V, VSS = AVREFM = 0 V
Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM
Target pins for conversions: ANI2 to ANI5, internal reference voltage, and temperature sensor output voltage
Parameter Min Typ Max Unit Test conditions

Conversion time*4 2.0 — — µs —

Offset error*1 *2 *3 — — ±9.0 LSB —

Full-scale error *1 *2 *3 — — ±9.0 LSB —

Absolute accuracy*1 *2 *3 — — ±9.5 LSB —

DNL differential nonlinearity error*1 — ±1.0 — LSB —

INL integral nonlinearity error*1 *3 — — ±3.0 LSB —

Analog input voltage range 0 — AVREFP V —

Note: These specification values apply during A/D conversion operation, while CPU is in Sleep mode and peripheral modules other than
A/D in module standby.
If CPU is running or peripheral modules other than A/D are running during A/D conversion, values might not fall within the indicated
ranges.
Note 1. This value does not include the quantization error (± 1/2 LSB).
Note 2. When pins ANI16 to ANI19 are selected as the target pins for conversion, the maximum values are as follows:
Absolute accuracy: Add ± 3 LSB to the maximum value.
Offset/full-scale error: Add ± 2 LSB to the maximum value.
Note 3. When AVREFP < VCC, the maximum values are as follows:
Absolute accuracy/Offset error/full-scale error: Add (± 0.75 LSB × (VCC voltage (V) - AVREFP voltage (V)) to the maximum value.
INL integral nonlinearity error: Add (± 0.2 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum value.
Note 4. When the internal reference voltage or the temperature sensor output voltage is selected as the target for conversion, the sampling
time must be at least 5 µs. Accordingly, use normal mode 2 and fAD = 32 MHz or less with the longer sampling time.

Table 2.43 A/D conversion characteristics (1) in Low-voltage modes 1 and 2

Conditions: VCC = AVREFP = 2.7 to 5.5 V, VSS = AVREFM = 0 V
Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM
Target pins for conversion: ANI2 to ANI5, internal reference voltage*4, and temperature sensor output voltage*4
Parameter Min Typ Max Unit Test conditions

Resolution — — 12 Bit —
Conversion clock (fAD) 1 — 24 MHz —

Conversion time*5 3.33 — — µs —

Offset error*1 *2 *3 — — ±8.5 LSB —

Full-scale error *1 *2 *3 — — ±8.5 LSB —

Absolute accuracy*1 *2 *3 — — ±9.0 LSB —

DNL differential nonlinearity error*1 — ±1.5 — LSB —

INL integral nonlinearity error*1 *3 — — ±4.0 LSB —

Analog input voltage range 0 — AVREFP V —

Note: These specification values apply during A/D conversion operation, while CPU is in Sleep mode and peripheral modules other than
A/D in module standby.
If CPU is running or peripheral modules other than A/D are running during A/D conversion, values might not fall within the indicated
ranges.
Note 1. This value does not include the quantization error (± 1/2 LSB).
Note 2. When pins ANI16 to ANI19 are selected as the target pins for conversion, the maximum values are as follows:
Absolute accuracy: Add ± 3 LSB to the maximum value.
Offset/full-scale error: Add ± 2 LSB to the maximum value.
Note 3. When AVREFP < VCC, the maximum values are as follows:
Absolute accuracy/Offset error/full-scale error: Add (± 0.75 LSB × (VCC voltage (V) - AVREFP voltage (V)) to the maximum value.
INL integral nonlinearity error: Add (± 0.2 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum value.
Note 4. If the internal reference voltage or temperature sensor output voltage is to be A/D converted, VCC must be at least 1.8 V.
Note 5. When the internal reference voltage or the temperature sensor output voltage is selected as the target for conversion, the sampling
time must be at least 5 µs. Accordingly, use a low-voltage mode 2 and fAD = 16 MHz or less with the longer sampling time.

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Table 2.44 A/D conversion characteristics (2) in Low-voltage modes 1 and 2

Conditions: VCC = AVREFP = 2.4 to 5.5 V, VSS = AVREFM = 0 V
Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM
Target pins for conversions: ANI2 to ANI5, internal reference voltage*4, and temperature sensor output voltage*4
Parameter Min Typ Max Unit Test conditions

Resolution — — 12 Bit —
Conversion clock (fAD) 1 — 16 MHz —

Conversion time*5 5.0 — — µs —

Offset error*1 *2 *3 — — ±9.0 LSB —

Full-scale error*1 *2 *3 — — ±9.0 LSB —

Absolute accuracy*1 *2 *3 — — ±9.5 LSB —

DNL differential nonlinearity error*1 — ±1.5 — LSB —

INL integral nonlinearity error*1 *3 — — ±4.0 LSB —

Analog input voltage range 0 — AVREFP V —

Note: These specification values apply during A/D conversion operation, while CPU is in Sleep mode and peripheral modules other than
A/D in module standby.
If CPU is running or peripheral modules other than A/D are running during A/D conversion, values might not fall within the indicated
ranges.
Note 1. This value does not include the quantization error (± 1/2 LSB).
Note 2. When pins ANI16 to ANI19 are selected as the target pins for conversion, the maximum values are as follows:
Absolute accuracy: Add ± 3 LSB to the maximum value.
Offset/full-scale error: Add ± 2 LSB to the maximum value.
Note 3. When AVREFP < VCC, the maximum values are as follows:
Absolute accuracy/Offset error/full-scale error: Add (± 0.75 LSB × (VCC voltage (V) - AVREFP voltage (V)) to the maximum value.
INL integral nonlinearity error: Add (± 0.2 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum value.
Note 4. If the internal reference voltage or temperature sensor output voltage is to be A/D converted, VCC must be at least 1.8 V.
Note 5. When the internal reference voltage or the temperature sensor output voltage is selected as the target for conversion, the sampling
time must be at least 5 µs. Accordingly, use low-voltage mode 2 and fAD = 16 MHz or less with the longer sampling time.

Table 2.45 A/D conversion characteristics (3) in Low-voltage modes 1 and 2

Conditions: VCC = AVREFP = 1.8 to 5.5 V, VSS = AVREFM = 0 V
Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM
Target pins for conversion: ANI2 to ANI5, internal reference voltage*4, and temperature sensor output voltage*4
Parameter Min Typ Max Unit Test conditions

Resolution — — 12 Bit —
Conversion clock (fAD) 1 — 8 MHz —

Conversion time*5 10.0 — — µs —

Offset error*1 *2 *3 — — ± 13.0 LSB —

Full-scale error*1 *2 *3 — — ± 13.0 LSB —

Absolute accuracy*1 *2 *3 — — ± 13.5 LSB —

DNL differential nonlinearity error*1 — ± 2.0 — LSB —

INL integral nonlinearity error*1 *3 — — ± 4.5 LSB —

Analog input voltage range 0 — AVREFP V —

Note: These specification values apply during A/D conversion operation, while CPU is in Sleep mode and peripheral modules other than
A/D in module standby.
If CPU is running or peripheral modules other than A/D are running during A/D conversion, values might not fall within the indicated
ranges.
Note 1. This value does not include the quantization error (± 1/2 LSB).
Note 2. When pins ANI16 to ANI19 are selected as the target pins for conversion, the maximum values are as follows:
Absolute accuracy: Add ± 3 LSB to the maximum value.
Offset/full-scale error: Add ± 2 LSB to the maximum value.
Note 3. When AVREFP < VCC, the maximum values are as follows:
Absolute accuracy/Offset error/full-scale error: Add (± 0.75 LSB × (VCC voltage (V) - AVREFP voltage (V)) to the maximum value.
INL integral nonlinearity error: Add (± 0.2 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum value.
Note 4. If the internal reference voltage or temperature sensor output voltage is to be A/D converted, VCC must be at least 1.8 V.

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Note 5. When the internal reference voltage or the temperature sensor output voltage is selected as the target for conversion, the sampling
time must be at least 5 µs. Accordingly, use low-voltage mode 2 and fAD = 16 MHz or less with the longer sampling time.

Table 2.46 A/D conversion characteristics (4) in Low-voltage modes 1 and 2

Conditions: VCC = AVREFP = 1.6 to 5.5 V, VSS = AVREFM = 0 V
Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM
Target pins for conversion: ANI2 to ANI5, internal reference voltage*4, and temperature sensor output voltage*4
Parameter Min Typ Max Unit Test conditions

Resolution — — 12 Bit —
Conversion clock (PCLKB) 1 — 4 MHz —

Conversion time*5 20.0 — — µs —

Offset error*1 *2 *3 *4 — — ±13.5 LSB —

Full-scale error*1 *2 *3 *4 — — ±13.5 LSB —

Absolute accuracy*1 *2 *3 *4 — — ±14.0 LSB —

DNL differential nonlinearity error*1 — ±2.0 — LSB —

INL integral nonlinearity error*1 *3 *4 — — ±4.5 LSB —

Analog input voltage range 0 — AVREFP V —

Note: These specification values apply during A/D conversion operation, while CPU is in Sleep mode and peripheral modules other than
A/D in module standby.
If CPU is running or peripheral modules other than A/D are running during A/D conversion, values might not fall within the indicated
ranges.
Note 1. This value does not include the quantization error (± 1/2 LSB).
Note 2. When pins ANI16 to ANI19 are selected as the target pins for conversion, the maximum values are as follows:
Absolute accuracy: Add ± 3 LSB to the maximum value.
Offset/full-scale error: Add ± 2 LSB to the maximum value.
Note 3. When AVREFP < VCC, the maximum values are as follows:
Absolute accuracy/Offset error/full-scale error: Add (± 0.75 LSB × (VCC voltage (V) - AVREFP voltage (V)) to the maximum value.
INL integral nonlinearity error: Add (± 0.2 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum value.
Note 4. If the internal reference voltage or temperature sensor output voltage is to be A/D converted, VCC must be at least 1.8 V.
Note 5. When the internal reference voltage or the temperature sensor output voltage is selected as the target for conversion, the sampling
time must be at least 5 µs. Accordingly, use low-voltage mode 2 and fAD = 16 MHz or less with the longer sampling time.

Table 2.47 A/D conversion characteristics in Low-voltage modes 1 and 2 when the internal reference voltage is
selected as reference voltage (+)
Conditions: VCC = 1.8 to 5.5 V, VSS = AVREFM = 0 V
Reference voltage (+) = internal reference voltage, Reference voltage (-) = AVREFM
Parameter Min Typ Max Unit Test conditions

Resolution — — 8 Bit —
Conversion clock (fAD) 1 — 2 MHz —

Offset error*1 — — 2 LSB —

DNL differential nonlinearity error*1 — 1 — LSB —

INL integral nonlinearity error*1 — — 2 LSB —

Analog input voltage range 0 — VBGR V

Note: These specification values apply during A/D conversion operation, while CPU is in Sleep mode and peripheral modules other than
A/D in module standby.
If CPU is running or peripheral modules other than A/D are running during A/D conversion, values might not fall within the indicated
ranges.
Note 1. This value does not include the quantization error (± 1/2 LSB).

Table 2.48 12-bit A/D converter channel classification (1 of 2)

Classification Channel Conditions Remarks

High-precision channel ANI0 to ANI5 VCC = 1.6 to 5.5 V Pins ANI0 to ANI5 cannot be used
as general I/O, TS transmission, when
the A/D converter is in use.
Normal-precision channel ANI16 to ANI19 —

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Table 2.48 12-bit A/D converter channel classification (2 of 2)

Classification Channel Conditions Remarks

Internal reference voltage Internal reference voltage VCC = 1.8 to 5.5 V —

input channel
Temperature sensor input Temperature sensor output —
channel

Table 2.49 A/D internal reference voltage characteristics

Conditions: VCC = 1.8 to 5.5 V, VSS = 0 V
Parameter Min Typ Max Unit Test conditions

Internal reference voltage input channel*1 1.40 1.47 1.54 V —

Sampling time*2 5.0 — — µs —

Note 1. The 12-bit A/D internal reference voltage indicates the voltage when the internal reference voltage is input to the 12-bit A/D
converter.
Note 2. When the internal reference voltage is converted.

0xFFF
Full-scale error

Integral nonlinearity
error (INL)
A/D converter
output code Ideal line of actual A/D
Actual A/D conversion conversion characteristic
characteristic

Ideal A/D conversion

characteristic Differential nonlinearity error (DNL)
1-LSB width for ideal A/D
conversion characteristic

Differential nonlinearity error (DNL)

1-LSB width for ideal A/D

conversion characteristic

Absolute accuracy

0x000 Offset error

0 Analog input voltage AVREFP
(full-scale)

Figure 2.26 Example of 12-bit A/D converter characteristic terms

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R9A02G021 Datasheet 2. Electrical Characteristics

Absolute accuracy
Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the
actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of the analog
input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D
conversion characteristics, is used as the analog input voltage. For example, if 12-bit resolution is used and the reference
voltage AVREFP = 3.072 V, then 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, and 1.5 mV are used as the analog
input voltages. If analog input voltage is 6 mV, an absolute accuracy of ±5 LSB means that the actual A/D conversion result
is in the range of 0x003 to 0x00D, though an output code of 0x008 can be expected from the theoretical A/D conversion
characteristics.

Integral nonlinearity error (INL)

Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale errors
are zeroed, and the actual output code.

Differential nonlinearity error (DNL)

Differential nonlinearity error is the difference between 1-LSB width based on the ideal A/D conversion characteristics and
the width of the actual output code.

Offset error
Offset error is the difference between the transition point of the ideal first output code and the actual first output code.

Full-scale error
Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code.

2.5 CMP Characteristics

Table 2.50 CMP characteristics
Conditions: VCC = 1.6 to 5.5 V, VSS = 0 V
Parameter Symbol Min Typ Max Unit Test conditions

Input voltage range IVREF 0 — VCC − V Input to the IVREF0 and

1.4 IVREF1 pins
C0LVL = 0, C1LVL = 0
1.4 — VCC Input to the IVREF0 and
IVREF1 pins
C0LVL = 1, C1LVL = 1
IVCMP −0.3 — VCC + Input to the IVCMP0 and
0.3 IVCMP1 pins
Output delay High- — — — 1.5 μs VCC = 3.0 V
speed Input slew rate > 1 V/us
mode
Low- — 3.0 —
speed
mode
Offset voltage High- — — — 50 mV —
speed
mode
Low- — — 40
speed
mode
Operation stabilization wait time tCMP 30 — — μs —

Internal reference voltage*1 — 1.34 1.44 1.54 V —

Note 1. The internal reference voltage can be selected as CMP reference voltage only when 1.8 V ≤ VCC ≤ 5.5 V.

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2.6 DAC8 Characteristics

Table 2.51 D/A conversion characteristics
Conditions: VCC = 2.7 to 5.5 V, VSS = 0 V
Parameter Symbol Min Typ Max Unit Test conditions

Resolution — — — 8 bit —
Conversion time tDCONV — — 3.0 µs —

Absolute accuracy — — — ±3.0 LSB —

Resistive load — 4 — — MΩ —

Capacitive load*1 — — — 35 pF —

Output resistance — — 9.0 — kΩ —

Note 1. Including IO input capacitance of 15 pF.

2.7 TSN Characteristics

Table 2.52 TSN characteristics
Conditions: VCC = 1.8 to 5.5 V, VSS = 0 V
Parameter Symbol Min Typ Max Unit Test conditions

Temperature slope — — −3.3 — mV/°C —

Output voltage (at 25°C) — — 1.05 — V VCC = 3.3 V
Sampling time — 5.0 — — µs —

2.8 POR and LVD Characteristics

Table 2.53 Power-on reset circuit and voltage detection circuit characteristics (1) (1 of 2)
Parameter Symbol Min Typ Max Unit Test Conditions

Voltage detection Power-on reset When power supply rise VPOR 1.47 1.51 1.55 V Figure 2.27
level*1 (POR)
When power supply fall VPDR 1.46 1.50 1.54 Figure 2.28

Voltage detection When power supply rise Vdet0_0 3.74 3.91 4.06 V Figure 2.29
circuit (LVD0)*2 At falling edge
When power supply fall 3.68 3.85 4.00 VCC
When power supply rise Vdet0_1 2.73 2.9 3.01
When power supply fall 2.68 2.85 2.96
When power supply rise Vdet0_2 2.44 2.59 2.70
When power supply fall 2.38 2.53 2.64
When power supply rise Vdet0_3 1.83 1.95 2.07
When power supply fall 1.78 1.90 2.02
When power supply rise Vdet0_4 1.66 1.75 1.88
When power supply fall 1.60 1.69 1.82

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R9A02G021 Datasheet 2. Electrical Characteristics

Table 2.53 Power-on reset circuit and voltage detection circuit characteristics (1) (2 of 2)
Parameter Symbol Min Typ Max Unit Test Conditions

Voltage detection Voltage detection When power supply rise Vdet1_0 4.23 4.39 4.55 V Figure 2.30
level*1 circuit (LVD1)*3 At falling edge
When power supply fall 4.13 4.29 4.45 VCC
When power supply rise Vdet1_1 4.07 4.25 4.39
When power supply fall 3.98 4.16 4.30
When power supply rise Vdet1_2 3.97 4.14 4.29
When power supply fall 3.86 4.03 4.18
When power supply rise Vdet1_3 3.74 3.92 4.06
When power supply fall 3.68 3.86 4.00
When power supply rise Vdet1_4 3.05 3.17 3.29
When power supply fall 2.98 3.10 3.22
When power supply rise Vdet1_5 2.95 3.06 3.17
When power supply fall 2.89 3.00 3.11
When power supply rise Vdet1_6 2.86 2.97 3.08
When power supply fall 2.79 2.90 3.01
When power supply rise Vdet1_7 2.74 2.85 2.96
When power supply fall 2.68 2.79 2.90
Voltage detection Voltage detection When power supply rise Vdet1_8 2.63 2.75 2.85 V Figure 2.30
level*1 circuit (LVD1)*3 At falling edge
When power supply fall 2.58 2.68 2.78 VCC
When power supply rise Vdet1_9 2.54 2.64 2.75
When power supply fall 2.48 2.58 2.68
When power supply rise Vdet1_A 2.43 2.53 2.63
When power supply fall 2.38 2.48 2.58
When power supply rise Vdet1_B 2.16 2.26 2.36
When power supply fall 2.10 2.20 2.30
When power supply rise Vdet1_C 1.88 2 2.09
When power supply fall 1.84 1.96 2.05
When power supply rise Vdet1_D 1.78 1.9 1.99
When power supply fall 1.74 1.86 1.95
When power supply rise Vdet1_E 1.67 1.79 1.88
When power supply fall 1.63 1.75 1.84
When power supply rise Vdet1_F 1.65 1.7 1.78
When power supply fall 1.60 1.65 1.73
Voltage detection Voltage detection When power supply rise Vdet2_0 4.20 4.40 4.57 V Figure 2.31
level*1 circuit (LVD2)*4 At falling edge
When power supply fall 4.11 4.31 4.48 VCC
When power supply rise Vdet2_1 4.05 4.25 4.42
When power supply fall 3.97 4.17 4.34
When power supply rise Vdet2_2 3.91 4.11 4.28
When power supply fall 3.83 4.03 4.20
When power supply rise Vdet2_3 3.71 3.91 4.08
When power supply fall 3.64 3.84 4.01
Note 1. These characteristics apply when noise is not superimposed on the power supply. When a setting causes this voltage detection
level to overlap with that of the voltage detection circuit, it cannot be specified whether LVD1 or LVD2 is used for voltage detection.
Note 2. # in the symbol Vdet0_# denotes the value of the OFS1.VDSEL0[2:0] bits.

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R9A02G021 Datasheet 2. Electrical Characteristics

Note 3. # in the symbol Vdet1_# denotes the value of the LVDLVLR.LVD1LVL[4:0] bits.
Note 4. # in the symbol Vdet2_# denotes the value of the LVDLVLR.LVD2LVL[2:0] bits.

Table 2.54 Power-on reset circuit and voltage detection circuit characteristics (2)
Parameter Symbol Min Typ Max Unit Test Conditions

Wait time after power-on LVD0: enable tPOR — 4.3 — ms —

reset cancellation
LVD0: disable tPOR — 3.7 — ms —

Wait time after voltage LVD0: enable*1 tLVD0,1,2 — 1.4 — ms —

monitor 0, 1, 2 reset
cancellation LVD0: disable*2 tLVD1,2 — 0.7 — ms —

Power-on reset response delay time*3 tdet — — 500 µs Figure 2.27, Figure 2.28

LVD0 response delay time*3 tdet — — 500 µs Figure 2.29

LVD1 response delay time*3 tdet — — 350 µs Figure 2.30

LVD2 response delay time*3 tdet — — 600 µs Figure 2.31

Minimum VCC down time tVOFF 500 — — µs Figure 2.27, VCC = 1.0 V or
above
Power-on reset enable time tW (POR) 1 — — ms Figure 2.28, VCC = below 1.0
V
LVD1 operation stabilization time (after LVD1 is Td (E-A) — — 300 µs Figure 2.30
enabled)
LVD2 operation stabilization time (after LVD2 is Td (E-A) — — 1200 µs Figure 2.31
enabled)
Hysteresis width (POR) VPORH — 10 — mV —

Hysteresis width (LVD0, LVD1 and LVD2) VLVH — 60 — mV LVD0 selected

— 110 — Vdet1_0 to Vdet1_2 selected

— 70 — Vdet1_3 to Vdet1_9 selected

— 60 — Vdet1_A to Vdet1_B selected

— 50 — Vdet1_C to Vdet1_F selected

— 90 — LVD2 selected
Note 1. When OFS1.LVDAS = 0.
Note 2. When OFS1.LVDAS = 1.
Note 3. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet0,
Vdet1, and Vdet2 for the POR/LVD.

tVOFF
VCC

VPOR

1.0 V

Internal reset signal

(active-low)

tdet tdet tPOR

Figure 2.27 Voltage detection reset timing

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R9A02G021 Datasheet 2. Electrical Characteristics

VPOR
VCC

1.0 V

tw(POR)
*1
Internal reset signal
(active-low)

tdet tPOR

Note 1. tw(POR) is the time required for a power-on reset to be enabled while the external power VCC is being held below the
valid voltage (1.0 V).
When VCC turns on, maintain tw(POR) for 1.0 ms or more.

Figure 2.28 Power-on reset timing

tVOFF

VCC Vdet0 VLVH

Internal reset signal

(active-low)
tdet tdet tLVD0

Figure 2.29 Voltage detection circuit timing (Vdet0)

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R9A02G021 Datasheet 2. Electrical Characteristics

tVOFF

VCC Vdet1 VLVH

LVCMPCR.LVD1E

Td(E-A)
LVD1
Comparator output

LVD1CR0.CMPE

LVD1SR.MON
Internal reset signal
(active-low)
When LVD1CR0.RN = 0

tdet tdet tLVD1

When LVD1CR0.RN = 1

tLVD1

Figure 2.30 Voltage detection circuit timing (Vdet1)

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R9A02G021 Datasheet 2. Electrical Characteristics

tVOFF

VCC Vdet2 VLVH

LVCMPCR.LVD2E

Td(E-A)
LVD2
Comparator output

LVD2CR0.CMPE

LVD2SR.MON
Internal reset signal
(active-low)
When LVD2CR0.RN = 0

tdet tdet tLVD2

When LVD2CR0.RN = 1

tLVD2

Figure 2.31 Voltage detection circuit timing (Vdet2)

2.9 Flash Memory Characteristics

2.9.1 Code Flash Memory Characteristics

Table 2.55 Code flash characteristics (1)
Parameter Symbol Min Typ Max Unit Conditions

Reprogramming/erasure cycle*1 NPEC 10000 — — Times —

Data hold time After 10000 times NPEC tDRP 20*2 *3 — — Year Ta = 105°C

10 — — Ta = 125°C

Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 1,0000),
erasing can be performed n times for each block. For instance, when 8-byte programming is performed 256 times for different
addresses in 2-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming
the same address for several times as one erasure is not enabled (overwriting is prohibited).
Note 2. Characteristic when using the flash memory programmer and the self-programming library provided by Renesas Electronics.
Note 3. This result is target spec, may changed after reliability testing.

Table 2.56 Code flash characteristics (2) (1 of 2)

High-speed mode
Conditions: VCC = 1.8 to 5.5 V, Ta = −40°C to 125°C
ICLK = 1 MHz ICLK = 48 MHz
Parameter Symbol Min Typ Max Min Typ Max Unit

Programming time 8-byte tP4 — 97 843 — 47 446 µs

Erasure time 2-KB tE2K — 8.7 282 — 5.7 221 ms

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R9A02G021 Datasheet 2. Electrical Characteristics

Table 2.56 Code flash characteristics (2) (2 of 2)

High-speed mode
Conditions: VCC = 1.8 to 5.5 V, Ta = −40°C to 125°C
ICLK = 1 MHz ICLK = 48 MHz
Parameter Symbol Min Typ Max Min Typ Max Unit

Blank check time 8-byte tBC4 — — 45 — — 8.7 µs

2-KB tBC2K — — 3239 — — 235 µs

Erase suspended time tSED — — 22.8 — — 11.0 µs

Access window information program tAWSSAS — 16.3 509 — 11.8 444 ms

Start-up area selection and security
setting time
OCD/serial programmer ID setting time tOSIS — 65.1 2036 — 46.9 1773.9 µs

Flash memory mode transition wait tDIS 2 — — 2 — —

time 1
Flash memory mode transition wait tMS 15 — — 15 — — µs
time 2
Note: Does not include the time until each operation of the flash memory is started after instructions are executed by software.
Note: The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 4 MHz, the
frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
Note: The frequency accuracy of ICLK must be ± 1.5% during programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.

Table 2.57 Code flash characteristics (3)

Middle-speed mode
Conditions: VCC = 1.6 to 5.5 V, Ta = −40°C to 125°C
ICLK = 1 MHz ICLK = 24 MHz
Parameter Symbol Min Typ Max Min Typ Max Unit

Programming time 8-byte tP4 — 97 843 — 48 450 µs

Erasure time 2-KB tE2K — 8.7 282 — 5.7 220 ms

Blank check time 8- byte tBC4 — — 45 — — 9.1 µs

2-KB tBC2K — — 3239 — — 236 µs

Erase suspended time tSED — — 22.8 — — 11.2 µs

Access window information program tAWSSAS — 16.3 509 — 11.4 442 ms

Start-up area selection and security
setting time
OCD/serial programmer ID setting tOSIS — 84.7 2280 — 45.3 1690 ms
time*1
Flash memory mode transition wait tDIS 2 — — 2 — — µs
time 1
Flash memory mode transition wait tMS 15 — — 15 — — µs
time 2
Note: Does not include the time until each operation of the flash memory is started after instructions are executed by software.
Note: The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 4 MHz, the
frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
Note: The frequency accuracy of ICLK must be ± 1.5% during programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.
Note 1. When 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V

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R9A02G021 Datasheet 2. Electrical Characteristics

Table 2.58 Code flash characteristics (4)

Low-speed mode
Conditions: VCC = 1.6 to 5.5 V, Ta = −40°C to 125°C
ICLK = 1 MHz
Parameter Symbol Min Typ Max Unit

Programming time 8-byte tP4 — 97 843 µs

Erasure time 2-KB tE2K — 8.7 282 ms

Blank check time 8-byte tBC4 — — 45 µs

2-KB tBC2K — — 3239 µs

Erase suspended time tSED — — 22.8 µs

Access window information program Start-up area tAWSSAS — 16.3 509 ms

selection and security setting time
OCD/serial programmer ID setting time tOSIS — 65.1 2036 ms

Flash memory mode transition wait time 1 tDIS 2 — — µs

Flash memory mode transition wait time 2 tMS 15 — — µs

Note: Does not include the time until each operation of the flash memory is started after instructions are executed by software.
Note: The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory.
Note: The frequency accuracy of ICLK must be ± 1.5% during programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.

2.9.2 Data Flash Memory Characteristics

Table 2.59 Data flash characteristics (1)
Parameter Symbol Min Typ Max Unit Conditions

Reprogramming/erasure cycle*1 NDPEC 100000 1000000 — Times —

Data hold time After 10000 tDDRP 20*2 *3 — — Year Ta = 105℃

times of
NDPEC 10 — — Year Ta = 125℃

After 100000 5*2 *3 — — Year

times of
NDPEC
After 1000000 — 1*2 *3 — Year Ta = 25℃
times of
NDPEC
Note 1. The reprogram/erase cycle is the number of erasure for each block. When the reprogram/erase cycle is n times (n = 100,000),
erasing can be performed n times for each block. For instance, when 1-byte programming is performed 1,024 times for different
addresses in 1-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming
the same address for several times as one erasure is not enabled (overwriting is prohibited).
Note 2. Characteristics when using the flash memory programmer and the self-programming library provided by Renesas Electronics.
Note 3. These results are target spec, and may changed after reliability testing.

Table 2.60 Data flash characteristics (2)

High-speed mode
Conditions: VCC = 1.8 to 5.5 V, Ta = −40℃ to 125℃
ICLK = 1 MHz ICLK = 48 MHz
Parameter Symbol Min Typ Max Min Typ Max Unit

Programming time 1-byte tDP1 — 84 708 — 36 336 µs

Erasure time 1-KB tDE1K — 8.6 281 — 6.3 234 ms

Blank check time 1-byte tDBC1 — — 14.8 — — 8.7 µs

1-KB tDBC1K — — 1602 — — 450 µs

Suspended time during erasing tDSED — — 22.8 — — 11.0 µs

Data flash STOP recovery time tDSTOP 250 — — 250 — — µs

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R9A02G021 Datasheet 2. Electrical Characteristics

Note: Does not include the time until each operation of the flash memory is started after instructions are executed by software.
Note: The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 4 MHz, the
frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
Note: The frequency accuracy of ICLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.

Table 2.61 Data flash characteristics (3)

Middle-speed mode
Conditions: VCC = 1.6 to 5.5 V, Ta = −40℃ to 125℃
ICLK = 1 MHz ICLK = 24 MHz*1
Parameter Symbol Min Typ Max Min Typ Max Unit

Programming time 1-byte tDP1 — 84 708 — 40 365 µs

Erasure time 1-KB tDE1K — 8.6 281 — 7 249 ms

Blank check time 1- byte tDBC1 — — 14.8 — — 11.2 µs

1-KB tDBC1K — — 1602 — — 806 µs

Suspended time during erasing tDSED — — 22.8 — — 11.2 µs

Data flash STOP recovery time tDSTOP 250 — — 250 — — µs

Note: Does not include the time until each operation of the flash memory is started after instructions are executed by software.
Note: The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 4 MHz, the
frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
Note: The frequency accuracy of ICLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.
Note 1. When 1.8 V ≤ VCC ≤ 5.5 V

Table 2.62 Data flash characteristics (4)

Low-speed mode
Conditions: VCC = 1.6 to 5.5 V, Ta = −40℃ to 125℃
ICLK = 1 MHz
Parameter Symbol Min Typ Max Unit

Programming time 1-byte tDP1 — 84 708 µs

Erasure time 1-KB tDE1K — 8.6 281 ms

Blank check time 1-byte tDBC1 — — 14.8 µs

1-KB tDBC1K — — 1602 µs

Suspended time during erasing tDSED — — 22.8 µs

Data flash STOP recovery time tDSTOP 250 — — µs

Note: Does not include the time until each operation of the flash memory is started after instructions are executed by software.
Note: The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory.
Note: The frequency accuracy of ICLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.

2.10 Compact JTAG (cJTAG)

Table 2.63 cJTAG Characteristics
Conditions: VCC = 2.7 to 5.5 V
No. Parameter Symbol Min Max Unit

1 TCKC clock cycle time tCTCKcyc 160 — ns

1a TCKC clock high pulse width tCTCKH 70 — ns

1b TCKC clock low pulse width tCTCKL 70 — ns

2 TMSC setup time tCTMSS 14 — ns

3 TMSC hold time tCTMSH 2 — ns

4 Delay time, TCKC to TMSC valid/disable td(CTCKL-CTMS) 5 60 ns

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R9A02G021 Datasheet 2. Electrical Characteristics

1a 1b

2
3
TCKC

TMSC Data input Data output

Figure 2.32 cJTAG timing

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R9A02G021 Datasheet Appendix 1. Port States in Each Processing Mode

Appendix 1. Port States in Each Processing Mode

Table 1.1 Port states in each processing mode
Function Pin function Reset Software Standby mode

Mode MD Pull-up Keep-O

cJTAG TMSC/TCKC Pull-up Keep-O
IRQ IRQn Hi-Z Keep-O*1 *2
NMI Hi-Z Hi-Z*3
SOSC XT1, XT2 Hi-Z [Sub-clock Oscillator selected] Sub-clock Oscillator is operating
[Other than the above] Hi-Z
KINT KR0n Hi-Z Keep-O*1 *2
SAU [UART mode] RXD0, RXD2 Hi-Z Keep-O*2
[SPI mode] SCK00, SCK20
IICA SCLAn/SDAAn Hi-Z Keep-O*1
UARTA TxDAn/RxDAn/CLKAn Hi-Z Keep-O*1
REMC RIN0 Hi-Z Keep-O*2
RTC RTC1HZ Hi-Z [RTC selected] RTC1HZ output
CLKOUT CLKOUT_A/B Hi-Z [CLKOUT selected] CLKOUT output
CMP VCOUTn Hi-Z [VCOUT selected] VCOUT output
DAC8 DACOUTn Hi-Z [DACOUTn output (DAOE = 1)] D/A output retained
P303 — Pull-up Keep-O
Others — Hi-Z Keep-O
Note: Hi-Z: High-impedance
Keep-O: Output pins retain their previous values. Input pins become high-impedance.
Note 1. Input is enabled if the pin is specified as the software standby canceling source while it is used as an external interrupt pin.
Note 2. Input is enabled if the pin is specified as the snooze mode request trigger in software Standby mode while it is used as an external
interrupt pin.
Note 3. Input is enabled.

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R9A02G021 Datasheet Appendix 2. Package Dimensions

Appendix 2. Package Dimensions

Information on the latest version of the package dimensions or mountings is displayed in packages on the Renesas
Electronics Corporation website.

R01DS0422EJ0110 Rev.1.10 Page 62 of 72

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R9A02G021 Datasheet Appendix 2. Package Dimensions

JEITA Package code RENESAS code MASS(TYP.)[g]

P-HWQFN048-7x7-0.50 PWQN0048KC-A 0.13 g

2X
aaa C
36 25

37 24

INDEX AREA
(D/2 X E/2)

48 13
2X
aaa C
1 12

B E A

ccc C
C

SEATING PLANE
A (A3) A1
e b(48X) bbb C A B
48X
ddd C
eee C Dimension in Millimeters
Reference
Symbol
E2 fff C A B Min. Nom. Max.

1 12 A － － 0.80
EXPOSED A1 0.00 0.02 0.05
fff C A B 48 13 DIE PAD
A3 0.203 REF.
b 0.20 0.25 0.30
D 7.00 BSC
E 7.00 BSC
D2 e 0.50 BSC
L 0.30 0.40 0.50
K 0.20 － －
D2 5.25 5.30 5.35
24 E2 5.25 5.30 5.35
37
aaa 0.15
36 25
bbb 0.10
L(48X) K(48X)
ccc 0.10
ddd 0.05
eee 0.08
fff 0.10

Figure 2.1 HWQFN 48-pin

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 RDK-G-001445 1/1
外形図 Outline drawing
R9A02G021 Datasheet Appendix 2. Package Dimensions
Renesasコード PWQN0032KE-A ルネサスエレクトロニクス株式会社
Renesas Electronics Corporation

JEITA Package code RENESAS code MASS(TYP.)[g]

P-HWQFN032-5x5-0.50 PWQN0032KE-A 0.06

2X
aaa C
24 17

25 16

INDEX AREA
(D/2 X E/2)
32 9
2X
aaa C 8
1

B E A

ccc C
C

SEATING PLANE
A (A3) A1
32X e b(32X) bbb C A B
ddd C Dimension in Millimeters
eee C Reference
Symbol
Min. Nom. Max.
E2 fff C A B
A － － 0.80
1 8
A1 0.00 0.02 0.05
A3 0.203 REF.
fff C A B 32 9
b 0.18 0.25 0.30
D 5.00 BSC
E 5.00 BSC
D2 e 0.50 BSC
L 0.35 0.40 0.45
K 0.20 － －
25 16 D2 3.15 3.20 3.25
E2 3.15 3.20 3.25
24 17
aaa 0.15
L(32X) K(32X) bbb 0.10
ccc 0.10
ddd 0.05
eee 0.08
fff 0.10

Figure 2.2 HWQFN 32-pin

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R9A02G021 Datasheet Appendix 2. Package Dimensions

JEITA Package Code RENESAS Code MASS (Typ.) [g]

P-HWQFN24-4 x 4-0.50 PWQN0024KG-A 0.04

T"
E

��1�
8 ----���
13

19 12

0
INDEX AREA
(D/2 X E/2)

24 7

cl
2X
·. aaa

CCC IC
I□� □I
1

L_:c ... ..... I

SEATING PLANE Reference Dimension in Mi I I imeters
L _
t
:

l b(24X) · , .bbb(,i, C
l l
.. . AIB
(..)
J e I" . . ..·· Symbol
Min Norn. Max.
(]) •. ddd• 11 C
(])
(])
A - - 0.80
·] �><
_'_ A, 0.00 0.02 0.05
A3 0.203 REF.
b 0. 18 0.25 0.30
cc E2 rt I fff,· CIAIB D 4.00 BSC
(..) x E 4.00 BSC
-st
N
SZ' e 0.50 BSC
!E 6
L 0.35 0.40 0.45
7 K 0.20 - -
D2 2. 65 2. 70 2. 75
N
E2 2. 65 2. 70 2. 75
x
0

-st aaa 0. 15
12 bbb 0. 10
CCC 0. 10
ddd 0.05
�EXPOSED eee 0.08
DIE PAD
fff 0. 10

Figure 2.3 HWQFN 24-pin

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Feb 29, 2024
 RDK-G-001794 1/1
Outline drawing
Renesas
R9A02G021 Datasheet SUBG0016LC-A Appendix 2. Package Dimensions
Renesas Electronics Corporation

JEITA Package code RENESAS code MASS(TYP.)[g]

S-UFBGA16-1.99x1.99-0.40 SUBG0016LC-A 0.01

E aaa C 2X
B
INDEX AREA
A
D

aaa C 2X

TOP VIEW
A

16X
C
ccc C
A1

SIDE VIEW

ddd C A B
1 2 3 4
e

SD

Reference Dimension in Millimeters

D Symbol
Min. Nom. Max.
C
D1

D (1.94) 1.99 (2.04)

B
E (1.94) 1.99 (2.04)
A
D1 1.20
E1 1.20

SE A (0.45) (0.50) 0.55

A1 0.175 0.20 0.225
e b 0.24 0.265 0.29
E1 e 0.40
aaa 0.05
BOTTOM VIEW ccc 0.05
ddd 0.05
SD 0.200
SE 0.200

Figure 2.4 WLCSP 16-pin

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R9A02G021 Datasheet Appendix 3. I/O Registers

Appendix 3. I/O Registers

This appendix describes I/O register addresses, access cycles, and reset values by function.

3.1 Peripheral Base Addresses

This section provides the base addresses for peripherals described in this manual.
Table 3.1 shows the name, description, and the base address of each peripheral.
Table 3.1 Peripheral base address (1 of 2)
Name Description Base address

SRAM SRAM Control 0x4000_2000

BUS BUS Control 0x4000_3000
DTC Data Transfer Controller 0x4000_5400
ICU Interrupt Controller 0x4000_6000
CPU_AUX CPU Auxiliary Registers 0x4001_A000
CPU_DBG Debug Function 0x4001_B000
SYSC System Control 0x4001_E000
PORT0 Port 0 Control Registers 0x4004_0000
PORT1 Port 1 Control Registers 0x4004_0020
PORT2 Port 2 Control Registers 0x4004_0040
PORT3 Port 3 Control Registers 0x4004_0060
PORT4 Port 4 Control Registers 0x4004_0080
PFS Pmn Pin Function Control Register 0x4004_0800
ELC Event Link Control 0x4004_1000
WDT Watchdog Timer 0x4004_4200
IWDT Independent Watchdog Timer 0x4004_4400
CAC Clock Frequency Accuracy Measurement Circuit 0x4004_4600
MSTP Module Stop Control B, C, D 0x4004_7000
DAC8 8-bit D/A Converter 0x4005_E000
CRC CRC Calculator 0x4007_4000
KINT Key Interrupt Function 0x4008_0000
DOC Data Operation Circuit 0x4008_5F00
PORGA Product Organize Register 0x4009_1000
TRNG True Random Number Generator 0x4009_1100
CMP Comparator 0x4009_1200
RTC Realtime Clock 0x4009_2000
REMC Remote Control Signal Receiver 0x4009_2100
TML32 32-bit Interval Timer 0x4009_2200
IICA0 I2C Bus Interface 0 0x4009_3000

IICA1 I2C Bus Interface 1 0x4009_3100

SAU0 Serial Array Unit 0 0x4009_4000

SAU1 Serial Array Unit 1 0x4009_4100
TAU Timer Array Unit 0x4009_5000
UARTA Serial Interface UARTA 0x4009_6000
ADC12 12-bit A/D Converter 0x4009_C000

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R9A02G021 Datasheet Appendix 3. I/O Registers

Table 3.1 Peripheral base address (2 of 2)

Name Description Base address

FLCN Flash I/O Registers 0x407E_C000

CLIC Core-Local Interrupt Controller 0xE200_0000
IMT Machine Timer 0xE600_0000
DBG Debug Module 0xE680_0000
Note: Name = Peripheral name
Description = Peripheral functionality
Base address = Lowest reserved address or address used by the peripheral

3.2 Access Cycles

This section provides access cycle information for the I/O registers described in this manual.
The following information applies to Table 3.2:
● Registers are grouped by associated module.
● The number of access cycles indicates the number of cycles based on the specified reference clock.
● In the internal I/O area, reserved addresses that are not allocated to registers must not be accessed, otherwise operations
cannot be guaranteed.
● The number of I/O access cycles depends on bus cycles of the internal peripheral bus, divided clock synchronization
cycles, and wait cycles of each module. Divided clock synchronization cycles differ depending on the frequency ratio
between ICLK and PCLK.
● When the frequency of ICLK is equal to that of PCLK, the number of divided clock synchronization cycles is always
constant.
● When the frequency of ICLK is greater than that of PCLK, at least 1 PCLK cycle is added to the number of divided
clock synchronization cycles.

Note: This applies to the number of cycles when access from the CPU does not conflict with the instruction fetching to the
external memory or bus access from other bus master such as DTC.

Table 3.2 shows the register access cycles.

Table 3.2 Access cycles (1 of 2)
Number of access cycles

Address ICLK = PCLK ICLK > PCLK*1

Cycle
Peripherals From To Read Write Read Write unit Related function

RAM, BUS, DTC, 0x4000_0000 0x4001_BFFF 2 ICLK Memory Protection Unit, SRAM,
ICU, CPU_AUX, Buses, Data Transfer Controller,
CPU_DBG Interrupt Controller, CPU

SYSC*2 0x4001_E000 0x4001_EFFF 4 ICLK Low Power Modes, Resets,

Low Voltage Detection, Clock
Generation Circuit, Register
Write Protection
PORT, PFS, ELC 0x4004_0000 0x4004_1FFF 3*3 3 2 to 4*3 2 to 4 PCLKB I/O Ports, Event Link Control

WDT, IWDT, CAC, 0x4004_2000 0x4005_FFFF 3 2 to 4 PCLKB Watchdog Timer, Independent

MSTP, DAC8 Watchdog Timer, Clock
Frequency Accuracy
Measurement Circuit, Module
Stop Control, Data Operation
Circuit, 12-bit A/D Converter, 8-
bit D/A Converter
CRC 0x4007_4000 0x4007_40FF 3 2 to 4 PCLKB CRC Calculator
KINT 0x4008_0000 0x4008_00FF 2 2 1 to 3 PCLKB Key Interrupt Function
DOC 0x4008_5F00 0x4008_5FFF 3 3 2 to 4 PCLKB Data Operation Circuit

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R9A02G021 Datasheet Appendix 3. I/O Registers

Table 3.2 Access cycles (2 of 2)

Number of access cycles

Address ICLK = PCLK ICLK > PCLK*1

Cycle
Peripherals From To Read Write Read Write unit Related function

PORGA 0x4009_1000 0x4009_10FF 2 1 to 3 PCLKB Product Organize Register

TRNG 0x4009_1100 0x4009_11FF 3 2 to 4 PCLKB True Random Number Generator
CMP, RTC 0x4009_1200 0x4009_20FF 2 2 1 to 3 PCLKB Comparator, Realtime Clock
REMC, TML32 0x4009_2100 0x4009_22FF 2 1 to 3 PCLKB Remote Control Signal Receiver,
32-bit Interval Timer
IICA, SAU, TAU, 0x4009_3000 0x4009_C0FF 2 1 to 3 PCLKB I2C Bus Interface, Serial Array
UARTA, ADC12 Unit, Timer Array Unit, Serial
Interface UARTA, 12-bit A/D
Converter
FLCN 0x407E_0000 0x407F_FFFF 3 ICLK Temperature Sensor, Flash
Control
CLIC, IMT, DBG 0xE200_0000 0xE680_0FFF 2 ICLK CPU
Note: When accessing the 16-bit register (RDRHL, TDRHL, and CDR), access is 2 cycles more than the value in Table 3.2.
Note 1. If the number of PCLK cycles is non-integer (for example 1.5), the minimum value is without the decimal point, and the maximum
value is rounded up to the decimal point. For example, 1.5 to 2.5 is 1 to 3.
Note 2. These values indicate the minimum numbers of cycles for access by the CPU. They do not include the cycles required for changes
in the source of the ICLK clock and frequency after changes to the SCKSCR and SCKDIVCR registers.
Note 3. When reading the PCNTR2, PIDR, and PmnPFS* registers, access is (setting value of the PRWCNTR register) cycles more than
this value.

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R9A02G021 Datasheet Revision History

Revision History
Revision 1.00 — Nov 15, 2023
Initial release

Revision 1.10 — February 29, 2024

Features:
● Updated information for Connectivity and Timers.
1. Overview:
● Updated Figure 1.1 Block diagram.
2. Electrical Characteristics:
● Updated Table 2.4 I/O VIH, VIL.
● Updated values in the Typ column of Table 2.10 Operating and standby current (1).
● Updated the Note in Table 2.11 Operating and standby current (2).
● Updated Table 2.12 Operating and standby current (3).
● Updated Table 2.56 Code flash characteristics (2).
● Updated Table 2.57 Code flash characteristics (3).
● Updated Table 2.58 Code flash characteristics (4).
● Updated Table 2.60 Data flash characteristics (2).
● Updated Table 2.61 Data flash characteristics (3).
● Updated Table 2.62 Data flash characteristics (4).

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General Precautions in the Handling of Microprocessing Unit and Microcontroller
Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the
products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.

1. Precaution against Electrostatic Discharge (ESD)

A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps
must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be
adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.
Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor
devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.
2. Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of
register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset
pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins
in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the
level at which resetting is specified.
3. Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal
elements. Follow the guideline for input signal during power-off state as described in your product documentation.
4. Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are
generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of
the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
become possible.
5. Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program
execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator
during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal
produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
6. Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the
input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.).
7. Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these
addresses as the correct operation of the LSI is not guaranteed.
8. Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.
The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms
of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,
operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-
evaluation test for the given product.
Notice
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