csci3575lec03 (1)

CSCI3575: EMBEDDED SYSTEMS
TOPIC: GPIO, C++

PROF. HAMID
09/12/2024
METRO MINI 328 DEVELOPMENT BOARD
Digital pins
D0 ~ D13
How do the pins get

their input?
Analog pins
A0 ~ A5
https://www.hackerearth.com/blog/developers/a-tour-of-the-arduino-uno-board/
MICRO-CONTROLLER BLOCK DIAGRAM (OVERSIMPLIFIED)
Reading:
Datasheet,
Section 2 and
6.1,6.2
From which memory

do the pins receive
the inputs intended
for themselves?
AVR CPU CORE [Section 6, pg 09]
 Main function of the CPU Core:

 Correct program execution
 To maximize the performance and parallelism AVR model uses a modified Harvard architecture
 separate buses for program and data
AVR MEMORY
 The AVR architecture has two main memory spaces,

 the data memory (SRAM) and
 the program memory space (FLASH).
 In addition, the ATmega328P features an EEPROM memory for data storage.
 All three memory spaces are linear and regular.

PROGRAM MEMORY (FLASH), Sec 7.2, pg 17
 The program memory is in-system reprogrammable flash

memory.
 Instructions in the program memory (flash) are executed with a
single level pipelining.
 While one instruction is being executed, the next instruction is prefetched from
the program memory.
 This approach enables instructions to be executed in every clock cycle.
PROGRAM MEMORY (FLASH), Sec 7.2, pg 17
 The ATmega328P contains 32Kbytes on-chip in-system

reprogrammable flash memory for program storage.
 All AVR instructions are 16 or 32 bits wide, the flash is organized as

16K*16
 the ATmega328P microcontroller has a 16-bit address bus
 The ATmega328P program counter (PC) is 14 bits wide, thus

addressing the 16K program memory locations.
[214 = 24 ∗ 210 = 16 ∗ 210 = 16𝐾]
32 GENERAL PURPOSE REGISTERS [Section 6.4, pg 12]
 The fast-access register file contains 32 * 8-bit general

purpose working registers with a single clock cycle
access time.
 This allows single-cycle arithmetic logic unit (ALU)
operation.
 The registers R26..R31 have some added functions to
their general purpose usage.
 These registers are 16-bit address pointers for indirect
addressing of the data space.
32 GENERAL PURPOSE REGISTERS [SECTION 6.4, pg 12]
 Each register is also assigned a data

memory address, mapping them directly
into the first 32 locations of the user data
space.
 Although not being physically implemented
as SRAM locations, this memory
organization provides great flexibility
RAM: AVR DATA MEMORY MAP (SRAM, 2KB), Figure 7.2
 The first 32 locations address the register file,

 the next 64 location the standard I/O memory, then
 160 locations of extended I/O memory, and
2048 * 8  the next 2048 locations address the internal data

IO REGISTERS
 Pins are wired to specific bits in I/O registers.

 IO registers are the software-hardware interface.
 This is how your software controls circuits.
2048 * 8
Variables, methods, etc. live in Internal

SRAM
4 SPECIAL PURPOSE REGISTERS
 Program Counter (PC):

 keeps track of the memory address of the next instruction to be executed
 Instruction Register (IR):
 stores the actual instruction
 Status Register(SReg):
 The status register contains information about the result of the most recently executed arithmetic instruction. This information can be
used for altering program flow in order to perform conditional operations. [sec 6.3]
 Stack Pointer(SP):
 The stack is mainly used for storing temporary data, local variables and return addresses after interrupts and subroutine calls.
 The stack pointer points to the data SRAM stack area where the subroutine and interrupt stacks are located.
 The stack is implemented as growing from higher to lower memory locations. The stack pointer register always points to the top of the
stack. [sec 6.5]
PINOUT DIAGRAM
 B port = [PB0~PB5], D8~D13

 C port = [PC0 ~ PC5], D14~D19
 D port = [PD0~PD7], D0~D7
 There are dedicated PORT registers which will

allow lower level and faster manipulation of
the IO pins.
 PORTB, PINB, DDRB
 PORTC, PINC, DDRC
 PORTA, PINA, DDRA
FROM WHICH MEMORY DO THE PINS RECEIVE THE
INPUTS INTENDED FOR THEMSELVES?
IO REGISTERS <INTERNAL SRAM>
EXAMPLES: PORTB, PORTC, ….
C++
DATA TYPES IN C++
Numeric Logical Text
int<4 bytes> bool <1 byte> char <1 byte>

short int <2 bytes> char[] …
float <8 bytes> true [non-zero]
long <8 byte> false [zero]
uint8_t <1 byte>
uint16_t <2 bytes>
https://www.tutorialspoint.com/cplusplus/cpp_data_types.htm
VARIABLES IN C++
FUNCTIONS AND FUNCTION CALLING IN C++
https://www.programiz.com/cpp-programming/online-compiler/
https://www.incredibuild.com/blog/best-c-ides
OPERATORS IN C++
Arithmetic Logical Bitwise

❑ + Addition ❑ && and ❑ & bitwise and
❑ - Subtraction ❑ || or ❑ | bitwise or
❑ * Multiplication ❑ ! not ❑ ~ inversion
❑ / Division ❑ != not equivalent ❑ << left shift
❑ ++ increment by 1 ❑ == equivalent ❑ >> right shift
❑ -- decrement by 1 ❑ > greater than
❑ % modulo ❑ >= greater than or equal to
❑ < smaller than
❑ <= smaller than or equal to
❑ = Assignment
• * pointer
• & reference
LOGICAL AND [&&]
Binary operator, true if both operands are true/non-zero
LOGICAL OR [||], NOT[!]
|| binary operator, true when at least one operand is non-zero
! Unary operator, reverses the input
BIT-WISE OPERATIONS [&]
[A bit of output for each pair of input bits: 1 (true) or 0 (false)]
uint8_t x = 0b1010 & 0b00000011 = 0b________
00001010
& 00000011
----------
0??????0
BIT-WISE OPERATIONS [|]
[A bit of output for each pair of input bits: 1 (true) or 0 (false)]
uint8_t x = 0b1010 | 0b00000011 = 0b________
00001010
| 00000011
----------
0??????1
LOGICAL VS BITWISE
BITWISE OPERATION (LEFT SHIFT)
BITWISE OPERATIONS (RIGHT SHIFT)
LOGICAL AND BITWISE OPERATIONS
LOGICAL AND BITWISE OPERATIONS
 Logical operations are most common in conditionals.

 Bitwise operations are most common for bit masking
(hiding some bits coming through a port/device)
NEXT …
 Reading: Number system [Binary, Decimal, Hexadecimal]

 Quiz 02: Number system and C++ basic instructions
 Lab 03: Input-Output Handling through the GPIO and Number Systems
 Lab 04: Accessing PORT registers

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CSCI3575: EMBEDDED SYSTEMS

TOPIC: GPIO, C++

How do the pins get

From which memory

 Main function of the CPU Core:

 The AVR architecture has two main memory spaces,

 All three memory spaces are linear and regular.

 The program memory is in-system reprogrammable flash

 The ATmega328P contains 32Kbytes on-chip in-system

 All AVR instructions are 16 or 32 bits wide, the flash is organized as

 The ATmega328P program counter (PC) is 14 bits wide, thus

 The fast-access register file contains 32 * 8-bit general

 Each register is also assigned a data

 The first 32 locations address the register file,

2048 * 8  the next 2048 locations address the internal data

 Pins are wired to specific bits in I/O registers.

Variables, methods, etc. live in Internal

 Program Counter (PC):

 B port = [PB0~PB5], D8~D13

 There are dedicated PORT registers which will

Numeric Logical Text

int<4 bytes> bool <1 byte> char <1 byte>

Arithmetic Logical Bitwise

uint8_t x = 0b1010 & 0b00000011 = 0b________

uint8_t x = 0b1010 | 0b00000011 = 0b________

 Logical operations are most common in conditionals.

 Reading: Number system [Binary, Decimal, Hexadecimal]

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