ST72325xx

8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS,

5 timers, SPI, SCI, I2C interface

Features
■ Memories
– 16K to 60K dual voltage High Density Flash
(HDFlash) or up to 32K ROM with read-out LQFP64 LQFP44 LQFP48 LQFP32
protection capability. In-Application Program- 10 x 10 10 x 10 7x7 7x7
ming and In-Circuit Programming for HDFlash
devices
– 512 to 2048 bytes RAM
– HDFlash endurance: 100 cycles, data reten-
tion: 40 years at 85°C
■ Clock, reset and supply management LQFP64 SDIP42 SDIP32
14 x 14 600 mil 400 mil
– Enhanced low voltage supervisor (LVD) for
main supply and auxiliary voltage detector – Configurable watchdog timer
(AVD) with interrupt capability – Two 16-bit timers with: 2 input captures, 2 out-
– Clock sources: crystal/ceramic resonator os- put compares, external clock input on one tim-
cillators, internal RC oscillator and bypass for er, PWM and pulse generator modes
external clock – 8-bit PWM Auto-reload timer with: 2 input cap-
– PLL for 2x frequency multiplication tures, 4 PWM outputs, output compare and
– Four Power Saving Modes: Halt, Active-Halt, time base interrupt, external clock with event
Wait and Slow detector
– Clock Security System ■ 3 Communication interfaces
■ Interrupt management – SPI synchronous serial interface
– Nested interrupt controller – SCI asynchronous serial interface
– 14 interrupt vectors plus TRAP and RESET – I2C multimaster interface
– Top Level Interrupt (TLI) pin on 64-pin devices ■ 1 Analog peripheral (low current coupling)
– 9/6 external interrupt lines (on 4 vectors) – 10-bit ADC with up to 16 robust input ports
■ Up to 48 I/O ports ■ Instruction set
– 48/36/32/24 multifunctional bidirectional I/O – 8-bit Data Manipulation
lines – 63 Basic Instructions
– 34/26/22/17 alternate function lines – 17 main Addressing Modes
– 16/13/12/10 high sink outputs – 8 x 8 Unsigned Multiply Instruction
■ 5 timers ■ Development tools
– Main Clock Controller with: Real time base, – Full hardware/software development package
Beep and Clock-out capabilities – DM (Debug module)
Table 1. Device summary
ST72325R9 /
ST72325S4 / ST72325S6 /
Features ST72325J7 ST72325AR9 /
ST72325J4 / ST72325K4 ST72325J6 / ST72325K6
ST72325C9 /ST72325J9
Program memory - bytes Flash/ROM 16K Flash/ROM 32K Flash 48K Flash 60K
RAM (stack) - bytes 512 (256) 1024(256) 1536 (256) 2048(256)
Operating Voltage 3.8V to 5.5V
Temp. Range up to -40°C to +125°C
LQFP64 14x14(R), LQFP64
LQFP48(S), LQFP44/SDIP42 (J), LQFP48(S) , LQFP44/ SDIP42 (J),
Package LQFP44 (J) 10x10(AR), LQFP48(C),
LQFP32/DIP32 (K) LQFP32/DIP32 (K)
LQFP44 (J)

October 2008 Rev 4 1/197

1
 Table of Contents
1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3.1 Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.7.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3.3 External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3.4 Internal Low Voltage Detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3.5 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4.1 Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4.2 Auxiliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.4.3 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.6.1 I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . . . 43
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
197
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.5.1 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.4 How to Program the Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.1.6 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.1.7 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . . 59
10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.1.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . . 61
10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.3 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.3.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.4.6 Summary of Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

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10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.5.4 Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
10.5.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
10.5.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.5.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.5.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
10.6 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.6.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
10.6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
10.6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
10.6.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
10.7 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
10.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
10.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
10.7.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
10.7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
10.7.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
10.7.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
10.7.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
10.8 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
10.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
10.8.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
10.8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.8.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.8.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
. . . 142
12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

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12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.3.2 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . 145
12.3.3 Auxiliary Voltage Detector (AVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.3.4 External Voltage Detector (EVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.4.1 CURRENT CONSUMPTION ..................................... 146
12.4.2 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.4.3 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
12.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
12.5.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.5.5 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.5.6 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.6.2 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.7.1 Functional EMS (Electro Magnetic Susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . 156
12.7.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.7.3 Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . . . . 158
12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12.9.2 ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.10TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.10.1 8-Bit PWM-ART Auto-Reload Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.10.2 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.11COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 166
12.11.1 SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.11.2 I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.1210-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
12.12.1 Analog Power Supply and Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
12.12.2 General PCB Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
12.12.3 ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

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13.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
14 ST72325 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . 181
14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 183
14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
14.3.1 Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
14.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
14.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
14.3.4 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
15 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
15.1 ALL DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
15.1.1 Unexpected Reset Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
15.1.2 External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
15.1.3 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . . . . . . . 193
15.1.4 SCI Wrong Break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.1.5 16-bit Timer PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.1.6 TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.1.7 I2C Multimaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.1.8 Pull-up always active on PE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
15.1.9 ADC accuracy 16/32K Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

197

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 ST72325xx

1 DESCRIPTION HALT mode when the application is in idle or

stand-by state.
The ST72F325 Flash and ST72325 ROM devices
are members of the ST7 microcontroller family de- Typical applications are consumer, home, office
signed for mid-range applications. and industrial products.
They are derivatives of the ST72321 and ST72324 The devices feature an on-chip Debug Module
devices, with enhanced characteristics and robust (DM) to support in-circuit debugging (ICD). For a
Clock Security System. description of the DM registers, refer to the ST7
ICC Protocol Reference Manual.
All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc- Main Differences with ST72321:
tion set and are available with Flash or ROM pro- – LQFP48 and LQFP32 packages
gram memory. The ST7 family architecture offers – Clock Security System
both power and flexibility to software developers,
enabling the design of highly efficient and compact – Internal RC, Readout protection, LVD and PLL
application code. without limitations
The on-chip peripherals include an A/D converter, – Negative current injection not allowed on I/O port
a PWM Autoreload timer, 2 general purpose tim- PB0 (instead of PC6).
ers, I2C bus, SPI interface and an SCI interface. – External interrupts have Exit from Active Halt
For power economy, microcontroller can switch mode capability.
dynamically into WAIT, SLOW, ACTIVE-HALT or
Figure 1. Device Block Diagram

8-BIT CORE PROGRAM

ALU MEMORY
(16K - 60K Bytes1))
RESET
CONTROL
VPP
RAM
TLI
VSS (512 - 2048 Bytes1))
VDD LVD

EVD AVD WATCHDOG

OSC1
OSC DEBUG MODULE
OSC2
ADDRESS AND DATA BUS

MCC/RTC/BEEP
I2C
PA7:0
(8 bits on AR devices)
PORT F PORT A (5 bits on C/J devices)
PF7:0 (4 bits on K devices)
(8 bits on AR devices)
(6 bits on C/J devices) TIMER A
PORT B
(5 bits on K devices)
PB7:0
BEEP (8 bits on AR devices)
PWM ART (5 bits on C/J devices)
(3 bits on K devices)
PORT E
PE7:0 PORT C
(8 bits on AR devices)
(2 bits on C/J/K devices) SCI
TIMER B PC7:0
(8 bits)
PORT D
PD7:0 SPI
(8 bits on AR devices)
(6 bits on C/J devices) 10-BIT ADC
(2 bits on K devices)
VAREF
VSSA
1) ROM devices have up to 32 Kbytes of program memory and up to 1 Kbyte of RAM.

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ST72325xx

2 PIN DESCRIPTION
Figure 2. 64-Pin LQFP 14x14 and 10x10 Package Pinout

PA6 (HS) / SDAI

PA7 (HS) / SCLI
VPP / ICCSEL
PE0 / TDO
PE1 / RDI

PA5 (HS)
PA4 (HS)
RESET
VDD_2

VSS_2
OSC1
OSC2

EVD
PE3
PE2

TLI
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
(HS) PE4 1 48 VSS_1
(HS) PE5 2 47 VDD_1
(HS) PE6 3 46 PA3 (HS)
(HS) PE7 4 45 PA2
ei0
PWM3 / PB0 5 44 PA1
PWM2 / PB1 6 43 PA0
PWM1 / PB2 ei2 42 PC7 / SS / AIN15
7
PWM0 / PB3 8 41 PC6 / SCK / ICCCLK
ARTCLK / (HS) PB4 9 40 PC5 / MOSI / AIN14
ARTIC1 / PB5 10 39 PC4 / MISO / ICCDATA
ARTIC2 / PB6 11 ei3 38 PC3 (HS) / ICAP1_B
PB7 12 37 PC2 (HS) / ICAP2_B
AIN0 / PD0 13 36 PC1 / OCMP1_B / AIN13
AIN1 / PD1 14 35 PC0 / OCMP2_B / AIN12
AIN2 / PD2 15 ei1 34 VSS_0
AIN3 / PD3 16 33 VDD_0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
BEEP / (HS) PF1

EXTCLK_A / (HS) PF7

VSSA
VDD_3
VSS_3

OCMP2_A / AIN9 / PF3

ICAP2_A / AIN11 / PF5

AIN4 / PD4
AIN5 / PD5
AIN6 / PD6
AIN7 / PD7

MCO / AIN8 / PF0

(HS) PF2

OCMP1_A / AIN10 / PF4

ICAP1_A / (HS) PF6

VAREF

(HS) 20mA high sink capability

eix associated external interrupt vector

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 ST72325xx

Figure 3. 48-Pin LQFP 7x7 Device Pinout

PA6 (HS) / SDAI

PA7 (HS) / SCLI
VPP/ICCSEL
PE0 / TDO
PE1/ RDI

PA5 (HS)
PA4 (HS)
RESET
VDD_2

VSS_2
OSC1
OSC2
48 47 46 45 44 43 42 41 40 39 38 37
PE2 1 36 VSS_1
(HS) PE4 2 35 VDD_1
PWM3 / PB0 3 34 PA3 (HS)
PWM2 / PB1 ei2 PA2
4 33
PWM1 / PB2 5 32 PC7 / SS / AIN15
PWM0 / PB3 6 ei3 ei0 31 PC6 / SCK / ICCCLK
ARTCLK / (HS) PB4 7 30 PC5 / MOSI / AIN14
ARTIC1 / PB5 8 29 PC4 / MISO / ICCDATA
AIN0 / PD0 9 28 PC3 (HS) / ICAP1_B
AIN1 / PD1 10 27 PC2 (HS) / ICAP2_B
AIN3 / PD2 11 26 PC1 / OCMP1_B / AIN13
ei1
AIN4 / PD3 12 25 PC0 / OCMP2_B / AIN12
13 14 15 16 17 18 19 20 21 22 23 24
OCMP1_A / AIN10 / PF4
BEEP / (HS) PF1

EXTCLK_A / (HS) PF7

VSSA
AIN4 / PD4
AIN5 / PD5

MCO / AIN8 / PF0

(HS) PF2

ICAP1_A / (HS) PF6

VAREF

VDD_0
VSS_0

Legend
(HS) 20mA high sink capability
= Pin not connected in ST72325S devices
eix associated external interrupt vector

Caution: 48-pin ‘C’ devices have unbonded pins that require software initialization. Refer
to Note 4 on page 16 for details on initializing the I/O registers for these devices.

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ST72325xx

Figure 4. 44/42-Pin LQFP Package Pinouts

PA6 (HS) / SDAI

PA7 (HS) / SCLI
VPP / ICCSEL
PE0 / TDO

PA5 (HS)
PA4 (HS)
RESET
VDD_2

VSS_2
OSC1
OSC2
44 43 42 41 40 39 38 37 36 35 34
RDI / PE1 1 33 VSS_1
PB0 2 32 VDD_1
PB1 3 ei0 31 PA3 (HS)
ei2
PB2 4 30 PC7 / SS / AIN15
PB3 5 29 PC6 / SCK / ICCCLK
(HS) PB4 6 ei3 28 PC5 / MOSI / AIN14
AIN0 / PD0 7 27 PC4 / MISO / ICCDATA
AIN1 / PD1 8 26 PC3 (HS) / ICAP1_B
AIN2 / PD2 9 25 PC2 (HS) / ICAP2_B
AIN3 / PD3 10 ei1 24 PC1 / OCMP1_B / AIN13
AIN4 / PD4 11 23 PC0 / OCMP2_B / AIN12
12 13 14 15 16 17 18 19 20 21 22
VSSA

BEEP / (HS) PF1

ICAP1_A / (HS) PF6

VDD_0
VSS_0
AIN5 / PD5

MCO / AIN8 / PF0

(HS) PF2
OCMP1_A / AIN10 / PF4

EXTCLK_A / (HS) PF7

VAREF

(HS) PB4 1 ei3 42 PB3

AIN0 / PD0 2 41 PB2
AIN1 / PD1 3 ei2 PB1
40
AIN2 / PD2 4 39 PB0
AIN3 / PD3 5 38 PE1 / RDI
AIN4 / PD4 6 37 PE0 / TDO
AIN5 / PD5 7 36 VDD_2
VAREF 8 35 OSC1
VSSA 9 34 OSC2
MCO / AIN8 / PF0 10 33 VSS_2
BEEP / (HS) PF1 11 ei1 32 RESET
(HS) PF2 12 31 VPP / ICCSEL
AIN10 / OCMP1_A / PF4 13 30 PA7 (HS) / SCLI
ICAP1_A / (HS) PF6 14 29 PA6 (HS) / SDAI
EXTCLK_A / (HS) PF7 15 28 PA5 (HS)
AIN12 / OCMP2_B / PC0 16 27 PA4 (HS)
AIN13 / OCMP1_B / PC1 17 26 VSS_1
ICAP2_B/ (HS) PC2 18 25 VDD_1
ICAP1_B / (HS) PC3 19 ei0 24 PA3 (HS)
ICCDATA / MISO / PC4 20 23 PC7 / SS / AIN15
AIN14 / MOSI / PC5 21 22 PC6 / SCK / ICCCLK
(HS) 20mA high sink capability
eix associated external interrupt vector

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 ST72325xx

Figure 5. 32-Pin LQFP/DIP Package Pinouts

PB4 (HS) / ARTCLK

PB3 / PWM0
PB0 / PWM3
PD1 / AIN1
PD0 / AIN0

PE0 / TDO
PE1 / RDI

VDD_2
32 31 30 29 28 27 26 25
VAREF 1 24 OSC1
ei3 ei2
VSSA 2 23 OSC2
MCO / AIN8 / PF0 3 22 VSS_2
ei1
BEEP / (HS) PF1 4 21 RESET
OCMP1_A / AIN10 / PF4 5 20 VPP / ICCSEL
ICAP1_A / (HS) PF6 6 19 PA7 (HS)/SCLI
EXTCLK_A / (HS) PF7 7 18 PA6 (HS) / SDAI
AIN12 / OCMP2_B / PC0 8 ei0 17 PA4 (HS)
9 10 11 12 13 14 15 16
ICCDATA / MISO / PC4

(HS) PA3
AIN13 / OCMP1_B / PC1
ICAP2_B / (HS) PC2
ICAP1_B / (HS) PC3

AIN14 / MOSI / PC5

ICCCLK / SCK / PC6
AIN15 / SS / PC7

(HS) PB4 1 PB3

ei3 32
AIN0 / PD0 ei2 PB0
2 31
AIN1 / PD1 3 30 PE1 / RDI
VAREF 4 29 PE0 / TDO
VSSA 5 28 VDD_2
MCO / AIN8 / PF0 6 27 OSC1
ei1
BEEP / (HS) PF1 7 26 OSC2
OCMP1_A / AIN10 / PF4 8 25 VSS_2
ICAP1_A / (HS) PF6 9 24 RESET
EXTCLK_A / (HS) PF7 10 23 VPP / ICCSEL
AIN12 / OCMP2_B / PC0 11 22 PA7 (HS) / SCLI
AIN13 / OCMP1_B / PC1 12 21 PA6 (HS) / SDAI
ICAP2_B / (HS) PC2 13 20 PA4 (HS)
ICAP1_B / (HS) PC3 14 ei0 19 PA3 (HS)
ICCDATA/ MISO / PC4 15 18 PC7 / SS / AIN15
AIN14 / MOSI / PC5 16 17 PC6 / SCK / ICCCLK
(HS) 20mA high sink capability
eix associated external interrupt vector

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ST72325xx

PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 142.
Legend / Abbreviations for Table 2 and Table 3:
Type: I = input, O = output, S = supply
Input level: A = Dedicated analog input
In/Output level: C = CMOS 0.3VDD/0.7VDD
CT= CMOS 0.3VDD/0.7VDD with input trigger
Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration:
– Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog
– Output: OD = open drain 2), PP = push-pull
Refer to “I/O PORTS” on page 50 for more details on the software configuration of the I/O ports.
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.
= Pin not connected in ST72325S devices

Table 2. LQFP64/48/44 and SDIP42 Device Pin Descriptions

Pin n° Level Port
Main
LQFP48C

Type
LQFP48S

Output function
LQFP64

LQFP44

Input
SDIP42

Output

Pin Name Alternate function

Input

(after
float
wpu

ana

reset)
OD
PP
int

1 2 - - - PE4 (HS) I/O CT HS X X X X Port E4

2 -4) - - - PE5 (HS) I/O CT HS X X X X Port E5
3 -4) - - - PE6 (HS) I/O CT HS X X X X Port E6
4)
4 - - - - PE7 (HS) I/O CT HS X X X X Port E7
PWM Output 3

5 3 3 2 39 PB0/PWM3 I/O CT X ei2 X X Port B0 Caution: Negative cur-

rent injection not al-
lowed on this pin
6 4 4 3 40 PB1/PWM2 I/O CT X ei2 X X Port B1 PWM Output 2
7 5 5 4 41 PB2/PWM1 I/O CT X ei2 X X Port B2 PWM Output 1
8 6 6 5 42 PB3/PWM0 I/O CT X ei2 X X Port B3 PWM Output 0
PWM-ART External
9 7 7 6 1 PB4 (HS)/ARTCLK I/O CT HS X ei3 X X Port B4
Clock
PWM-ART Input Cap-
10 8 - - - PB5 / ARTIC1 I/O CT X ei3 X X Port B5
ture 1
PWM-ART Input Cap-
11 -4) - - - PB6 / ARTIC2 I/O CT X ei3 X X Port B6
ture 2
12 -4) - - - PB7 I/O CT X ei3 X X Port B7
13 9 9 7 2 PD0/AIN0 I/O CT X X X X X Port D0 ADC Analog Input 0
14 19 10 8 3 PD1/AIN1 I/O CT X X X X X Port D1 ADC Analog Input 1
15 11 11 9 4 PD2/AIN2 I/O CT X X X X X Port D2 ADC Analog Input 2
16 12 12 10 5 PD3/AIN3 I/O CT X X X X X Port D3 ADC Analog Input 3

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 ST72325xx

Pin n° Level Port

Main
LQFP48C

Type
LQFP48S

function
LQFP64

LQFP44
Input Output
SDIP42

Output
Pin Name Alternate function

Input
(after

float
wpu

ana
reset)

OD
PP
int
17 13 13 11 6 PD4/AIN4 I/O CT X X X X X Port D4 ADC Analog Input 4
18 14 14 12 7 PD5/AIN5 I/O CT X X X X X Port D5 ADC Analog Input 5
4)
19 - - - - PD6/AIN6 I/O CT X X X X X Port D6 ADC Analog Input 6
20 -4) - - - PD7/AIN7 I/O CT X X X X X Port D7 ADC Analog Input 7
Analog Reference Voltage for
21 15 15 13 8 VAREF6) I
ADC
22 16 16 14 9 VSSA6) S Analog Ground Voltage
23 - - - - VDD_36) S Digital Main Supply Voltage
24 - - - - VSS_36) S Digital Ground Voltage
ADC Ana-
Main clock
25 17 17 15 10 PF0/MCO/AIN8 I/O CT X ei1 X X X Port F0 log
out (fOSC/2)
Input 8
26 18 18 16 11 PF1 (HS)/BEEP I/O CT HS X ei1 X X Port F1 Beep signal output
27 19 19 17 12 PF2 (HS) I/O CT HS X ei1 X X Port F2
Timer A ADC Ana-
PF3/OCMP2_A/
28 -4) - - - I/O CT X X X X X Port F3 Output log
AIN9
Compare 2 Input 9
Timer A ADC Ana-
PF4/OCMP1_A/
29 20 20 18 13 I/O CT X X X X X Port F4 Output log
AIN10
Compare 1 Input 10
Timer A In- ADC Ana-
PF5/ICAP2_A/
30 -4) - - - I/O CT X X X X X Port F5 put Cap- log
AIN11
ture 2 Input 11
31 21 21 19 14 PF6 (HS)/ICAP1_A I/O CT HS X X X X Port F6 Timer A Input Capture 1
PF7 (HS)/ Timer A External Clock
32 22 22 20 15 I/O CT HS X X X X Port F7
EXTCLK_A Source
33 23 23 21 - VDD_06) S Digital Main Supply Voltage
6)
34 24 24 22 - VSS_0 S Digital Ground Voltage
Timer B ADC Ana-
PC0/OCMP2_B/
35 25 25 23 16 I/O CT X X X X X Port C0 Output log
AIN12
Compare 2 Input 12
Timer B ADC Ana-
PC1/OCMP1_B/
36 26 26 24 17 I/O CT X X X X X Port C1 Output log
AIN13
Compare 1 Input 13
37 27 27 25 18 PC2 (HS)/ICAP2_B I/O CT HS X X X X Port C2 Timer B Input Capture 2
38 28 28 26 19 PC3 (HS)/ICAP1_B I/O CT HS X X X X Port C3 Timer B Input Capture 1
SPI Master
PC4/MISO/ICCDA- ICC Data
39 29 29 27 20 I/O CT X X X X Port C4 In / Slave
TA Input
Out Data
SPI Master ADC Ana-
40 30 30 28 21 PC5/MOSI/AIN14 I/O CT X X X X X Port C5 Out / Slave log
In Data Input 14
SPI Serial ICC Clock
41 31 31 29 22 PC6/SCK/ICCCLK I/O CT X X X X Port C6
Clock Output

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ST72325xx

Pin n° Level Port

Main
LQFP48C

Type
LQFP48S

function
LQFP64

LQFP44
Input Output
SDIP42

Output
Pin Name Alternate function

Input
(after

float
wpu

ana
reset)

OD
PP
int
SPI Slave ADC Ana-
42 32 32 30 23 PC7/SS/AIN15 I/O CT X X X X X Port C7 Select (ac- log
tive low) Input 15
43 -4) - - - PA0 I/O CT X ei0 X X Port A0
44 -4) - - - PA1 I/O CT X ei0 X X Port A1
45 33 - - - PA2 I/O CT X ei0 X X Port A2
46 34 34 31 24 PA3 (HS) I/O CT HS X ei0 X X Port A3
47 35 35 32 25 VDD_16) S Digital Main Supply Voltage
48 36 36 33 26 VSS_1 6) S Digital Ground Voltage
49 37 37 34 27 PA4 (HS) I/O CT HS X X X X Port A4
50 38 38 35 28 PA5 (HS) I/O CT HS X X X X Port A5
51 39 39 36 29 PA6 (HS)/SDAI I/O CT HS X T Port A6 I2C Data 1)
52 40 40 37 30 PA7 (HS)/SCLI I/O CT HS X T Port A7 I2C Clock 1)
Must be tied low. In flash program-
ming mode, this pin acts as the
programming voltage input VPP.
53 41 41 38 31 VPP/ ICCSEL I
See Section 12.9.2 for more de-
tails. High voltage must not be ap-
plied to ROM devices
Top priority non maskable inter-
54 42 42 39 32 RESET I/O CT
rupt.
55 - - - - EVD External voltage detector
56 - - - - TLI I CT X Top level interrupt input pin
57 43 43 40 33 VSS_26) S Digital Ground Voltage
Resonator oscillator inverter out-
58 44 44 41 34 OSC23) I/O
put
External clock input or Resonator
59 45 45 42 35 OSC13) I
oscillator inverter input
60 46 46 43 36 VDD_26) S Digital Main Supply Voltage
61 47 47 44 37 PE0/TDO I/O CT X X X X Port E0 SCI Transmit Data Out
62 48 48 1 38 PE1/RDI I/O CT X X X X Port E1 SCI Receive Data In
63 1 - - - PE2 I/O CT X X X4) X4) Port E2
64 -4) - - - PE3 I/O CT X X X X Port E3

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 ST72325xx

Table 3. LQFP32/DIP32 Device Pin Description

Pin n° Level Port
Main

Type
function
LQFP32

Input Output

Output
Pin Name Alternate function
DIP32

Input
(after

float
wpu

ana
reset)

OD

PP
int
1 4 VAREF6) I Analog Reference Voltage for ADC
6)
2 5 VSSA S Analog Ground Voltage
Main clock out ADC Analog
3 6 PF0/MCO/AIN8 I/O CT X ei1 X X X Port F0
(fOSC/2) Input 8
4 7 PF1 (HS)/BEEP I/O CT HS X ei1 X X Port F1 Beep signal output
PF4/OCMP1_A/ Timer A Output ADC Analog
5 8 I/O CT X X X X X Port F4
AIN10 Compare 1 Input 10
6 9 PF6 (HS)/ICAP1_A I/O CT HS X X X X Port F6 Timer A Input Capture 1
PF7 (HS)/
7 10 I/O CT HS X X X X Port F7 Timer A External Clock Source
EXTCLK_A
PC0/OCMP2_B/ Timer B Output ADC Analog
8 11 I/O CT X X X X X Port C0
AIN12 Compare 2 Input 12
PC1/OCMP1_B/ Timer B Output ADC Analog
9 12 I/O CT X X X X X Port C1
AIN13 Compare 1 Input 13
10 13 PC2 (HS)/ICAP2_B I/O CT HS X X X X Port C2 Timer B Input Capture 2
11 14 PC3 (HS)/ICAP1_B I/O CT HS X X X X Port C3 Timer B Input Capture 1
PC4/MISO/ICCDA- SPI Master In /
12 15 I/O CT X X X X Port C4 ICC Data Input
TA Slave Out Data
SPI Master Out / ADC Analog
13 16 PC5/MOSI/AIN14 I/O CT X X X X X Port C5
Slave In Data Input 14
ICC Clock
14 17 PC6/SCK/ICCCLK I/O CT X X X X Port C6 SPI Serial Clock
Output
SPI Slave Select ADC Analog
15 18 PC7/SS/AIN15 I/O CT X X X X X Port C7
(active low) Input 15
16 19 PA3 (HS) I/O CT HS X ei0 X X Port A3
17 20 PA4 (HS) I/O CT HS X X X X Port A4
18 21 PA6 (HS)/SDAI I/O CT HS X T Port A6 I2C Data 1)
19 22 PA7 (HS)/SCLI I/O CT HS X T Port A7 I2C Clock 1)
Must be tied low. In flash programming
mode, this pin acts as the programming
20 23 VPP/ ICCSEL I voltage input VPP. See Section 12.9.2 for
more details. High voltage must not be ap-
plied to ROM devices
21 24 RESET I/O CT Top priority non maskable interrupt.
22 25 VSS_2 6) S Digital Ground Voltage
23 26 OSC23) I/O Resonator oscillator inverter output
External clock input or Resonator oscillator
24 27 OSC13) I
inverter input
25 28 VDD_26) S Digital Main Supply Voltage
26 29 PE0/TDO I/O CT X X X X Port E0 SCI Transmit Data Out
27 30 PE1/RDI I/O CT X X X X Port E1 SCI Receive Data In

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ST72325xx

Pin n° Level Port

Main

Type
function
LQFP32

Input Output

Output
Pin Name Alternate function
DIP32

Input
(after

float
wpu

ana
reset)

OD

PP
int
PWM Output 3
28 31 PB0/PWM3 I/O CT X ei2 X X Port B0 Caution: Negative current injec-
tion not allowed on this pin
29 32 PB3/PWM0 I/O CT X ei2 X X Port B3 PWM Output 0
30 1 PB4 (HS)/ARTCLK I/O CT HS X ei3 X X Port B4 PWM-ART External Clock
31 2 PD0/AIN0 I/O CT X X X X X Port D0 ADC Analog Input 0
32 3 PD1/AIN1 I/O CT X X X X X Port D1 ADC Analog Input 1

Notes for Table 2 and Table 3:

1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD
are not implemented). See See “I/O PORTS” on page 50. and Section 12.8 I/O PORT PIN CHARACTER-
ISTICS for more details.
3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscil-
lator; see Section 1 DESCRIPTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for
more details.
4. On the chip, each I/O port may have up to 8 pads:
– In all devices except 48-pin ST72325C, pads that are not bonded to external pins are forced by hardware
in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to
avoid added current consumption.
– In 48-pin ST72325C devices, unbonded pads PA0, PA1, PB6, PB7, PD6, PD7, PE3, PE5, PE6, PE7,
PF3 and PF5) are in input floating configuration after reset. To avoid added current consumption, the
application must force these ports in input pull-up state by writing to the OR and DDR registers after re-
set. This initialization is not necessary in 48-pin ST72325S devices.
5. Pull-up always activated on PE2 see limitation Section 15.1.8.
6. It is mandatory to connect all available VDD and VREF pins to the supply voltage and all VSS and VSSA
pins to ground.

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 ST72325xx

3 REGISTER & MEMORY MAP

As shown in Figure 6, the MCU is capable of ad- IMPORTANT: Memory locations marked as “Re-
dressing 64K bytes of memories and I/O registers. served” must never be accessed. Accessing a re-
The available memory locations consist of 128 seved area can have unpredictable effects on the
bytes of register locations, up to 2Kbytes of RAM device.
and up to 60Kbytes of user program memory. The Related Documentation
RAM space includes up to 256 bytes for the stack AN 985: Executing Code in ST7 RAM
from 0100h to 01FFh.
The highest address bytes contain the user reset
and interrupt vectors.
Figure 6. Memory Map

0000h 0080h
HW Registers
Short Addressing
(see Table 4)
007Fh RAM (zero page)
0080h 00FFh
0100h
RAM 256 Bytes Stack
(2048, 1536, 1024,
01FFh
or 512 Bytes) 1000h
0200h 60 KBytes
087Fh 16-bit Addressing
0880h
Reserved RAM 4000h
027Fh 48 KBytes
0FFFh
1000h or 047Fh
or 067Fh 8000h
Program Memory 32 KBytes
or 087Fh
(60,48, 32 or 16K) C000h
FFDFh 16 KBytes
FFE0h
Interrupt & Reset Vectors
(see Table 9) FFFFh
FFFFh

17/197
ST72325xx

Table 4. Hardware Register Map

Register Reset
Address Block Register Name Remarks
Label Status

0000h PADR Port A Data Register 00h1) R/W

0001h Port A PADDR Port A Data Direction Register 00h R/W
0002h PAOR Port A Option Register 00h R/W

0003h PBDR Port B Data Register 00h1) R/W

0004h Port B PBDDR Port B Data Direction Register 00h R/W
0005h PBOR Port B Option Register 00h R/W

0006h PCDR Port C Data Register 00h1) R/W

0007h Port C PCDDR Port C Data Direction Register 00h R/W
0008h PCOR Port C Option Register 00h R/W

0009h PDDR Port D Data Register 00h1) R/W

000Ah Port D PDDDR Port D Data Direction Register 00h R/W
000Bh PDOR Port D Option Register 00h R/W

000Ch PEDR Port E Data Register 00h1) R/W

000Dh Port E PEDDR Port E Data Direction Register 00h R/W2)
000Eh PEOR Port E Option Register 00h R/W2)

000Fh PFDR Port F Data Register 00h1) R/W

0010h Port F PFDDR Port F Data Direction Register 00h R/W
0011h PFOR Port F Option Register 00h R/W

0018h I2CCR I2C Control Register 00h R/W

0019h I2CSR1 I2C Status Register 1 00h Read Only
001Ah I2CSR2 I2C Status Register 2 00h Read Only
001Bh I 2C I2CCCR I2C Clock Control Register 00h R/W
001Ch I2COAR1 I2C Own Address Register 1 00h R/W
001Dh I2COAR2 I2C Own Address Register2 00h R/W
001Eh I2CDR I2C Data Register 00h R/W

001Fh
Reserved Area (2 Bytes)
0020h

0021h SPIDR SPI Data I/O Register xxh R/W

0022h SPI SPICR SPI Control Register 0xh R/W
0023h SPICSR SPI Control/Status Register 00h R/W

0024h ISPR0 Interrupt Software Priority Register 0 FFh R/W

0025h ISPR1 Interrupt Software Priority Register 1 FFh R/W
0026h ISPR2 Interrupt Software Priority Register 2 FFh R/W
ITC
0027h ISPR3 Interrupt Software Priority Register 3 FFh R/W

0028h EICR External Interrupt Control Register 00h R/W

0029h FLASH FCSR Flash Control/Status Register 00h R/W

002Ah WATCHDOG WDGCR Watchdog Control Register 7Fh R/W

002Bh SICSR System Integrity Control/Status Register 000x 000x b R/W

18/197
 ST72325xx

Register Reset
Address Block Register Name Remarks
Label Status

002Ch MCCSR Main Clock Control / Status Register 00h R/W

MCC
002Dh MCCBCR Main Clock Controller: Beep Control Register 00h R/W

002Eh
to Reserved Area (3 Bytes)
0030h

0031h TACR2 Timer A Control Register 2 00h R/W

0032h TACR1 Timer A Control Register 1 00h R/W
0033h TACSR Timer A Control/Status Register xxxx x0xx b R/W
0034h TAIC1HR Timer A Input Capture 1 High Register xxh Read Only
0035h TAIC1LR Timer A Input Capture 1 Low Register xxh Read Only
0036h TAOC1HR Timer A Output Compare 1 High Register 80h R/W
0037h TAOC1LR Timer A Output Compare 1 Low Register 00h R/W
0038h TIMER A TACHR Timer A Counter High Register FFh Read Only
0039h TACLR Timer A Counter Low Register FCh Read Only
003Ah TAACHR Timer A Alternate Counter High Register FFh Read Only
003Bh TAACLR Timer A Alternate Counter Low Register FCh Read Only
003Ch TAIC2HR Timer A Input Capture 2 High Register xxh Read Only
003Dh TAIC2LR Timer A Input Capture 2 Low Register xxh Read Only
003Eh TAOC2HR Timer A Output Compare 2 High Register 80h R/W
003Fh TAOC2LR Timer A Output Compare 2 Low Register 00h R/W

0040h Reserved Area (1 Byte)

0041h TBCR2 Timer B Control Register 2 00h R/W

0042h TBCR1 Timer B Control Register 1 00h R/W
0043h TBCSR Timer B Control/Status Register xxxx x0xx b R/W
0044h TBIC1HR Timer B Input Capture 1 High Register xxh Read Only
0045h TBIC1LR Timer B Input Capture 1 Low Register xxh Read Only
0046h TBOC1HR Timer B Output Compare 1 High Register 80h R/W
0047h TBOC1LR Timer B Output Compare 1 Low Register 00h R/W
0048h TIMER B TBCHR Timer B Counter High Register FFh Read Only
0049h TBCLR Timer B Counter Low Register FCh Read Only
004Ah TBACHR Timer B Alternate Counter High Register FFh Read Only
004Bh TBACLR Timer B Alternate Counter Low Register FCh Read Only
004Ch TBIC2HR Timer B Input Capture 2 High Register xxh Read Only
004Dh TBIC2LR Timer B Input Capture 2 Low Register xxh Read Only
004Eh TBOC2HR Timer B Output Compare 2 High Register 80h R/W
004Fh TBOC2LR Timer B Output Compare 2 Low Register 00h R/W

0050h SCISR SCI Status Register C0h Read Only

0051h SCIDR SCI Data Register xxh R/W
0052h SCIBRR SCI Baud Rate Register 00h R/W
0053h SCICR1 SCI Control Register 1 x000 0000b R/W
SCI
0054h SCICR2 SCI Control Register 2 00h R/W
0055h SCIERPR SCI Extended Receive Prescaler Register 00h R/W
0056h Reserved area ---
0057h SCIETPR SCI Extended Transmit Prescaler Register 00h R/W

19/197
ST72325xx

Register Reset
Address Block Register Name Remarks
Label Status

0058h DMCR DM Control Register 00h R/W

0059h DMSR DM Status Register 00h R/W
005Ah DMBK1H DM Breakpoint Register 1 High 00h R/W
DM3)
005Bh DMBK1L DM Breakpoint Register 1 Low 00h R/W
005Ch DMBK2H DM Breakpoint Register 2 High 00h R/W
005Dh DMBK2L DM Breakpoint Register 2 Low 00h R/W

005Eh
to Reserved Area (18 Bytes)
006Fh

0070h ADCCSR Control/Status Register 00h R/W

0071h ADC ADCDRH Data High Register 00h Read Only
0072h ADCDRL Data Low Register 00h Read Only

0073h PWMDCR3 PWM AR Timer Duty Cycle Register 3 00h R/W

0074h PWMDCR2 PWM AR Timer Duty Cycle Register 2 00h R/W
0075h PWMDCR1 PWM AR Timer Duty Cycle Register 1 00h R/W
0076h PWMDCR0 PWM AR Timer Duty Cycle Register 0 00h R/W
0077h PWMCR PWM AR Timer Control Register 00h R/W
0078h PWM ART ARTCSR Auto-Reload Timer Control/Status Register 00h R/W
0079h ARTCAR Auto-Reload Timer Counter Access Register 00h R/W
007Ah ARTARR Auto-Reload Timer Auto-Reload Register 00h R/W
007Bh ARTICCSR AR Timer Input Capture Control/Status Reg. 00h R/W
007Ch ARTICR1 AR Timer Input Capture Register 1 00h Read Only
007Dh ARTICR2 AR Timer Input Capture Register 1 00h Read Only

007Eh
Reserved Area (2 Bytes)
007Fh

Legend: x=undefined, R/W=read/write

Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
3. For a description of the Debug Module registers, see ICC Protocol Reference manual.

20/197
 ST72325xx

4 FLASH PROGRAM MEMORY

4.1 Introduction Depending on the overall Flash memory size in the

microcontroller device, there are up to three user
The ST7 dual voltage High Density Flash sectors (see Table 5). Each of these sectors can
(HDFlash) is a non-volatile memory that can be be erased independently to avoid unnecessary
electrically erased as a single block or by individu- erasing of the whole Flash memory when only a
al sectors and programmed on a Byte-by-Byte ba- partial erasing is required.
sis using an external VPP supply.
The first two sectors have a fixed size of 4 Kbytes
The HDFlash devices can be programmed and (see Figure 7). They are mapped in the upper part
erased off-board (plugged in a programming tool) of the ST7 addressing space so the reset and in-
or on-board using ICP (In-Circuit Programming) or terrupt vectors are located in Sector 0 (F000h-
IAP (In-Application Programming). FFFFh).
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting Table 5. Sectors available in Flash devices
other sectors.
Flash Size (bytes) Available Sectors

4.2 Main Features 4K Sector 0

8K Sectors 0,1
■ Three Flash programming modes:
> 8K Sectors 0,1, 2
– Insertion in a programming tool. In this mode,
all sectors including option bytes can be pro-
grammed or erased. 4.3.1 Read-out Protection
– ICP (In-Circuit Programming). In this mode, all Read-out protection, when selected, provides a
sectors including option bytes can be pro-
grammed or erased without removing the de- protection against Program Memory content ex-
vice from the application board. traction and against write access to Flash memo-
– IAP (In-Application Programming) In this ry. Even if no protection can be considered as to-
mode, all sectors except Sector 0, can be pro- tally unbreakable, the feature provides a very high
grammed or erased without removing the de- level of protection for a general purpose microcon-
vice from the application board and while the troller.
application is running.
■ ICT (In-Circuit Testing) for downloading and In flash devices, this protection is removed by re-
executing user application test patterns in RAM programming the option. In this case, the entire
program memory is first automatically erased and
■ Read-out protection the device can be reprogrammed.
■ Register Access Security System (RASS) to
prevent accidental programming or erasing Read-out protection selection depends on the de-
vice type:
– In Flash devices it is enabled and removed
4.3 Structure
through the FMP_R bit in the option byte.
The Flash memory is organised in sectors and can – In ROM devices it is enabled by mask option
be used for both code and data storage. specified in the Option List.

Figure 7. Memory Map and Sector Address

4K 8K 10K 16K 24K 32K 48K 60K FLASH
1000h MEMORY SIZE
3FFFh
7FFFh
9FFFh
SECTOR 2
BFFFh
D7FFh
2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes 52 Kbytes
DFFFh
EFFFh
4 Kbytes SECTOR 1
FFFFh
4 Kbytes SECTOR 0

21/197
ST72325xx

FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC Interface – ICCCLK: ICC output serial clock pin

– ICCDATA: ICC input/output serial data pin
ICC needs a minimum of 4 and up to 6 pins to be
connected to the programming tool (see Figure 8). – ICCSEL/VPP: programming voltage
These pins are: – OSC1(or OSCIN): main clock input for exter-
nal source (optional)
– RESET: device reset – VDD: application board power supply (option-
– VSS: device power supply ground al, see Figure 8, Note 3)
Figure 8. Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR

ICC Cable
APPLICATION BOARD

(See Note 3) ICC CONNECTOR

OPTIONAL HE10 CONNECTOR TYPE
(See Note 4) 9 7 5 3 1

10 8 6 4 2
APPLICATION
RESET SOURCE
See Note 2

10kΩ

APPLICATION CL2 CL1

POWER SUPPLY See Note 1

APPLICATION
RESET

ICCCLK

ICCDATA
OSC1

ICCSEL/VPP
OSC2

VSS
VDD

I/O

ST7

Notes:
1. If the ICCCLK or ICCDATA pins are only used agement IC with open drain output and pull-up re-
as outputs in the application, no signal isolation is sistor>1K, no additional components are needed.
necessary. As soon as the Programming Tool is In all cases the user must ensure that no external
plugged to the board, even if an ICC session is not reset is generated by the application during the
in progress, the ICCCLK and ICCDATA pins are ICC session.
not available for the application. If they are used as 3. The use of Pin 7 of the ICC connector depends
inputs by the application, isolation such as a serial on the Programming Tool architecture. This pin
resistor has to implemented in case another de- must be connected when using most ST Program-
vice forces the signal. Refer to the Programming ming Tools (it is used to monitor the application
Tool documentation for recommended resistor val- power supply). Please refer to the Programming
ues. Tool manual.
2. During the ICC session, the programming tool 4. Pin 9 has to be connected to the OSC1 or OS-
must control the RESET pin. This can lead to con- CIN pin of the ST7 when the clock is not available
flicts between the programming tool and the appli- in the application or if the selected clock option is
cation reset circuit if it drives more than 5mA at not programmed in the option byte. ST7 devices
high level (push pull output or pull-up resistor<1K). with multi-oscillator capability need to have OSC2
A schottky diode can be used to isolate the appli- grounded in this case.
cation RESET circuit in this case. When using a
classical RC network with R>1K or a reset man-

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 ST72325xx

FLASH PROGRAM MEMORY (Cont’d)

4.5 ICP (In-Circuit Programming) possible to download code from the SPI, SCI, USB
or CAN interface and program it in the Flash. IAP
To perform ICP the microcontroller must be mode can be used to program any of the Flash
switched to ICC (In-Circuit Communication) mode sectors except Sector 0, which is write/erase pro-
by an external controller or programming tool. tected to allow recovery in case errors occur dur-
Depending on the ICP code downloaded in RAM, ing the programming operation.
Flash memory programming can be fully custom-
ized (number of bytes to program, program loca- 4.7 Related Documentation
tions, or selection serial communication interface
for downloading). For details on Flash programming and ICC proto-
When using an STMicroelectronics or third-party col, refer to the ST7 Flash Programming Refer-
programming tool that supports ICP and the spe- ence Manual and to the ST7 ICC Protocol Refer-
cific microcontroller device, the user needs only to ence Manual.
implement the ICP hardware interface on the ap- 4.7.1 Register Description
plication board (see Figure 8). For more details on FLASH CONTROL/STATUS REGISTER (FCSR)
the pin locations, refer to the device pinout de-
scription. Read/Write
Reset Value: 0000 0000 (00h)
4.6 IAP (In-Application Programming)
7 0
This mode uses a BootLoader program previously
stored in Sector 0 by the user (in ICP mode or by
0 0 0 0 0 0 0 0
plugging the device in a programming tool).
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us- This register is reserved for use by Programming
er-defined strategy for entering programming Tool software. It controls the Flash programming
mode, choice of communications protocol used to and erasing operations.
fetch the data to be stored, etc.). For example, it is
Figure 9. Flash Control/Status Register Address and Reset Value
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
FCSR
0029h
Reset Value 0 0 0 0 0 0 0 0

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ST72325xx

5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION 5.3 CPU REGISTERS

This CPU has a full 8-bit architecture and contains The six CPU registers shown in Figure 1 are not
six internal registers allowing efficient 8-bit data present in the memory mapping and are accessed
manipulation. by specific instructions.
Accumulator (A)
5.2 MAIN FEATURES The Accumulator is an 8-bit general purpose reg-
■ Enable executing 63 basic instructions ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
■ Fast 8-bit by 8-bit multiply data.
■ 17 main addressing modes (with indirect
Index Registers (X and Y)
addressing mode)
■ Two 8-bit index registers These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
■ 16-bit stack pointer manipulation. (The Cross-Assembler generates a
■ Low power HALT and WAIT modes precede instruction (PRE) to indicate that the fol-
■ Priority maskable hardware interrupts lowing instruction refers to the Y register.)
■ Non-maskable software/hardware interrupts The Y register is not affected by the interrupt auto-
matic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
Figure 10. CPU Registers
7 0
ACCUMULATOR
RESET VALUE = XXh
7 0
X INDEX REGISTER
RESET VALUE = XXh
7 0
Y INDEX REGISTER
RESET VALUE = XXh

15 PCH 8 7 PCL 0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7 0
1 1 I1 H I0 N Z C CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X

15 8 7 0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value

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 ST72325xx

CENTRAL PROCESSING UNIT (Cont’d)

Condition Code Register (CC) Bit 1 = Z Zero.
Read/Write This bit is set and cleared by hardware. This bit in-
Reset Value: 111x1xxx dicates that the result of the last arithmetic, logical
or data manipulation is zero.
7 0 0: The result of the last operation is different from
zero.
1 1 I1 H I0 N Z C 1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
The 8-bit Condition Code register contains the in- instructions.
terrupt masks and four flags representative of the
Bit 0 = C Carry/borrow.
result of the instruction just executed. This register
can also be handled by the PUSH and POP in- This bit is set and cleared by hardware and soft-
structions. ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
These bits can be individually tested and/or con- 0: No overflow or underflow has occurred.
trolled by specific instructions. 1: An overflow or underflow has occurred.
Arithmetic Management Bits This bit is driven by the SCF and RCF instructions
Bit 4 = H Half carry. and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
This bit is set by hardware when a carry occurs be- rotate instructions.
tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during Interrupt Management Bits
the same instructions.
Bit 5,3 = I1, I0 Interrupt
0: No half carry has occurred.
1: A half carry has occurred. The combination of the I1 and I0 bits gives the cur-
rent interrupt software priority.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou- Interrupt Software Priority I1 I0
tines. Level 0 (main) 1 0
Bit 2 = N Negative. Level 1 0 1
Level 2 0 0
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic, Level 3 (= interrupt disable) 1 1
logical or data manipulation. It’s a copy of the re- These two bits are set/cleared by hardware when
sult 7th bit. entering in interrupt. The loaded value is given by
0: The result of the last operation is positive or null. the corresponding bits in the interrupt software pri-
1: The result of the last operation is negative ority registers (IxSPR). They can be also set/
(that is, the most significant bit is a logic 1). cleared by software with the RIM, SIM, IRET,
This bit is accessed by the JRMI and JRPL instruc- HALT, WFI and PUSH/POP instructions.
tions. See the interrupt management chapter for more
details.

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CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP) The least significant byte of the Stack Pointer
Read/Write (called S) can be directly accessed by a LD in-
struction.
Reset Value: 01 FFh
Note: When the lower limit is exceeded, the Stack
15 8
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
0 0 0 0 0 0 0 1 fore lost. The stack also wraps in case of an under-
flow.
7 0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
The Stack Pointer is a 16-bit register which is al- at the first location pointed to by the SP. Then the
ways pointing to the next free location in the stack. other registers are stored in the next locations as
It is then decremented after data has been pushed shown in Figure 2.
onto the stack and incremented before data is
popped from the stack (see Figure 2). – When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
Since the stack is 256 bytes deep, the 8 most sig-
nificant bits are forced by hardware. Following an – On return from interrupt, the SP is incremented
MCU Reset, or after a Reset Stack Pointer instruc- and the context is popped from the stack.
tion (RSP), the Stack Pointer contains its reset val- A subroutine call occupies two locations and an in-
ue (the SP7 to SP0 bits are set) which is the stack terrupt five locations in the stack area.
higher address.
Figure 11. Stack Manipulation Example
CALL Interrupt PUSH Y POP Y IRET RET
Subroutine Event or RSP

@ 0100h

SP
SP SP
Y
CC CC CC
A A A
X X X
PCH PCH PCH
SP SP
PCL PCL PCL
PCH PCH PCH PCH PCH
SP
@ 01FFh PCL PCL PCL PCL PCL

Stack Higher Address = 01FFh

Stack Lower Address = 0100h

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 ST72325xx

6 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for 6.1 PHASE LOCKED LOOP
securing the application in critical situations (for
example in case of a power brown-out), and re- If the clock frequency input to the PLL is in the
ducing the number of external components. An range 2 to 4 MHz, the PLL can be used to multiply
overview is shown in Figure 13. the frequency by two to obtain an fOSC2 of 4 to 8
MHz. The PLL is enabled by option byte. If the PLL
For more details, refer to dedicated parametric is disabled, then fOSC2 = fOSC/2.
section.
Caution: The PLL is not recommended for appli-
Main features cations where timing accuracy is required. See
■ Optional PLL for multiplying the frequency by 2
“PLL Characteristics” on page 154.
(not to be used with internal RC oscillator)
Figure 12. PLL Block Diagram
■ Reset Sequence Manager (RSM)

■ Multi-Oscillator Clock Management (MO)

PLL x 2 0
– 5 Crystal/Ceramic resonator oscillators fOSC
fOSC2
– 1 Internal RC oscillator
/2 1
■ System Integrity Management (SI)

– Main supply Low voltage detection (LVD) PLL OPTION BIT

– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply
– Clock Security System (CSS) with Clock Filter
and Backup Safe Oscillator (enabled by op-
tion byte)
Figure 13. Clock, Reset and Supply Block Diagram
SYSTEM INTEGRITY MANAGEMENT

CLOCK SECURITY SYSTEM

(CSS)

OSC2 MULTI- fOSC fOSC2 MAIN CLOCK fCPU

fOSC2 CLOCK SAFE CONTROLLER
OSCILLATOR PLL WITH REALTIME
(option) FILTER OSC
OSC1 (MO) CLOCK (MCC/RTC)

RESET SEQUENCE AVD Interrupt Request WATCHDOG

RESET MANAGER SICSR TIMER (WDG)
(RSM) AVD AVD AVD LVD CSS CSS WDG
0
S IE F RF IE D RF

CSS Interrupt Request

LOW VOLTAGE
VSS DETECTOR
VDD (LVD)

0 AUXILIARY VOLTAGE
DETECTOR
EVD 1
(AVD)

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ST72325xx

6.2 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by the drawback of a lower frequency accuracy and
three different source types coming from the multi- should not be used in applications that require ac-
oscillator block: curate timing.
■ an external source In this mode, the two oscillator pins have to be tied
■ 4 crystal or ceramic resonator oscillators to ground.
■ an internal high frequency RC oscillator
Table 6. ST7 Clock Sources
Each oscillator is optimized for a given frequency
Hardware Configuration
range in terms of consumption and is selectable
through the option byte. The associated hardware
configurations are shown in Table 6. Refer to the
electrical characteristics section for more details. ST7

External Clock
OSC1 OSC2
External Clock Source
In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground. EXTERNAL
SOURCE
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of pro-
Crystal/Ceramic Resonators

ducing a very accurate rate on the main clock of

the ST7. The selection within a list of 4 oscillators ST7
OSC1 OSC2
with different frequency ranges has to be done by
option byte in order to reduce consumption (refer
to section 14.1 on page 181 for more details on the
frequency ranges). In this mode of the multi-oscil-
lator, the resonator and the load capacitors have
to be placed as close as possible to the oscillator CL1 CL2
pins in order to minimize output distortion and LOAD
CAPACITORS
start-up stabilization time. The loading capaci-
tance values must be adjusted according to the
selected oscillator.
Internal RC Oscillator

These oscillators are not stopped during the ST7

OSC1 OSC2
RESET phase to avoid losing time in the oscillator
start-up phase.
Internal RC Oscillator
This oscillator allows a low cost solution for the
main clock of the ST7 using only an internal resis-
tor and capacitor. Internal RC oscillator mode has

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 ST72325xx

6.3 RESET SEQUENCE MANAGER (RSM)

6.3.1 Introduction Figure 14. RESET Sequence Phases
The reset sequence manager includes three RE-
SET sources as shown in Figure 15:
■ External RESET source pulse RESET
■ Internal LVD RESET (Low Voltage Detection) INTERNAL RESET FETCH
Active Phase
256 or 4096 CLOCK CYCLES VECTOR
■ Internal WATCHDOG RESET

These sources act on the RESET pin and it is al-

ways kept low during the delay phase. Caution: When the ST7 is unprogrammed or fully
erased, the Flash is blank and the RESET vector
The RESET service routine vector is fixed at ad-
is not programmed.
dresses FFFEh-FFFFh in the ST7 memory map.
For this reason, it is recommended to keep the
The basic RESET sequence consists of 3 phases
RESET pin in low state until programming mode is
as shown in Figure 14:
entered, in order to avoid unwanted behavior.
■ Active Phase depending on the RESET source

■ 256 or 4096 CPU clock cycle delay (selected by

6.3.2 Asynchronous External RESET pin
option byte) The RESET pin is both an input and an open-drain
■ RESET vector fetch output with integrated RON weak pull-up resistor.
This pull-up has no fixed value but varies in ac-
The 256 or 4096 CPU clock cycle delay allows the cordance with the input voltage. It can be pulled
oscillator to stabilise and ensures that recovery low by external circuitry to reset the device. See
has taken place from the Reset state. The shorter “CONTROL PIN CHARACTERISTICS” on
or longer clock cycle delay should be selected by page 162 for more details.
option byte to correspond to the stabilization time
of the external oscillator used in the application A RESET signal originating from an external
(see section 14.1 on page 181). source must have a duration of at least th(RSTL)in in
order to be recognized (see Figure 16). This de-
The RESET vector fetch phase duration is 2 clock tection is asynchronous and therefore the MCU
cycles. can enter reset state even in HALT mode.
Figure 15. Reset Block Diagram

VDD

RON

Filter INTERNAL
RESET
RESET

PULSE
WATCHDOG RESET
GENERATOR
LVD RESET

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ST72325xx

RESET SEQUENCE MANAGER (Cont’d)

The RESET pin is an asynchronous signal which A proper reset signal for a slow rising VDD supply
plays a major role in EMS performance. In a noisy can generally be provided by an external RC net-
environment, it is recommended to follow the work connected to the RESET pin.
guidelines mentioned in the electrical characteris-
tics section. 6.3.4 Internal Low Voltage Detector (LVD)
RESET
If the external RESET pulse is shorter than
tw(RSTL)out (see short ext. Reset in Figure 16), the Two different RESET sequences caused by the in-
signal on the RESET pin may be stretched. Other- ternal LVD circuitry can be distinguished:
wise the delay will not be applied (see long ext. ■ Power-On RESET
Reset in Figure 16). Starting from the external RE- ■ Voltage Drop RESET
SET pulse recognition, the device RESET pin acts
as an output that is pulled low during at least The device RESET pin acts as an output that is
tw(RSTL)out. pulled low when VDD<VIT+ (rising edge) or
VDD<VIT- (falling edge) as shown in Figure 16.
6.3.3 External Power-On RESET
The LVD filters spikes on VDD larger than tg(VDD) to
If the LVD is disabled by option byte, to start up the avoid parasitic resets.
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset 6.3.5 Internal Watchdog RESET
signal is held low until VDD is over the minimum The RESET sequence generated by a internal
level specified for the selected fOSC frequency. Watchdog counter overflow is shown in Figure 16.
(see “OPERATING CONDITIONS” on page 144)
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least tw(RSTL)out.
Figure 16. RESET Sequences
VDD

VIT+(LVD)
VIT-(LVD)

LVD SHORT EXT. LONG EXT. WATCHDOG

RESET RESET RESET RESET
RUN RUN ACTIVE
RUN ACTIVE
RUN ACTIVE
RUN
ACTIVE PHASE PHASE PHASE PHASE

tw(RSTL)out tw(RSTL)out

th(RSTL)in th(RSTL)in tw(RSTL)out

DELAY
EXTERNAL
RESET
SOURCE

RESET PIN

WATCHDOG
RESET

WATCHDOG UNDERFLOW

INTERNAL RESET (256 or 4096 TCPU)

VECTOR FETCH

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 ST72325xx

6.4 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Management block contains – under full software control
the Low Voltage Detector (LVD) Auxiliary Voltage – in static safe reset
Detector (AVD) functions and Clock Security Sys- In these conditions, secure operation is always en-
tem (CSS). It is managed by the SICSR register. sured for the application without the need for ex-
6.4.1 Low Voltage Detector (LVD) ternal reset hardware.
The Low Voltage Detector function (LVD) gener- During a Low Voltage Detector Reset, the RESET
ates a static reset when the VDD supply voltage is pin is held low, thus permitting the MCU to reset
below a VIT- reference value. This means that it other devices.
secures the power-up as well as the power-down
keeping the ST7 in reset.
Notes:
The VIT- reference value for a voltage drop is lower
than the VIT+ reference value for power-on in order The LVD allows the device to be used without any
to avoid a parasitic reset when the MCU starts run- external RESET circuitry.
ning and sinks current on the supply (hysteresis). If the medium or low thresholds are selected, the
The LVD Reset circuitry generates a reset when detection may occur outside the specified operat-
VDD is below: ing voltage range. Below 3.8V, device operation is
not guaranteed.
– VIT+ when VDD is rising
– VIT- when VDD is falling The LVD is an optional function which can be se-
lected by option byte.
The LVD function is illustrated in Figure 17.
It is recommended to make sure that the VDD sup-
The voltage threshold can be configured by option ply voltage rises monotonously when the device is
byte to be low, medium or high. exiting from Reset, to ensure the application func-
tions properly.
Provided the minimum VDD value (guaranteed for
the oscillator frequency) is above VIT-, the MCU
can only be in two modes:
Figure 17. Low Voltage Detector vs Reset

VDD

Vhys
VIT+
VIT-

RESET

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ST72325xx

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.2 Auxiliary Voltage Detector (AVD) In the case of a drop in voltage, the AVD interrupt
The Voltage Detector function (AVD) is based on acts as an early warning, allowing software to shut
an analog comparison between a VIT-(AVD) and down safely before the LVD resets the microcon-
VIT+(AVD) reference value and the VDD main sup- troller. See Figure 18.
ply or the external EVD pin voltage level (VEVD). The interrupt on the rising edge is used to inform
The VIT- reference value for falling voltage is lower the application that the VDD warning state is over.
than the VIT+ reference value for rising voltage in If the voltage rise time trv is less than 256 or 4096
order to avoid parasitic detection (hysteresis). CPU cycles (depending on the reset delay select-
The output of the AVD comparator is directly read- ed by option byte), no AVD interrupt will be gener-
able by the application software through a real ated when VIT+(AVD) is reached.
time status bit (AVDF) in the SICSR register. This If trv is greater than 256 or 4096 cycles then:
bit is read only.
– If the AVD interrupt is enabled before the
Caution: The AVD function is active only if the
LVD is enabled through the option byte. VIT+(AVD) threshold is reached, then 2 AVD inter-
rupts will be received: the first when the AVDIE
6.4.2.1 Monitoring the VDD Main Supply bit is set, and the second when the threshold is
This mode is selected by clearing the AVDS bit in reached.
the SICSR register. – If the AVD interrupt is enabled after the VIT+(AVD)
The AVD voltage threshold value is relative to the threshold is reached then only one AVD interrupt
selected LVD threshold configured by option byte will occur.
(see section 14.1 on page 181).
If the AVD interrupt is enabled, an interrupt is gen-
erated when the voltage crosses the VIT+(AVD) or
VIT-(AVD) threshold (AVDF bit toggles).
Figure 18. Using the AVD to Monitor VDD (AVDS bit=0)

VDD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
Vhyst
VIT+(AVD)

VIT-(AVD)
VIT+(LVD)

VIT-(LVD) trv VOLTAGE RISE TIME

AVDF bit 0 1 RESET VALUE 1 0

AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
INTERRUPT PROCESS INTERRUPT PROCESS

LVD RESET

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 ST72325xx

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.2.2 Monitoring a Voltage on the EVD pin of the comparator output. This means it is generat-
This mode is selected by setting the AVDS bit in ed when either one of these two events occur:
the SICSR register. – VEVD rises up to VIT+(EVD)
The AVD circuitry can generate an interrupt when – VEVD falls down to VIT-(EVD)
the AVDIE bit of the SICSR register is set. This in- The EVD function is illustrated in Figure 19.
terrupt is generated on the rising and falling edges For more details, refer to the Electrical Character-
istics section.
Figure 19. Using the Voltage Detector to Monitor the EVD pin (AVDS bit=1)

VEVD

Vhyst
VIT+(EVD)

VIT-(EVD)

AVDF 0 1 0

AVD INTERRUPT
REQUEST
IF AVDIE = 1
INTERRUPT PROCESS INTERRUPT PROCESS

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ST72325xx

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.3 Clock Security System (CSS) CSSIE bit has been previously set.
The Clock Security System (CSS) protects the These two bits are described in the SICSR register
ST7 against breakdowns, spikes and overfrequen- description.
cies occurring on the main clock source (fOSC). It 6.4.4 Low Power Modes
is based on a clock filter and a clock detection con-
trol with an internal safe oscillator (fSFOSC). Mode Description
6.4.3.1 Clock Filter Control No effect on SI. CSS and AVD interrupts
WAIT
cause the device to exit from Wait mode.
The PLL has an integrated glitch filtering capability
making it possible to protect the internal clock from The SICSR register is frozen.The CSS (in-
overfrequencies created by individual spikes. This cluding the safe oscillator) is disabled until
feature is available only when the PLL is enabled. HALT mode is exited. The previous CSS
If glitches occur on fOSC (for example, due to loose configuration resumes when the MCU is
HALT
connection or noise), the CSS filters these auto- woken up by an interrupt with “exit from
matically, so the internal CPU frequency (fCPU) HALT mode” capability or from the counter
continues deliver a glitch-free signal (see Figure reset value when the MCU is woken up by a
RESET.
20).
6.4.3.2 Clock detection Control 6.4.4.1 Interrupts
If the clock signal disappears (due to a broken or The CSS orAVD interrupt events generate an in-
disconnected resonator...), the safe oscillator de- terrupt if the corresponding Enable Control Bit
livers a low frequency clock signal (fSFOSC) which (CSSIE or AVDIE) is set and the interrupt mask in
allows the ST7 to perform some rescue opera- the CC register is reset (RIM instruction).
tions.
Automatically, the ST7 clock source switches back Enable Exit Exit
Event
from the safe oscillator (fSFOSC) if the main clock Interrupt Event Control from from
Flag
source (fOSC) recovers. Bit Wait Halt

When the internal clock (fCPU) is driven by the safe CSS event detection
oscillator (fSFOSC), the application software is noti- (safe oscillator acti- CSSD CSSIE Yes No
fied by hardware setting the CSSD bit in the SIC- vated as main clock)
SR register. An interrupt can be generated if the AVD event AVDF AVDIE Yes No

Figure 20. Clock Filter Function

Clock Filter Function

fOSC2
PLL ON

fCPU

Clock Detection Function

fOSC2

fSFOSC

fCPU

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 ST72325xx

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.5 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read/Write is detected by the Clock Security System (CSSD
Reset Value: 000x 000x (00h) bit set). It is set and cleared by software.
0: Clock security system interrupt disabled
7 0 1: Clock security system interrupt enabled
When the CSS is disabled by OPTION BYTE, the
AVD AVD AVD LVD CSS CSS WDG CSSIE bit has no effect.
0
S IE F RF IE D RF
Bit 1 = CSSD Clock security system detection
Bit 7 = AVDS Voltage Detection selection This bit indicates that the safe oscillator of the
This bit is set and cleared by software. Voltage De- Clock Security System block has been selected by
tection is available only if the LVD is enabled by hardware due to a disturbance on the main clock
option byte. signal (fOSC). It is set by hardware and cleared by
0: Voltage detection on VDD supply reading the SICSR register when the original oscil-
1: Voltage detection on EVD pin lator recovers.
0: Safe oscillator is not active
1: Safe oscillator has been activated
Bit 6 = AVDIE Voltage Detector interrupt enable When the CSS is disabled by OPTION BYTE, the
This bit is set and cleared by software. It enables CSSD bit value is forced to 0.
an interrupt to be generated when the AVDF flag
changes (toggles). The pending interrupt informa-
tion is automatically cleared when software enters Bit 0 = WDGRF Watchdog reset flag
the AVD interrupt routine. This bit indicates that the last Reset was generat-
0: AVD interrupt disabled ed by the Watchdog peripheral. It is set by hard-
1: AVD interrupt enabled ware (watchdog reset) and cleared by software
(writing zero) or an LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
Bit 5 = AVDF Voltage Detector flag starts).
This read-only bit is set and cleared by hardware. Combined with the LVDRF flag information, the
If the AVDIE bit is set, an interrupt request is gen- flag description is given by the following table.
erated when the AVDF bit changes value. Refer to
Figure 18 and to Section 6.4.2.1 for additional de- RESET Sources LVDRF WDGRF
tails. External RESET pin 0 0
0: VDD or VEVD over VIT+(AVD) threshold Watchdog 0 1
1: VDD or VEVD under VIT-(AVD) threshold
LVD 1 X

Bit 4 = LVDRF LVD reset flag

This bit indicates that the last Reset was generat- Application notes
ed by the LVD block. It is set by hardware (LVD re- The LVDRF flag is not cleared when another RE-
set) and cleared by software (writing zero). See SET type occurs (external or watchdog), the
WDGRF flag description for more details. When LVDRF flag remains set to keep trace of the origi-
the LVD is disabled by OPTION BYTE, the LVDRF nal failure.
bit value is undefined. In this case, a watchdog reset can be detected by
software while an external reset can not.
Bit 3 = Reserved, must be kept cleared. CAUTION: When the LVD is not activated with the
associated option byte, the WDGRF flag can not
be used in the application.
Bit 2 = CSSIE Clock security syst interrupt enable
.

This bit enables the interrupt when a disturbance

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ST72325xx

7 INTERRUPTS

7.1 INTRODUCTION each interrupt vector (see Table 7). The process-
ing flow is shown in Figure 21
The ST7 enhanced interrupt management pro-
vides the following features: When an interrupt request has to be serviced:
■ Hardware interrupts – Normal processing is suspended at the end of
■ Software interrupt (TRAP)
the current instruction execution.
■ Nested or concurrent interrupt management
– The PC, X, A and CC registers are saved onto
with flexible interrupt priority and level the stack.
management: – I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
– Up to 4 software programmable nesting levels of the serviced interrupt vector.
– Up to 16 interrupt vectors fixed by hardware
– The PC is then loaded with the interrupt vector of
– 2 non maskable events: RESET, TRAP the interrupt to service and the first instruction of
– 1 maskable Top Level event: TLI the interrupt service routine is fetched (refer to
This interrupt management is based on: “Interrupt Mapping” table for vector addresses).
– Bit 5 and bit 3 of the CPU CC register (I1:0), The interrupt service routine should end with the
IRET instruction which causes the contents of the
– Interrupt software priority registers (ISPRx), saved registers to be recovered from the stack.
– Fixed interrupt vector addresses located at the
high addresses of the memory map (FFE0h to Note: As a consequence of the IRET instruction,
FFFFh) sorted by hardware priority order. the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest-
ed) ST7 interrupt controller. Table 7. Interrupt Software Priority Levels
Interrupt software priority Level I1 I0
7.2 MASKING AND PROCESSING FLOW Level 0 (main) Low 1 0
The interrupt masking is managed by the I1 and I0 Level 1 0 1
bits of the CC register and the ISPRx registers Level 2 0 0
which give the interrupt software priority level of Level 3 (= interrupt disable) High 1 1

Figure 21. Interrupt Processing Flowchart

PENDING Y Y
RESET TRAP
INTERRUPT

Interrupt has the same or a N

N lower software priority
than current one
I1:0
Interrupt has a higher

FETCH NEXT THE INTERRUPT

than current one
software priority

INSTRUCTION STAYS PENDING

Y
“IRET”

RESTORE PC, X, A, CC EXECUTE

FROM STACK INSTRUCTION STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR

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Servicing Pending Interrupts ■ TRAP (Non Maskable Software Interrupt)
As several interrupts can be pending at the same This software interrupt is serviced when the TRAP
time, the interrupt to be taken into account is deter- instruction is executed. It will be serviced accord-
mined by the following two-step process: ing to the flowchart in Figure 21.
– the highest software priority interrupt is serviced, Caution: TRAP can be interrupted by a TLI.
– if several interrupts have the same software pri- ■ RESET
ority then the interrupt with the highest hardware The RESET source has the highest priority in the
priority is serviced first. ST7. This means that the first current routine has
Figure 22 describes this decision process. the highest software priority (level 3) and the high-
est hardware priority.
Figure 22. Priority Decision Process See the RESET chapter for more details.
PENDING Maskable Sources
INTERRUPTS
Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
Same SOFTWARE Different
and I0 in CC register). If any of these two condi-
PRIORITY tions is false, the interrupt is latched and thus re-
mains pending.
■ TLI (Top Level Hardware Interrupt)
HIGHEST SOFTWARE
PRIORITY SERVICED This hardware interrupt occurs when a specific
edge is detected on the dedicated TLI pin. It will be
serviced according to the flowchart in Figure 21 as
HIGHEST HARDWARE
a trap.
PRIORITY SERVICED
Caution: A TRAP instruction must not be used in a
TLI service routine.
When an interrupt request is not serviced immedi- ■ External Interrupts
ately, it is latched and then processed when its External interrupts allow the processor to exit from
software priority combined with the hardware pri- HALT low power mode. External interrupt sensitiv-
ority becomes the highest one. ity is software selectable through the External In-
Note 1: The hardware priority is exclusive while terrupt Control register (EICR).
the software one is not. This allows the previous External interrupt triggered on edge will be latched
process to succeed with only one interrupt. and the interrupt request automatically cleared
Note 2: TLI,RESET and TRAP can be considered upon entering the interrupt service routine.
as having the highest software priority in the deci- If several input pins of a group connected to the
sion process. same interrupt line are selected simultaneously,
these will be logically ORed.
Different Interrupt Vector Sources
■ Peripheral Interrupts
Two interrupt source types are managed by the
ST7 interrupt controller: the non-maskable type Usually the peripheral interrupts cause the MCU to
(RESET, TRAP) and the maskable type (external exit from HALT mode except those mentioned in
or from internal peripherals). the “Interrupt Mapping” table. A peripheral inter-
rupt occurs when a specific flag is set in the pe-
Non-Maskable Sources ripheral status registers and if the corresponding
enable bit is set in the peripheral control register.
These sources are processed regardless of the
The general sequence for clearing an interrupt is
state of the I1 and I0 bits of the CC register (see
based on an access to the status register followed
Figure 21). After stacking the PC, X, A and CC
by a read or write to an associated register.
registers (except for RESET), the corresponding
Note: The clearing sequence resets the internal
vector is loaded in the PC register and the I1 and
latch. A pending interrupt (i.e. waiting for being
I0 bits of the CC are set to disable interrupts (level
serviced) will therefore be lost if the clear se-
3). These sources allow the processor to exit
quence is executed.
HALT mode.

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7.3 INTERRUPTS AND LOW POWER MODES 7.4 CONCURRENT & NESTED MANAGEMENT
All interrupts allow the processor to exit the WAIT The following Figure 23 and Figure 24 show two
low power mode. On the contrary, only external different interrupt management modes. The first is
and other specified interrupts allow the processor called concurrent mode and does not allow an in-
to exit from the HALT modes (see column “Exit terrupt to be interrupted, unlike the nested mode in
from HALT” in “Interrupt Mapping” table). When Figure 24. The interrupt hardware priority is given
several pending interrupts are present while exit- in this order from the lowest to the highest: MAIN,
ing HALT mode, the first one serviced can only be IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
an interrupt with exit from HALT mode capability given for each interrupt.
and it is selected through the same decision proc- Warning: A stack overflow may occur without no-
ess shown in Figure 22. tifying the software of the failure.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
Figure 23. Concurrent Interrupt Management
TRAP

SOFTWARE
I1 I0
IT2

IT1

IT4

IT3

IT0

PRIORITY
LEVEL
HARDWARE PRIORITY

USED STACK = 10 BYTES

TRAP 3 1 1
IT0 3 1 1
IT1 IT1 3 1 1
IT2 3 1 1
IT3 3 1 1
RIM
IT4 3 1 1
MAIN MAIN 3/0
11 / 10 10

Figure 24. Nested Interrupt Management

TRAP

SOFTWARE
I1 I0
IT0
IT2

IT1

IT4

IT3

PRIORITY
LEVEL
USED STACK = 20 BYTES
HARDWARE PRIORITY

TRAP 3 1 1
IT0 3 1 1
IT1 IT1 2 0 0
IT2 IT2 1 0 1
IT3 3 1 1
RIM
IT4 IT4 3 1 1
MAIN MAIN 3/0
11 / 10 10

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7.5 INTERRUPT REGISTER DESCRIPTION INTERRUPT SOFTWARE PRIORITY REGIS-

TERS (ISPRX)
CPU CC REGISTER INTERRUPT BITS
Read/Write (bit 7:4 of ISPR3 are read only)
Read/Write
Reset Value: 1111 1111 (FFh)
Reset Value: 111x 1010 (xAh) 7 0

7 0
ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0

1 1 I1 H I0 N Z C
ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4

Bit 5, 3 = I1, I0 Software Interrupt Priority

ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8
These two bits indicate the current interrupt soft-
ware priority.
ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12
Interrupt Software Priority Level I1 I0
Level 0 (main) Low 1 0
These four registers contain the interrupt software
Level 1 0 1 priority of each interrupt vector.
Level 2 0 0
– Each interrupt vector (except RESET and TRAP)
Level 3 (= interrupt disable*) High 1 1 has corresponding bits in these registers where
its own software priority is stored. This corre-
These two bits are set/cleared by hardware when spondance is shown in the following table.
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri- Vector address ISPRx bits
ority registers (ISPRx).
FFFBh-FFFAh I1_0 and I0_0 bits*
They can be also set/cleared by software with the FFF9h-FFF8h I1_1 and I0_1 bits
RIM, SIM, HALT, WFI, IRET and PUSH/POP in-
... ...
structions (see “Interrupt Dedicated Instruction
Set” table). FFE1h-FFE0h I1_13 and I0_13 bits

*Note: TRAP and RESET events can interrupt a – Each I1_x and I0_x bit value in the ISPRx regis-
level 3 program. ters has the same meaning as the I1 and I0 bits
in the CC register.
– Level 0 can not be written (I1_x=1, I0_x=0). In
this case, the previously stored value is kept. (ex-
ample: previous=CFh, write=64h, result=44h)
The TLI, RESET, and TRAP vectors have no soft-
ware priorities. When one is serviced, the I1 and I0
bits of the CC register are both set.
*Note: Bits in the ISPRx registers which corre-
spond to the TLI can be read and written but they
are not significant in the interrupt process man-
agement.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following be-
haviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previ-
ous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the inter-
rupt x).

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Table 8. Dedicated Interrupt Instruction Set

Instruction New Description Function/Example I1 H I0 N Z C
HALT Entering Halt mode 1 0
IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C
JRM Jump if I1:0=11 (level 3) I1:0=11 ?
JRNM Jump if I1:0<>11 I1:0<>11 ?
POP CC Pop CC from the Stack Mem => CC I1 H I0 N Z C
RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0
SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1
TRAP Software trap Software NMI 1 1
WFI Wait for interrupt 1 0

Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current
software priority up to the next IRET instruction or one of the previously mentioned instructions.

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Table 9. Interrupt Mapping
Exit
from
Source Register Priority Address
N° Description HALT/
Block Label Order Vector
ACTIVE
HALT
RESET Reset yes FFFEh-FFFFh
N/A
TRAP Software interrupt no FFFCh-FFFDh
0 TLI External top level interrupt EICR yes FFFAh-FFFBh
MCC/RTC/ Main clock controller time base interrupt MCCSR-
1 Higher yes FFF8h-FFF9h
CSS Safe oscillator activation interrupt SICSR
Priority
2 ei0 External interrupt port A3..0 yes FFF6h-FFF7h
3 ei1 External interrupt port F2..0 yes FFF4h-FFF5h
N/A
4 ei2 External interrupt port B3..0 yes FFF2h-FFF3h
5 ei3 External interrupt port B7..4 yes FFF0h-FFF1h
6 Not used FFEEh-FFEFh
7 SPI SPI peripheral interrupts SPICSR yes1 FFECh-FFEDh
8 TIMER A TIMER A peripheral interrupts TASR no FFEAh-FFEBh
9 TIMER B TIMER B peripheral interrupts TBSR no FFE8h-FFE9h
10 SCI SCI Peripheral interrupts SCISR Lower no FFE6h-FFE7h
11 AVD Auxiliary Voltage detector interrupt SICSR Priority no FFE4h-FFE5h
12 I2C I2C Peripheral interrupts (see periph) no FFE2h-FFE3h
13 PWM ART PWM ART interrupt ARTCSR yes2 FFE0h-FFE1h

Notes:
1. Exit from HALT possible when SPI is in slave mode.
2. Exit from HALT possible when PWM ART is in external clock mode.

7.6 EXTERNAL INTERRUPTS

7.6.1 I/O Port Interrupt Sensitivity ■ Falling edge and low level
The external interrupt sensitivity is controlled by ■ Rising edge and high level (only for ei0 and ei2)
the IPA, IPB and ISxx bits of the EICR register To guarantee correct functionality, the sensitivity
(Figure 25). This control allows to have up to 4 fully bits in the EICR register can be modified only
independent external interrupt source sensitivities. when the I1 and I0 bits of the CC register are both
Each external interrupt source can be generated set to 1 (level 3). This means that interrupts must
on four (or five) different events on the pin: be disabled before changing sensitivity.
■ Falling edge The pending interrupts are cleared by writing a dif-
■ Rising edge ferent value in the ISx[1:0], IPA or IPB bits of the
EICR.
■ Falling and rising edge

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Figure 25. External Interrupt Control bits

PORT A3 INTERRUPT EICR

IS20 IS21
PAOR.3
PADDR.3
SENSITIVITY ei0 INTERRUPT SOURCE
PA3
CONTROL

IPA BIT

PORT F [2:0] INTERRUPTS EICR

IS20 IS21
PFOR.2
PFDDR.2
SENSITIVITY PF2
PF2 PF1 ei1 INTERRUPT SOURCE
CONTROL
PF0

PORT B [3:0] INTERRUPTS EICR

IS10 IS11
PBOR.3
PBDDR.3
SENSITIVITY PB3
PB3 ei2 INTERRUPT SOURCE
CONTROL PB2
PB1
PB0
IPB BIT

PORT B4 INTERRUPT EICR

IS10 IS11
PBOR.4
PBDDR.4
SENSITIVITY ei3 INTERRUPT SOURCE
PB4 CONTROL

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7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)

Read/Write - ei0 (port A3)
Reset Value: 0000 0000 (00h)
External Interrupt Sensitivity
IS21 IS20
7 0 IPA bit =0 IPA bit =1
Falling edge & Rising edge
IS11 IS10 IPB IS21 IS20 IPA TLIS TLIE 0 0
low level & high level
0 1 Rising edge only Falling edge only
Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity 1 0 Falling edge only Rising edge only
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the following external interrupts: 1 1 Rising and falling edge
- ei2 (port B3..0)
External Interrupt Sensitivity - ei1 (port F2..0)
IS11 IS10
IPB bit =0 IPB bit =1 IS21 IS20 External Interrupt Sensitivity
Falling edge & Rising edge 0 0 Falling edge & low level
0 0
low level & high level
0 1 Rising edge only
0 1 Rising edge only Falling edge only
1 0 Falling edge only
1 0 Falling edge only Rising edge only
1 1 Rising and falling edge
1 1 Rising and falling edge
These 2 bits can be written only when I1 and I0 of
- ei3 (port B4) the CC register are both set to 1 (level 3).
IS11 IS10 External Interrupt Sensitivity
0 0 Falling edge & low level Bit 2 = IPA Interrupt polarity for port A
This bit is used to invert the sensitivity of the port A
0 1 Rising edge only
[3:0] external interrupts. It can be set and cleared
1 0 Falling edge only by software only when I1 and I0 of the CC register
1 1 Rising and falling edge are both set to 1 (level 3).
0: No sensitivity inversion
These 2 bits can be written only when I1 and I0 of 1: Sensitivity inversion
the CC register are both set to 1 (level 3).
Bit 1 = TLIS TLI sensitivity
Bit 5 = IPB Interrupt polarity for port B This bit allows to toggle the TLI edge sensitivity. It
This bit is used to invert the sensitivity of the port B can be set and cleared by software only when
[3:0] external interrupts. It can be set and cleared TLIE bit is cleared.
by software only when I1 and I0 of the CC register 0: Falling edge
are both set to 1 (level 3). 1: Rising edge
0: No sensitivity inversion
1: Sensitivity inversion
Bit 0 = TLIE TLI enable
Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity This bit allows to enable or disable the TLI capabil-
The interrupt sensitivity, defined using the IS2[1:0] ity on the dedicated pin. It is set and cleared by
bits, is applied to the following external interrupts: software.
0: TLI disabled
1: TLI enabled
Note: a parasitic interrupt can be generated when
clearing the TLIE bit.

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INTERRUPTS (Cont’d)
Table 10. Nested Interrupts Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
ei1 ei0 MCC + SI TLI
0024h ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1
Reset Value 1 1 1 1 1 1 1 1
SPI ei3 ei2
0025h ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4
Reset Value 1 1 1 1 1 1 1 1
AVD SCI TIMER B TIMER A
0026h ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8
Reset Value 1 1 1 1 1 1 1 1
PWMART I2C
0027h ISPR3 I1_13 I0_13 I1_12 I0_12
Reset Value 1 1 1 1 1 1 1 1
EICR IS11 IS10 IPB IS21 IS20 IPA TLIS TLIE
0028h
Reset Value 0 0 0 0 0 0 0 0

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8 POWER SAVING MODES

8.1 INTRODUCTION 8.2 SLOW MODE

To give a large measure of flexibility to the applica- This mode has two targets:
tion in terms of power consumption, four main – To reduce power consumption by decreasing the
power saving modes are implemented in the ST7 internal clock in the device,
(see Figure 26): SLOW, WAIT (SLOW WAIT), AC-
TIVE HALT and HALT. – To adapt the internal clock frequency (fCPU) to
the available supply voltage.
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives SLOW mode is controlled by three bits in the
the device (CPU and embedded peripherals) by MCCSR register: the SMS bit which enables or
means of a master clock which is based on the disables Slow mode and two CPx bits which select
main oscillator frequency divided or multiplied by 2 the internal slow frequency (fCPU).
(fOSC2). In this mode, the master clock frequency (fOSC2)
From RUN mode, the different power saving can be divided by 2, 4, 8 or 16. The CPU and pe-
modes may be selected by setting the relevant ripherals are clocked at this lower frequency
register bits or by calling the specific ST7 software (fCPU).
instruction whose action depends on the oscillator Note: SLOW-WAIT mode is activated when enter-
status. ing the WAIT mode while the device is already in
SLOW mode.
Figure 26. Power Saving Mode Transitions
Figure 27. SLOW Mode Clock Transitions
High
fOSC2/2 fOSC2/4 fOSC2

RUN fCPU

SLOW fOSC2
MCCSR

CP1:0 00 01
WAIT
SMS

SLOW WAIT
NORMAL RUN MODE
NEW SLOW REQUEST
FREQUENCY
ACTIVE HALT REQUEST

HALT

Low
POWER CONSUMPTION

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POWER SAVING MODES (Cont’d)

8.3 WAIT MODE Figure 28. WAIT Mode Flow-chart

WAIT mode places the MCU in a low power con- OSCILLATOR ON
sumption mode by stopping the CPU. PERIPHERALS ON
This power saving mode is selected by calling the WFI INSTRUCTION
CPU OFF
‘WFI’ instruction. I[1:0] BITS 10
All peripherals remain active. During WAIT mode,
the I[1:0] bits of the CC register are forced to ‘10’,
to enable all interrupts. All other registers and
memory remain unchanged. The MCU remains in N
RESET
WAIT mode until an interrupt or RESET occurs,
whereupon the Program Counter branches to the Y
starting address of the interrupt or Reset service N
INTERRUPT
routine.
The MCU will remain in WAIT mode until a Reset Y
or an Interrupt occurs, causing it to wake up. OSCILLATOR ON
Refer to Figure 28. PERIPHERALS OFF
CPU ON
I[1:0] BITS 10

256 OR 4096 CPU CLOCK

CYCLE DELAY

OSCILLATOR ON
PERIPHERALS ON
CPU ON
I[1:0] BITS XX 1)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.

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8.4 ACTIVE-HALT AND HALT MODES the interrupt occurs (tDELAY = 256 or 4096 tCPU de-
lay depending on option byte). Otherwise, the ST7
ACTIVE-HALT and HALT modes are the two low- enters HALT mode for the remaining tDELAY peri-
est power consumption modes of the MCU. They od.
are both entered by executing the ‘HALT’ instruc-
tion. The decision to enter either in ACTIVE-HALT Figure 29. ACTIVE-HALT Timing Overview
or HALT mode is given by the MCC/RTC interrupt
enable flag (OIE bit in MCCSR register). ACTIVE 256 OR 4096 CPU
RUN HALT CYCLE DELAY 1) RUN
MCCSR Power Saving Mode entered when HALT
OIE bit instruction is executed
RESET
0 HALT mode OR
HALT INTERRUPT
1 ACTIVE-HALT mode INSTRUCTION FETCH
[MCCSR.OIE=1] VECTOR

8.4.1 ACTIVE-HALT MODE

Figure 30. ACTIVE-HALT Mode Flow-chart
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock OSCILLATOR ON
available. It is entered by executing the ‘HALT’ in- HALT INSTRUCTION PERIPHERALS 2) OFF
struction when the OIE bit of the Main Clock Con- (MCCSR.OIE=1) CPU OFF
I[1:0] BITS 10
troller Status register (MCCSR) is set (see section
10.2 on page 61 for more details on the MCCSR
register). N
RESET
The MCU can exit ACTIVE-HALT mode on recep-
N Y
tion of an external interrupt, MCC/RTC interrupt or INTERRUPT
a RESET. When exiting ACTIVE-HALT mode by OSCILLATOR ON
means of an interrupt, no 256 or 4096 CPU cycle PERIPHERALS OFF
Y
delay occurs. The CPU resumes operation by CPU ON
servicing the interrupt or by fetching the reset vec- I[1:0] BITS XX 3)
tor which woke it up (see Figure 30).
When entering ACTIVE-HALT mode, the I[1:0] bits 256 OR 4096 CPU CLOCK
in the CC register are forced to ‘10b’ to enable in- CYCLE DELAY
terrupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.
OSCILLATOR ON
In ACTIVE-HALT mode, only the main oscillator PERIPHERALS ON
and its associated counter (MCC/RTC) are run- CPU ON
ning to keep a wake-up time base. All other periph- I[1:0] BITS XX 3)
erals are not clocked except those which get their
clock supply from another clock generator (such FETCH RESET VECTOR
as external or auxiliary oscillator). OR SERVICE INTERRUPT
The safeguard against staying locked in ACTIVE-
HALT mode is provided by the oscillator interrupt. Notes:
Note: As soon as the interrupt capability of one of 1. This delay occurs only if the MCU exits ACTIVE-
the oscillators is selected (MCCSR.OIE bit set), HALT mode by means of a RESET.
2. Peripheral clocked with an external clock source
entering ACTIVE-HALT mode while the Watchdog can still be active.
is active does not generate a RESET. 3. Before servicing an interrupt, the CC register is
This means that the device cannot spend more pushed on the stack. The I[1:0] bits of the CC reg-
than a defined delay in this power saving mode. ister are set to the current software priority level of
CAUTION: When exiting ACTIVE-HALT mode fol- the interrupt routine and restored when the CC
lowing an MCC/RTC interrupt, OIE bit of MCCSR register is popped.
register must not be cleared before tDELAY after

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POWER SAVING MODES (Cont’d)

8.4.2 HALT MODE Figure 32. HALT Mode Flow-chart
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the HALT INSTRUCTION
‘HALT’ instruction when the OIE bit of the Main (MCCSR.OIE=0)
Clock Controller Status register (MCCSR) is ENABLE
cleared (see section 10.2 on page 61 for more de- WATCHDOG
tails on the MCCSR register).
0 DISABLE
The MCU can exit HALT mode on reception of ei- WDGHALT 1)
ther a specific interrupt (see Table 9, “Interrupt
1
Mapping,” on page 41) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt, WATCHDOG
the oscillator is immediately turned on and the 256 OSCILLATOR OFF
RESET PERIPHERALS 2) OFF
or 4096 CPU cycle delay is used to stabilize the
CPU OFF
oscillator. After the start up delay, the CPU
I[1:0] BITS 10
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see Fig-
ure 32).
When entering HALT mode, the I[1:0] bits in the N
RESET
CC register are forced to ‘10b’to enable interrupts.
Therefore, if an interrupt is pending, the MCU Y
wakes up immediately. N
INTERRUPT 3)
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in- Y OSCILLATOR ON
cluding the operation of the on-chip peripherals. PERIPHERALS OFF
All peripherals are not clocked except the ones CPU ON
which get their clock supply from another clock I[1:0] BITS XX 4)
generator (such as an external or auxiliary oscilla-
tor). 256 OR 4096 CPU CLOCK
The compatibility of Watchdog operation with CYCLE DELAY
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
OSCILLATOR ON
when executed while the Watchdog system is en- PERIPHERALS ON
abled, can generate a Watchdog RESET (see sec- CPU ON
tion 14.1 on page 181 for more details). I[1:0] BITS XX 4)
Figure 31. HALT Timing Overview
FETCH RESET VECTOR
256 OR 4096 CPU OR SERVICE INTERRUPT
RUN HALT CYCLE DELAY RUN
Notes:
RESET 1. WDGHALT is an option bit. See option byte sec-
OR tion for more details.
HALT INTERRUPT 2. Peripheral clocked with an external clock source
INSTRUCTION FETCH can still be active.
[MCCSR.OIE=0] VECTOR 3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 9, “Interrupt Mapping,” on page 41 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.

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8.4.2.1 Halt Mode Recommendations ry. For example, avoid defining a constant in
– Make sure that an external event is available to ROM with the value 0x8E.
wake up the microcontroller from Halt mode. – As the HALT instruction clears the interrupt mask
– When using an external interrupt to wake up the in the CC register to allow interrupts, the user
microcontroller, reinitialize the corresponding I/O may choose to clear all pending interrupt bits be-
as “Input Pull-up with Interrupt” before executing fore executing the HALT instruction. This avoids
the HALT instruction. The main reason for this is entering other peripheral interrupt routines after
that the I/O may be wrongly configured due to ex- executing the external interrupt routine corre-
ternal interference or by an unforeseen logical sponding to the wake-up event (reset or external
condition. interrupt).
– For the same reason, reinitialize the level sensi- Related Documentation
tiveness of each external interrupt as a precau- AN 980: ST7 Keypad Decoding Techniques, Im-
tionary measure. plementing Wake-Up on Keystroke
– The opcode for the HALT instruction is 0x8E. To AN1014: How to Minimize the ST7 Power Con-
avoid an unexpected HALT instruction due to a sumption
program counter failure, it is advised to clear all AN1605: Using an active RC to wakeup the
occurrences of the data value 0x8E from memo- ST7LITE0 from power saving mode

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9 I/O PORTS

9.1 INTRODUCTION Each pin can independently generate an interrupt

request. The interrupt sensitivity is independently
The I/O ports offer different functional modes: programmable using the sensitivity bits in the
– transfer of data through digital inputs and outputs EICR register.
and for specific pins: Each external interrupt vector is linked to a dedi-
– external interrupt generation cated group of I/O port pins (see pinout description
– alternate signal input/output for the on-chip pe- and interrupt section). If several input pins are se-
ripherals. lected simultaneously as interrupt sources, these
An I/O port contains up to 8 pins. Each pin can be are first detected according to the sensitivity bits in
programmed independently as digital input (with or the EICR register and then logically ORed.
without interrupt generation) or digital output. The external interrupts are hardware interrupts,
which means that the request latch (not accessible
9.2 FUNCTIONAL DESCRIPTION directly by the application) is automatically cleared
when the corresponding interrupt vector is
Each port has two main registers: fetched. To clear an unwanted pending interrupt
– Data Register (DR) by software, the sensitivity bits in the EICR register
– Data Direction Register (DDR) must be modified.
and one optional register: 9.2.2 Output Modes
– Option Register (OR) The output configuration is selected by setting the
corresponding DDR register bit. In this case, writ-
Each I/O pin may be programmed using the corre- ing the DR register applies this digital value to the
sponding register bits in the DDR and OR regis- I/O pin through the latch. Then reading the DR reg-
ters: Bit X corresponding to pin X of the port. The ister returns the previously stored value.
same correspondence is used for the DR register.
Two different output modes can be selected by
The following description takes into account the software through the OR register: Output push-pull
OR register, (for specific ports which do not pro- and open-drain.
vide this register refer to the I/O Port Implementa-
tion section). The generic I/O block diagram is DR register value and output pin status:
shown in Figure 1 DR Push-pull Open-drain
9.2.1 Input Modes 0 VSS Vss
The input configuration is selected by clearing the 1 VDD Floating
corresponding DDR register bit.
9.2.3 Alternate Functions
In this case, reading the DR register returns the
digital value applied to the external I/O pin. When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
Different input modes can be selected by software ed. This alternate function takes priority over the
through the OR register. standard I/O programming.
Notes: When the signal is coming from an on-chip periph-
1. Writing the DR register modifies the latch value
but does not affect the pin status. eral, the I/O pin is automatically configured in out-
2. When switching from input to output mode, the put mode (push-pull or open drain according to the
DR register has to be written first to drive the cor- peripheral).
rect level on the pin as soon as the port is config- When the signal is going to an on-chip peripheral,
ured as an output. the I/O pin must be configured in input mode. In
3. Do not use read/modify/write instructions (BSET this case, the pin state is also digitally readable by
or BRES) to modify the DR register as this might addressing the DR register.
corrupt the DR content for I/Os configured as input.
Note: Input pull-up configuration can cause unex-
External interrupt function pected value at the input of the alternate peripheral
When an I/O is configured as Input with Interrupt, input. When an on-chip peripheral use a pin as in-
an event on this I/O can generate an external inter- put and output, this pin has to be configured in in-
rupt request to the CPU. put floating mode.

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I/O PORTS (Cont’d)

Figure 33. I/O Port General Block Diagram

ALTERNATE
REGISTER 1
OUTPUT VDD P-BUFFER
ACCESS
(see table below)
0
ALTERNATE PULL-UP
ENABLE (see table below)

DR VDD

DDR

PULL-UP
PAD
CONDITION
OR
DATA BUS

If implemented

OR SEL

N-BUFFER
DIODES
(see table below)
DDR SEL
ANALOG
INPUT
CMOS
SCHMITT
DR SEL
1 TRIGGER

0
ALTERNATE
INPUT
EXTERNAL
INTERRUPT
SOURCE (eix)

Table 11. I/O Port Mode Options

Diodes
Configuration Mode Pull-Up P-Buffer
to VDD to VSS
Floating with/without Interrupt Off
Input Off
Pull-up with/without Interrupt On
On
Push-pull On On
Off
Output Open Drain (logic level) Off
True Open Drain NI NI NI (see note)

Legend: NI - not implemented Note: The diode to VDD is not implemented in the
Off - implemented not activated true open drain pads. A local protection between
On - implemented and activated the pad and VSS is implemented to protect the de-
vice against positive stress.

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I/O PORTS (Cont’d)

Table 12. I/O Port Configurations
Hardware Configuration

NOT IMPLEMENTED IN DR REGISTER ACCESS

VDD
TRUE OPEN DRAIN
I/O PORTS
RPU PULL-UP
CONDITION DR W
REGISTER DATA BUS
PAD R
INPUT 1)

ALTERNATE INPUT

EXTERNAL INTERRUPT
SOURCE (eix)

INTERRUPT
CONDITION

ANALOG INPUT

NOT IMPLEMENTED IN DR REGISTER ACCESS

TRUE OPEN DRAIN VDD
OPEN-DRAIN OUTPUT 2)

I/O PORTS

RPU
DR R/W
REGISTER DATA BUS
PAD

ALTERNATE ALTERNATE
ENABLE OUTPUT

NOT IMPLEMENTED IN DR REGISTER ACCESS

TRUE OPEN DRAIN VDD
PUSH-PULL OUTPUT 2)

I/O PORTS

RPU
DR R/W
REGISTER DATA BUS
PAD

ALTERNATE ALTERNATE
ENABLE OUTPUT

Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.

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CAUTION: The alternate function must not be ac- Figure 34. Interrupt I/O Port State Transitions
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts. 01 00 10 11
Analog alternate function INPUT INPUT OUTPUT OUTPUT
When the pin is used as an ADC input, the I/O floating/pull-up floating open-drain push-pull
interrupt (reset state)
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers) XX = DDR, OR
switches the analog voltage present on the select-
ed pin to the common analog rail which is connect-
ed to the ADC input.
9.4 LOW POWER MODES
It is recommended not to change the voltage level
or loading on any port pin while conversion is in Mode Description
progress. Furthermore it is recommended not to No effect on I/O ports. External interrupts
have clocking pins located close to a selected an- WAIT
cause the device to exit from WAIT mode.
alog pin.
No effect on I/O ports. External interrupts
WARNING: The analog input voltage level must HALT
cause the device to exit from HALT mode.
be within the limits stated in the absolute maxi-
mum ratings.
9.5 INTERRUPTS
9.3 I/O PORT IMPLEMENTATION The external interrupt event generates an interrupt
if the corresponding configuration is selected with
The hardware implementation on each I/O port de- DDR and OR registers and the interrupt mask in
pends on the settings in the DDR and OR registers the CC register is not active (RIM instruction).
and specific feature of the I/O port such as ADC In-
put or true open drain. Enable Exit Exit
Event
Switching these I/O ports from one state to anoth- Interrupt Event Control from from
Flag
er should be done in a sequence that prevents un- Bit Wait Halt
wanted side effects. Recommended safe transi- External interrupt on
tions are illustrated in Figure 2 on page 4. Other DDRx
selected external - Yes
transitions are potentially risky and should be ORx
event
avoided, since they are likely to present unwanted
side-effects such as spurious interrupt generation.

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I/O PORTS (Cont’d)

9.5.1 I/O Port Implementation MODE DDR OR
The I/O port register configurations are summa- floating input 0 0
rised as follows. floating interrupt input 0 1
Standard Ports open drain output 1 0
push-pull output 1 1
PA5:4, PC7:0, PD7:0, PE7:3,
PE1:0, PF7:3,
MODE DDR OR True Open Drain Ports
floating input 0 0 PA7:6
pull-up input 0 1 MODE DDR
open drain output 1 0 floating input 0
push-pull output 1 1 open drain (high sink ports) 1

Interrupt Ports Pull-Up Input Port PE2

PA2:0, PB6:5, PB4, PB2:0, PF1:0 (with pull-up)
MODE DDR OR
MODE DDR OR pull-up input 0 x
floating input 0 0 open drain output* 1 0
pull-up interrupt input 0 1 push-pull output* 1 1
open drain output 1 0
push-pull output 1 1

Table 13. Port Configuration

Input Output
Port Pin name
OR = 0 OR = 1 OR = 0 OR = 1
PA7:6 floating true open-drain
PA5:4 floating pull-up open drain push-pull
Port A
PA3 floating floating interrupt open drain push-pull
PA2:0 floating pull-up interrupt open drain push-pull
PB7, PB3 floating floating interrupt open drain push-pull
Port B PB6:5, PB4,
floating pull-up interrupt open drain push-pull
PB2:0
Port C PC7:0 floating pull-up open drain push-pull
Port D PD7:0 floating pull-up open drain push-pull
PE7:3, PE1:0 floating pull-up open drain push-pull
Port E
PE2 pull-up input only open drain* push-pull*
PF7:3 floating pull-up open drain push-pull
Port F PF2 floating floating interrupt open drain push-pull
PF1:0 floating pull-up interrupt open drain push-pull
*Pull-up always activated on PE2.

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I/O PORTS (Cont’d)

Table 14. I/O Port Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
Reset Value
0 0 0 0 0 0 0 0
of all I/O port registers
0000h PADR
0001h PADDR MSB LSB
0002h PAOR
0003h PBDR
0004h PBDDR MSB LSB
0005h PBOR
0006h PCDR
0007h PCDDR MSB LSB
0008h PCOR
0009h PDDR
000Ah PDDDR MSB LSB
000Bh PDOR
000Ch PEDR
000Dh PEDDR MSB LSB
000Eh PEOR
000Fh PFDR
0010h PFDDR MSB LSB
0011h PFOR

Related Documentation AN1045: S/W implementation of I2C bus master

AN 970: SPI Communication between ST7 and AN1048: Software LCD driver
EEPROM

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ST72325xx

10 ON-CHIP PERIPHERALS

10.1 WATCHDOG TIMER (WDG)

10.1.1 Introduction If the watchdog is activated (the WDGA bit is set)
The Watchdog timer is used to detect the occur- and when the 7-bit timer (bits T[6:0]) rolls over
rence of a software fault, usually generated by ex- from 40h to 3Fh (T6 becomes cleared), it initiates
ternal interference or by unforeseen logical condi- a reset cycle pulling the reset pin low for typically
tions, which causes the application program to 30µs.
abandon its normal sequence. The Watchdog cir- The application program must write in the
cuit generates an MCU reset on expiry of a pro- WDGCR register at regular intervals during normal
grammed time period, unless the program refresh- operation to prevent an MCU reset. This down-
es the counter’s contents before the T6 bit be- counter is free-running: it counts down even if the
comes cleared. watchdog is disabled. The value to be stored in the
10.1.2 Main Features WDGCR register must be between FFh and C0h:
■ Programmable free-running downcounter – The WDGA bit is set (watchdog enabled)
■ Programmable reset – The T6 bit is set to prevent generating an imme-
■ Reset (if watchdog activated) when the T6 bit
diate reset
reaches zero – The T[5:0] bits contain the number of increments
■ Optional reset on HALT instruction which represents the time delay before the
(configurable by option byte) watchdog produces a reset (see Figure 2. Ap-
proximate Timeout Duration). The timing varies
■ Hardware Watchdog selectable by option byte
between a minimum and a maximum value due
to the unknown status of the prescaler when writ-
10.1.3 Functional Description ing to the WDGCR register (see Figure 3).
The counter value stored in the Watchdog Control Following a reset, the watchdog is disabled. Once
register (WDGCR bits T[6:0]), is decremented activated it cannot be disabled, except by a reset.
every 16384 fOSC2 cycles (approx.), and the The T6 bit can be used to generate a software re-
length of the timeout period can be programmed set (the WDGA bit is set and the T6 bit is cleared).
by the user in 64 increments. If the watchdog is activated, the HALT instruction
will generate a Reset.
Figure 35. Watchdog Block Diagram

RESET
fOSC2

MCC/RTC
WATCHDOG CONTROL REGISTER (WDGCR)

DIV 64 WDGA T6 T5 T4 T3 T2 T1 T0

6-BIT DOWNCOUNTER (CNT)

12-BIT MCC
RTC COUNTER WDG PRESCALER
TB[1:0] bits DIV 4
MSB LSB
(MCCSR
11 6 5 0
Register)

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WATCHDOG TIMER (Cont’d)

10.1.4 How to Program the Watchdog Timeout more precision is needed, use the formulae in Fig-
Figure 2 shows the linear relationship between the ure 3.
6-bit value to be loaded in the Watchdog Counter Caution: When writing to the WDGCR register, al-
(CNT) and the resulting timeout duration in milli- ways write 1 in the T6 bit to avoid generating an
seconds. This can be used for a quick calculation immediate reset.
without taking the timing variations into account. If
Figure 36. Approximate Timeout Duration

3F

38

30

28
CNT Value (hex.)

20

18

10

08

00
1.5 18 34 50 65 82 98 114 128
Watchdog timeout (ms) @ 8 MHz. fOSC2

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ST72325xx

WATCHDOG TIMER (Cont’d)

Figure 37. Exact Timeout Duration (tmin and tmax)
WHERE:
tmin0 = (LSB + 128) x 64 x tOSC2
tmax0 = 16384 x tOSC2
tOSC2 = 125ns if fOSC2=8 MHz
CNT = Value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits
in the MCCSR register
TB1 Bit TB0 Bit Selected MCCSR
MSB LSB
(MCCSR Reg.) (MCCSR Reg.) Timebase
0 0 2ms 4 59
0 1 4ms 8 53
1 0 10ms 20 35
1 1 25ms 49 54

To calculate the minimum Watchdog Timeout (tmin):

IF CNT < MSB

------------- THEN t min = t min0 + 16384 × CNT × tosc2
4

ELSE t min = t min0 + 16384 × ⎛⎝ CNT – 4CNT

----------------- ⎞ + ( 192 + LSB ) × 64 × -----------------
4CNT
× t
MSB ⎠ MSB osc2

To calculate the maximum Watchdog Timeout (tmax):

IF CNT ≤ MSB
------------- THEN t max = t max0 + 16384 × CNT × t osc2
4

ELSEt max = t max0 + 16384 × ⎛⎝ CNT – 4CNT 4CNT

----------------- ⎞ + ( 192 + LSB ) × 64 × ----------------- × t
MSB ⎠ MSB osc2

Note: In the above formulae, division results must be rounded down to the next integer value.
Example:
With 2ms timeout selected in MCCSR register
Min. Watchdog Max. Watchdog
Value of T[5:0] Bits in
Timeout (ms) Timeout (ms)
WDGCR Register (Hex.)
tmin tmax
00 1.496 2.048
3F 128 128.552

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WATCHDOG TIMER (Cont’d)

10.1.5 Low Power Modes
Mode Description
SLOW No effect on Watchdog.
WAIT No effect on Watchdog.
OIE bit in WDGHALT bit
MCCSR in Option
register Byte
No Watchdog reset is generated. The MCU enters Halt mode. The Watch-
dog counter is decremented once and then stops counting and is no longer
able to generate a watchdog reset until the MCU receives an external inter-
rupt or a reset.
0 0
If an external interrupt is received, the Watchdog restarts counting after 256
HALT or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset
state) unless Hardware Watchdog is selected by option byte. For applica-
tion recommendations see Section 0.1.7 below.
0 1 A reset is generated.
No reset is generated. The MCU enters Active Halt mode. The Watchdog
counter is not decremented. It stop counting. When the MCU receives an
1 x oscillator interrupt or external interrupt, the Watchdog restarts counting im-
mediately. When the MCU receives a reset the Watchdog restarts counting
after 256 or 4096 CPU clocks.

10.1.6 Hardware Watchdog Option 10.1.9 Register Description

If Hardware Watchdog is selected by option byte, CONTROL REGISTER (WDGCR)
the watchdog is always active and the WDGA bit in Read/Write
the WDGCR is not used. Refer to the Option Byte
description. Reset Value: 0111 1111 (7Fh)
10.1.7 Using Halt Mode with the WDG 7 0
(WDGHALT option)
WDGA T6 T5 T4 T3 T2 T1 T0
The following recommendation applies if Halt
mode is used when the watchdog is enabled.
– Before executing the HALT instruction, refresh Bit 7 = WDGA Activation bit.
the WDG counter, to avoid an unexpected WDG This bit is set by software and only cleared by
reset immediately after waking up the microcon- hardware after a reset. When WDGA = 1, the
troller. watchdog can generate a reset.
10.1.8 Interrupts 0: Watchdog disabled
1: Watchdog enabled
None.
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bit 6:0 = T[6:0] 7-bit counter (MSB to LSB).
These bits contain the value of the watchdog
counter. It is decremented every 16384 fOSC2 cy-
cles (approx.). A reset is produced when it rolls
over from 40h to 3Fh (T6 becomes cleared).

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ST72325xx

Table 15. Watchdog Timer Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
WDGCR WDGA T6 T5 T4 T3 T2 T1 T0
002Ah
Reset Value 0 1 1 1 1 1 1 1

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 ST72325xx

10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)
The Main Clock Controller consists of three differ- external devices. It is controlled by the MCO bit in
ent functions: the MCCSR register.
■ a programmable CPU clock prescaler CAUTION: When selected, the clock out pin sus-
■ a clock-out signal to supply external devices
pends the clock during ACTIVE-HALT mode.
■ a real time clock timer with interrupt capability
10.2.3 Real Time Clock Timer (RTC)
Each function can be used independently and si- The counter of the real time clock timer allows an
multaneously. interrupt to be generated based on an accurate
real time clock. Four different time bases depend-
10.2.1 Programmable CPU Clock Prescaler ing directly on fOSC2 are available. The whole
The programmable CPU clock prescaler supplies functionality is controlled by four bits of the MCC-
the clock for the ST7 CPU and its internal periph- SR register: TB[1:0], OIE and OIF.
erals. It manages SLOW power saving mode (See When the RTC interrupt is enabled (OIE bit set),
Section 8.2 SLOW MODE for more details). the ST7 enters ACTIVE-HALT mode when the
The prescaler selects the fCPU main clock frequen- HALT instruction is executed. See Section 8.4 AC-
cy and is controlled by three bits in the MCCSR TIVE-HALT AND HALT MODES for more details.
register: CP[1:0] and SMS. 10.2.4 Beeper
10.2.2 Clock-out Capability The beep function is controlled by the MCCBCR
The clock-out capability is an alternate function of register. It can output three selectable frequencies
an I/O port pin that outputs a fCPU clock to drive on the BEEP pin (I/O port alternate function).

Figure 38. Main Clock Controller (MCC/RTC) Block Diagram

BC1 BC0

MCCBCR
BEEP
BEEP SIGNAL
SELECTION
MCO

12-BIT MCC RTC TO

DIV 64
COUNTER WATCHDOG
TIMER

MCO CP1 CP0 SMS TB1 TB0 OIE OIF

MCCSR MCC/RTC INTERRUPT

fOSC2
DIV 2, 4, 8, 16 1
fCPU CPU CLOCK
TO CPU AND
0 PERIPHERALS

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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

10.2.5 Low Power Modes
Mode Description
Bit 6:5 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is
No effect on MCC/RTC peripheral. applied in the different slow modes. Their action is
WAIT MCC/RTC interrupt cause the device to exit conditioned by the setting of the SMS bit. These
from WAIT mode. two bits are set and cleared by software
No effect on MCC/RTC counter (OIE bit is
ACTIVE- set), the registers are frozen. fCPU in SLOW mode CP1 CP0
HALT MCC/RTC interrupt cause the device to exit fOSC2 / 2 0 0
from ACTIVE-HALT mode.
fOSC2 / 4 0 1
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the fOSC2 / 8 1 0
HALT
MCU is woken up by an interrupt with “exit fOSC2 / 16 1 1
from HALT” capability.

10.2.6 Interrupts Bit 4 = SMS Slow mode select

The MCC/RTC interrupt event generates an inter- This bit is set and cleared by software.
rupt if the OIE bit of the MCCSR register is set and 0: Normal mode. fCPU = fOSC2
the interrupt mask in the CC register is not active 1: Slow mode. fCPU is given by CP1, CP0
(RIM instruction). See Section 8.2 SLOW MODE and Section 10.2
MAIN CLOCK CONTROLLER WITH REAL TIME
Enable Exit Exit CLOCK AND BEEPER (MCC/RTC) for more de-
Event tails.
Interrupt Event Control from from
Flag
Bit Wait Halt
Time base overflow Bit 3:2 = TB[1:0] Time base control
OIF OIE Yes No 1)
event
These bits select the programmable divider time
Note: base. They are set and cleared by software.
The MCC/RTC interrupt wakes up the MCU from Time Base
Counter
ACTIVE-HALT mode, not from HALT mode. TB1 TB0
Prescaler f
OSC2 =4MHz fOSC2=8MHz

16000 4ms 2ms 0 0

10.2.7 Register Description 32000 8ms 4ms 0 1

MCC CONTROL/STATUS REGISTER (MCCSR) 80000 20ms 10ms 1 0

200000 50ms 25ms 1 1
Read/Write
Reset Value: 0000 0000 (00h) A modification of the time base is taken into ac-
count at the end of the current period (previously
7 0 set) to avoid an unwanted time shift. This allows to
use this time base as a real time clock.
MCO CP1 CP0 SMS TB1 TB0 OIE OIF
Bit 1 = OIE Oscillator interrupt enable
Bit 7 = MCO Main clock out selection This bit set and cleared by software.
This bit enables the MCO alternate function on the 0: Oscillator interrupt disabled
PF0 I/O port. It is set and cleared by software. 1: Oscillator interrupt enabled
0: MCO alternate function disabled (I/O pin free for This interrupt can be used to exit from ACTIVE-
general-purpose I/O) HALT mode.
1: MCO alternate function enabled (fCPU on I/O When this bit is set, calling the ST7 software HALT
port) instruction enters the ACTIVE-HALT power saving
Note: To reduce power consumption, the MCO mode.
function is not active in ACTIVE-HALT mode.

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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

Bit 0 = OIF Oscillator interrupt flag MCC BEEP CONTROL REGISTER (MCCBCR)
This bit is set by hardware and cleared by software Read/Write
reading the MCCSR register. It indicates when set
that the main oscillator has reached the selected Reset Value: 0000 0000 (00h)
elapsed time (TB1:0).
0: Timeout not reached 7 0
1: Timeout reached
0 0 0 0 0 0 BC1 BC0
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit. Bit 7:2 = Reserved, must be kept cleared.

Bit 1:0 = BC[1:0] Beep control

These 2 bits select the PF1 pin beep capability.
BC1 BC0 Beep mode with fOSC2=8MHz

0 0 Off
0 1 ~2-KHz
Output
1 0 ~1-KHz Beep signal
~50% duty cycle
1 1 ~500-Hz

The beep output signal is available in ACTIVE-

HALT mode but has to be disabled to reduce the
consumption.
Table 16. Main Clock Controller Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
SICSR AVDS AVDIE AVDF LVDRF CSSIE CSSD WDGRF
002Bh
Reset Value 0 0 0 x 0 0 0 x
MCCSR MCO CP1 CP0 SMS TB1 TB0 OIE OIF
002Ch
Reset Value 0 0 0 0 0 0 0 0
MCCBCR BC1 BC0
002Dh
Reset Value 0 0 0 0 0 0 0 0

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ST72325xx

10.3 PWM AUTO-RELOAD TIMER (ART)

10.3.1 Introduction
The Pulse Width Modulated Auto-Reload Timer – Up to two input capture functions
on-chip peripheral consists of an 8-bit auto reload – External event detector
counter with compare/capture capabilities and of a
7-bit prescaler clock source. – Up to two external interrupt sources
These resources allow five possible operating The three first modes can be used together with a
modes: single counter frequency.
– Generation of up to 4 independent PWM signals The timer can be used to wake up the MCU from
WAIT and HALT modes.
– Output compare and Time base interrupt
Figure 39. PWM Auto-Reload Timer Block Diagram

PWMCR OEx OPx OCRx DCRx

REGISTER REGISTER

LOAD
PORT
POLARITY
PWMx ALTERNATE COMPARE
FUNCTION CONTROL

ARR 8-BIT COUNTER LOAD

REGISTER (CAR REGISTER)

INPUT CAPTURE LOAD ICRx

ARTICx
CONTROL REGISTER

ICSx ICIEx ICFx ICCSR

ICx INTERRUPT
fEXT
ARTCLK
fCOUNTER
fCPU

MUX

fINPUT PROGRAMMABLE
PRESCALER

EXCL CC2 CC1 CC0 TCE FCRL OIE OVF ARTCSR

OVF INTERRUPT

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ON-CHIP PERIPHERALS (Cont’d)

10.3.2 Functional Description
Counter Counter and Prescaler Initialization
The free running 8-bit counter is fed by the output After RESET, the counter and the prescaler are
of the prescaler, and is incremented on every ris- cleared and fINPUT = fCPU.
ing edge of the clock signal. The counter can be initialized by:
It is possible to read or write the contents of the – Writing to the ARTARR register and then setting
counter on the fly by reading or writing the Counter the FCRL (Force Counter Re-Load) and the TCE
Access register (ARTCAR). (Timer Counter Enable) bits in the ARTCSR reg-
When a counter overflow occurs, the counter is ister.
automatically reloaded with the contents of the – Writing to the ARTCAR counter access register,
ARTARR register (the prescaler is not affected).
In both cases the 7-bit prescaler is also cleared,
Counter clock and prescaler whereupon counting will start from a known value.
The counter clock frequency is given by: Direct access to the prescaler is not possible.
fCOUNTER = fINPUT / 2CC[2:0] Output compare control
The timer counter’s input clock (fINPUT) feeds the The timer compare function is based on four differ-
7-bit programmable prescaler, which selects one ent comparisons with the counter (one for each
of the 8 available taps of the prescaler, as defined PWMx output). Each comparison is made be-
by CC[2:0] bits in the Control/Status Register tween the counter value and an output compare
(ARTCSR). Thus the division factor of the prescal- register (OCRx) value. This OCRx register can not
er can be set to 2n (where n = 0, 1,..7). be accessed directly, it is loaded from the duty cy-
This fINPUT frequency source is selected through cle register (PWMDCRx) at each overflow of the
the EXCL bit of the ARTCSR register and can be counter.
either the fCPU or an external input frequency fEXT. This double buffering method avoids glitch gener-
The clock input to the counter is enabled by the ation when changing the duty cycle on the fly.
TCE (Timer Counter Enable) bit in the ARTCSR
register. When TCE is reset, the counter is
stopped and the prescaler and counter contents
are frozen. When TCE is set, the counter runs at
the rate of the selected clock source.
Figure 40. Output compare control

fCOUNTER

ARTARR=FDh

COUNTER FDh FEh FFh FDh FEh FFh FDh FEh FFh

OCRx FDh FEh

PWMDCRx FDh FEh

PWMx

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ST72325xx

ON-CHIP PERIPHERALS (Cont’d)

Independent PWM signal generation When the counter reaches the value contained in
This mode allows up to four Pulse Width Modulat- one of the output compare register (OCRx) the
ed signals to be generated on the PWMx output corresponding PWMx pin level is restored.
pins with minimum core processing overhead. It should be noted that the reload values will also
This function is stopped during HALT mode. affect the value and the resolution of the duty cycle
Each PWMx output signal can be selected inde- of the PWM output signal. To obtain a signal on a
pendently using the corresponding OEx bit in the PWMx pin, the contents of the OCRx register must
PWM Control register (PWMCR). When this bit is be greater than the contents of the ARTARR reg-
set, the corresponding I/O pin is configured as out- ister.
put push-pull alternate function. The maximum available resolution for the PWMx
The PWM signals all have the same frequency duty cycle is:
which is controlled by the counter period and the Resolution = 1 / (256 - ARTARR)
ARTARR register value. Note: To get the maximum resolution (1/256), the
fPWM = fCOUNTER / (256 - ARTARR) ARTARR register must be 0. With this maximum
When a counter overflow occurs, the PWMx pin resolution, 0% and 100% can be obtained by
level is changed depending on the corresponding changing the polarity.
OPx (output polarity) bit in the PWMCR register.
Figure 41. PWM Auto-reload Timer Function

255
DUTY CYCLE
REGISTER
COUNTER

(PWMDCRx)

AUTO-RELOAD
REGISTER
(ARTARR)
000
t
PWMx OUTPUT

WITH OEx=1
AND OPx=0

WITH OEx=1
AND OPx=1

Figure 42. PWM Signal from 0% to 100% Duty Cycle

fCOUNTER

ARTARR=FDh

COUNTER FDh FEh FFh FDh FEh FFh FDh FEh

OCRx=FCh
PWMx OUTPUT
WITH OEx=1
AND OPx=0

OCRx=FDh

OCRx=FEh

OCRx=FFh

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 ST72325xx

ON-CHIP PERIPHERALS (Cont’d)

Output compare and Time base interrupt External clock and event detector mode
On overflow, the OVF flag of the ARTCSR register Using the fEXT external prescaler input clock, the
is set and an overflow interrupt request is generat- auto-reload timer can be used as an external clock
ed if the overflow interrupt enable bit, OIE, in the event detector. In this mode, the ARTARR register
ARTCSR register, is set. The OVF flag must be re- is used to select the nEVENT number of events to
set by the user software. This interrupt can be be counted before setting the OVF flag.
used as a time base in the application. nEVENT = 256 - ARTARR
Caution: The external clock function is not availa-
ble in HALT mode. If HALT mode is used in the ap-
plication, prior to executing the HALT instruction,
the counter must be disabled by clearing the TCE
bit in the ARTCSR register to avoid spurious coun-
ter increments.
Figure 43. External Event Detector Example (3 counts)

fEXT=fCOUNTER
ARTARR=FDh

COUNTER FDh FEh FFh FDh FEh FFh FDh

OVF

ARTCSR READ ARTCSR READ

INTERRUPT INTERRUPT
IF OIE=1 IF OIE=1

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ST72325xx

ON-CHIP PERIPHERALS (Cont’d)

Input capture function
This mode allows the measurement of external External interrupt capability
signal pulse widths through ARTICRx registers. This mode allows the Input capture capabilities to
Each input capture can generate an interrupt inde- be used as external interrupt sources. The inter-
pendently on a selected input signal transition. rupts are generated on the edge of the ARTICx
This event is flagged by a set of the corresponding signal.
CFx bits of the Input Capture Control/Status regis- The edge sensitivity of the external interrupts is
ter (ARTICCSR). programmable (CSx bit of ARTICCSR register)
These input capture interrupts are enabled and they are independently enabled through CIEx
through the CIEx bits of the ARTICCSR register. bits of the ARTICCSR register. After fetching the
The active transition (falling or rising edge) is soft- interrupt vector, the CFx flags can be read to iden-
ware programmable through the CSx bits of the tify the interrupt source.
ARTICCSR register. During HALT mode, the external interrupts can be
The read only input capture registers (ARTICRx) used to wake up the micro (if the CIEx bit is set).
are used to latch the auto-reload counter value
when a transition is detected on the ARTICx pin
(CFx bit set in ARTICCSR register). After fetching
the interrupt vector, the CFx flags can be read to
identify the interrupt source.
Note: After a capture detection, data transfer in
the ARTICRx register is inhibited until it is read
(clearing the CFx bit).
The timer interrupt remains pending while the CFx
flag is set when the interrupt is enabled (CIEx bit
set). This means, the ARTICRx register has to be
read at each capture event to clear the CFx flag.

The timing resolution is given by auto-reload coun-

ter cycle time (1/fCOUNTER).

Note: During HALT mode, if both input capture

and external clock are enabled, the ARTICRx reg-
ister value is not guaranteed if the input capture
pin and the external clock change simultaneously.
Figure 44. Input Capture Timing Diagram

fCOUNTER

COUNTER
01h 02h 03h 04h 05h 06h 07h

ARTICx PIN INTERRUPT

CFx FLAG

xxh 04h
ICRx REGISTER
t

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 ST72325xx

ON-CHIP PERIPHERALS (Cont’d)

10.3.3 Register Description
CONTROL / STATUS REGISTER (ARTCSR) 0: New transition not yet reached
Read/Write 1: Transition reached
Reset Value: 0000 0000 (00h) COUNTER ACCESS REGISTER (ARTCAR)
7 0
Read/Write
Reset Value: 0000 0000 (00h)
EXCL CC2 CC1 CC0 TCE FCRL OIE OVF
7 0

Bit 7 = EXCL External Clock CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
This bit is set and cleared by software. It selects the
input clock for the 7-bit prescaler.
0: CPU clock. Bit 7:0 = CA[7:0] Counter Access Data
1: External clock. These bits can be set and cleared either by hard-
Bit 6:4 = CC[2:0] Counter Clock Control ware or by software. The ARTCAR register is used
These bits are set and cleared by software. They to read or write the auto-reload counter “on the fly”
determine the prescaler division ratio from fINPUT. (while it is counting).

fCOUNTER With fINPUT=8 MHz CC2 CC1 CC0

fINPUT 8 MHz 0 0 0
fINPUT / 2 4 MHz 0 0 1 AUTO-RELOAD REGISTER (ARTARR)
fINPUT / 4 2 MHz 0 1 0 Read/Write
fINPUT / 8 1 MHz 0 1 1
fINPUT / 16 500 kHz 1 0 0 Reset Value: 0000 0000 (00h)
fINPUT / 32 250 kHz 1 0 1
7 0
fINPUT / 64 125 kHz 1 1 0
fINPUT / 128 62.5 kHz 1 1 1 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0

Bit 3 = TCE Timer Counter Enable

This bit is set and cleared by software. It puts the Bit 7:0 = AR[7:0] Counter Auto-Reload Data
timer in the lowest power consumption mode. These bits are set and cleared by software. They
0: Counter stopped (prescaler and counter frozen). are used to hold the auto-reload value which is au-
1: Counter running. tomatically loaded in the counter when an overflow
Bit 2 = FCRL Force Counter Re-Load occurs. At the same time, the PWM output levels
This bit is write-only and any attempt to read it will are changed according to the corresponding OPx
yield a logical zero. When set, it causes the contents bit in the PWMCR register.
of ARTARR register to be loaded into the counter, This register has two PWM management func-
and the content of the prescaler register to be tions:
cleared in order to initialize the timer before starting
– Adjusting the PWM frequency
to count.
– Setting the PWM duty cycle resolution
Bit 1 = OIE Overflow Interrupt Enable
This bit is set and cleared by software. It allows to PWM Frequency vs Resolution:
enable/disable the interrupt which is generated
when the OVF bit is set. ARTARR fPWM
0: Overflow Interrupt disable. Resolution
value Min Max
1: Overflow Interrupt enable.
Bit 0 = OVF Overflow Flag 0 8-bit ~0.244 kHz 31.25 kHz
This bit is set by hardware and cleared by software [ 0..127 ] > 7-bit ~0.244 kHz 62.5 kHz
reading the ARTCSR register. It indicates the tran- [ 128..191 ] > 6-bit ~0.488 kHz 125 kHz
sition of the counter from FFh to the ARTARR val- [ 192..223 ] > 5-bit ~0.977 kHz 250 kHz
ue.
[ 224..239 ] > 4-bit ~1.953 kHz 500 kHz

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ST72325xx

ON-CHIP PERIPHERALS (Cont’d)

PWM CONTROL REGISTER (PWMCR) DUTY CYCLE REGISTERS (PWMDCRx)
Read/Write Read/Write
Reset Value: 0000 0000 (00h) Reset Value: 0000 0000 (00h)
7 0 7 0

OE3 OE2 OE1 OE0 OP3 OP2 OP1 OP0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

Bit 7:4 = OE[3:0] PWM Output Enable Bit 7:0 = DC[7:0] Duty Cycle Data
These bits are set and cleared by software. They These bits are set and cleared by software.
enable or disable the PWM output channels inde-
pendently acting on the corresponding I/O pin. A PWMDCRx register is associated with the OCRx
0: PWM output disabled. register of each PWM channel to determine the
1: PWM output enabled. second edge location of the PWM signal (the first
edge location is common to all channels and given
by the ARTARR register). These PWMDCR regis-
Bit 3:0 = OP[3:0] PWM Output Polarity ters allow the duty cycle to be set independently
These bits are set and cleared by software. They for each PWM channel.
independently select the polarity of the four PWM
output signals.
PWMx output level
OPx
Counter <= OCRx Counter > OCRx
1 0 0
0 1 1

Note: When an OPx bit is modified, the PWMx out-

put signal polarity is immediately reversed.

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 ST72325xx

ON-CHIP PERIPHERALS (Cont’d)

INPUT CAPTURE INPUT CAPTURE REGISTERS (ARTICRx)
CONTROL / STATUS REGISTER (ARTICCSR) Read only
Read/Write Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7 0
7 0
IC7 IC6 IC5 IC4 IC3 IC2 IC1 IC0
0 0 CS2 CS1 CIE2 CIE1 CF2 CF1

Bit 7:0 = IC[7:0] Input Capture Data

Bit 7:6 = Reserved, always read as 0. These read only bits are set and cleared by hard-
ware. An ARTICRx register contains the 8-bit
Bit 5:4 = CS[2:1] Capture Sensitivity auto-reload counter value transferred by the input
These bits are set and cleared by software. They capture channel x event.
determine the trigger event polarity on the corre-
sponding input capture channel.
0: Falling edge triggers capture on channel x.
1: Rising edge triggers capture on channel x.

Bit 3:2 = CIE[2:1] Capture Interrupt Enable

These bits are set and cleared by software. They
enable or disable the Input capture channel inter-
rupts independently.
0: Input capture channel x interrupt disabled.
1: Input capture channel x interrupt enabled.

Bit 1:0 = CF[2:1] Capture Flag

These bits are set by hardware and cleared by
software reading the corresponding ARTICRx reg-
ister. Each CFx bit indicates that an input capture x
has occurred.
0: No input capture on channel x.
1: An input capture has occurred on channel x.

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ST72325xx

PWM AUTO-RELOAD TIMER (Cont’d)

Table 17. PWM Auto-Reload Timer Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

PWMDCR3 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

0073h
Reset Value 0 0 0 0 0 0 0 0

PWMDCR2 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

0074h
Reset Value 0 0 0 0 0 0 0 0

PWMDCR1 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

0075h
Reset Value 0 0 0 0 0 0 0 0

PWMDCR0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

0076h
Reset Value 0 0 0 0 0 0 0 0

PWMCR OE3 OE2 OE1 OE0 OP3 OP2 OP1 OP0

0077h
Reset Value 0 0 0 0 0 0 0 0

ARTCSR EXCL CC2 CC1 CC0 TCE FCRL RIE OVF

0078h
Reset Value 0 0 0 0 0 0 0 0

ARTCAR CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0

0079h
Reset Value 0 0 0 0 0 0 0 0

ARTARR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0

007Ah
Reset Value 0 0 0 0 0 0 0 0

ARTICCSR CS2 CS1 CIE2 CIE1 CF2 CF1

007Bh
Reset Value 0 0 0 0 0 0 0 0

ARTICR1 IC7 IC6 IC5 IC4 IC3 IC2 IC1 IC0

007Ch
Reset Value 0 0 0 0 0 0 0 0

ARTICR2 IC7 IC6 IC5 IC4 IC3 IC2 IC1 IC0

007Dh
Reset Value 0 0 0 0 0 0 0 0

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 ST72325xx

10.4 16-BIT TIMER

10.4.1 Introduction When reading an input signal on a non-bonded
The timer consists of a 16-bit free-running counter pin, the value will always be ‘1’.
driven by a programmable prescaler. 10.4.3 Functional Description
It may be used for a variety of purposes, including 10.4.3.1 Counter
pulse length measurement of up to two input sig- The main block of the Programmable Timer is a
nals (input capture) or generation of up to two out- 16-bit free running upcounter and its associated
put waveforms (output compare and PWM). 16-bit registers. The 16-bit registers are made up
Pulse lengths and waveform periods can be mod- of two 8-bit registers called high and low.
ulated from a few microseconds to several milli- Counter Register (CR):
seconds using the timer prescaler and the CPU
clock prescaler. – Counter High Register (CHR) is the most sig-
nificant byte (MS Byte).
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not – Counter Low Register (CLR) is the least sig-
share any resources. They are synchronized after nificant byte (LS Byte).
a MCU reset as long as the timer clock frequen- Alternate Counter Register (ACR)
cies are not modified. – Alternate Counter High Register (ACHR) is the
This description covers one or two 16-bit timers. In most significant byte (MS Byte).
ST7 devices with two timers, register names are – Alternate Counter Low Register (ACLR) is the
prefixed with TA (Timer A) or TB (Timer B). least significant byte (LS Byte).
10.4.2 Main Features These two read-only 16-bit registers contain the
■ Programmable prescaler: fCPU divided by 2, 4 or 8 same value but with the difference that reading the
■ Overflow status flag and maskable interrupt
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
■ External clock input (must be at least four times
(see note at the end of paragraph titled 16-bit read
slower than the CPU clock speed) with the choice sequence).
of active edge
Writing in the CLR register or ACLR register resets
■ 1 or 2 Output Compare functions each with:
the free running counter to the FFFCh value.
– 2 dedicated 16-bit registers Both counters have a reset value of FFFCh (this is
– 2 dedicated programmable signals the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
– 2 dedicated status flags FFFCh in One Pulse mode and PWM mode.
– 1 dedicated maskable interrupt
■ 1 or 2 Input Capture functions each with:
The timer clock depends on the clock control bits
– 2 dedicated 16-bit registers of the CR2 register, as illustrated in Table 1. The
– 2 dedicated active edge selection signals value in the counter register repeats every
131072, 262144 or 524288 CPU clock cycles de-
– 2 dedicated status flags pending on the CC[1:0] bits.
– 1 dedicated maskable interrupt The timer frequency can be fCPU/2, fCPU/4, fCPU/8
■ Pulse width modulation mode (PWM) or an external frequency.
■ One Pulse mode

■ Reduced Power Mode

■ 5 alternate functions on I/O ports (ICAP1, ICAP2,

OCMP1, OCMP2, EXTCLK)*

The Block Diagram is shown in Figure 1.

*Note: Some timer pins may not be available (not
bonded) in some ST7 devices. Refer to the device
pin out description.

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ST72325xx

16-BIT TIMER (Cont’d)

Figure 45. Timer Block Diagram

ST7 INTERNAL BUS

fCPU
MCU-PERIPHERAL INTERFACE

8 high 8 low
8-bit 8 8 8 8 8 8 8 8
buffer

high

high

high

high
low

low

low

low
EXEDG
16

1/2 OUTPUT OUTPUT INPUT INPUT

COUNTER
COMPARE COMPARE CAPTURE CAPTURE
1/4
REGISTER REGISTER REGISTER REGISTER REGISTER
1/8
1 2 1 2
EXTCLK ALTERNATE
pin COUNTER
16 16
REGISTER
16
CC[1:0]
TIMER INTERNAL BUS
16 16

OVERFLOW
OUTPUT COMPARE EDGE DETECT ICAP1
DETECT
CIRCUIT CIRCUIT1 pin
CIRCUIT

6 EDGE DETECT ICAP2

CIRCUIT2 pin

LATCH1 OCMP1
pin
ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0
(Control/Status Register) LATCH2 OCMP2
CSR pin

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

(Control Register 1) CR1 (Control Register 2) CR2

(See note)

TIMER INTERRUPT Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)

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 ST72325xx

16-BIT TIMER (Cont’d)

16-bit read sequence: (from either the Counter Clearing the overflow interrupt request is done in
Register or the Alternate Counter Register). two steps:
Beginning of the sequence 1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Read LS Byte Notes: The TOF bit is not cleared by accesses to
At t0 MS Byte is buffered ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
Other it allows simultaneous use of the overflow function
instructions and reading the free running counter at random
times (for example, to measure elapsed time) with-
Read Returns the buffered out the risk of clearing the TOF bit erroneously.
At t0 +Δt LS Byte LS Byte value at t0 The timer is not affected by WAIT mode.
Sequence completed In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
The user must read the MS Byte first, then the LS previous count (MCU awakened by an interrupt) or
Byte value is buffered automatically. from the reset count (MCU awakened by a Reset).
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the 10.4.3.2 External Clock
user reads the MS Byte several times.
The external clock (where available) is selected if
After a complete reading sequence, if only the CC0 = 1 and CC1 = 1 in the CR2 register.
CLR register or ACLR register are read, they re-
The status of the EXEDG bit in the CR2 register
turn the LS Byte of the count value at the time of
determines the type of level transition on the exter-
the read.
nal clock pin EXTCLK that will trigger the free run-
Whatever the timer mode used (input capture, out- ning counter.
put compare, One Pulse mode or PWM mode) an
The counter is synchronized with the falling edge
overflow occurs when the counter rolls over from
of the internal CPU clock.
FFFFh to 0000h then:
A minimum of four falling edges of the CPU clock
– The TOF bit of the SR register is set.
must occur between two consecutive active edges
– A timer interrupt is generated if: of the external clock; thus the external clock fre-
– TOIE bit of the CR1 register is set and quency must be less than a quarter of the CPU
clock frequency.
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.

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ST72325xx

16-BIT TIMER (Cont’d)

Figure 46. Counter Timing Diagram, Internal Clock Divided by 2

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFD FFFE FFFF 0000 0001 0002 0003

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Figure 47. Counter Timing Diagram, Internal Clock Divided by 4

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER FFFC FFFD 0000 0001

TIMER OVERFLOW FLAG (TOF)

Figure 48. Counter Timing Diagram, Internal Clock Divided By 8

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER FFFC FFFD 0000

TIMER OVERFLOW FLAG (TOF)

Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.

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 ST72325xx

16-BIT TIMER (Cont’d)

10.4.3.3 Input Capture When an input capture occurs:
In this section, the index, i, may be 1 or 2 because – ICFi bit is set.
there are two input capture functions in the 16-bit – The ICiR register contains the value of the free
timer. running counter on the active transition on the
The two 16-bit input capture registers (IC1R and ICAPi pin (see Figure 6).
IC2R) are used to latch the value of the free run- – A timer interrupt is generated if the ICIE bit is set
ning counter after a transition is detected on the and the I bit is cleared in the CC register. Other-
ICAPi pin (see Figure 5). wise, the interrupt remains pending until both
MS Byte LS Byte conditions become true.
ICiR ICiHR ICiLR Clearing the Input Capture interrupt request (that
is, clearing the ICFi bit) is done in two steps:
ICiR register is a read-only register. 1. Reading the SR register while the ICFi bit is set.
The active transition is software programmable 2. An access (read or write) to the ICiLR register.
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
counter: (fCPU/CC[1:0]). Notes:
1. After reading the ICiHR register, transfer of
input capture data is inhibited and ICFi will
Procedure: never be set until the ICiLR register is also
To use the input capture function select the follow- read.
ing in the CR2 register: 2. The ICiR register contains the free running
– Select the timer clock (CC[1:0]) (see Table 1). counter value which corresponds to the most
– Select the edge of the active transition on the recent input capture.
ICAP2 pin with the IEDG2 bit (the ICAP2 pin 3. The two input capture functions can be used
must be configured as floating input or input with together even if the timer also uses the two out-
pull-up without interrupt if this configuration is put compare functions.
available). 4. In One Pulse mode and PWM mode only Input
And select the following in the CR1 register: Capture 2 can be used.
– Set the ICIE bit to generate an interrupt after an 5. The alternate inputs (ICAP1 and ICAP2) are
input capture coming from either the ICAP1 pin always directly connected to the timer. So any
or the ICAP2 pin transitions on these pins activates the input
– Select the edge of the active transition on the capture function.
ICAP1 pin with the IEDG1 bit (the ICAP1pin must Moreover if one of the ICAPi pins is configured
be configured as floating input or input with pull- as an input and the second one as an output,
up without interrupt if this configuration is availa- an interrupt can be generated if the user tog-
ble). gles the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion i is disabled by reading the ICiHR (see note
1).
6. The TOF bit can be used with interrupt genera-
tion in order to measure events that go beyond
the timer range (FFFFh).

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ST72325xx

16-BIT TIMER (Cont’d)

Figure 49. Input Capture Block Diagram

ICAP1 (Control Register 1) CR1

pin
EDGE DETECT EDGE DETECT ICIE IEDG1
ICAP2 CIRCUIT2 CIRCUIT1
pin (Status Register) SR

IC2R Register IC1R Register ICF1 ICF2 0 0 0

16-BIT (Control Register 2) CR2

16-BIT FREE RUNNING CC1 CC0 IEDG2

COUNTER

Figure 50. Input Capture Timing Diagram

TIMER CLOCK

COUNTER REGISTER FF01 FF02 FF03

ICAPi PIN

ICAPi FLAG

ICAPi REGISTER FF03

Note: The rising edge is the active edge.

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 ST72325xx

16-BIT TIMER (Cont’d)

10.4.3.4 Output Compare – The OCMPi pin takes OLVLi bit value (OCMPi
In this section, the index, i, may be 1 or 2 because pin latch is forced low during reset).
there are two output compare functions in the 16- – A timer interrupt is generated if the OCIE bit is
bit timer. set in the CR1 register and the I bit is cleared in
This function can be used to control an output the CC register (CC).
waveform or indicate when a period of time has
elapsed. The OCiR register value required for a specific tim-
When a match is found between the Output Com- ing application can be calculated using the follow-
pare register and the free running counter, the out- ing formula:
put compare function:
– Assigns pins with a programmable value if the Δt * fCPU
OCiE bit is set Δ OCiR =
PRESC
– Sets a flag in the status register
Where:
– Generates an interrupt if enabled
Δt = Output compare period (in seconds)
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R) fCPU = CPU clock frequency (in hertz)
contain the value to be compared to the counter PRESC = Timer prescaler factor (2, 4 or 8 de-
register each timer clock cycle. pending on CC[1:0] bits, see Table 1)
MS Byte LS Byte
OCiR OCiHR OCiLR If the timer clock is an external clock, the formula
is:
These registers are readable and writable and are
not affected by the timer hardware. A reset event Δ OCiR = Δt * fEXT
changes the OCiR value to 8000h.
Where:
Timing resolution is one count of the free running
counter: (fCPU/CC[1:0]). Δt = Output compare period (in seconds)
fEXT = External timer clock frequency (in hertz)
Procedure:
To use the output compare function, select the fol- Clearing the output compare interrupt request
lowing in the CR2 register: (that is, clearing the OCFi bit) is done by:
– Set the OCiE bit if an output is needed then the 1. Reading the SR register while the OCFi bit is
OCMPi pin is dedicated to the output compare i set.
signal. 2. An access (read or write) to the OCiLR register.
– Select the timer clock (CC[1:0]) (see Table 1). The following procedure is recommended to pre-
And select the following in the CR1 register: vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs. – Write to the OCiHR register (further compares
are inhibited).
– Set the OCIE bit to generate an interrupt if it is
needed. – Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
When a match is found between OCiR register
and CR register: – Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
– OCFi bit is set.

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Notes: Forced Compare Output capability
1. After a processor write cycle to the OCiHR reg- When the FOLVi bit is set by software, the OLVLi
ister, the output compare function is inhibited bit is copied to the OCMPi pin. The OLVi bit has to
until the OCiLR register is also written. be toggled in order to toggle the OCMPi pin when
2. If the OCiE bit is not set, the OCMPi pin is a it is enabled (OCiE bit = 1). The OCFi bit is then
general I/O port and the OLVLi bit will not not set by hardware, and thus no interrupt request
appear when a match is found but an interrupt is generated.
could be generated if the OCIE bit is set. The FOLVLi bits have no effect in both One Pulse
3. In both internal and external clock modes, mode and PWM mode.
OCFi and OCMPi are set while the counter
value equals the OCiR register value (see Fig-
ure 8 for an example with fCPU/2 and Figure 9
for an example with fCPU/4). This behavior is
the same in OPM or PWM mode.
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.

Figure 51. Output Compare Block Diagram

16 BIT FREE RUNNING OC1E OC2E CC1 CC0

COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE Latch
OCIE FOLV2 FOLV1 OLVL2 OLVL1 OCMP1
CIRCUIT 1
Pin
16-bit 16-bit
Latch
2
OCMP2
OC1R Register Pin
OCF1 OCF2 0 0 0
OC2R Register
(Status Register) SR

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Figure 52. Output Compare Timing Diagram, fTIMER = fCPU/2

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4

OUTPUT COMPARE REGISTER i (OCRi) 2ED3

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi = 1)

Figure 53. Output Compare Timing Diagram, fTIMER = fCPU/4

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4

OUTPUT COMPARE REGISTER i (OCRi) 2ED3

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi = 1)

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16-BIT TIMER (Cont’d)

10.4.3.5 One Pulse Mode Clearing the Input Capture interrupt request (that
One Pulse mode enables the generation of a is, clearing the ICFi bit) is done in two steps:
pulse when an external event occurs. This mode is 1. Reading the SR register while the ICFi bit is set.
selected via the OPM bit in the CR2 register. 2. An access (read or write) to the ICiLR register.
The One Pulse mode uses the Input Capture1 The OC1R register value required for a specific
function and the Output Compare1 function. timing application can be calculated using the fol-
Procedure: lowing formula:
To use One Pulse mode: t * fCPU -5
OCiR Value =
1. Load the OC1R register with the value corre- PRESC
sponding to the length of the pulse (see the for- Where:
mula in the opposite column). t = Pulse period (in seconds)
2. Select the following in the CR1 register: fCPU = CPU clock frequency (in hertz)
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse. PRESC = Timer prescaler factor (2, 4 or 8 depend-
ing on the CC[1:0] bits, see Table 1)
– Using the OLVL2 bit, select the level to be ap- If the timer clock is an external clock the formula is:
plied to the OCMP1 pin during the pulse.
– Select the edge of the active transition on the OCiR = t * fEXT -5
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input). Where:
3. Select the following in the CR2 register: t = Pulse period (in seconds)
– Set the OC1E bit, the OCMP1 pin is then ded- fEXT = External timer clock frequency (in hertz)
icated to the Output Compare 1 function.
– Set the OPM bit. When the value of the counter is equal to the value
– Select the timer clock CC[1:0] (see Table 1). of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 10).

One Pulse mode cycle

Notes:
ICR1 = Counter 1. The OCF1 bit cannot be set by hardware in
When One Pulse mode but the OCF2 bit can generate
event occurs OCMP1 = OLVL2
an Output Compare interrupt.
on ICAP1 Counter is reset
to FFFCh 2. When the Pulse Width Modulation (PWM) and
One Pulse mode (OPM) bits are both set, the
ICF1 bit is set PWM mode is the only active one.
3. If OLVL1 = OLVL2 a continuous signal will be
When
Counter seen on the OCMP1 pin.
= OC1R OCMP1 = OLVL1 4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
Then, on a valid event on the ICAP1 pin, the coun- loaded) but the user must take care that the
ter is initialized to FFFCh and OLVL2 bit is loaded counter is reset each time a valid edge occurs
on the OCMP1 pin, the ICF1 bit is set and the val- on the ICAP1 pin and ICF1 can also generates
ue FFFDh is loaded in the IC1R register. interrupt if ICIE is set.
Because the ICF1 bit is set when an active edge 5. When One Pulse mode is used OC1R is dedi-
occurs, an interrupt can be generated if the ICIE cated to this mode. Nevertheless OC2R and
bit is set. OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an out-
put waveform because the level OLVL2 is dedi-
cated to the One Pulse mode.

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Figure 54. One Pulse Mode Timing Example

IC1R 01F8 2ED3

01F8 FFFC FFFD FFFE 2ED0 2ED1 2ED2 FFFC FFFD

COUNTER
2ED3

ICAP1

OLVL2 OLVL1 OLVL2

OCMP1
compare1

Note: IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1

Figure 55. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions

COUNTER 34E2 FFFC FFFD FFFE 2ED0 2ED1 2ED2 34E2 FFFC

OCMP1 OLVL2 OLVL1 OLVL2

compare2 compare1 compare2

Note: OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1

Note: On timers with only one Output Compare register, a fixed frequency PWM signal can be generated
using the output compare and the counter overflow to define the pulse length.

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10.4.3.6 Pulse Width Modulation Mode If OLVL1 = 1 and OLVL2 = 0 the length of the pos-
Pulse Width Modulation (PWM) mode enables the itive pulse is the difference between the OC2R and
generation of a signal with a frequency and pulse OC1R registers.
length determined by the value of the OC1R and If OLVL1 = OLVL2 a continuous signal will be
OC2R registers. seen on the OCMP1 pin.
Pulse Width Modulation mode uses the complete The OCiR register value required for a specific tim-
Output Compare 1 function plus the OC2R regis- ing application can be calculated using the follow-
ter, and so this functionality can not be used when ing formula:
PWM mode is activated. t * fCPU
OCiR Value =
-5
In PWM mode, double buffering is implemented on
PRESC
the output compare registers. Any new values writ-
ten in the OC1R and OC2R registers are taken Where:
into account only at the end of the PWM period t = Signal or pulse period (in seconds)
(OC2) to avoid spikes on the PWM output pin fCPU = CPU clock frequency (in hertz)
(OCMP1).
PRESC = Timer prescaler factor (2, 4 or 8 depend-
Procedure ing on CC[1:0] bits, see Table 1)
To use Pulse Width Modulation mode: If the timer clock is an external clock the formula is:
1. Load the OC2R register with the value corre-
sponding to the period of the signal using the OCiR = t * fEXT -5
formula in the opposite column. Where:
2. Load the OC1R register with the value corre- t = Signal or pulse period (in seconds)
sponding to the period of the pulse if
(OLVL1 = 0 and OLVL2 = 1) using the formula fEXT = External timer clock frequency (in hertz)
in the opposite column.
3. Select the following in the CR1 register: The Output Compare 2 event causes the counter
– Using the OLVL1 bit, select the level to be ap- to be initialized to FFFCh (See Figure 11)
plied to the OCMP1 pin after a successful Notes:
comparison with the OC1R register.
1. After a write instruction to the OCiHR register,
– Using the OLVL2 bit, select the level to be ap- the output compare function is inhibited until the
plied to the OCMP1 pin after a successful OCiLR register is also written.
comparison with the OC2R register.
2. The OCF1 and OCF2 bits cannot be set by
4. Select the following in the CR2 register: hardware in PWM mode therefore the Output
– Set OC1E bit: the OCMP1 pin is then dedicat- Compare interrupt is inhibited.
ed to the output compare 1 function. 3. The ICF1 bit is set by hardware when the coun-
– Set the PWM bit. ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
– Select the timer clock (CC[1:0]) (see Table 1).
cleared.
Pulse Width Modulation cycle 4. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is discon-
When nected to the timer. The ICAP2 pin can be used
Counter OCMP1 = OLVL1 to perform input capture (ICF2 can be set and
= OC1R IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
When OCMP1 = OLVL2 5. When the Pulse Width Modulation (PWM) and
Counter Counter is reset One Pulse mode (OPM) bits are both set, the
= OC2R to FFFCh PWM mode is the only active one.
ICF1 bit is set

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16-BIT TIMER (Cont’d)

10.4.4 Low Power Modes
Mode Description
No effect on 16-bit Timer.
WAIT
Timer interrupts cause the device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
HALT reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.

10.4.5 Interrupts
Enable Exit Exit
Event
Interrupt Event Control from from
Flag
Bit Wait Halt
Input Capture 1 event/Counter reset in PWM mode ICF1
ICIE
Input Capture 2 event ICF2
Output Compare 1 event (not available in PWM mode) OCF1 Yes No
OCIE
Output Compare 2 event (not available in PWM mode) OCF2
Timer Overflow event TOF TOIE

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).

10.4.6 Summary of Timer Modes

TIMER RESOURCES
MODES
Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2
Input Capture (1 and/or 2)
Yes Yes Yes Yes
Output Compare (1 and/or 2)
One Pulse Mode Not Recommended1) Partially 2)
No No
PWM Mode Not Recommended3) No

1) See note 4 in Section 0.1.3.5 One Pulse Mode

2) See note 5 in Section 0.1.3.5 One Pulse Mode
3) See note 4 in Section 0.1.3.6 Pulse Width Modulation Mode

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10.4.7 Register Description Bit 4 = FOLV2 Forced Output Compare 2.
Each Timer is associated with three control and This bit is set and cleared by software.
status registers, and with six pairs of data registers 0: No effect on the OCMP2 pin.
(16-bit values) relating to the two input captures, 1: Forces the OLVL2 bit to be copied to the
the two output compares, the counter and the al- OCMP2 pin, if the OC2E bit is set and even if
ternate counter. there is no successful comparison.

CONTROL REGISTER 1 (CR1) Bit 3 = FOLV1 Forced Output Compare 1.

This bit is set and cleared by software.
Read/Write 0: No effect on the OCMP1 pin.
Reset Value: 0000 0000 (00h) 1: Forces OLVL1 to be copied to the OCMP1 pin, if
7 0 the OC1E bit is set and even if there is no suc-
cessful comparison.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 2 = OLVL2 Output Level 2.
Bit 7 = ICIE Input Capture Interrupt Enable. This bit is copied to the OCMP2 pin whenever a
0: Interrupt is inhibited. successful comparison occurs with the OC2R reg-
1: A timer interrupt is generated whenever the ister and OCxE is set in the CR2 register. This val-
ICF1 or ICF2 bit of the SR register is set. ue is copied to the OCMP1 pin in One Pulse mode
and Pulse Width Modulation mode.

Bit 6 = OCIE Output Compare Interrupt Enable.

0: Interrupt is inhibited. Bit 1 = IEDG1 Input Edge 1.
1: A timer interrupt is generated whenever the This bit determines which type of level transition
OCF1 or OCF2 bit of the SR register is set. on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF Bit 0 = OLVL1 Output Level 1.
bit of the SR register is set. The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.

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16-BIT TIMER (Cont’d)

CONTROL REGISTER 2 (CR2) Bit 4 = PWM Pulse Width Modulation.
Read/Write 0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
Reset Value: 0000 0000 (00h) programmable cyclic signal; the length of the
7 0
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Bit 3, 2 = CC[1:0] Clock Control.

Bit 7 = OC1E Output Compare 1 Pin Enable.
The timer clock mode depends on these bits:
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com- Table 18. Clock Control Bits
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E Timer Clock CC1 CC0
bit, the Output Compare 1 function of the timer re- fCPU / 4 0
mains active. 0
fCPU / 2 1
0: OCMP1 pin alternate function disabled (I/O pin fCPU / 8 0
free for general-purpose I/O). 1
1: OCMP1 pin alternate function enabled. External Clock (where available) 1

Bit 6 = OC2E Output Compare 2 Pin Enable. Note: If the external clock pin is not available, pro-
This bit is used only to output the signal from the gramming the external clock configuration stops
timer on the OCMP2 pin (OLV2 in Output Com- the counter.
pare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer re-
Bit 1 = IEDG2 Input Edge 2.
mains active.
This bit determines which type of level transition
0: OCMP2 pin alternate function disabled (I/O pin
on the ICAP2 pin will trigger the capture.
free for general-purpose I/O).
0: A falling edge triggers the capture.
1: OCMP2 pin alternate function enabled.
1: A rising edge triggers the capture.

Bit 5 = OPM One Pulse Mode.

Bit 0 = EXEDG External Clock Edge.
0: One Pulse mode is not active.
This bit determines which type of level transition
1: One Pulse mode is active, the ICAP1 pin can be
on the external clock pin EXTCLK will trigger the
used to trigger one pulse on the OCMP1 pin; the
counter register.
active transition is given by the IEDG1 bit. The
0: A falling edge triggers the counter register.
length of the generated pulse depends on the
1: A rising edge triggers the counter register.
contents of the OC1R register.

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16-BIT TIMER (Cont’d)

CONTROL/STATUS REGISTER (CSR) Note: Reading or writing the ACLR register does
Read/Write (bits 7:3 read only) not clear TOF.
Reset Value: xxxx x0xx (xxh)
7 0 Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0 1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
Bit 7 = ICF1 Input Capture Flag 1. (IC2LR) register.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin Bit 3 = OCF2 Output Compare Flag 2.
or the counter has reached the OC2R value in 0: No match (reset value).
PWM mode. To clear this bit, first read the SR 1: The content of the free running counter has
register, then read or write the low byte of the matched the content of the OC2R register. To
IC1R (IC1LR) register. clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
Bit 6 = OCF1 Output Compare Flag 1. ister.
0: No match (reset value).
1: The content of the free running counter has Bit 2 = TIMD Timer disable.
matched the content of the OC1R register. To This bit is set and cleared by software. When set, it
clear this bit, first read the SR register, then read freezes the timer prescaler and counter and disa-
or write the low byte of the OC1R (OC1LR) reg- bled the output functions (OCMP1 and OCMP2
ister. pins) to reduce power consumption. Access to the
timer registers is still available, allowing the timer
Bit 5 = TOF Timer Overflow Flag. configuration to be changed, or the counter reset,
0: No timer overflow (reset value). while it is disabled.
1: The free running counter rolled over from FFFFh 0: Timer enabled
to 0000h. To clear this bit, first read the SR reg- 1: Timer prescaler, counter and outputs disabled
ister, then read or write the low byte of the CR
(CLR) register. Bits 1:0 = Reserved, must be kept cleared.

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16-BIT TIMER (Cont’d)

INPUT CAPTURE 1 HIGH REGISTER (IC1HR) OUTPUT COMPARE 1 HIGH REGISTER
Read Only (OC1HR)
Reset Value: Undefined Read/Write
This is an 8-bit read only register that contains the Reset Value: 1000 0000 (80h)
high part of the counter value (transferred by the This is an 8-bit register that contains the high part
input capture 1 event). of the value to be compared to the CHR register.
7 0 7 0

MSB LSB MSB LSB

INPUT CAPTURE 1 LOW REGISTER (IC1LR) OUTPUT COMPARE 1 LOW REGISTER

Read Only (OC1LR)
Reset Value: Undefined Read/Write
This is an 8-bit read only register that contains the Reset Value: 0000 0000 (00h)
low part of the counter value (transferred by the in- This is an 8-bit register that contains the low part of
put capture 1 event). the value to be compared to the CLR register.
7 0 7 0

MSB LSB MSB LSB

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16-BIT TIMER (Cont’d)

OUTPUT COMPARE 2 HIGH REGISTER ALTERNATE COUNTER HIGH REGISTER
(OC2HR) (ACHR)
Read/Write Read Only
Reset Value: 1000 0000 (80h) Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part This is an 8-bit register that contains the high part
of the value to be compared to the CHR register. of the counter value.
7 0 7 0

MSB LSB MSB LSB

OUTPUT COMPARE 2 LOW REGISTER ALTERNATE COUNTER LOW REGISTER

(OC2LR) (ACLR)
Read/Write Read Only
Reset Value: 0000 0000 (00h) Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of This is an 8-bit register that contains the low part of
the value to be compared to the CLR register. the counter value. A write to this register resets the
counter. An access to this register after an access
7 0 to CSR register does not clear the TOF bit in the
CSR register.
MSB LSB
7 0

COUNTER HIGH REGISTER (CHR) MSB LSB

Read Only
Reset Value: 1111 1111 (FFh)
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
This is an 8-bit register that contains the high part
of the counter value. Read Only
Reset Value: Undefined
7 0 This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
MSB LSB Input Capture 2 event).
7 0

COUNTER LOW REGISTER (CLR) MSB LSB

Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of INPUT CAPTURE 2 LOW REGISTER (IC2LR)
the counter value. A write to this register resets the
counter. An access to this register after accessing Read Only
the CSR register clears the TOF bit. Reset Value: Undefined
This is an 8-bit read only register that contains the
7 0 low part of the counter value (transferred by the In-
put Capture 2 event).
MSB LSB
7 0

MSB LSB

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16-BIT TIMER (Cont’d)

Table 19. 16-Bit Timer Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
Timer A: 32 CR1 ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Timer B: 42 Reset Value 0 0 0 0 0 0 0 0
Timer A: 31 CR2 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Timer B: 41 Reset Value 0 0 0 0 0 0 0 0
Timer A: 33 CSR ICF1 OCF1 TOF ICF2 OCF2 TIMD - -
Timer B: 43 Reset Value x x x x x 0 x x
Timer A: 34 IC1HR MSB LSB
Timer B: 44 Reset Value x x x x x x x x
Timer A: 35 IC1LR MSB LSB
Timer B: 45 Reset Value x x x x x x x x
Timer A: 36 OC1HR MSB LSB
Timer B: 46 Reset Value 1 0 0 0 0 0 0 0
Timer A: 37 OC1LR MSB LSB
Timer B: 47 Reset Value 0 0 0 0 0 0 0 0
Timer A: 3E OC2HR MSB LSB
Timer B: 4E Reset Value 1 0 0 0 0 0 0 0
Timer A: 3F OC2LR MSB LSB
Timer B: 4F Reset Value 0 0 0 0 0 0 0 0
Timer A: 38 CHR MSB LSB
Timer B: 48 Reset Value 1 1 1 1 1 1 1 1
Timer A: 39 CLR MSB LSB
Timer B: 49 Reset Value 1 1 1 1 1 1 0 0
Timer A: 3A ACHR MSB LSB
Timer B: 4A Reset Value 1 1 1 1 1 1 1 1
Timer A: 3B ACLR MSB LSB
Timer B: 4B Reset Value 1 1 1 1 1 1 0 0
Timer A: 3C IC2HR MSB LSB
Timer B: 4C Reset Value x x x x x x x x
Timer A: 3D IC2LR MSB LSB
Timer B: 4D Reset Value x x x x x x x x

Related Documentation AN1041: Using ST7 PWM signal to generate ana-

AN 973: SCI software communications using 16- log input (sinusoid)
bit timer AN1046: UART emulation software
AN 974: Real Time Clock with ST7 Timer Output AN1078: PWM duty cycle switch implementing
Compare true 0 or 100 per cent duty cycle
AN 976: Driving a buzzer through the ST7 Timer AN1504: Starting a PWM signal directly at high
PWM function level using the ST7 16-Bit timer

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10.5 SERIAL PERIPHERAL INTERFACE (SPI)

10.5.1 Introduction Note: In slave mode, continuous transmission is
The Serial Peripheral Interface (SPI) allows full- not possible at maximum frequency due to the
duplex, synchronous, serial communication with software overhead for clearing status flags and to
external devices. An SPI system may consist of a initiate the next transmission sequence.
master and one or more slaves however the SPI 10.5.3 General Description
interface can not be a master in a multi-master Figure 56 shows the serial peripheral interface
system. (SPI) block diagram. There are 3 registers:
10.5.2 Main Features – SPI Control Register (SPICR)
■ Full duplex synchronous transfers (on 3 lines)
– SPI Control/Status Register (SPICSR)
■ Simplex synchronous transfers (on 2 lines)
– SPI Data Register (SPIDR)
■ Master or slave operation
The SPI is connected to external devices through
■ Six master mode frequencies (fCPU/4 max.)
4 pins:
■ fCPU/2 max. slave mode frequency (see note)
– MISO: Master In / Slave Out data
■ SS Management by software or hardware
– MOSI: Master Out / Slave In data
■ Programmable clock polarity and phase
– SCK: Serial Clock out by SPI masters and in-
■ End of transfer interrupt flag
put by SPI slaves
■ Write collision, Master Mode Fault and Overrun
flags
Figure 56. Serial Peripheral Interface Block Diagram

Data/Address Bus

SPIDR Read
Interrupt
request
Read Buffer

MOSI
7 SPICSR 0
MISO 8-Bit Shift Register
SPIF WCOL OVR MODF 0 SOD SSM SSI

Write
SOD
bit 1
SS
SPI 0
SCK STATE
CONTROL

7 SPICR 0

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

MASTER
CONTROL

SERIAL CLOCK
GENERATOR
SS

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SERIAL PERIPHERAL INTERFACE (Cont’d)

– SS: Slave select: The communication is always initiated by the mas-
This input signal acts as a ‘chip select’ to let ter. When the master device transmits data to a
the SPI master communicate with slaves indi- slave device via MOSI pin, the slave device re-
vidually and to avoid contention on the data sponds by sending data to the master device via
lines. Slave SS inputs can be driven by stand- the MISO pin. This implies full duplex communica-
ard I/O ports on the master MCU. tion with both data out and data in synchronized
10.5.3.1 Functional Description with the same clock signal (which is provided by
the master device via the SCK pin).
A basic example of interconnections between a
single master and a single slave is illustrated in To use a single data line, the MISO and MOSI pins
Figure 57. must be connected at each node ( in this case only
simplex communication is possible).
The MOSI pins are connected together and the
MISO pins are connected together. In this way Four possible data/clock timing relationships may
data is transferred serially between master and be chosen (see Figure 60) but master and slave
slave (most significant bit first). must be programmed with the same timing mode.

Figure 57. Single Master/ Single Slave Application

MASTER SLAVE
MSBit LSBit MSBit LSBit
MISO MISO
8-BIT SHIFT REGISTER 8-BIT SHIFT REGISTER

MOSI MOSI

SPI
SCK SCK
CLOCK
GENERATOR
SS SS
+5V
Not used if SS is managed
by software

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.3.2 Slave Select Management In Slave Mode:
As an alternative to using the SS pin to control the There are two cases depending on the data/clock
Slave Select signal, the application can choose to timing relationship (see Figure 58):
manage the Slave Select signal by software. This If CPHA=1 (data latched on 2nd clock edge):
is configured by the SSM bit in the SPICSR regis-
ter (see Figure 59) – SS internal must be held low during the entire
transmission. This implies that in single slave
In software management, the external SS pin is applications the SS pin either can be tied to
free for other application uses and the internal SS VSS, or made free for standard I/O by manag-
signal level is driven by writing to the SSI bit in the ing the SS function by software (SSM= 1 and
SSI=0 in the in the SPICSR register)
SPICSR register.
If CPHA=0 (data latched on 1st clock edge):
In Master mode:
– SS internal must be held low during byte
– SS internal must be held high continuously transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see Section 10.5.5.3).
Figure 58. Generic SS Timing Diagram

MOSI/MISO Byte 1 Byte 2 Byte 3

Master SS

Slave SS
(if CPHA=0)

Slave SS
(if CPHA=1)

Figure 59. Hardware/Software Slave Select Management

SSM bit

SSI bit 1
SS internal
SS external pin 0

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10.5.3.3 Master Mode Operation Note: While the SPIF bit is set, all writes to the
In master mode, the serial clock is output on the SPIDR register are inhibited until the SPICSR reg-
SCK pin. The clock frequency, polarity and phase ister is read.
are configured by software (refer to the description 10.5.3.5 Slave Mode Operation
of the SPICSR register). In slave mode, the serial clock is received on the
Note: The idle state of SCK must correspond to SCK pin from the master device.
the polarity selected in the SPICSR register (by To operate the SPI in slave mode:
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0). 1. Write to the SPICSR register to perform the fol-
lowing actions:
To operate the SPI in master mode, perform the
following steps in order (if the SPICSR register is – Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits (see
not written first, the SPICR register setting Figure 60).
(MSTR bit) may be not taken into account): Note: The slave must have the same CPOL
1. Write to the SPICR register: and CPHA settings as the master.
– Manage the SS pin as described in Section
– Select the clock frequency by configuring the 10.5.3.2 and Figure 58. If CPHA=1 SS must
SPR[2:0] bits. be held low continuously. If CPHA=0 SS must
– Select the clock polarity and clock phase by be held low during byte transmission and
configuring the CPOL and CPHA bits. Figure pulled up between each byte to let the slave
60 shows the four possible configurations. write in the shift register.
Note: The slave must have the same CPOL 2. Write to the SPICR register to clear the MSTR
and CPHA settings as the master.
bit and set the SPE bit to enable the SPI I/O
2. Write to the SPICSR register: functions.
– Either set the SSM bit and set the SSI bit or 10.5.3.6 Slave Mode Transmit Sequence
clear the SSM bit and tie the SS pin high for
the complete byte transmit sequence. When software writes to the SPIDR register, the
3. Write to the SPICR register: data byte is loaded into the 8-bit shift register and
– Set the MSTR and SPE bits then shifted out serially to the MISO pin most sig-
Note: MSTR and SPE bits remain set only if nificant bit first.
SS is high). The transmit sequence begins when the slave de-
The transmit sequence begins when software vice receives the clock signal and the most signifi-
writes a byte in the SPIDR register. cant bit of the data on its MOSI pin.
10.5.3.4 Master Mode Transmit Sequence When data transfer is complete:
When software writes to the SPIDR register, the – The SPIF bit is set by hardware
data byte is loaded into the 8-bit shift register and
– An interrupt request is generated if SPIE bit is
then shifted out serially to the MOSI pin most sig-
set and interrupt mask in the CCR register is
nificant bit first.
cleared.
When data transfer is complete: Clearing the SPIF bit is performed by the following
– The SPIF bit is set by hardware software sequence:
– An interrupt request is generated if the SPIE 1. An access to the SPICSR register while the
bit is set and the interrupt mask in the CCR SPIF bit is set.
register is cleared.
2. A write or a read to the SPIDR register.
Clearing the SPIF bit is performed by the following
Notes: While the SPIF bit is set, all writes to the
software sequence:
SPIDR register are inhibited until the SPICSR reg-
1. An access to the SPICSR register while the ister is read.
SPIF bit is set
The SPIF bit can be cleared during a second
2. A read to the SPIDR register. transmission; however, it must be cleared before
the second SPIF bit in order to prevent an Overrun
condition (see Section 10.5.5.2).

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10.5.4 Clock Phase and Clock Polarity Figure 60, shows an SPI transfer with the four
Four possible timing relationships may be chosen combinations of the CPHA and CPOL bits. The di-
by software, using the CPOL and CPHA bits (See agram may be interpreted as a master or slave
Figure 60). timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
Note: The idle state of SCK must correspond to master and the slave device.
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if Note: If CPOL is changed at the communication
CPOL=0). byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge
Figure 60. Data Clock Timing Diagram
CPHA =1
SCK
(CPOL = 1)

SCK
(CPOL = 0)

MISO MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from master)

MOSI MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from slave)

SS
(to slave)
CAPTURE STROBE

CPHA =0
SCK
(CPOL = 1)

SCK
(CPOL = 0)

MISO MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from master)

MOSI MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from slave)

SS
(to slave)
CAPTURE STROBE

Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.

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10.5.5 Error Flags not cleared the SPIF bit issued from the previously
10.5.5.1 Master Mode Fault (MODF) transmitted byte.
Master mode fault occurs when the master device When an Overrun occurs:
has its SS pin pulled low. – The OVR bit is set and an interrupt request is
When a Master mode fault occurs: generated if the SPIE bit is set.
– The MODF bit is set and an SPI interrupt re- In this case, the receiver buffer contains the byte
quest is generated if the SPIE bit is set. sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
– The SPE bit is reset. This blocks all output bytes are lost.
from the device and disables the SPI periph-
eral. The OVR bit is cleared by reading the SPICSR
register.
– The MSTR bit is reset, thus forcing the device
into slave mode. 10.5.5.3 Write Collision Error (WCOL)
Clearing the MODF bit is done through a software A write collision occurs when the software tries to
sequence: write to the SPIDR register while a data transfer is
taking place with an external device. When this
1. A read access to the SPICSR register while the happens, the transfer continues uninterrupted;
MODF bit is set. and the software write will be unsuccessful.
2. A write to the SPICR register. Write collisions can occur both in master and slave
Notes: To avoid any conflicts in an application mode. See also Section 10.5.3.2 Slave Select
with multiple slaves, the SS pin must be pulled Management.
high during the MODF bit clearing sequence. The Note: a "read collision" will never occur since the
SPE and MSTR bits may be restored to their orig- received data byte is placed in a buffer in which
inal state during or after this clearing sequence. access is always synchronous with the MCU oper-
Hardware does not allow the user to set the SPE ation.
and MSTR bits while the MODF bit is set except in The WCOL bit in the SPICSR register is set if a
the MODF bit clearing sequence. write collision occurs.
10.5.5.2 Overrun Condition (OVR) No SPI interrupt is generated when the WCOL bit
An overrun condition occurs, when the master de- is set (the WCOL bit is a status flag only).
vice has sent a data byte and the slave device has Clearing the WCOL bit is done through a software
sequence (see Figure 61).
Figure 61. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
1st Step

RESULT
2nd Step Read SPIDR SPIF =0
WCOL=0

Clearing sequence before SPIF = 1 (during a data byte transfer)

Read SPICSR
1st Step
RESULT Note: Writing to the SPIDR regis-
ter instead of reading it does not
2nd Step Read SPIDR WCOL=0 reset the WCOL bit

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10.5.5.4 Single Master Systems Note: To prevent a bus conflict on the MISO line
A typical single master system may be configured, the master allows only one active slave device
using an MCU as the master and four MCUs as during a transmission.
slaves (see Figure 62). For more security, the slave device may respond
The master device selects the individual slave de- to the master with the received data byte. Then the
vices by using four pins of a parallel port to control master will receive the previous byte back from the
the four SS pins of the slave devices. slave device if all MISO and MOSI pins are con-
nected and the slave has not written to its SPIDR
The SS pins are pulled high during reset since the register.
master device ports will be forced to be inputs at
that time, thus disabling the slave devices. Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
Figure 62. Single Master / Multiple Slave Configuration

SS SS SS SS
SCK SCK SCK SCK
Slave Slave Slave Slave
MCU MCU MCU MCU

MOSI MISO MOSI MISO MOSI MISO MOSI MISO

MOSI MISO
SCK
Ports

Master
MCU
5V SS

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10.5.6 Low Power Modes Note: When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to per-
Mode Description
form an extra communications cycle to bring the
No effect on SPI. SPI from Halt mode state to normal state. If the
WAIT SPI interrupt events cause the device to exit SPI exits from Slave mode, it returns to normal
from WAIT mode. state immediately.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI oper-
Caution: The SPI can wake up the ST7 from Halt
ation resumes when the MCU is woken up by
mode only if the Slave Select signal (external SS
an interrupt with “exit from HALT mode” ca- pin or the SSI bit in the SPICSR register) is low
pability. The data received is subsequently when the ST7 enters Halt mode. So if Slave selec-
HALT read from the SPIDR register when the soft- tion is configured as external (see Section
ware is running (interrupt vector fetching). If 10.5.3.2), make sure the master drives a low level
several data are received before the wake- on the SS pin when the slave enters Halt mode.
up event, then an overrun error is generated. 10.5.7 Interrupts
This error can be detected after the fetch of
the interrupt routine that woke up the device. Enable Exit Exit
Event
Interrupt Event Control from from
Flag
Bit Wait Halt
10.5.6.1 Using the SPI to wakeup the MCU from
Halt mode SPI End of Transfer
SPIF Yes Yes
Event
In slave configuration, the SPI is able to wakeup Master Mode Fault SPIE
the ST7 device from HALT mode through a SPIF MODF Yes No
Event
interrupt. The data received is subsequently read
Overrun Error OVR Yes No
from the SPIDR register when the software is run-
ning (interrupt vector fetch). If multiple data trans-
Note: The SPI interrupt events are connected to
fers have been performed before software clears
the same interrupt vector (see Interrupts chapter).
the SPIF bit, then the OVR bit is set by hardware.
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in

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10.5.8 Register Description
CONTROL REGISTER (SPICR)
Read/Write Bit 3 = CPOL Clock Polarity.
Reset Value: 0000 xxxx (0xh) This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
7 0
CPOL bit affects both the master and slave
modes.
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication
Bit 7 = SPIE Serial Peripheral Interrupt Enable. byte boundaries, the SPI must be disabled by re-
This bit is set and cleared by software. setting the SPE bit.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever Bit 2 = CPHA Clock Phase.
SPIF=1, MODF=1 or OVR=1 in the SPICSR This bit is set and cleared by software.
register 0: The first clock transition is the first data capture
edge.
Bit 6 = SPE Serial Peripheral Output Enable. 1: The second clock transition is the first capture
This bit is set and cleared by software. It is also edge.
cleared by hardware when, in master mode, SS=0 Note: The slave must have the same CPOL and
(see Section 10.5.5.1 Master Mode Fault CPHA settings as the master.
(MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the ex-
ternal pins. Bits 1:0 = SPR[1:0] Serial Clock Frequency.
0: I/O pins free for general purpose I/O These bits are set and cleared by software. Used
1: SPI I/O pin alternate functions enabled with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
Bit 5 = SPR2 Divider Enable. Note: These 2 bits have no effect in slave mode.
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to Table 20. SPI Master mode SCK Frequency
set the baud rate. Refer to Table 20 SPI Master
mode SCK Frequency. Serial Clock SPR2 SPR1 SPR0
0: Divider by 2 enabled fCPU/4 1 0 0
1: Divider by 2 disabled
fCPU/8 0 0 0
Note: This bit has no effect in slave mode.
fCPU/16 0 0 1
fCPU/32 1 1 0
Bit 4 = MSTR Master Mode.
This bit is set and cleared by software. It is also fCPU/64 0 1 0
cleared by hardware when, in master mode, SS=0 fCPU/128 0 1 1
(see Section 10.5.5.1 Master Mode Fault
(MODF)).
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.

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CONTROL/STATUS REGISTER (SPICSR) Bit 3 = Reserved, must be kept cleared.
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)
Bit 2 = SOD SPI Output Disable.
7 0 This bit is set and cleared by software. When set, it
disables the alternate function of the SPI output
SPIF WCOL OVR MODF - SOD SSM SSI (MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE=1)
1: SPI output disabled
Bit 7 = SPIF Serial Peripheral Data Transfer Flag
(Read only).
This bit is set by hardware when a transfer has Bit 1 = SSM SS Management.
been completed. An interrupt is generated if This bit is set and cleared by software. When set, it
SPIE=1 in the SPICR register. It is cleared by a disables the alternate function of the SPI SS pin
software sequence (an access to the SPICSR and uses the SSI bit value instead. See Section
register followed by a write or a read to the 10.5.3.2 Slave Select Management.
SPIDR register). 0: Hardware management (SS managed by exter-
0: Data transfer is in progress or the flag has been nal pin)
cleared. 1: Software management (internal SS signal con-
1: Data transfer between the device and an exter- trolled by SSI bit. External SS pin free for gener-
nal device has been completed. al-purpose I/O)
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg- Bit 0 = SSI SS Internal Mode.
ister is read. This bit is set and cleared by software. It acts as a
‘chip select’ by controlling the level of the SS slave
select signal when the SSM bit is set.
Bit 6 = WCOL Write Collision status (Read only). 0 : Slave selected
This bit is set by hardware when a write to the 1 : Slave deselected
SPIDR register is done during a transmit se-
quence. It is cleared by a software sequence (see
Figure 61). DATA I/O REGISTER (SPIDR)
0: No write collision occurred Read/Write
1: A write collision has been detected Reset Value: Undefined
7 0
Bit 5 = OVR SPI Overrun error (Read only).
This bit is set by hardware when the byte currently D7 D6 D5 D4 D3 D2 D1 D0
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(See Section 10.5.5.2). An interrupt is generated if The SPIDR register is used to transmit and receive
SPIE = 1 in SPICR register. The OVR bit is cleared data on the serial bus. In a master device, a write
by software reading the SPICSR register. to this register will initiate transmission/reception
0: No overrun error of another byte.
1: Overrun error detected Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
Bit 4 = MODF Mode Fault flag (Read only). the serial peripheral data I/O register, the buffer is
This bit is set by hardware when the SS pin is actually being read.
pulled low in master mode (see Section 10.5.5.1
Master Mode Fault (MODF)). An SPI interrupt can While the SPIF bit is set, all writes to the SPIDR
be generated if SPIE=1 in the SPICSR register. register are inhibited until the SPICSR register is
This bit is cleared by a software sequence (An ac- read.
cess to the SPICR register while MODF=1 fol- Warning: A write to the SPIDR register places
lowed by a write to the SPICR register). data directly into the shift register for transmission.
0: No master mode fault detected
A read to the SPIDR register returns the value lo-
1: A fault in master mode has been detected
cated in the buffer and not the content of the shift
register (see Figure 56).

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Table 21. SPI Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
SPIDR MSB LSB
0021h
Reset Value x x x x x x x x
SPICR SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
0022h
Reset Value 0 0 0 0 x x x x
SPICSR SPIF WCOL OVR MODF SOD SSM SSI
0023h
Reset Value 0 0 0 0 0 0 0 0

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10.6 SERIAL COMMUNICATIONS INTERFACE (SCI)

10.6.1 Introduction 10.6.3 General Description
The Serial Communications Interface (SCI) offers The interface is externally connected to another
a flexible means of full-duplex data exchange with device by two pins (see Figure 2.):
external equipment requiring an industry standard – TDO: Transmit Data Output. When the transmit-
NRZ asynchronous serial data format. The SCI of- ter and the receiver are disabled, the output pin
fers a very wide range of baud rates using two returns to its I/O port configuration. When the
baud rate generator systems. transmitter and/or the receiver are enabled and
10.6.2 Main Features nothing is to be transmitted, the TDO pin is at
■ Full duplex, asynchronous communications high level.
■ NRZ standard format (Mark/Space) – RDI: Receive Data Input is the serial data input.
■ Dual baud rate generator systems
Oversampling techniques are used for data re-
covery by discriminating between valid incoming
■ Independently programmable transmit and data and noise.
receive baud rates up to 500K baud
Through these pins, serial data is transmitted and
■ Programmable data word length (8 or 9 bits)
received as frames comprising:
■ Receive buffer full, Transmit buffer empty and
– An Idle Line prior to transmission or reception
End of Transmission flags
■ Two receiver wake-up modes:
– A start bit
– Address bit (MSB) – A data word (8 or 9 bits) least significant bit first
– Idle line – A Stop bit indicating that the frame is complete
■ Muting function for multiprocessor configurations This interface uses two types of baud rate generator:
■ Separate enable bits for Transmitter and – A conventional type for commonly-used baud
Receiver rates
■ Four error detection flags: – An extended type with a prescaler offering a very
– Overrun error wide range of baud rates even with non-standard
oscillator frequencies
– Noise error
– Frame error
– Parity error
■ Five interrupt sources with flags:

– Transmit data register empty

– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
■ Parity control:

– Transmits parity bit

– Checks parity of received data byte
■ Reduced power consumption mode

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Figure 63. SCI Block Diagram

Write Read (DATA REGISTER) DR

Transmit Data Register (TDR) Received Data Register (RDR)

TDO

Transmit Shift Register Received Shift Register

RDI
CR1
R8 T8 SCID M WAKE PCE PS PIE

WAKE
TRANSMIT UP RECEIVER RECEIVER
CONTROL UNIT CONTROL CLOCK

CR2 SR
TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE PE

SCI
INTERRUPT
CONTROL

TRANSMITTER
CLOCK
TRANSMITTER RATE
CONTROL
fCPU
/16 /PR
BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0

RECEIVER RATE
CONTROL

CONVENTIONAL BAUD RATE GENERATOR

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10.6.4 Functional Description 10.6.4.1 Serial Data Format
The block diagram of the Serial Control Interface, Word length may be selected as being either 8 or 9
is shown in Figure 1. It contains six dedicated reg- bits by programming the M bit in the SCICR1 reg-
isters: ister (see Figure 1.).
– Two control registers (SCICR1 & SCICR2) The TDO pin is in low state during the start bit.
– A status register (SCISR) The TDO pin is in high state during the stop bit.
– A baud rate register (SCIBRR) An Idle character is interpreted as an entire frame
– An extended prescaler receiver register (SCIER- of “1”s followed by the start bit of the next frame
PR) which contains data.
– An extended prescaler transmitter register (SCI- A Break character is interpreted on receiving “0”s
ETPR) for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
Refer to the register descriptions in Section 0.1.7 tra “1” bit to acknowledge the start bit.
for the definitions of each bit.
Transmission and reception are driven by their
own baud rate generator.
Figure 64. Word Length Programming

9-bit Word length (M bit is set)

Possible Next Data Frame
Parity
Data Frame Bit Next
Start Stop Start
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit
Bit

Start
Idle Frame Bit

Break Frame Extra Start

‘1’ Bit

8-bit Word length (M bit is reset)

Possible Next Data Frame
Data Frame Parity
Bit Next
Start Stop Start
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit
Bit

Start
Idle Frame Bit

Break Frame Extra Start

‘1’ Bit

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10.6.4.2 Transmitter When a frame transmission is complete (after the
The transmitter can send data words of either 8 or stop bit) the TC bit is set and an interrupt is gener-
9 bits depending on the M bit status. When the M ated if the TCIE is set and the I bit is cleared in the
bit is set, word length is 9 bits and the 9th bit (the CCR register.
MSB) has to be stored in the T8 bit in the SCICR1 Clearing the TC bit is performed by the following
register. software sequence:
Character Transmission 1. An access to the SCISR register
During an SCI transmission, data shifts out least 2. A write to the SCIDR register
significant bit first on the TDO pin. In this mode, Note: The TDRE and TC bits are cleared by the
the SCIDR register consists of a buffer (TDR) be- same software sequence.
tween the internal bus and the transmit shift regis-
ter (see Figure 1.). Break Characters
Procedure Setting the SBK bit loads the shift register with a
break character. The break frame length depends
– Select the M bit to define the word length. on the M bit (see Figure 2.).
– Select the desired baud rate using the SCIBRR As long as the SBK bit is set, the SCI send break
and the SCIETPR registers. frames to the TDO pin. After clearing this bit by
– Set the TE bit to assign the TDO pin to the alter- software the SCI insert a logic 1 bit at the end of
nate function and to send a idle frame as first the last break frame to guarantee the recognition
transmission. of the start bit of the next frame.
– Access the SCISR register and write the data to Idle Characters
send in the SCIDR register (this sequence clears Setting the TE bit drives the SCI to send an idle
the TDRE bit). Repeat this sequence for each frame before the first data frame.
data to be transmitted.
Clearing and then setting the TE bit during a trans-
Clearing the TDRE bit is always performed by the mission sends an idle frame after the current word.
following software sequence:
Note: Resetting and setting the TE bit causes the
1. An access to the SCISR register data in the TDR register to be lost. Therefore the
2. A write to the SCIDR register best time to toggle the TE bit is when the TDRE bit
The TDRE bit is set by hardware and it indicates: is set, that is, before writing the next byte in the
SCIDR.
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the SCIDR regis-
ter without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CCR register.
When a transmission is taking place, a write in-
struction to the SCIDR register stores the data in
the TDR register and which is copied in the shift
register at the end of the current transmission.
When no transmission is taking place, a write in-
struction to the SCIDR register places the data di-
rectly in the shift register, the data transmission
starts, and the TDRE bit is immediately set.

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10.6.4.3 Receiver RDR register as long as the RDRF bit is not
The SCI can receive data words of either 8 or 9 cleared.
bits. When the M bit is set, word length is 9 bits When an overrun error occurs:
and the MSB is stored in the R8 bit in the SCICR1 – The OR bit is set.
register.
– The RDR content is not lost.
Character reception
– The shift register is overwritten.
During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, the – An interrupt is generated if the RIE bit is set and
SCIDR register consists or a buffer (RDR) be- the I bit is cleared in the CCR register.
tween the internal bus and the received shift regis- The OR bit is reset by an access to the SCISR reg-
ter (see Figure 1.). ister followed by a SCIDR register read operation.
Procedure Noise Error
– Select the M bit to define the word length. Oversampling techniques are used for data recov-
– Select the desired baud rate using the SCIBRR ery by discriminating between valid incoming data
and the SCIERPR registers. and noise. Normal data bits are considered valid if
three consecutive samples (8th, 9th, 10th) have
– Set the RE bit, this enables the receiver which the same bit value, otherwise the NF flag is set. In
begins searching for a start bit. the case of start bit detection, the NF flag is set on
When a character is received: the basis of an algorithm combining both valid
– The RDRF bit is set. It indicates that the content edge detection and three samples (8th, 9th, 10th).
of the shift register is transferred to the RDR. Therefore, to prevent the NF flag getting set during
start bit reception, there should be a valid edge de-
– An interrupt is generated if the RIE bit is set and tection as well as three valid samples.
the I bit is cleared in the CCR register.
When noise is detected in a frame:
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re- – The NF flag is set at the rising edge of the RDRF
ception. bit.
Clearing the RDRF bit is performed by the following – Data is transferred from the Shift register to the
software sequence done by: SCIDR register.
1. An access to the SCISR register – No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
2. A read to the SCIDR register. generates an interrupt.
The RDRF bit must be cleared before the end of the The NF flag is reset by a SCISR register read op-
reception of the next character to avoid an overrun eration followed by a SCIDR register read opera-
error. tion.
Break Character During reception, if a false start bit is detected (e.g.
When a break character is received, the SCI han- 8th, 9th, 10th samples are 011,101,110), the
dles it as a framing error. frame is discarded and the receiving sequence is
Idle Character not started for this frame. There is no RDRF bit set
for this frame and the NF flag is set internally (not
When a idle frame is detected, there is the same accessible to the user). This NF flag is accessible
procedure as a data received character plus an in- along with the RDRF bit when a next valid frame is
terrupt if the ILIE bit is set and the I bit is cleared in received.
the CCR register.
Note: If the application Start Bit is not long enough
Overrun Error to match the above requirements, then the NF
An overrun error occurs when a character is re- Flag may get set due to the short Start Bit. In this
ceived when RDRF has not been reset. Data can case, the NF flag may be ignored by the applica-
not be transferred from the shift register to the tion software when the first valid byte is received.
See also Section 0.1.4.10 .

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Figure 65. SCI Baud Rate and Extended Prescaler Block Diagram

TRANSMITTER
CLOCK
EXTENDED PRESCALER TRANSMITTER RATE CONTROL

SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER

SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER

RECEIVER
CLOCK
EXTENDED PRESCALER RECEIVER RATE CONTROL

EXTENDED PRESCALER

fCPU

TRANSMITTER RATE
CONTROL
/16 /PR
SCIBRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0

RECEIVER RATE
CONTROL

CONVENTIONAL BAUD RATE GENERATOR

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Framing Error Note: the extended prescaler is activated by set-
A framing error is detected when: ting the SCIETPR or SCIERPR register to a value
other than zero. The baud rates are calculated as
– The stop bit is not recognized on reception at the follows:
expected time, following either a de-synchroni-
zation or excessive noise. fCPU fCPU
– A break is received. Tx = Rx =
16*ETPR*(PR*TR) 16*ERPR*(PR*RR)
When the framing error is detected:
– the FE bit is set by hardware
with:
– Data is transferred from the Shift register to the
SCIDR register. ETPR = 1,..,255 (see SCIETPR register)
– No interrupt is generated. However this bit rises ERPR = 1,.. 255 (see SCIERPR register)
at the same time as the RDRF bit which itself 10.6.4.6 Receiver Muting and Wake-up Feature
generates an interrupt. In multiprocessor configurations it is often desira-
The FE bit is reset by a SCISR register read oper- ble that only the intended message recipient
ation followed by a SCIDR register read operation. should actively receive the full message contents,
10.6.4.4 Conventional Baud Rate Generation thus reducing redundant SCI service overhead for
all non addressed receivers.
The baud rate for the receiver and transmitter (Rx
and Tx) are set independently and calculated as The non addressed devices may be placed in
follows: sleep mode by means of the muting function.
Setting the RWU bit by software puts the SCI in
fCPU fCPU
Tx = Rx = sleep mode:
(16*PR)*TR (16*PR)*RR All the reception status bits can not be set.
with: All the receive interrupts are inhibited.
PR = 1, 3, 4 or 13 (see SCP[1:0] bits) A muted receiver may be awakened by one of the
following two ways:
TR = 1, 2, 4, 8, 16, 32, 64,128
– by Idle Line detection if the WAKE bit is reset,
(see SCT[2:0] bits)
– by Address Mark detection if the WAKE bit is set.
RR = 1, 2, 4, 8, 16, 32, 64,128
Receiver wakes-up by Idle Line detection when
(see SCR[2:0] bits) the Receive line has recognized an Idle Frame.
All these bits are in the SCIBRR register. Then the RWU bit is reset by hardware but the
IDLE bit is not set.
Example: If fCPU is 8 MHz (normal mode) and if
PR = 13 and TR = RR = 1, the transmit and re- Receiver wakes-up by Address Mark detection
ceive baud rates are 38400 baud. when it received a “1” as the most significant bit of
a word, thus indicating that the message is an ad-
Note: The baud rate registers MUST NOT be
dress. The reception of this particular word wakes
changed while the transmitter or the receiver is en-
up the receiver, resets the RWU bit and sets the
abled.
RDRF bit, which allows the receiver to receive this
10.6.4.5 Extended Baud Rate Generation word normally and to use it as an address word.
The extended prescaler option gives a very fine CAUTION: In Mute mode, do not write to the
tuning on the baud rate, using a 255 value prescal- SCICR2 register. If the SCI is in Mute mode during
er, whereas the conventional Baud Rate Genera- the read operation (RWU = 1) and a address mark
tor retains industry standard software compatibili- wake up event occurs (RWU is reset) before the
ty. write operation, the RWU bit is set again by this
The extended baud rate generator block diagram write operation. Consequently the address byte is
is described in the Figure 3. lost and the SCI is not woken up from Mute mode.
The output clock rate sent to the transmitter or to
the receiver is the output from the 16 divider divid-
ed by a factor ranging from 1 to 255 set in the SCI-
ERPR or the SCIETPR register.

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10.6.4.7 Parity Control even number of “1s” if even parity is selected
Parity control (generation of parity bit in transmis- (PS = 0) or an odd number of “1s” if odd parity is
sion and parity checking in reception) can be ena- selected (PS = 1). If the parity check fails, the PE
bled by setting the PCE bit in the SCICR1 register. flag is set in the SCISR register and an interrupt is
Depending on the frame length defined by the M generated if PIE is set in the SCICR1 register.
bit, the possible SCI frame formats are as listed in 10.6.4.8 SCI Clock Tolerance
Table 1. During reception, each bit is sampled 16 times.
Table 22. Frame Formats The majority of the 8th, 9th and 10th samples is
considered as the bit value. For a valid bit detec-
M bit PCE bit SCI frame tion, all the three samples should have the same
0 0 | SB | 8 bit data | STB | value otherwise the noise flag (NF) is set. For ex-
0 1 | SB | 7-bit data | PB | STB | ample: If the 8th, 9th and 10th samples are 0, 1
and 1 respectively, then the bit value is “1”, but the
1 0 | SB | 9-bit data | STB |
Noise Flag bit is set because the three samples
1 1 | SB | 8-bit data PB | STB | values are not the same.
Legend: SB = Start Bit, STB = Stop Bit,
Consequently, the bit length must be long enough
PB = Parity Bit
so that the 8th, 9th and 10th samples have the de-
Note: In case of wake up by an address mark, the sired bit value. This means the clock frequency
MSB bit of the data is taken into account and not should not vary more than 6/16 (37.5%) within one
the parity bit bit. The sampling clock is resynchronized at each
Even parity: the parity bit is calculated to obtain start bit, so that when receiving 10 bits (one start
an even number of “1s” inside the frame made of bit, 1 data byte, 1 stop bit), the clock deviation
the 7 or 8 LSB bits (depending on whether M is must not exceed 3.75%.
equal to 0 or 1) and the parity bit. Note: The internal sampling clock of the microcon-
Example: data = 00110101; 4 bits set => parity bit troller samples the pin value on every falling edge.
is 0 if even parity is selected (PS bit = 0). Therefore, the internal sampling clock and the time
the application expects the sampling to take place
Odd parity: the parity bit is calculated to obtain an may be out of sync. For example: If the baud rate
odd number of “1s” inside the frame made of the 7 is 15.625 Kbaud (bit length is 64µs), then the 8th,
or 8 LSB bits (depending on whether M is equal to 9th and 10th samples are at 28µs, 32µs and 36µs
0 or 1) and the parity bit. respectively (the first sample starting ideally at
Example: data = 00110101; 4 bits set => parity bit 0µs). But if the falling edge of the internal clock oc-
is 1 if odd parity is selected (PS bit = 1). curs just before the pin value changes, the sam-
Transmission mode: If the PCE bit is set then the ples would then be out of sync by ~4us. This
MSB bit of the data written in the data register is means the entire bit length must be at least 40µs
not transmitted but is changed by the parity bit. (36µs for the 10th sample + 4µs for synchroniza-
tion with the internal sampling clock).
Reception mode: If the PCE bit is set then the in-
terface checks if the received data byte has an

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10.6.4.9 Clock Deviation Causes 10.6.4.10 Noise Error Causes
The causes which contribute to the total deviation See also description of Noise error in Section
are: 0.1.4.3 .
– DTRA: Deviation due to transmitter error (Local Start bit
oscillator error of the transmitter or the trans- The noise flag (NF) is set during start bit reception
mitter is transmitting at a different baud rate). if one of the following conditions occurs:
– DQUANT: Error due to the baud rate quantiza- 1. A valid falling edge is not detected. A falling
tion of the receiver. edge is considered to be valid if the 3 consecu-
– DREC: Deviation of the local oscillator of the tive samples before the falling edge occurs are
receiver: This deviation can occur during the detected as '1' and, after the falling edge
reception of one complete SCI message as- occurs, during the sampling of the 16 samples,
suming that the deviation has been compen- if one of the samples numbered 3, 5 or 7 is
sated at the beginning of the message. detected as a “1”.
– DTCL: Deviation due to the transmission line 2. During sampling of the 16 samples, if one of the
(generally due to the transceivers) samples numbered 8, 9 or 10 is detected as a
All the deviations of the system should be added “1”.
and compared to the SCI clock tolerance: Therefore, a valid Start Bit must satisfy both the
DTRA + DQUANT + DREC + DTCL < 3.75% above conditions to prevent the Noise Flag getting
set.
Data Bits
The noise flag (NF) is set during normal data bit re-
ception if the following condition occurs:
– During the sampling of 16 samples, if all three
samples numbered 8, 9 and10 are not the same.
The majority of the 8th, 9th and 10th samples is
considered as the bit value.
Therefore, a valid Data Bit must have samples 8, 9
and 10 at the same value to prevent the Noise
Flag getting set.

Figure 66. Bit Sampling in Reception Mode

RDI LINE

sampled values

Sample
clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

6/16

7/16 7/16
One bit time

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10.6.5 Low Power Modes 10.6.6 Interrupts
Mode Description The SCI interrupt events are connected to the
No effect on SCI. same interrupt vector.
WAIT SCI interrupts cause the device to exit from These events generate an interrupt if the corre-
Wait mode. sponding Enable Control Bit is set and the inter-
SCI registers are frozen.
rupt mask in the CC register is reset (RIM instruc-
tion).
HALT In Halt mode, the SCI stops transmitting/re-
ceiving until Halt mode is exited. Enable Exit Exit
Event
Interrupt Event Control from from
Flag
Bit Wait Halt
Transmit Data Register
TDRE TIE Yes No
Empty
Transmission Com-
TC TCIE Yes No
plete
Received Data Ready
RDRF Yes No
to be Read
RIE
Overrun Error Detect-
OR Yes No
ed
Idle Line Detected IDLE ILIE Yes No
Parity Error PE PIE Yes No

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10.6.7 Register Description Note: The IDLE bit is not set again until the RDRF
STATUS REGISTER (SCISR) bit has been set itself (that is, a new idle line oc-
Read Only curs).
Reset Value: 1100 0000 (C0h)
7 0 Bit 3 = OR Overrun error.
This bit is set by hardware when the word currently
being received in the shift register is ready to be
TDRE TC RDRF IDLE OR NF FE PE
transferred into the RDR register while RDRF = 1.
An interrupt is generated if RIE = 1 in the SCICR2
Bit 7 = TDRE Transmit data register empty. register. It is cleared by a software sequence (an
This bit is set by hardware when the content of the access to the SCISR register followed by a read to
TDR register has been transferred into the shift the SCIDR register).
register. An interrupt is generated if the TIE bit = 1 0: No Overrun error
in the SCICR2 register. It is cleared by a software 1: Overrun error is detected
sequence (an access to the SCISR register fol- Note: When this bit is set RDR register content is
lowed by a write to the SCIDR register). not lost but the shift register is overwritten.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Note: Data is not transferred to the shift register Bit 2 = NF Noise flag.
unless the TDRE bit is cleared. This bit is set by hardware when noise is detected
on a received frame. It is cleared by a software se-
quence (an access to the SCISR register followed
Bit 6 = TC Transmission complete. by a read to the SCIDR register).
This bit is set by hardware when transmission of a 0: No noise is detected
frame containing Data is complete. An interrupt is 1: Noise is detected
generated if TCIE = 1 in the SCICR2 register. It is Note: This bit does not generate interrupt as it ap-
cleared by a software sequence (an access to the pears at the same time as the RDRF bit which it-
SCISR register followed by a write to the SCIDR self generates an interrupt.
register).
0: Transmission is not complete
1: Transmission is complete Bit 1 = FE Framing error.
Note: TC is not set after the transmission of a Pre- This bit is set by hardware when a de-synchroniza-
amble or a Break. tion, excessive noise or a break character is de-
tected. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
Bit 5 = RDRF Received data ready flag. the SCIDR register).
This bit is set by hardware when the content of the 0: No Framing error is detected
RDR register has been transferred to the SCIDR 1: Framing error or break character is detected
register. An interrupt is generated if RIE = 1 in the
SCICR2 register. It is cleared by a software se- Note: This bit does not generate interrupt as it ap-
quence (an access to the SCISR register followed pears at the same time as the RDRF bit which it-
by a read to the SCIDR register). self generates an interrupt. If the word currently
0: Data is not received being transferred causes both frame error and
1: Received data is ready to be read overrun error, it will be transferred and only the OR
bit will be set.
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when a Idle Line is de- Bit 0 = PE Parity error.
tected. An interrupt is generated if the ILIE = 1 in This bit is set by hardware when a parity error oc-
the SCICR2 register. It is cleared by a software se- curs in receiver mode. It is cleared by a software
quence (an access to the SCISR register followed sequence (a read to the status register followed by
by a read to the SCIDR register). an access to the SCIDR data register). An inter-
0: No Idle Line is detected rupt is generated if PIE = 1 in the SCICR1 register.
1: Idle Line is detected 0: No parity error
1: Parity error

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CONTROL REGISTER 1 (SCICR1)
Read/Write Bit 3 = WAKE Wake-Up method.
Reset Value: x000 0000 (x0h) This bit determines the SCI Wake-Up method, it is
set or cleared by software.
7 0 0: Idle Line
1: Address Mark
R8 T8 SCID M WAKE PCE PS PIE

Bit 2 = PCE Parity control enable.

Bit 7 = R8 Receive data bit 8. This bit selects the hardware parity control (gener-
This bit is used to store the 9th bit of the received ation and detection). When the parity control is en-
word when M = 1. abled, the computed parity is inserted at the MSB
position (9th bit if M = 1; 8th bit if M = 0) and parity
is checked on the received data. This bit is set and
Bit 6 = T8 Transmit data bit 8. cleared by software. Once it is set, PCE is active
This bit is used to store the 9th bit of the transmit- after the current byte (in reception and in transmis-
ted word when M = 1. sion).
0: Parity control disabled
1: Parity control enabled
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs
are stopped and the end of the current byte trans- Bit 1 = PS Parity selection.
fer in order to reduce power consumption.This bit This bit selects the odd or even parity when the
is set and cleared by software. parity generation/detection is enabled (PCE bit
0: SCI enabled set). It is set and cleared by software. The parity is
1: SCI prescaler and outputs disabled selected after the current byte.
0: Even parity
1: Odd parity
Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software. Bit 0 = PIE Parity interrupt enable.
0: 1 Start bit, 8 Data bits, 1 Stop bit This bit enables the interrupt capability of the hard-
1: 1 Start bit, 9 Data bits, 1 Stop bit ware parity control when a parity error is detected
(PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
Note: The M bit must not be modified during a data
1: Parity error interrupt enabled.
transfer (both transmission and reception).

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CONTROL REGISTER 2 (SCICR2) Notes:
Read/Write – During transmission, a “0” pulse on the TE bit
Reset Value: 0000 0000 (00h) (“0” followed by “1”) sends a preamble (idle line)
after the current word.
7 0 – When TE is set there is a 1 bit-time delay before
the transmission starts.
TIE TCIE RIE ILIE TE RE RWU SBK
CAUTION: The TDO pin is free for general pur-
pose I/O only when the TE and RE bits are both
Bit 7 = TIE Transmitter interrupt enable. cleared (or if TE is never set).
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever Bit 2 = RE Receiver enable.
TDRE=1 in the SCISR register This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled
Bit 6 = TCIE Transmission complete interrupt ena- 1: Receiver is enabled and begins searching for a
ble start bit
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC=1 in Bit 1 = RWU Receiver wake-up.
the SCISR register This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
Bit 5 = RIE Receiver interrupt enable. recognized.
This bit is set and cleared by software. 0: Receiver in Active mode
0: Interrupt is inhibited 1: Receiver in Mute mode
1: An SCI interrupt is generated whenever OR=1
or RDRF=1 in the SCISR register Note: Before selecting Mute mode (setting the
RWU bit), the SCI must receive some data first,
otherwise it cannot function in Mute mode with
Bit 4 = ILIE Idle line interrupt enable. wake-up by idle line detection.
This bit is set and cleared by software.
0: Interrupt is inhibited Bit 0 = SBK Send break.
1: An SCI interrupt is generated whenever IDLE=1 This bit set is used to send break characters. It is
in the SCISR register. set and cleared by software.
0: No break character is transmitted
Bit 3 = TE Transmitter enable. 1: Break characters are transmitted
This bit enables the transmitter. It is set and Note: If the SBK bit is set to “1” and then to “0”, the
cleared by software. transmitter sends a BREAK word at the end of the
0: Transmitter is disabled current word.
1: Transmitter is enabled

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DATA REGISTER (SCIDR) Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
Read/Write These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
Reset Value: Undefined clock to yield the transmit rate clock in convention-
Contains the Received or Transmitted data char- al Baud Rate Generator mode.
acter, depending on whether it is read from or writ-
TR dividing factor SCT2 SCT1 SCT0
ten to.
1 0 0 0
7 0
2 0 0 1
4 0 1 0
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
8 0 1 1
The Data register performs a double function (read 16 1 0 0
and write) since it is composed of two registers, 32 1 0 1
one for transmission (TDR) and one for reception 64 1 1 0
(RDR).
128 1 1 1
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 1.). Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
The RDR register provides the parallel interface These 3 bits, in conjunction with the SCP[1:0] bits
between the input shift register and the internal define the total division applied to the bus clock to
bus (see Figure 1.). yield the receive rate clock in conventional Baud
Rate Generator mode.
BAUD RATE REGISTER (SCIBRR) RR Dividing factor SCR2 SCR1 SCR0
Read/Write 1 0 0 0
Reset Value: 0000 0000 (00h) 2 0 0 1
4 0 1 0
7 0
8 0 1 1
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 16 1 0 0
32 1 0 1
Bits 7:6 = SCP[1:0] First SCI Prescaler 64 1 1 0
These 2 prescaling bits allow several standard 128 1 1 1
clock division ranges:
PR Prescaling factor SCP1 SCP0
1 0 0
3 0 1
4 1 0
13 1 1

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EXTENDED RECEIVE PRESCALER DIVISION EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIERPR) REGISTER (SCIETPR)
Read/Write Read/Write
Reset Value: 0000 0000 (00h) Reset Value:0000 0000 (00h)
Allows setting of the Extended Prescaler rate divi- Allows setting of the External Prescaler rate divi-
sion factor for the receive circuit. sion factor for the transmit circuit.
7 0 7 0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Bits 7:0 = ERPR[7:0] 8-bit Extended Receive Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit
Prescaler Register. Prescaler Register.
The extended Baud Rate Generator is activated The extended Baud Rate Generator is activated
when a value different from 00h is stored in this when a value different from 00h is stored in this
register. Therefore the clock frequency issued register. Therefore the clock frequency issued
from the 16 divider (see Figure 3.) is divided by the from the 16 divider (see Figure 3.) is divided by the
binary factor set in the SCIERPR register (in the binary factor set in the SCIETPR register (in the
range 1 to 255). range 1 to 255).
The extended baud rate generator is not used af- The extended baud rate generator is not used af-
ter a reset. ter a reset.
Table 23. Baudrate Selection
Conditions
Baud
Symbol Parameter Accuracy vs Standard Unit
fCPU Prescaler Rate
Standard
Conventional Mode
TR (or RR)=128, PR=13 300 ~300.48
TR (or RR)= 32, PR=13 1200 ~1201.92
TR (or RR)= 16, PR=13 2400 ~2403.84
~0.16% TR (or RR)= 8, PR=13 4800 ~4807.69
fTx TR (or RR)= 4, PR=13 9600 ~9615.38
Communication frequency 8 MHz TR (or RR)= 16, PR= 3 10400 ~10416.67 Hz
fRx
TR (or RR)= 2, PR=13 19200 ~19230.77
TR (or RR)= 1, PR=13 38400 ~38461.54
Extended Mode
~0.79% ETPR (or ERPR) = 35, 14400 ~14285.71
TR (or RR)= 1, PR=1

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Table 24. SCI Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
SCISR TDRE TC RDRF IDLE OVR NF FE PE
0050h
Reset Value 1 1 0 0 0 0 0 0
SCIDR MSB LSB
0051h
Reset Value x x x x x x x x
SCIBRR SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
0052h
Reset Value 0 0 0 0 0 0 0 0
SCICR1 R8 T8 SCID M WAKE PCE PS PIE
0053h
Reset Value x 0 0 0 0 0 0 0
SCICR2 TIE TCIE RIE ILIE TE RE RWU SBK
0054h
Reset Value 0 0 0 0 0 0 0 0
SCIERPR MSB LSB
0055h
Reset Value 0 0 0 0 0 0 0 0
SCIPETPR MSB LSB
0057h
Reset Value 0 0 0 0 0 0 0 0

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10.7 I2C BUS INTERFACE (I2C)

10.7.1 Introduction and vice versa, using either an interrupt or polled
The I2C Bus Interface serves as an interface be- handshake. The interrupts are enabled or disabled
tween the microcontroller and the serial I2C bus. It by software. The interface is connected to the I2C
provides both multimaster and slave functions, bus by a data pin (SDAI) and by a clock pin (SCLI).
and controls all I2C bus-specific sequencing, pro- It can be connected both with a standard I2C bus
tocol, arbitration and timing. It supports fast I2C and a Fast I2C bus. This selection is made by soft-
mode (400kHz). ware.
10.7.2 Main Features Mode Selection
2
■ Parallel-bus/I C protocol converter The interface can operate in the four following
modes:
■ Multi-master capability

■ 7-bit/10-bit Addressing
– Slave transmitter/receiver
■ SMBus V1.1 Compliant
– Master transmitter/receiver
■ Transmitter/Receiver flag By default, it operates in slave mode.
■ End-of-byte transmission flag The interface automatically switches from slave to
■ Transfer problem detection
master after it generates a START condition and
from master to slave in case of arbitration loss or a
I2C Master Features: STOP generation, allowing then Multi-Master ca-
■ Clock generation pability.
2
■ I C bus busy flag Communication Flow
■ Arbitration Lost Flag In Master mode, it initiates a data transfer and
■ End of byte transmission flag generates the clock signal. A serial data transfer
■ Transmitter/Receiver Flag
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
■ Start bit detection flag
generated in master mode by software.
■ Start and Stop generation
In Slave mode, the interface is capable of recog-
I2C Slave Features: nising its own address (7 or 10-bit), and the Gen-
■ Stop bit detection eral Call address. The General Call address de-
2
■ I C bus busy flag
tection may be enabled or disabled by software.
■ Detection of misplaced start or stop condition
Data and addresses are transferred as 8-bit bytes,
2 MSB first. The first byte(s) following the start con-
■ Programmable I C Address detection
dition contain the address (one in 7-bit mode, two
■ Transfer problem detection in 10-bit mode). The address is always transmitted
■ End-of-byte transmission flag in Master mode.
■ Transmitter/Receiver flag A 9th clock pulse follows the 8 clock cycles of a
10.7.3 General Description byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to Fig-
In addition to receiving and transmitting data, this ure 67.
interface converts it from serial to parallel format
Figure 67. I2C BUS Protocol

SDA
MSB ACK

SCL
1 2 8 9

START STOP
CONDITION CONDITION
VR02119B

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I2C BUS INTERFACE (Cont’d)

Acknowledge may be enabled and disabled by The SCL frequency (Fscl) is controlled by a pro-
software. grammable clock divider which depends on the
The I2C interface address and/or general call ad- I2C bus mode.
dress can be selected by software. When the I2C cell is enabled, the SDA and SCL
The speed of the I2C interface may be selected ports must be configured as floating inputs. In this
between Standard (up to 100KHz) and Fast I2C case, the value of the external pull-up resistor
(up to 400KHz). used depends on the application.
When the I2C cell is disabled, the SDA and SCL
ports revert to being standard I/O port pins.
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the micro-
controller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
Figure 68. I2C Interface Block Diagram
DATA REGISTER (DR)

SDA or SDAI DATA CONTROL

DATA SHIFT REGISTER

COMPARATOR

OWN ADDRESS REGISTER 1 (OAR1)

OWN ADDRESS REGISTER 2 (OAR2)

SCL or SCLI CLOCK CONTROL

CLOCK CONTROL REGISTER (CCR)

CONTROL REGISTER (CR)

STATUS REGISTER 1 (SR1) CONTROL LOGIC

STATUS REGISTER 2 (SR2)

INTERRUPT

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I2C BUS INTERFACE (Cont’d)

10.7.4 Functional Description Then the interface waits for a read of the SR1 reg-
Refer to the CR, SR1 and SR2 registers in Section ister followed by a read of the DR register, holding
10.7.7. for the bit definitions. the SCL line low (see Figure 69 Transfer se-
quencing EV2).
By default the I2C interface operates in Slave
mode (M/SL bit is cleared) except when it initiates Slave Transmitter
a transmit or receive sequence. Following the address reception and after SR1
First the interface frequency must be configured register has been read, the slave sends bytes from
using the FRi bits in the OAR2 register. the DR register to the SDA line via the internal shift
register.
10.7.4.1 Slave Mode
The slave waits for a read of the SR1 register fol-
As soon as a start condition is detected, the lowed by a write in the DR register, holding the
address is received from the SDA line and sent to SCL line low (see Figure 69 Transfer sequencing
the shift register; then it is compared with the EV3).
address of the interface or the General Call
address (if selected by software). When the acknowledge pulse is received:
Note: In 10-bit addressing mode, the comparison – The EVF and BTF bits are set by hardware with
includes the header sequence (11110xx0) and the an interrupt if the ITE bit is set.
two most significant bits of the address. Closing slave communication
Header matched (10-bit mode only): the interface After the last data byte is transferred a Stop Con-
generates an acknowledge pulse if the ACK bit is dition is generated by the master. The interface
set. detects this condition and sets:
Address not matched: the interface ignores it – EVF and STOPF bits with an interrupt if the ITE
and waits for another Start condition. bit is set.
Address matched: the interface generates in se- Then the interface waits for a read of the SR2 reg-
quence: ister (see Figure 69 Transfer sequencing EV4).
– Acknowledge pulse if the ACK bit is set. Error Cases
– EVF and ADSL bits are set with an interrupt if the – BERR: Detection of a Stop or a Start condition
ITE bit is set. during a byte transfer. In this case, the EVF and
the BERR bits are set with an interrupt if the ITE
Then the interface waits for a read of the SR1 reg- bit is set.
ister, holding the SCL line low (see Figure 69 If it is a Stop then the interface discards the data,
Transfer sequencing EV1). released the lines and waits for another Start
Next, in 7-bit mode read the DR register to deter- condition.
mine from the least significant bit (Data Direction If it is a Start then the interface discards the data
Bit) if the slave must enter Receiver or Transmitter and waits for the next slave address on the bus.
mode.
– AF: Detection of a non-acknowledge bit. In this
In 10-bit mode, after receiving the address se- case, the EVF and AF bits are set with an inter-
quence the slave is always in receive mode. It will rupt if the ITE bit is set.
enter transmit mode on receiving a repeated Start The AF bit is cleared by reading the I2CSR2 reg-
condition followed by the header sequence with ister. However, if read before the completion of
matching address bits and the least significant bit the transmission, the AF flag will be set again,
set (11110xx1). thus possibly generating a new interrupt. Soft-
Slave Receiver ware must ensure either that the SCL line is back
Following the address reception and after SR1 at 0 before reading the SR2 register, or be able
register has been read, the slave receives bytes to correctly handle a second interrupt during the
from the SDA line into the DR register via the inter- 9th pulse of a transmitted byte.
nal shift register. After each byte the interface gen- Note: In case of errors, SCL line is not held low;
erates in sequence: however, the SDA line can remain low if the last
bits transmitted are all 0. While AF=1, the SCL line
– Acknowledge pulse if the ACK bit is set
may be held low due to SB or BTF flags that are
– EVF and BTF bits are set with an interrupt if the set at the same time. It is then necessary to re-
ITE bit is set. lease both lines by software.

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I2C INTERFACE (Cont’d)

How to release the SDA / SCL lines Then the second address byte is sent by the inter-
Set and subsequently clear the STOP bit while face.
BTF is set. The SDA/SCL lines are released after
the transfer of the current byte. After completion of this transfer (and acknowledge
from the slave if the ACK bit is set):
SMBus Compatibility – The EVF bit is set by hardware with interrupt
ST7 I2C is compatible with SMBus V1.1 protocol. It generation if the ITE bit is set.
supports all SMBus adressing modes, SMBus bus Then the master waits for a read of the SR1 regis-
protocols and CRC-8 packet error checking. Refer ter followed by a write in the CR register (for exam-
to AN1713: SMBus Slave Driver For ST7 I2C Pe- ple set PE bit), holding the SCL line low (see Fig-
ripheral. ure 69 Transfer sequencing EV6).

10.7.4.2 Master Mode Next the master must enter Receiver or Transmit-
To switch from default Slave mode to Master ter mode.
mode a Start condition generation is needed. Note: In 10-bit addressing mode, to switch the
master to Receiver mode, software must generate
a repeated Start condition and resend the header
Start condition sequence with the least significant bit set
Setting the START bit while the BUSY bit is (11110xx1).
cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condi-
tion. Master Receiver
Once the Start condition is sent: Following the address transmission and after SR1
and CR registers have been accessed, the master
– The EVF and SB bits are set by hardware with receives bytes from the SDA line into the DR reg-
an interrupt if the ITE bit is set. ister via the internal shift register. After each byte
Then the master waits for a read of the SR1 regis- the interface generates in sequence:
ter followed by a write in the DR register with the – Acknowledge pulse if the ACK bit is set
Slave address, holding the SCL line low (see
Figure 69 Transfer sequencing EV5). – EVF and BTF bits are set by hardware with an in-
terrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 reg-
Slave address transmission ister followed by a read of the DR register, holding
Then the slave address is sent to the SDA line via the SCL line low (see Figure 69 Transfer se-
the internal shift register. quencing EV7).
In 7-bit addressing mode, one address byte is To close the communication: before reading the
sent. last byte from the DR register, set the STOP bit to
In 10-bit addressing mode, sending the first byte generate the Stop condition. The interface goes
including the header sequence causes the follow- automatically back to slave mode (M/SL bit
ing event: cleared).
– The EVF bit is set by hardware with interrupt Note: In order to generate the non-acknowledge
generation if the ITE bit is set. pulse after the last received data byte, the ACK bit
Then the master waits for a read of the SR1 regis- must be cleared just before reading the second
ter followed by a write in the DR register, holding last data byte.
the SCL line low (see Figure 69 Transfer se-
quencing EV9).

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I2C BUS INTERFACE (Cont’d)

Master Transmitter of communication gives the possibility to reiniti-
Following the address transmission and after SR1 ate transmission.
register has been read, the master sends bytes Multimaster Mode
from the DR register to the SDA line via the inter- Normally the BERR bit would be set whenever
nal shift register. unauthorized transmission takes place while
transfer is already in progress. However, an is-
The master waits for a read of the SR1 register fol- sue will arise if an external master generates an
lowed by a write in the DR register, holding the unauthorized Start or Stop while the I2C master
SCL line low (see Figure 69 Transfer sequencing is on the first or second pulse of a 9-bit transac-
EV8). tion. It is possible to work around this by polling
When the acknowledge bit is received, the the BUSY bit during I2C master mode transmis-
interface sets: sion. The resetting of the BUSY bit can then be
handled in a similar manner as the BERR flag
– EVF and BTF bits with an interrupt if the ITE bit
being set.
is set.
To close the communication: after writing the last – AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
byte to the DR register, set the STOP bit to gener-
with an interrupt if the ITE bit is set. To resume,
ate the Stop condition. The interface goes auto-
set the Start or Stop bit.
matically back to slave mode (M/SL bit cleared).
The AF bit is cleared by reading the I2CSR2 reg-
ister. However, if read before the completion of
Error Cases the transmission, the AF flag will be set again,
thus possibly generating a new interrupt. Soft-
– BERR: Detection of a Stop or a Start condition ware must ensure either that the SCL line is back
during a byte transfer. In this case, the EVF and at 0 before reading the SR2 register, or be able
BERR bits are set by hardware with an interrupt to correctly handle a second interrupt during the
if ITE is set. 9th pulse of a transmitted byte.
Note that BERR will not be set if an error is de-
tected during the first or second pulse of each 9- – ARLO: Detection of an arbitration lost condition.
bit transaction: In this case the ARLO bit is set by hardware (with
Single Master Mode an interrupt if the ITE bit is set and the interface
If a Start or Stop is issued during the first or sec- goes automatically back to slave mode (the M/SL
ond pulse of a 9-bit transaction, the BERR flag bit is cleared).
will not be set and transfer will continue however Note: In all these cases, the SCL line is not held
the BUSY flag will be reset. To work around this, low; however, the SDA line can remain low due to
slave devices should issue a NACK when they possible «0» bits transmitted last. It is then neces-
receive a misplaced Start or Stop. The reception sary to release both lines by software.
of a NACK or BUSY by the master in the middle

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I2C BUS INTERFACE (Cont’d)

Figure 69. Transfer Sequencing
7-bit Slave receiver:
S Address A Data1 A Data2 A DataN A P
.....
EV1 EV2 EV2 EV2 EV4

7-bit Slave transmitter:

S Address A Data1 A Data2 A DataN NA P
.....
EV1 EV3 EV3 EV3 EV3-1 EV4

7-bit Master receiver:

S Address A Data1 A Data2 A DataN NA P
.....
EV5 EV6 EV7 EV7 EV7

7-bit Master transmitter:

S Address A Data1 A Data2 A DataN A P
.....
EV5 EV6 EV8 EV8 EV8 EV8

10-bit Slave receiver:

S Header A Address A Data1 A DataN A P
.....
EV1 EV2 EV2 EV4

10-bit Slave transmitter:

Sr Header A Data1 A .... DataN A P
EV1 EV3 EV3 . EV3-1 EV4

10-bit Master transmitter

S Header A Address A Data1 A DataN A P
.....
EV5 EV9 EV6 EV8 EV8 EV8

10-bit Master receiver:

Sr Header A Data1 A DataN A P
.....
EV5 EV6 EV7 EV7

Legend: S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,

EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the
lines (STOP=1, STOP=0) or by writing DR register (DR=FFh). Note: If lines are released by
STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.

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I2C BUS INTERFACE (Cont’d)

10.7.5 Low Power Modes
Mode Description
No effect on I2C interface.
WAIT
I2C interrupts cause the device to exit from WAIT mode.
I2C registers are frozen.
HALT In HALT mode, the I2C interface is inactive and does not acknowledge data on the bus. The I2C interface
resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.

10.7.6 Interrupts
Figure 70. Event Flags and Interrupt Generation

ADD10 ITE
BTF
ADSL
SB INTERRUPT
AF
STOPF
ARLO EVF
BERR
*
* EVF can also be set by EV6 or an error from the SR2 register.

Enable Exit Exit

Event
Interrupt Event Control from from
Flag
Bit Wait Halt
10-bit Address Sent Event (Master mode) ADD10 Yes No
End of Byte Transfer Event BTF Yes No
Address Matched Event (Slave mode) ADSEL Yes No
Start Bit Generation Event (Master mode) SB Yes No
ITE
Acknowledge Failure Event AF Yes No
Stop Detection Event (Slave mode) STOPF Yes No
Arbitration Lost Event (Multimaster configuration) ARLO Yes No
Bus Error Event BERR Yes No

Note: The I2C interrupt events are connected to

the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bit in the CC reg-
ister is reset (RIM instruction).

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I2C BUS INTERFACE (Cont’d)

10.7.7 Register Description – In slave mode:
I2C CONTROL REGISTER (CR) 0: No start generation
Read / Write 1: Start generation when the bus is free
Reset Value: 0000 0000 (00h)
Bit 2 = ACK Acknowledge enable.
7 0 This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
0 0 PE ENGC START ACK STOP ITE bled (PE=0).
0: No acknowledge returned
1: Acknowledge returned after an address byte or
a data byte is received
Bit 7:6 = Reserved. Forced to 0 by hardware.

Bit 5 = PE Peripheral enable. Bit 1 = STOP Generation of a Stop condition.

This bit is set and cleared by software. This bit is set and cleared by software. It is also
0: Peripheral disabled cleared by hardware in master mode. Note: This
1: Master/Slave capability bit is not cleared when the interface is disabled
Notes: (PE=0).
– When PE=0, all the bits of the CR register and – In master mode:
the SR register except the Stop bit are reset. All 0: No stop generation
outputs are released while PE=0 1: Stop generation after the current byte transfer
– When PE=1, the corresponding I/O pins are se- or after the current Start condition is sent. The
lected by hardware as alternate functions. STOP bit is cleared by hardware when the Stop
– To enable the I2C interface, write the CR register condition is sent.
TWICE with PE=1 as the first write only activates – In slave mode:
the interface (only PE is set).
0: No stop generation
1: Release the SCL and SDA lines after the cur-
Bit 4 = ENGC Enable General Call. rent byte transfer (BTF=1). In this mode the
This bit is set and cleared by software. It is also STOP bit has to be cleared by software.
cleared by hardware when the interface is disa-
bled (PE=0). The 00h General Call address is ac- Bit 0 = ITE Interrupt enable.
knowledged (01h ignored). This bit is set and cleared by software and cleared
0: General Call disabled
by hardware when the interface is disabled
1: General Call enabled (PE=0).
0: Interrupts disabled
Note: In accordance with the I2C standard, when
1: Interrupts enabled
GCAL addressing is enabled, an I2C slave can Refer to Figure 70 for the relationship between the
only receive data. It will not transmit data to the events and the interrupt.
master. SCL is held low when the ADD10, SB, BTF or
ADSL flags or an EV6 event (See Figure 69) is de-
Bit 3 = START Generation of a Start condition. tected.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0) or when the Start condition is sent
(with interrupt generation if ITE=1).
– In master mode:
0: No start generation
1: Repeated start generation

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I2C BUS INTERFACE (Cont’d)

I2C STATUS REGISTER 1 (SR1) 1: Data byte transmitted
Read Only
Reset Value: 0000 0000 (00h) Bit 4 = BUSY Bus busy.
This bit is set by hardware on detection of a Start
7 0
condition and cleared by hardware on detection of
a Stop condition. It indicates a communication in
EVF ADD10 TRA BUSY BTF ADSL M/SL SB progress on the bus. The BUSY flag of the I2CSR1
register is cleared if a Bus Error occurs.
Bit 7 = EVF Event flag. 0: No communication on the bus
This bit is set by hardware as soon as an event oc- 1: Communication ongoing on the bus
curs. It is cleared by software reading SR2 register Note:
in case of error event or as described in Figure 69. – The BUSY flag is NOT updated when the inter-
It is also cleared by hardware when the interface is face is disabled (PE=0). This can have conse-
disabled (PE=0). quences when operating in Multimaster mode;
0: No event i.e. a second active I2C master commencing a
1: One of the following events has occurred: transfer with an unset BUSY bit can cause a con-
flict resulting in lost data. A software workaround
– BTF=1 (Byte received or transmitted) consists of checking that the I2C is not busy be-
– ADSL=1 (Address matched in Slave mode fore enabling the I2C Multimaster cell.
while ACK=1)
– SB=1 (Start condition generated in Master Bit 3 = BTF Byte transfer finished.
mode) This bit is set by hardware as soon as a byte is cor-
– AF=1 (No acknowledge received after byte rectly received or transmitted with interrupt gener-
transmission) ation if ITE=1. It is cleared by software reading
– STOPF=1 (Stop condition detected in Slave SR1 register followed by a read or write of DR reg-
mode) ister. It is also cleared by hardware when the inter-
face is disabled (PE=0).
– ARLO=1 (Arbitration lost in Master mode)
– Following a byte transmission, this bit is set after
– BERR=1 (Bus error, misplaced Start or Stop reception of the acknowledge clock pulse. In
condition detected) case an address byte is sent, this bit is set only
– ADD10=1 (Master has sent header byte) after the EV6 event (See Figure 69). BTF is
– Address byte successfully transmitted in Mas- cleared by reading SR1 register followed by writ-
ter mode. ing the next byte in DR register.
– Following a byte reception, this bit is set after
transmission of the acknowledge clock pulse if
Bit 6 = ADD10 10-bit addressing in Master mode. ACK=1. BTF is cleared by reading SR1 register
This bit is set by hardware when the master has followed by reading the byte from DR register.
sent the first byte in 10-bit address mode. It is
cleared by software reading SR2 register followed The SCL line is held low while BTF=1.
by a write in the DR register of the second address 0: Byte transfer not done
byte. It is also cleared by hardware when the pe- 1: Byte transfer succeeded
ripheral is disabled (PE=0).
0: No ADD10 event occurred. Bit 2 = ADSL Address matched (Slave mode).
1: Master has sent first address byte (header) This bit is set by hardware as soon as the received
slave address matched with the OAR register con-
Bit 5 = TRA Transmitter/Receiver. tent or a general call is recognized. An interrupt is
When BTF is set, TRA=1 if a data byte has been generated if ITE=1. It is cleared by software read-
transmitted. It is cleared automatically when BTF ing SR1 register or by hardware when the inter-
is cleared. It is also cleared by hardware after de- face is disabled (PE=0).
tection of Stop condition (STOPF=1), loss of bus The SCL line is held low while ADSL=1.
arbitration (ARLO=1) or when the interface is disa- 0: Address mismatched or not received
bled (PE=0). 1: Received address matched
0: Data byte received (if BTF=1)

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I2C BUS INTERFACE (Cont’d)

Bit 1 = M/SL Master/Slave. The SCL line is not held low while STOPF=1.
This bit is set by hardware as soon as the interface 0: No Stop condition detected
is in Master mode (writing START=1). It is cleared 1: Stop condition detected
by hardware after detecting a Stop condition on
the bus or a loss of arbitration (ARLO=1). It is also
cleared when the interface is disabled (PE=0). Bit 2 = ARLO Arbitration lost.
0: Slave mode This bit is set by hardware when the interface los-
1: Master mode es the arbitration of the bus to another master. An
interrupt is generated if ITE=1. It is cleared by soft-
ware reading SR2 register or by hardware when
Bit 0 = SB Start bit (Master mode). the interface is disabled (PE=0).
This bit is set by hardware as soon as the Start
condition is generated (following a write After an ARLO event the interface switches back
START=1). An interrupt is generated if ITE=1. It is automatically to Slave mode (M/SL=0).
cleared by software reading SR1 register followed The SCL line is not held low while ARLO=1.
by writing the address byte in DR register. It is also 0: No arbitration lost detected
cleared by hardware when the interface is disa-
1: Arbitration lost detected
bled (PE=0).
Note:
0: No Start condition
– In a Multimaster environment, when the interface
1: Start condition generated is configured in Master Receive mode it does not
perform arbitration during the reception of the
I2C STATUS REGISTER 2 (SR2) Acknowledge Bit. Mishandling of the ARLO bit
Read Only from the I2CSR2 register may occur when a sec-
Reset Value: 0000 0000 (00h) ond master simultaneously requests the same
data from the same slave and the I2C master
7 0
does not acknowledge the data. The ARLO bit is
then left at 0 instead of being set.
0 0 0 AF STOPF ARLO BERR GCAL

Bit 1 = BERR Bus error.

This bit is set by hardware when the interface de-
Bit 7:5 = Reserved. Forced to 0 by hardware. tects a misplaced Start or Stop condition. An inter-
rupt is generated if ITE=1. It is cleared by software
reading SR2 register or by hardware when the in-
Bit 4 = AF Acknowledge failure.
terface is disabled (PE=0).
This bit is set by hardware when no acknowledge
is returned. An interrupt is generated if ITE=1. It is The SCL line is not held low while BERR=1.
cleared by software reading SR2 register or by 0: No misplaced Start or Stop condition
hardware when the interface is disabled (PE=0). 1: Misplaced Start or Stop condition
The SCL line is not held low while AF=1 but by oth- Note:
er flags (SB or BTF) that are set at the same time. – If a Bus Error occurs, a Stop or a repeated Start
condition should be generated by the Master to
0: No acknowledge failure re-synchronize communication, get the transmis-
1: Acknowledge failure sion acknowledged and the bus released for fur-
Note: ther communication
– When an AF event occurs, the SCL line is not
held low; however, the SDA line can remain low
if the last bits transmitted are all 0. It is then nec- Bit 0 = GCAL General Call (Slave mode).
essary to release both lines by software. This bit is set by hardware when a general call ad-
dress is detected on the bus while ENGC=1. It is
cleared by hardware detecting a Stop condition
Bit 3 = STOPF Stop detection (Slave mode). (STOPF=1) or when the interface is disabled
This bit is set by hardware when a Stop condition (PE=0).
is detected on the bus after an acknowledge (if
ACK=1). An interrupt is generated if ITE=1. It is 0: No general call address detected on bus
cleared by software reading SR2 register or by 1: general call address detected on bus
hardware when the interface is disabled (PE=0).

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I2C BUS INTERFACE (Cont’d)

I2C CLOCK CONTROL REGISTER (CCR) I2C DATA REGISTER (DR)
Read / Write Read / Write
Reset Value: 0000 0000 (00h) Reset Value: 0000 0000 (00h)
7 0 7 0

FM/SM CC6 CC5 CC4 CC3 CC2 CC1 CC0 D7 D6 D5 D4 D3 D2 D1 D0

Bit 7 = FM/SM Fast/Standard I2C mode.

This bit is set and cleared by software. It is not Bit 7:0 = D[7:0] 8-bit Data Register.
cleared when the interface is disabled (PE=0). These bits contain the byte to be received or trans-
0: Standard I2C mode mitted on the bus.
1: Fast I2C mode
– Transmitter mode: Byte transmission start auto-
matically when the software writes in the DR reg-
Bit 6:0 = CC[6:0] 7-bit clock divider. ister.
These bits select the speed of the bus (FSCL) de- – Receiver mode: the first data byte is received au-
pending on the I2C mode. They are not cleared tomatically in the DR register using the least sig-
when the interface is disabled (PE=0). nificant bit of the address.
Refer to the Electrical Characteristics section for Then, the following data bytes are received one
the table of values. by one after reading the DR register.
Note: The programmed FSCL assumes no load on
SCL and SDA lines.

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I2C BUS INTERFACE (Cont’d)

I2C OWN ADDRESS REGISTER (OAR1) I2C OWN ADDRESS REGISTER (OAR2)
Read / Write Read / Write
Reset Value: 0000 0000 (00h) Reset Value: 0100 0000 (40h)
7 0 7 0

ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 FR1 FR0 0 0 0 ADD9 ADD8 0

7-bit Addressing Mode Bit 7:6 = FR[1:0] Frequency bits.

Bit 7:1 = ADD[7:1] Interface address. These bits are set by software only when the inter-
These bits define the I2C bus address of the inter- face is disabled (PE=0). To configure the interface
face. They are not cleared when the interface is to I2C specified delays select the value corre-
disabled (PE=0). sponding to the microcontroller frequency FCPU.
fCPU FR1 FR0
Bit 0 = ADD0 Address direction bit. < 6 MHz 0 0
This bit is don’t care, the interface acknowledges 6 to 8 MHz 0 1
either 0 or 1. It is not cleared when the interface is
disabled (PE=0).
Note: Address 01h is always ignored. Bit 5:3 = Reserved

10-bit Addressing Mode Bit 2:1 = ADD[9:8] Interface address.

Bit 7:0 = ADD[7:0] Interface address. These are the most significant bits of the I2C bus
These are the least significant bits of the I2C bus address of the interface (10-bit mode only). They
address of the interface. They are not cleared are not cleared when the interface is disabled
when the interface is disabled (PE=0). (PE=0).

Bit 0 = Reserved.

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I²C BUS INTERFACE (Cont’d)

Table 25. I2C Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

I2CCR PE ENGC START ACK STOP ITE

0018h
Reset Value 0 0 0 0 0 0 0 0
I2CSR1 EVF ADD10 TRA BUSY BTF ADSL M/SL SB
0019h
Reset Value 0 0 0 0 0 0 0 0
I2CSR2 AF STOPF ARLO BERR GCAL
001Ah
Reset Value 0 0 0 0 0 0 0 0
I2CCCR FM/SM CC6 CC5 CC4 CC3 CC2 CC1 CC0
001Bh
Reset Value 0 0 0 0 0 0 0 0
I2COAR1 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
001Ch
Reset Value 0 0 0 0 0 0 0 0
I2COAR2 FR1 FR0 ADD9 ADD8
001Dh
Reset Value 0 1 0 0 0 0 0 0
I2CDR MSB LSB
001Eh
Reset Value 0 0 0 0 0 0 0 0

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ST72325xx

10.8 10-BIT A/D CONVERTER (ADC)

10.8.1 Introduction 10.8.2 Main Features

The on-chip Analog to Digital Converter (ADC) pe- ■ 10-bit conversion
ripheral is a 10-bit, successive approximation con- ■ Up to 16 channels with multiplexed input
verter with internal sample and hold circuitry. This ■ Linear successive approximation
peripheral has up to 16 multiplexed analog input
■ Data register (DR) which contains the results
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage ■ Conversion complete status flag
levels from up to 16 different sources. ■ On/off bit (to reduce consumption)
The result of the conversion is stored in a 10-bit The block diagram is shown in Figure 71.
Data Register. The A/D converter is controlled
through a Control/Status Register.
Figure 71. ADC Block Diagram
fCPU DIV 4 0
fADC
DIV 2 1

EOC SPEED ADON 0 CH3 CH2 CH1 CH0 ADCCSR

AIN0

AIN1
ANALOG TO DIGITAL
ANALOG
MUX CONVERTER

AINx

ADCDRH D9 D8 D7 D6 D5 D4 D3 D2

ADCDRL 0 0 0 0 0 0 D1 D0

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10-BIT A/D CONVERTER (ADC) (Cont’d)

10.8.3 Functional Description
The conversion is monotonic, meaning that the re- To read the 10 bits, perform the following steps:
sult never decreases if the analog input does not 1. Poll the EOC bit
and never increases if the analog input does not.
2. Read the ADCDRL register
If the input voltage (VAIN) is greater than VAREF
(high-level voltage reference) then the conversion 3. Read the ADCDRH register. This clears EOC
result is FFh in the ADCDRH register and 03h in automatically.
the ADCDRL register (without overflow indication). Note: The data is not latched, so both the low and
If the input voltage (VAIN) is lower than VSSA (low- the high data register must be read before the next
level voltage reference) then the conversion result conversion is complete, so it is recommended to
in the ADCDRH and ADCDRL registers is 00 00h. disable interrupts while reading the conversion re-
sult.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRH and AD- To read only 8 bits, perform the following steps:
CDRL registers. The accuracy of the conversion is 1. Poll the EOC bit
described in the Electrical Characteristics Section. 2. Read the ADCDRH register. This clears EOC
RAIN is the maximum recommended impedance automatically.
for an analog input signal. If the impedance is too
10.8.3.3 Changing the conversion channel
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the The application can change channels during con-
alloted time. version. When software modifies the CH[3:0] bits
in the ADCCSR register, the current conversion is
10.8.3.1 A/D Converter Configuration
stopped, the EOC bit is cleared, and the A/D con-
The analog input ports must be configured as in- verter starts converting the newly selected chan-
put, no pull-up, no interrupt. Refer to the «I/O nel.
ports» chapter. Using these pins as analog inputs
10.8.4 Low Power Modes
does not affect the ability of the port to be read as
a logic input. Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
In the ADCCSR register:
power consumption when no conversion is need-
– Select the CS[3:0] bits to assign the analog ed and between single shot conversions.
channel to convert.
10.8.3.2 Starting the Conversion Mode Description
In the ADCCSR register: WAIT No effect on A/D Converter
– Set the ADON bit to enable the A/D converter A/D Converter disabled.
and to start the conversion. From this time on, After wakeup from Halt mode, the A/D
the ADC performs a continuous conversion of Converter requires a stabilization time
the selected channel. HALT
tSTAB (see Electrical Characteristics)
before accurate conversions can be
When a conversion is complete: performed.
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
A read to the ADCDRH or a write to any bit of the 10.8.5 Interrupts
ADCCSR register resets the EOC bit. None.

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10-BIT A/D CONVERTER (ADC) (Cont’d)

10.8.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR) Bit 3:0 = CH[3:0] Channel Selection
Read/Write (Except bit 7 read only) These bits are set and cleared by software. They
select the analog input to convert.
Reset Value: 0000 0000 (00h)
Channel Pin* CH3 CH2 CH1 CH0
7 0 AIN0 0 0 0 0
AIN1 0 0 0 1
EOC SPEED ADON 0 CH3 CH2 CH1 CH0 AIN2 0 0 1 0
AIN3 0 0 1 1
Bit 7 = EOC End of Conversion AIN4 0 1 0 0
This bit is set by hardware. It is cleared by hard- AIN5 0 1 0 1
ware when software reads the ADCDRH register AIN6 0 1 1 0
or writes to any bit of the ADCCSR register. AIN7 0 1 1 1
0: Conversion is not complete AIN8 1 0 0 0
1: Conversion complete AIN9 1 0 0 1
AIN10 1 0 1 0
Bit 6 = SPEED ADC clock selection AIN11 1 0 1 1
This bit is set and cleared by software. AIN12 1 1 0 0
0: fADC = fCPU/4 AIN13 1 1 0 1
1: fADC = fCPU/2 AIN14 1 1 1 0
AIN15 1 1 1 1
Bit 5 = ADON A/D Converter on *The number of channels is device dependent. Refer to
This bit is set and cleared by software. the device pinout description.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
DATA REGISTER (ADCDRH)
Bit 4 = Reserved. Must be kept cleared. Read Only
Reset Value: 0000 0000 (00h)

7 0

D9 D8 D7 D6 D5 D4 D3 D2

Bit 7:0 = D[9:2] MSB of Converted Analog Value

DATA REGISTER (ADCDRL)

Read Only
Reset Value: 0000 0000 (00h)

7 0

0 0 0 0 0 0 D1 D0

Bit 7:2 = Reserved. Forced by hardware to 0.

Bit 1:0 = D[1:0] LSB of Converted Analog Value

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10-BIT A/D CONVERTER (Cont’d)

Table 26. ADC Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

ADCCSR EOC SPEED ADON CH3 CH2 CH1 CH0

0070h
Reset Value 0 0 0 0 0 0 0 0
ADCDRH D9 D8 D7 D6 D5 D4 D3 D2
0071h
Reset Value 0 0 0 0 0 0 0 0
ADCDRL D1 D0
0072h
Reset Value 0 0 0 0 0 0 0 0

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ST72325xx

11 INSTRUCTION SET

11.1 CPU ADDRESSING MODES so, most of the addressing modes may be subdi-
vided in two submodes called long and short:
The CPU features 17 different addressing modes
which can be classified in seven main groups: – Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
Addressing Mode Example however it uses more bytes and more CPU cy-
Inherent nop cles.
Immediate ld A,#$55 – Short addressing mode is less powerful because
it can generally only access page zero (0000h -
Direct ld A,$55
00FFh range), but the instruction size is more
Indexed ld A,($55,X) compact, and faster. All memory to memory in-
Indirect ld A,([$55],X) structions use short addressing modes only
Relative jrne loop (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Bit operation bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
The CPU Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 27. CPU Addressing Mode Overview
Pointer Pointer Size Length
Mode Syntax Destination Address (Hex.) (Bytes)
(Hex.)
Inherent nop +0

Immediate ld A,#$55 +1

Short Direct ld A,$10 00..FF +1

Long Direct ld A,$1000 0000..FFFF +2

No Offset Direct Indexed ld A,(X) 00..FF +0

Short Direct Indexed ld A,($10,X) 00..1FE +1

Long Direct Indexed ld A,($1000,X) 0000..FFFF +2

Short Indirect ld A,[$10] 00..FF 00..FF byte +2

Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word +2

Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte +2

Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word +2

Relative Direct jrne loop PC+/-127 +1

Relative Indirect jrne [$10] PC+/-127 00..FF byte +2

Bit Direct bset $10,#7 00..FF +1

Bit Indirect bset [$10],#7 00..FF 00..FF byte +2

Bit Direct Relative btjt $10,#7,skip 00..FF +2

Bit Indirect Relative btjt [$10],#7,skip 00..FF 00..FF byte +3

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INSTRUCTION SET OVERVIEW (Cont’d)

11.1.1 Inherent 11.1.3 Direct
All Inherent instructions consist of a single byte. In Direct instructions, the operands are referenced
The opcode fully specifies all the required informa- by their memory address.
tion for the CPU to process the operation. The direct addressing mode consists of two sub-
Inherent Instruction Function modes:
NOP No operation Direct (short)
TRAP S/W Interrupt The address is a byte, thus requires only one byte
Wait For Interrupt (Low Pow-
after the opcode, but only allows 00 - FF address-
WFI
er Mode)
ing space.
Halt Oscillator (Lowest Power Direct (long)
HALT
Mode) The address is a word, thus allowing 64 Kbyte ad-
RET Sub-routine Return dressing space, but requires 2 bytes after the op-
code.
IRET Interrupt Sub-routine Return
SIM Set Interrupt Mask (level 3)
RIM Reset Interrupt Mask (level 0)
11.1.4 Indexed (No Offset, Short, Long)
SCF Set Carry Flag In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
RCF Reset Carry Flag addition of an index register (X or Y) with an offset.
RSP Reset Stack Pointer
The indirect addressing mode consists of three
LD Load submodes:
CLR Clear Indexed (No Offset)
PUSH/POP Push/Pop to/from the stack There is no offset, (no extra byte after the opcode),
INC/DEC Increment/Decrement and allows 00 - FF addressing space.
TNZ Test Negative or Zero Indexed (Short)
CPL, NEG 1 or 2 Complement The offset is a byte, thus requires only one byte af-
MUL Byte Multiplication ter the opcode and allows 00 - 1FE addressing
SLL, SRL, SRA, RLC,
space.
Shift and Rotate Operations Indexed (long)
RRC
SWAP Swap Nibbles The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
11.1.2 Immediate
Immediate instructions have 2 bytes, the first byte
contains the opcode, the second byte contains the 11.1.5 Indirect (Short, Long)
operand value. The required data byte to do the operation is found
Immediate Instruction Function
by its memory address, located in memory (point-
er).
LD Load
The pointer address follows the opcode. The indi-
CP Compare rect addressing mode consists of two submodes:
BCP Bit Compare Indirect (short)
AND, OR, XOR Logical Operations
The pointer address is a byte, the pointer size is a
ADC, ADD, SUB, SBC Arithmetic Operations byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.

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INSTRUCTION SET OVERVIEW (Cont’d)

11.1.6 Indirect Indexed (Short, Long) 11.1.7 Relative mode (Direct, Indirect)
This is a combination of indirect and short indexed This addressing mode is used to modify the PC
addressing modes. The operand is referenced by register value, by adding an 8-bit signed offset to
its memory address, which is defined by the un- it.
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point- Available Relative
er address follows the opcode. Direct/Indirect Function
Instructions
The indirect indexed addressing mode consists of
two submodes: JRxx Conditional Jump
CALLR Call Relative
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode. The relative addressing mode consists of two sub-
modes:
Indirect Indexed (Long) Relative (Direct)
The pointer address is a byte, the pointer size is a The offset is following the opcode.
word, thus allowing 64 Kbyte addressing space, Relative (Indirect)
and requires 1 byte after the opcode. The offset is defined in memory, which address
Table 28. Instructions Supporting Direct, follows the opcode.
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD Load
CP Compare
AND, OR, XOR Logical Operations
Arithmetic Additions/Sub-
ADC, ADD, SUB, SBC
stractions operations
BCP Bit Compare

Short Instructions Only Function

CLR Clear
INC, DEC Increment/Decrement
TNZ Test Negative or Zero
CPL, NEG 1 or 2 Complement
BSET, BRES Bit Operations
Bit Test and Jump Opera-
BTJT, BTJF
tions
SLL, SRL, SRA, RLC,
Shift and Rotate Operations
RRC
SWAP Swap Nibbles
CALL, JP Call or Jump subroutine

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INSTRUCTION SET OVERVIEW (Cont’d)

11.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set be subdivided into 13 main groups as illustrated in
consisting of 63 instructions. The instructions may the following table:

Load and Transfer LD CLR

Stack operation PUSH POP RSP
Increment/Decrement INC DEC
Compare and Tests CP TNZ BCP
Logical operations AND OR XOR CPL NEG
Bit Operation BSET BRES
Conditional Bit Test and Branch BTJT BTJF
Arithmetic operations ADC ADD SUB SBC MUL
Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA
Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET
Conditional Branch JRxx
Interruption management TRAP WFI HALT IRET
Condition Code Flag modification SIM RIM SCF RCF

Using a prebyte
The instructions are described with one to four op- These prebytes enable instruction in Y as well as
codes. indirect addressing modes to be implemented.
In order to extend the number of available op- They precede the opcode of the instruction in X or
codes for an 8-bit CPU (256 opcodes), three differ- the instruction using direct addressing mode. The
ent prebyte opcodes are defined. These prebytes prebytes are:
modify the meaning of the instruction they pre- PDY 90 Replace an X based instruction
cede. using immediate, direct, indexed, or inherent ad-
The whole instruction becomes: dressing mode by a Y one.
PC-2 End of previous instruction PIX 92 Replace an instruction using di-
rect, direct bit, or direct relative addressing mode
PC-1 Prebyte to an instruction using the corresponding indirect
PC Opcode addressing mode.
PC+1 Additional word (0 to 2) according It also changes an instruction using X indexed ad-
to the number of bytes required to compute the ef- dressing mode to an instruction using indirect X in-
fective address dexed addressing mode.
PIY 91 Replace an instruction using X in-
direct indexed addressing mode by a Y one.

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INSTRUCTION SET OVERVIEW (Cont’d)

Mnemo Description Function/Example Dst Src I1 H I0 N Z C

ADC Add with Carry A=A+M+C A M H N Z C
ADD Addition A=A+M A M H N Z C
AND Logical And A=A.M A M N Z
BCP Bit compare A, Memory tst (A . M) A M N Z
BRES Bit Reset bres Byte, #3 M
BSET Bit Set bset Byte, #3 M
BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C
BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C
CALL Call subroutine
CALLR Call subroutine relative
CLR Clear reg, M 0 1
CP Arithmetic Compare tst(Reg - M) reg M N Z C
CPL One Complement A = FFH-A reg, M N Z 1
DEC Decrement dec Y reg, M N Z
HALT Halt 1 0
IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C
INC Increment inc X reg, M N Z
JP Absolute Jump jp [TBL.w]
JRA Jump relative always
JRT Jump relative
JRF Never jump jrf *
JRIH Jump if ext. INT pin = 1 (ext. INT pin high)
JRIL Jump if ext. INT pin = 0 (ext. INT pin low)
JRH Jump if H = 1 H=1?
JRNH Jump if H = 0 H=0?
JRM Jump if I1:0 = 11 I1:0 = 11 ?
JRNM Jump if I1:0 <> 11 I1:0 <> 11 ?
JRMI Jump if N = 1 (minus) N=1?
JRPL Jump if N = 0 (plus) N=0?
JREQ Jump if Z = 1 (equal) Z=1?
JRNE Jump if Z = 0 (not equal) Z=0?
JRC Jump if C = 1 C=1?
JRNC Jump if C = 0 C=0?
JRULT Jump if C = 1 Unsigned <
JRUGE Jump if C = 0 Jmp if unsigned >=
JRUGT Jump if (C + Z = 0) Unsigned >

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INSTRUCTION SET OVERVIEW (Cont’d)

Mnemo Description Function/Example Dst Src I1 H I0 N Z C

JRULE Jump if (C + Z = 1) Unsigned <=
LD Load dst <= src reg, M M, reg N Z
MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0
NEG Negate (2's compl) neg $10 reg, M N Z C
NOP No Operation
OR OR operation A=A+M A M N Z
pop reg reg M
POP Pop from the Stack
pop CC CC M I1 H I0 N Z C
PUSH Push onto the Stack push Y M reg, CC
RCF Reset carry flag C=0 0
RET Subroutine Return
RIM Enable Interrupts I1:0 = 10 (level 0) 1 0
RLC Rotate left true C C <= A <= C reg, M N Z C
RRC Rotate right true C C => A => C reg, M N Z C
RSP Reset Stack Pointer S = Max allowed
SBC Substract with Carry A=A-M-C A M N Z C
SCF Set carry flag C=1 1
SIM Disable Interrupts I1:0 = 11 (level 3) 1 1
SLA Shift left Arithmetic C <= A <= 0 reg, M N Z C
SLL Shift left Logic C <= A <= 0 reg, M N Z C
SRL Shift right Logic 0 => A => C reg, M 0 Z C
SRA Shift right Arithmetic A7 => A => C reg, M N Z C
SUB Substraction A=A-M A M N Z C
SWAP SWAP nibbles A7-A4 <=> A3-A0 reg, M N Z
TNZ Test for Neg & Zero tnz lbl1 N Z
TRAP S/W trap S/W interrupt 1 1
WFI Wait for Interrupt 1 0
XOR Exclusive OR A = A XOR M A M N Z

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ST72325xx

12 ELECTRICAL CHARACTERISTICS

12.1 PARAMETER CONDITIONS

Unless otherwise specified, all voltages are re- Figure 73. Pin input voltage
ferred to VSS.
12.1.1 Minimum and Maximum values
Unless otherwise specified the minimum and max- ST7 PIN
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the VIN
devices with an ambient temperature at TA=25°C
and TA=TAmax (given by the selected temperature
range).
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
12.1.2 Typical values
Unless otherwise specified, typical data are based
on TA=25°C, VDD=5V.They are given only as de-
sign guidelines and are not tested.
12.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
12.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 72.
Figure 72. Pin loading conditions

ST7 PIN

CL

12.1.5 Pin input voltage

The input voltage measurement on a pin of the de-
vice is described in Figure 73.

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12.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as “absolute maxi- tions is not implied. Exposure to maximum rating
mum ratings” may cause permanent damage to conditions for extended periods may affect device
the device. This is a stress rating only and func- reliability.
tional operation of the device under these condi-
12.2.1 Voltage Characteristics
Symbol Ratings Maximum value Unit
VDD - VSS Supply voltage 6.5
VPP - VSS Programming Voltage 13
V
1) & 2)
Input Voltage on true open drain pin VSS-0.3 to 6.5
VIN
Input voltage on any other pin VSS-0.3 to VDD+0.3
|ΔVDDx| and |ΔVSSx| Variations between different digital power pins 50
mV
|VSSA - VSSx| Variations between digital and analog ground pins 50
VESD(HBM) Electro-static discharge voltage (Human Body Model)
see section 12.7.3 on page 158
VESD(MM) Electro-static discharge voltage (Machine Model)
12.2.2 Current Characteristics
Symbol Ratings Maximum value Unit
32-pin devices 75
Total current into VDD power lines
IVDD / IVSS 3) 44/48/64-pin mA
(source) and VSS ground lines (sink) 150
devices
Output current sunk by any standard I/O and control pin 25
IIO Output current sunk by any high sink I/O pin 50
Output current source by any I/Os and control pin - 25
Injected current on VPP pin ±5
Injected current on RESET pin ±5 mA
IINJ(PIN) 2) & 4) Injected current on OSC1 and OSC2 pins ±5
Injected current on PB0 (Flash devices only) +5
5) & 6)
Injected current on any other pin ±5
ΣIINJ(PIN) 2) Total injected current (sum of all I/O and control pins) 5) ± 25
Notes:
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). For the same reason, unused I/O pins must not be directly tied to VDD or VSS.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be
respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD
while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the
corresponding VIN maximum must always be respected
3. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
4. Negative injection disturbs the analog performance of the device. See note in “ADC Accuracy” on page 173.
For best reliability, it is recommended to avoid negative injection of more than 1.6mA.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive
and negative injected currents (instantaneous values). These results are based on characterisation with ΣIINJ(PIN) maxi-
mum current injection on four I/O port pins of the device.
6. True open drain I/O port pins do not accept positive injection.

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ST72325xx

12.2.3 Thermal Characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range -65 to +150 °C
TJ Maximum junction temperature (see Section 13.2 THERMAL CHARACTERISTICS)

12.3 OPERATING CONDITIONS

12.3.1 General Operating Conditions
Symbol Parameter Conditions Min Max Unit
fCPU Internal clock frequency 0 8 MHz
Standard voltage range (except Flash
3.8 5.5
VDD Write/Erase) V
Operating Voltage for Flash Write/Erase VPP = 11.4 to 12.6V 4.5 5.5
1 Suffix Version 0 70
5 Suffix Version -10 85
TA Ambient temperature range 6Suffix Versions -40 85 °C
7 Suffix Versions -40 105
3 Suffix Version -40 125

Figure 74. fCPU Max Versus VDD

fCPU [MHz]

8 FUNCTIONALITY
FUNCTIONALITY GUARANTEED
NOT GUARANTEED IN THIS AREA
6 (UNLESS
IN THIS AREA
OTHERWISE
4 SPECIFIED
IN THE TABLES
2 OF PARAMETRIC
DATA)
1
0
3.5 3.8 4.0 4.5 5.5

SUPPLY VOLTAGE [V]

Note: Some temperature ranges are only available with a specific package and memory size. Refer to Or-
dering Information.

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OPERATING CONDITIONS (Cont’d)

12.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for VDD, fCPU, and TA.
Symbol Parameter Conditions Min Typ Max Unit
VD level = High in option byte 4.01) 4.2 4.5
Reset release threshold
VIT+(LVD)
(VDD rise) VD level = Med. in option byte2) 3.551) 3.75 4.01)
VD level = Low in option byte2) 2.951) 3.15 3.351)
V
VD level = High in option byte 3.8 4.0 4.251)
Reset generation threshold
VIT-(LVD)
(VDD fall) VD level = Med. in option byte2) 3.351) 3.55 3.751))
VD level = Low in option byte2) 2.81) 3.0 3.15 1)
Vhys(LVD) LVD voltage threshold hysteresis VIT+(LVD)-VIT-(LVD) 200 mV
VtPOR VDD rise time 3) LVD enabled 6μs/V 100ms/V
VDD glitches filtered (not detect-
tg(VDD) 40 ns
ed) by LVD 3)
Notes:
1. Data based on characterization results, tested in production for ROM devices only.
2. If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range.
Below 3.8V, device operation is not guaranteed.
3. Data based on characterization results, not tested in production.

12.3.3 Auxiliary Voltage Detector (AVD) Thresholds

Subject to general operating conditions for VDD, fCPU, and TA.
Symbol Parameter Conditions Min Typ Max Unit
1) 1)
VD level = High in option byte 4.4 4.6 4.9
1 ⇒0 AVDF flag toggle threshold
VIT+(AVD)
(VDD rise) VD level = Med. in option byte 3.95 1) 4.15 4.41)
VD level = Low in option byte 3.4 1) 3.6 3.81)
V
VD level = High in option byte 4.21) 4.4 4.65 1)
0 ⇒1 AVDF flag toggle threshold
VIT-(AVD)
(VDD fall) VD level = Med. in option byte 3.751) 4.0 4.2 1)
VD level = Low in option byte 3.21) 3.4 3.61)
Vhys(AVD) AVD voltage threshold hysteresis VIT+(AVD)-VIT-(AVD) 200 mV
Voltage drop between AVD flag set
ΔVIT- VIT-(AVD)-VIT-(LVD) 450 mV
and LVD reset activated
1. Data based on characterization results, tested in production for ROM devices only.
12.3.4 External Voltage Detector (EVD) Thresholds
Subject to general operating conditions for VDD, fCPU, and TA.
Symbol Parameter Conditions Min Typ Max Unit
1 ⇒0 AVDF flag toggle threshold
VIT+(EVD) 1.15 1.26 1.35
(VDD rise)1)
V
0 ⇒1 AVDF flag toggle threshold
VIT-(EVD) 1.1 1.2 1.3
(VDD fall)1)
Vhys(EVD) EVD voltage threshold hysteresis VIT+(EVD)-VIT-(EVD) 200 mV
1. Data based on characterization results, not tested in production.

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12.4 SUPPLY CURRENT CHARACTERISTICS

The following current consumption specified for the ST7 functional operating modes over temperature
range does not take into account the clock source current consumption. To get the total device consump-
tion, the two current values must be added (except for HALT mode for which the clock is stopped).
12.4.1 CURRENT CONSUMPTION
Flash Devices ROM Devices
Symbol Parameter Conditions Unit
Typ Max 1) Typ Max 1)
fOSC=2MHz, fCPU=1MHz 1.3 3.0 0.5 1.0
f =4MHz, fCPU=2MHz 2.0 5.0 1.2 2.0
Supply current in RUN mode 2) OSC mA
fOSC=8MHz, fCPU=4MHz 3.6 8.0 2.2 4.0
fOSC=16MHz, fCPU=8MHz 7.1 15.0 4.8 8.0
fOSC=2MHz, fCPU=62.5kHz 600 2700 100 600
Supply current in SLOW mode fOSC=4MHz, fCPU=125kHz 700 3000 200 700
2) μA
fOSC=8MHz, fCPU=250kHz 800 3600 300 800
fOSC=16MHz, fCPU=500kHz 1100 4000 500 950
fOSC=2MHz, fCPU=1MHz 0.8 3.0 0.5 1.0
IDD Supply current in WAIT mode fOSC=4MHz, fCPU=2MHz 1.2 4.0 0.8 1.3
2) mA
fOSC=8MHz, fCPU=4MHz 2.0 5.0 1.5 2.2
fOSC=16MHz, fCPU=8MHz 3.5 7.0 3.0 4.0
fOSC=2MHz, fCPU=62.5kHz 580 1200 50 100
Supply current in SLOW WAIT fOSC=4MHz, fCPU=125kHz 650 1300 90 150
μA
mode 2) fOSC=8MHz, fCPU=250kHz 770 1800 180 300
fOSC=16MHz, fCPU=500kHz 1050 2000 350 600
Supply current in HALT mode -40°C ≤TA≤+85°C <1 10 <1 10
3) μA
-40°C ≤TA≤+125°C 5 50 <1 50
fOSC=2MHz 450 15 25
No max.
Supply current in ACTIVE- fOSC=4MHz 465 30 50
IDD guaran- μA
HALT mode 4) fOSC=8MHz 530 60 100
teed
fOSC =16MHz 650 120 200

Notes:
1. Data based on characterization results, tested in production at VDD max. and fCPU max.
2. Measurements are done in the following conditions:
- Program executed from RAM, CPU running with RAM access.
- All I/O pins in input mode with a static value at VDD or VSS (no load)
- All peripherals in reset state.
- CSS and LVD disabled.
- Clock input (OSC1) driven by external square wave.
- In SLOW and SLOW WAIT mode, fCPU is based on fOSC divided by 32.
To obtain the total current consumption of the device, add the clock source (Section 12.4.2) and the peripheral power
consumption (Section 12.4.3).
3. All I/O pins in push-pull 0 mode (when applicable) with a static value at VDD or VSS (no load), LVD disabled. Data
based on characterization results, tested in production at VDD max. and fCPU max.
4. Data based on characterisation results, not tested in production. All I/O pins in push-pull 0 mode (when applicable) with
a static value at VDD or VSS (no load); clock input (OSC1) driven by external square wave, LVD disabled. To obtain the
total current consumption of the device, add the clock source consumption (Section 12.4.2).

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SUPPLY CURRENT CHARACTERISTICS (Cont’d)

12.4.2 Supply and Clock Managers
The previous current consumption specified for the ST7 functional operating modes over temperature
range does not take into account the clock source current consumption. To get the total device consump-
tion, the two current values must be added (except for HALT mode).
Symbol Parameter Conditions Typ Max Unit
IDD(RCINT) Supply current of internal RC oscillator 625
see section
IDD(RES) Supply current of resonator oscillator 1) & 2) 12.5.3 on page
150 μA
IDD(PLL) PLL supply current VDD= 5V 360
IDD(CSS) Clock security system supply current VDD= 5V 250
IDD(LVD) LVD supply current VDD= 5V 150 300

Notes:
1.. Data based on characterization results done with the external components specified in Section 12.5.3, not tested in
production.
2. As the oscillator is based on a current source, the consumption does not depend on the voltage.

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SUPPLY CURRENT CHARACTERISTICS (Cont’d)

12.4.3 On-Chip Peripherals
Measured on LQFP64 generic board TA = 25°C fCPU=4MHz.
Symbol Parameter Conditions Typ Unit
IDD(TIM) 16-bit Timer supply current 1) VDD=5.0V 50 μA
IDD(ART) ART PWM supply current2) VDD=5.0V 75 μA
3)
IDD(SPI) SPI supply current VDD=5.0V 400 μA
IDD(SCI) SCI supply current 4) VDD=5.0V 400 μA
IDD(I2C) I2C supply current 5) VDD=5.0V 175 μA
IDD(ADC) ADC supply current when converting 6) VDD=5.0V 400 μA

Notes:
1. Data based on a differential IDD measurement between reset configuration (timer counter running at fCPU/4) and timer
counter stopped (only TIMD bit set). Data valid for one timer.
2. Data based on a differential IDD measurement between reset configuration (timer stopped) and timer counter enabled
(only TCE bit set).
3. Data based on a differential IDD measurement between reset configuration (SPI disabled) and a permanent SPI master
communication at maximum speed (data sent equal to 55h).This measurement includes the pad toggling consumption.
4. Data based on a differential IDD measurement between SCI low power state (SCID=1) and a permanent SCI data trans-
mit sequence.
5. Data based on a differential IDD measurement between reset configuration (I2C disabled) and a permanent I2C master
communication at 100kHz (data sent equal to 55h). This measurement include the pad toggling consumption (27kOhm
external pull-up on clock and data lines).
6. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions.

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 ST72325xx

12.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for VDD, fCPU, and TA.
12.5.1 General Timings
Symbol Parameter Conditions Min Typ 1) Max Unit
2 3 12 tCPU
tc(INST) Instruction cycle time
fCPU=8MHz 250 375 1500 ns
2) 10 22 tCPU
Interrupt reaction time
tv(IT)
tv(IT) = Δtc(INST) + 10 fCPU=8MHz 1.25 2.75 μs

12.5.2 External Clock Source

Symbol Parameter Conditions Min Typ Max Unit
VOSC1H OSC1 input pin high level voltage 0.7xVDD VDD
V
VOSC1L OSC1 input pin low level voltage VSS 0.3xVDD
tw(OSC1H)
OSC1 high or low time 3) see Figure 75 5
tw(OSC1L)
ns
tr(OSC1)
OSC1 rise or fall time 3) 15
tf(OSC1)
IL OSC1 Input leakage current VSS ≤VIN≤VDD ±1 μA

Figure 75. Typical Application with an External Clock Source

90%
VOSC1H
10%

VOSC1L

tr(OSC1) tf(OSC1) tw(OSC1H) tw(OSC1L)

OSC2
Not connected internally

fOSC
EXTERNAL
IL
CLOCK SOURCE
OSC1
ST72XXX

Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. Δtc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.

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ST72325xx

CLOCK AND TIMING CHARACTERISTICS (Cont’d)

12.5.3 Crystal and Ceramic Resonator Oscillators
The ST7 internal clock can be supplied with four close as possible to the oscillator pins in order to
different Crystal/Ceramic resonator oscillators. All minimize output distortion and start-up stabiliza-
the information given in this paragraph is based on tion time. Refer to the crystal/ceramic resonator
characterization results with specified typical ex- manufacturer for more details (frequency, pack-
ternal components. In the application, the resona- age, accuracy...).
tor and the load capacitors have to be placed as
Symbol Parameter Conditions Min Max Unit
fOSC Oscillator Frequency 1) 1 16 MHz
RF Feedback resistor2) 20 40 kΩ
fOSC= 1 to 2 MHz 20 60
CL1 Recommended load capacitance ver-
fOSC= 2 to 4 MHz 20 50
sus equivalent serial resistance of the pF
CL2 fOSC= 4 to 8 MHz 15 35
crystal or ceramic resonator (RS)3)
fOSC= 8 to 16 MHz 15 35

Symbol Parameter Conditions Typ Max Unit

VDD=5V:
fOSC= 2MHz, C0 = 6pF, Cl1 = Cl2 = 68pF 426
i2 OSC2 driving current fOSC= 4MHz, C0 = 6pF, Cl1 = Cl2 = 68pF 425 µA
fOSC= 8MHz, C0 = 6pF, Cl1 = Cl2 = 40pF 456
fOSC= 16MHz, C0 = 7pF, Cl1 = Cl2 = 20pF 660

Notes:
1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value.
Refer to crystal/ceramic resonator manufacturer for more details.
2. Data based on characterisation results, not tested in production.

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 ST72325xx

Figure 76. Typical Application with a Crystal or Ceramic Resonator

WHEN RESONATOR WITH

INTEGRATED CAPACITORS fOSC
POWER DOWN
CL1 OSC1
LOGIC
LINEAR FEEDBACK
AMPLIFIER LOOP

RESONATOR VDD/2 i2
Ref
RF
CL2
OSC2
ST72XXX

1. The relatively low value of the RF resistor, offers a good protection against issues resulting from use in a humid envi-
ronment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into
account if the µC is used in tough humidity conditions.
2. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5-pF to 25-pF range (typ.) designed
for high-frequency applications and selected to match the requirements of the crystal or resonator. CL1 and CL2, are usu-
ally the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1
and CL2. PCB and MCU pin capacitance must be included when sizing CL1 and CL2 (10 pF can be used as a rough esti-
mate of the combined pin and board capacitance).

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ST72325xx

CLOCK AND TIMING CHARACTERISTICS (Cont’d)

fOSC
Supplier Typical Ceramic Resonators2)
(MHz)
2 CSTCC2M00G56Z-R0
SMD CSTCR4M00G53Z-R0
4
Lead CSTLS4M00G53Z-R0
Murata

SMD CSTCE8M00G52Z-R0
8
Lead CSTLS4M0052Z-R0
SMD CSTCE16M0V51Z-R0
16
Lead CSTLS16M0X51Z-R0

Notes:
1. Resonator characteristics given by the ceramic resonator manufacturer.
2. SMD = [-R0: Plastic tape package (∅ =180mm), -B0: Bulk]
LEAD = [-A0: Flat pack package (Radial taping Ho= 18mm), -B0: Bulk]
For more information on these resonators, please consult www.murata.com

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 ST72325xx

CLOCK CHARACTERISTICS (Cont’d)

12.5.4 RC Oscillators
Symbol Parameter Conditions Min Typ Max Unit
Internal RC oscillator frequency
fOSC (RCINT) TA=25°C, VDD=5V 2 3.5 5.6 MHz
See Figure 77

Figure 77. Typical fOSC(RCINT) vs TA Note: To reduce disturbance to the RC oscillator,

it is recommended to place decoupling capacitors
between VDD and VSS as shown in Figure 97

4
Vdd = 5V
fOSC(RCINT) (MHz)

3.8
Vdd = 5.5V
3.6

3.4

3.2

3
-45 0 25 70 130
TA(°C)

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ST72325xx

CLOCK CHARACTERISTICS (Cont’d)

12.5.5 Clock Security System (CSS)
Symbol Parameter Conditions Min Typ Max Unit
fSFOSC Safe Oscillator Frequency 1) 3 MHz

Note:
1. Data based on characterization results.
12.5.6 PLL Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOSC PLL input frequency range 2 4 MHz
Δ fCPU/ fCPU Instantaneous PLL jitter 1) fOSC = 4 MHz. 0.7 2 %

Note:
1. Data characterized but not tested.
The user must take the PLL jitter into account in the application (for example in serial communication or
sampling of high frequency signals). The PLL jitter is a periodic effect, which is integrated over several
CPU cycles. Therefore the longer the period of the application signal, the less it will be impacted by the
PLL jitter.
Figure 78 shows the PLL jitter integrated on application signals in the range 125kHz to 4MHz. At frequen-
cies of less than 125KHz, the jitter is negligible.
Figure 78. Integrated PLL Jitter vs signal frequency1
+/-Jitter (%)
1.2

1 Max
Typ
0.8

0.6

0.4

0.2

0
4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz
Application Frequency

Note 1: Measurement conditions: fCPU = 8MHz.

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 ST72325xx

12.6 MEMORY CHARACTERISTICS

12.6.1 RAM and Hardware Registers
Symbol Parameter Conditions Min Typ Max Unit
VRM 1)
Data retention mode HALT mode (or RESET) 1.6 V

12.6.2 FLASH Memory

DUAL VOLTAGE HDFLASH MEMORY
Symbol Parameter Conditions Min 2) Typ Max 2) Unit
Read mode 0 8
fCPU Operating frequency MHz
Write / Erase mode 1 8
VPP Programming voltage 3) 4.5V ≤ VDD ≤ 5.5V 11.4 12.6 V
RUN mode (fCPU = 4MHz) 3
mA
IDD Supply current4) Write / Erase 0
Power down mode / HALT 1 10
µA
Read (VPP=12V) 200
IPP VPP current4)
Write / Erase 30 mA
tVPP Internal VPP stabilization time 10 µs
TA=85°C 40
tRET Data retention TA=105°C 15 years
TA=125°C 7
TA= 55°C 1000 cycles
NRW Write erase cycles
TA= 85°C 100 cycles
TPROG Programming or erasing tempera-
-40 25 85 °C
TERASE ture range
Notes:
1. Minimum VDD supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg-
isters (only in HALT mode). Not tested in production.
2. Data based on characterization results, not tested in production.
3. VPP must be applied only during the programming or erasing operation and not permanently for reliability reasons.
4. Data based on simulation results, not tested in production.
Warning: Do not connect 12V to VPP before VDD is powered on, as this may damage the device.

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ST72325xx

12.7 EMC CHARACTERISTICS should be noted that good EMC performance is

highly dependent on the user application and the
Susceptibility tests are performed on a sample ba- software in particular.
sis during product characterization.
Therefore it is recommended that the user applies
12.7.1 Functional EMS (Electro Magnetic EMC software optimization and prequalification
Susceptibility) tests in relation with the EMC level requested for
Based on a simple running application on the his application.
product (toggling 2 LEDs through I/O ports), the Software recommendations:
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs). The software flowchart must include the manage-
ment of runaway conditions such as:
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until – Corrupted program counter
a functional disturbance occurs. This test – Unexpected reset
conforms with the IEC 1000-4-2 standard.
– Critical Data corruption (control registers...)
■ FTB: A Burst of Fast Transient voltage (positive
and negative) is applied to VDD and VSS through Prequalification trials:
a 100pF capacitor, until a functional disturbance Most of the common failures (unexpected reset
occurs. This test conforms with the IEC 1000-4- and program counter corruption) can be repro-
4 standard. duced by manually forcing a low state on the RE-
A device reset allows normal operations to be re- SET pin or the Oscillator pins for 1 second.
sumed. The test results are given in the table be- To complete these trials, ESD stress can be ap-
low based on the EMS levels and classes defined plied directly on the device, over the range of
in application note AN1709. specification values. When unexpected behaviour
12.7.1.1 Designing hardened software to avoid is detected, the software can be hardened to pre-
noise problems vent unrecoverable errors occurring (see applica-
tion note AN1015)
EMC characterization and optimization are per-
formed at component level with a typical applica- .
tion environment and simplified MCU software. It
Level/
Symbol Parameter Conditions
Class
All Flash and ROM devices, VDD=5V,
Voltage limits to be applied on any I/O pin to induce a
VFESD TA=+25°C, fOSC=8 MHz, conforms to IEC 3B
functional disturbance
1000-4-2
Fast transient voltage burst limits to be applied
LQFP44, VDD=5V, TA=+25°C,
VFFTB through 100pF on VDD and VDD pins to induce a func- 3B
fOSC= 8 MHz, conforms to IEC 1000-4-4
tional disturbance

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 ST72325xx

EMC CHARACTERISTICS (Cont’d)

12.7.2 Electro Magnetic Interference (EMI)
Based on a simple application running on the
product (toggling 2 LEDs through the I/O ports),
the product is monitored in terms of emission. This
emission test is in line with the norm SAE J 1752/
3 which specifies the board and the loading of
each pin.
Monitored Max vs. [fOSC/fCPU]1 Unit
Symbol Parameter Conditions
Frequency Band 8/4MHz 16/8MHz

48/60K Flash Devices: 0.1MHz to 30MHz 15 20

VDD=5V, TA=+25°C, 30MHz to 130MHz 20 27 dBμV
SEMI Peak level
LQFP64 10x10 package 130MHz to 1GHz 7 12
conforming to SAE J 1752/3 SAE EMI Level 2.5 3 -
8/16/32K/Flash Devices: 0.1MHz to 30MHz 13 14
VDD=5V, TA=+25°C, 30MHz to 130MHz 20 25 dBμV
SEMI Peak level
LQFP44 10x10 package 130MHz to 1GHz 16 21
conforming to SAE J 1752/3 SAE EMI Level 3 3.5 -
60K ROM Devices: 0.1MHz to 30MHz 15 20
VDD=5V, TA=+25°C, 30MHz to 130MHz 20 27 dBμV
SEMI Peak level
LQFP64 package 130MHz to 1GHz 7 12
conforming to SAE J 1752/3 SAE EMI Level 2.5 3 -
32K ROM devices: VDD=5V, 0.1MHz to 30MHz 17 21
TA=+25°C, 30MHz to 130MHz 24 30 dBμV
SEMI Peak level
LQFP44 10x10 package 130MHz to 1GHz 18 23
conforming to SAE J 1752/3 SAE EMI Level 3 3.5 -
Notes:
1. Data based on characterization results, not tested in production.
2. Refer to Application Note AN1709 for data on other package types.

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ST72325xx

EMC CHARACTERISTICS (Cont’d)

12.7.3 Absolute Maximum Ratings (Electrical 12.7.3.1 Electro-Static Discharge (ESD)
Sensitivity) Electro-Static Discharges (a positive then a nega-
Based on two different tests (ESD and LU) using tive pulse separated by 1 second) are applied to
specific measurement methods, the product is the pins of each sample according to each pin
stressed in order to determine its performance in combination. The sample size depends on the
terms of electrical sensitivity. For more details, re- number of supply pins in the device (3 parts*(n+1)
fer to the application note AN1181. supply pin). Two models can be simulated: Human
Body Model and Machine Model. This test con-
forms to the JESD22-A114A/A115A standard.
Absolute Maximum Ratings
Symbol Ratings Conditions Maximum value 1) Unit
Electro-static discharge voltage
VESD(HBM) TA=+25°C 2000
(Human Body Model)
V
Electro-static discharge voltage
VESD(MM) TA=+25°C 200
(Machine Model)

Notes:
1. Data based on characterization results, not tested in production.
12.7.3.2 Static Latch-Up supply pin) and a current injection (applied to
■ LU: 2 complementary static tests are required each input, output and configurable I/O pin) are
on 6 parts to assess the latch-up performance. performed on each sample. This test conforms
A supply overvoltage (applied to each power to the EIA/JESD 78 IC latch-up standard.

Electrical Sensitivities
Symbol Parameter Conditions Class 1)
TA=+125°C
LU Static latch-up class II level A
conforming to JESD 78

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 ST72325xx

12.8 I/O PORT PIN CHARACTERISTICS

12.8.1 General Characteristics
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
1)
VIL Input low level voltage 0.3xVDD
VIH Input high level voltage 1) CMOS ports 0.7xVDD V
2)
Vhys Schmitt trigger voltage hysteresis 0.7
Injected Current on PB0 (Flash de-
0 +4
IINJ(PIN)3) vices only)
Injected Current on an I/O pin VDD=5V ±4 mA
Total injected current (sum of all I/O
ΣIINJ(PIN)3) ± 25
and control pins)
IL Input leakage current VSS≤VIN ≤VDD ±1
4) μA
IS Static current consumption Floating input mode 400
RPU Weak pull-up equivalent resistor 5) VIN=VSS VDD=5V 50 120 250 kΩ
CIO I/O pin capacitance 5 pF
tf(IO)out Output high to low level fall time 1) CL=50pF 25
ns
tr(IO)out Output low to high level rise time 1) Between 10% and 90% 25
tw(IT)in External interrupt pulse time 6) 1 tCPU

Figure 79. Unused I/Os configured as input Figure 80. Typical IPU vs. VDD with VIN=VSS
90
VDD ST7XXX Ta=140°C
80
Ta=95°C
70
10kΩ Ta=25°C
Ta=-45°C
UNUSED I/O PORT 60
Ipu(uA )

50
UNUSED I/O PORT
40
10kΩ
30

ST7XXX 20

10
Note: I/O can be left unconnected if it is configured as output
(0 or 1) by the software. This has the advantage of 0
greater EMC robustness and lower cost. 2 2.5 3 3.5 4 4.5 5 5.5 6
V dd(V)

Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. When the current limitation is not possible, the VIN maximum must be respected, otherwise refer to IINJ(PIN) specifica-
tion. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. Refer to section 12.2.2
on page 143 for more details.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example and leaving the I/O unconnected on the board or an external pull-up or pull-down resistor (see Figure 79). Static
peak current value taken at a fixed VIN value, based on design simulation and technology characteristics, not tested in
production. This value depends on VDD and temperature values.
5. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics de-
scribed in Figure 80).
6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.

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ST72325xx

I/O PORT PIN CHARACTERISTICS (Cont’d)

12.8.2 Output Driving Current
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Symbol Parameter Conditions Min Max Unit
Output low level voltage for a standard I/O pin IIO=+5mA 1.2
when 8 pins are sunk at same time
(see Figure 81) IIO=+2mA 0.5
VOL 1) IIO=+20mA, TA≤85°C 1.3
Output low level voltage for a high sink I/O pin

VDD=5V
when 4 pins are sunk at same time TA≥85°C 1.5 V
(see Figure 82 and Figure 84) IIO=+8mA 0.6
Output high level voltage for an I/O pin IIO=-5mA, TA≤85°C VDD-1.4
VOH 2) when 4 pins are sourced at same time TA≥85°C VDD-1.6
(see Figure 83 and Figure 86) IIO=-2mA VDD-0.7

Figure 81. Typical VOL at VDD=5V (standard) Figure 83. Typical VOH at VDD=5V
1.4
5.5

1.2
5

1
V dd-Voh (V) at Vdd=5V
V ol (V ) at Vdd=5V

4.5
0.8
4

0.6
3.5
Ta =14 0°C " V dd= 5V 1 40°C m in
0.4
Ta =95 °C 3 V dd= 5v 95°C m in
Ta =25 °C
0.2 V dd= 5v 25°C m in
Ta =-45 °C
2.5
V dd= 5v -4 5°C m in
0
2
0 0.005 0.01 0.015
Iio(A) -0.01 -0.008 -0.006 -0.004 -0.002 0

Figure 82. Typical VOL at VDD=5V (high-sink)

1

0.9

0.8

0.7
V ol(V ) at Vdd=5V

0.6

0.5

0.4
Ta= 140 °C
0.3
Ta= 95 °C
0.2 Ta= 25 °C

0.1 Ta= -45°C

0
0 0.01 0.02 0.03
Iio(A)
Notes:
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of
IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins do not have VOH.

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 ST72325xx

I/O PORT PIN CHARACTERISTICS (Cont’d)

Figure 84. Typical VOL vs. VDD (standard)
1 0.45
Ta= -4 5°C
Ta=-4 5°C
0.9
Ta= 25°C 0.4 Ta=2 5°C
0.8 Ta= 95°C Ta=9 5°C
Ta= 140 °C 0.35
0.7 Ta=1 40°C
V ol(V ) at Iio=5m A

Vol(V) at Iio=2mA
0.3
0.6

0.5 0.25

0.4 0.2

0.3 0.15
0.2
0.1
0.1
0.05
0
2 2.5 3 3.5 4 4.5 5 5.5 6 0
2 2.5 3 3.5 4 4.5 5 5.5 6
Vdd(V )
Vdd(V)

Figure 85. Typical VOL vs. VDD (high-sink)

0 .6 1 .6

1 .4 Ta = 140 °C
0 .5
Ta =95 °C
1 .2 Ta =25 °C

0 .4 Ta =-45°C
1
Vol(V ) at Iio=20m A
Vol(V ) at Iio=8m A

0 .3 0 .8

0 .6
0 .2
Ta= 14 0°C
0 .4
Ta=9 5°C
0 .1 Ta=2 5°C
0 .2
Ta=-45 °C

0 0
2 2.5 3 3.5 4 4.5 5 5.5 6 2 2.5 3 3.5 4 4.5 5 5.5 6

V dd (V ) V dd(V )

Figure 86. Typical VDD-VOH vs. VDD

5.5 6

Ta= -4 5°C
5
5 Ta= 25°C
Vdd-Voh(V) at Iio=-2m A

Ta= 95°C
Vdd-Voh(V) at Iio=-5mA

4.5
4 Ta= 140°C

4
3
3.5
Ta= -4 5°C
2
3 Ta= 25°C

Ta= 95°C
2.5 1
Ta= 140°C

2
0
2 2.5 3 3.5 4 4.5 5 5.5 6 2 2.5 3 3.5 4 4.5 5 5.5 6
Vdd(V) Vdd(V)

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12.9 CONTROL PIN CHARACTERISTICS

12.9.1 Asynchronous RESET Pin
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
1)
VIL Input low level voltage 0.3xVDD V
VIH Input high level voltage 1) 0.7xVDD
Vhys Schmitt trigger voltage hysteresis 2) 2.5
V
VOL Output low level voltage 3) VDD=5V IIO=+2mA 0.2 0.5
IIO Input current on RESET pin 2 mA
RON Weak pull-up equivalent resistor 20 30 120 kΩ
Stretch applied on
0 426) μs
tw(RSTL)out Generated reset pulse duration external pulse
Internal reset sources 20 30 426) μs
4)
th(RSTL)in External reset pulse hold time 2.5 μs
tg(RSTL)in Filtered glitch duration 5) 200 ns

Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
the RESET pin with a duration below th(RSTL)in can be ignored.
5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy en-
vironments.
6. Data guaranteed by design, not tested in production.

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CONTROL PIN CHARACTERISTICS (Cont’d)

Figure 87. RESET pin protection when LVD is enabled.1)2)3)4)

VDD ST72XXX

Required Optional RON

(note 3) INTERNAL
EXTERNAL RESET
RESET Filter

0.01μF
1MΩ WATCHDOG
PULSE
GENERATOR
LVD RESET

Figure 88. RESET pin protection when LVD is disabled.1)

VDD ST72XXX

RON
USER INTERNAL
EXTERNAL RESET
RESET Filter
CIRCUIT
0.01μF
PULSE
WATCHDOG
GENERATOR
Required

Note 1:
– The reset network protects the device against parasitic resets.
– The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the
device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
– Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go
below the VIL max. level specified in section 12.9.1 on page 162. Otherwise the reset will not be taken into account
internally.
– Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must en-
sure that the current sunk on the RESET pin is less than the absolute maximum value specified for IINJ(RESET) in
section 12.2.2 on page 143.
Note 2: When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down
capacitor is required to filter noise on the reset line.
Note 3: In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down resistor to the RESET
pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5µA to the power
consumption of the MCU).
Note 4: Tips when using the LVD:
– 1. Check that all recommendations related to reset circuit have been applied (see notes above).
– 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709 and
AN2017. If this cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET pin.
– 3. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality.
In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on the
RESET pin with a 5µF to 20µF capacitor.

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CONTROL PIN CHARACTERISTICS (Cont’d)

12.9.2 ICCSEL/VPP Pin
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Symbol Parameter Conditions Min Max1 Unit
IL Input leakage current VIN=VSS ±1 μA

Figure 89. Two typical Applications with ICCSEL/VPP Pin 2)

ICCSEL/VPP VPP
PROGRAMMING
TOOL
10kΩ
ST72XXX ST72XXX

Notes:
1. Data based on design simulation and/or technology characteristics, not tested in production.
2. When ICC mode is not required by the application ICCSEL/VPP pin must be tied to VSS.

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 ST72325xx

12.10 TIMER PERIPHERAL CHARACTERISTICS

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (out-
put compare, input capture, external clock, PWM output...).
12.10.1 8-Bit PWM-ART Auto-Reload Timer
Symbol Parameter Conditions Min Typ Max Unit
1 tCPU
tres(PWM) PWM resolution time
fCPU=8MHz 125 ns
fEXT ART external clock frequency 0 fCPU/2
MHz
fPWM PWM repetition rate 0 fCPU/2
ResPWM PWM resolution 8 bit
VOS PWM/DAC output step voltage VDD=5V, Res=8-bits 20 mV

12.10.2 16-Bit Timer

Symbol Parameter Conditions Min Typ Max Unit
tw(ICAP)in Input capture pulse time 1 tCPU
2 tCPU
tres(PWM) PWM resolution time
fCPU=8MHz 250 ns
fEXT Timer external clock frequency 0 fCPU/4 MHz
fPWM PWM repetition rate 0 fCPU/4 MHz
ResPWM PWM resolution 16 bit

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ST72325xx

12.11 COMMUNICATION INTERFACE CHARACTERISTICS

12.11.1 SPI - Serial Peripheral Interface Refer to I/O port characteristics for more details on
Subject to general operating conditions for VDD, the input/output alternate function characteristics
fCPU, and TA unless otherwise specified. (SS, SCK, MOSI, MISO).

Symbol Parameter Conditions Min Max Unit

Master fCPU/128 fCPU/4
fSCK fCPU=8MHz 0.0625 2
SPI clock frequency MHz
1/tc(SCK) Slave fCPU/2
0
fCPU=8MHz 4
tr(SCK)
SPI clock rise and fall time see I/O port pin description
tf(SCK)
tsu(SS) 4)
SS setup time Slave tCPU + 50
th(SS) SS hold time Slave 120
tw(SCKH) Master 100
SCK high and low time
tw(SCKL) Slave 90
tsu(MI) Master 100
Data input setup time
tsu(SI) Slave 100
ns
th(MI) Master 100
Data input hold time
th(SI) Slave 100
ta(SO) Data output access time Slave 0 120
tdis(SO) Data output disable time Slave 240
tv(SO) Data output valid time 120
Slave (after enable edge)
th(SO) Data output hold time 0
tv(MO) Data output valid time 120
Master (after enable edge) tCPU
th(MO) Data output hold time 0

Figure 90. SPI Slave Timing Diagram with CPHA=0 3)

SS INPUT
tsu(SS) tc(SCK) th(SS)

CPHA=0
SCK INPUT

CPOL=0
CPHA=0
CPOL=1
tw(SCKH)
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)
tf(SCK)
MISO OUTPUT see
see note 2 MSB OUT BIT6 OUT LSB OUT note 2

tsu(SI) th(SI)

MOSI INPUT MSB IN BIT1 IN LSB IN

Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
4. Depends on fCPU. For example, if fCPU = 8 MHz, then tCPU = 1 / fCPU = 125 ns and tsu(SS) = 175 ns.

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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

Figure 91. SPI Slave Timing Diagram with CPHA=11)

SS INPUT
tsu(SS) tc(SCK) th(SS)

CPHA=1
SCK INPUT

CPOL=0
CPHA=1
CPOL=1

ta(SO) tw(SCKH) tdis(SO)

tw(SCKL) tv(SO) th(SO)
tr(SCK)
tf(SCK)
MISO OUTPUT see see
note 2 HZ MSB OUT BIT6 OUT LSB OUT note 2

tsu(SI) th(SI)

MOSI INPUT MSB IN BIT1 IN LSB IN

Figure 92. SPI Master Timing Diagram 1)

SS INPUT
tc(SCK)

CPHA = 0
CPOL = 0
CPHA = 0
SCK INPUT

CPOL = 1

CPHA = 1
CPOL = 0

CPHA = 1
CPOL = 1
tw(SCKH) tr(SCK)
tw(SCKL) tf(SCK)

tsu(MI) th(MI)

MISO INPUT MSB IN BIT6 IN LSB IN

tv(MO) th(MO)

MOSI OUTPUT See note 2 MSB OUT BIT6 OUT LSB OUT See note 2

Notes:
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.

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ST72325xx

COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

12.11.2 I2C - Inter IC Control Interface Refer to I/O port characteristics for more details on
Subject to general operating conditions for VDD, the input/output alternate function characteristics
fCPU, and TA unless otherwise specified. (SDAI and SCLI). The ST7 I2C interface meets the
requirements of the Standard I2C communication
protocol described in the following table.
Standard mode I2C Fast mode I2C5)
Symbol Parameter Unit
Min 1) Max 1) Min 1) Max 1)
tw(SCLL) SCL clock low time 4.7 1.3
μs
tw(SCLH) SCL clock high time 4.0 0.6
tsu(SDA) SDA setup time 250 100
3) 0 2) 900 3)
th(SDA) SDA data hold time 0
tr(SDA) ns
SDA and SCL rise time 1000 20+0.1Cb 300
tr(SCL)
tf(SDA)
SDA and SCL fall time 300 20+0.1Cb 300
tf(SCL)
th(STA) START condition hold time 4.0 0.6
μs
tsu(STA) Repeated START condition setup time 4.7 0.6
tsu(STO) STOP condition setup time 4.0 0.6 μs
tw(STO:STA) STOP to START condition time (bus free) 4.7 1.3 μs
Cb Capacitive load for each bus line 400 400 pF

Figure 93. Typical Application with I2C Bus and Timing Diagram 4)
VDD VDD

4.7kΩ 4.7kΩ 100Ω SDAI

I2C BUS 100Ω SCLI

ST72XXX
REPEATED START
START
tsu(STA) tw(STO:STA)
START
SDA

tf(SDA) tr(SDA) tsu(SDA) th(SDA) STOP

SCK

th(STA) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) tsu(STO)

Notes:
1. Data based on standard I2C protocol requirement, not tested in production.
2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal.
4. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
5. At 4MHz fCPU, max.I2C speed (400kHz) is not achievable. In this case, max. I2C speed will be approximately 260KHz.

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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

The following table gives the values to be written in
the I2CCCR register to obtain the required I2C
SCL line frequency.
Table 29. SCL Frequency Table
I2CCCR Value
fSCL fCPU=4 MHz. fCPU=8 MHz.
(kHz) VDD = 4.1 V VDD = 5 V VDD = 4.1 V VDD = 5 V
RP=3.3kΩ RP=4.7kΩ RP=3.3kΩ RP=4.7kΩ RP=3.3kΩ RP=4.7kΩ RP=3.3kΩ RP=4.7kΩ
400 NA NA NA NA 83h 83 83h 83h
300 NA NA NA NA 85h 85h 85h 85h
200 83h 83h 83h 83h 8Ah 89h 8Ah 8Ah
100 10h 10h 10h 10h 24h 23h 24h 23h
50 24h 24h 24h 24h 4Ch 4Ch 4Ch 4Ch
20 5Fh 5Fh 5Fh 5Fh FFh FFh FFh FFh

Legend:
RP = External pull-up resistance
fSCL = I2C speed
NA = Not achievable
Note:
– For speeds around 200 kHz, achieved speed can have ±5% tolerance
– For other speed ranges, achieved speed can have ±2% tolerance
The above variations depend on the accuracy of the external components used.

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ST72325xx

12.12 10-BIT ADC CHARACTERISTICS

Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
fADC ADC clock frequency 0.4 2 MHz
VAREF Analog reference voltage 0.7*VDD ≤ VAREF ≤ VDD 3.8 VDD
1)
V
VAIN Conversion voltage range VSSA VAREF
Positive input leakage current for analog -40°C ≤ TA ≤ 85°C range ±250 nA
input Other TA ranges ±1 μA
Ilkg VIN<VSS, | IIN |< 400µA
Negative input leakage current on ro-
on adjacent robust ana- 5 6 μA
bust analog pins
log pin
RAIN External input impedance see kΩ
CAIN External capacitor on analog input Figure 94 pF
and
fAIN Variation freq. of analog input signal Figure 95 Hz
CADC Internal sample and hold capacitor 12 pF
Conversion time (Sample+Hold)
tADC 7.5 μs
fCPU=8MHz, SPEED=0 fADC=2MHz
- No of sample capacitor loading cycles 4
tADC 1/fADC
- No. of Hold conversion cycles 11

Notes:
1. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.

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ADC CHARACTERISTICS (Cont’d)

Figure 94. RAIN max. vs fADC with CAIN=0pF1) Figure 95. Recommended CAIN & RAIN values.2)
45 1000
40 Cain 10 nF
35 2 MHz Cain 22 nF
100
Max. R AIN (Kohm)

Max. R AIN (Kohm)

30 Cain 47 nF
1 MHz
25
10
20

15

10 1

0 0.1
0 10 30 70 0.01 0.1 1 10
CPARASITIC (pF) fAIN(KHz)

Figure 96. Typical A/D Converter Application

VDD
ST72XXX
VT
RAIN 0.6V
AINx 2kΩ(max) 10-Bit A/D
VAIN Conversion

CAIN VT
0.6V IL CADC
±1μA 12pF

Notes:
1. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-
pacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
2. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and
decreased to allow the use of a larger serial resistor (RAIN).

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ADC CHARACTERISTICS (Cont’d)

12.12.1 Analog Power Supply and Reference – Filter power to the analog power planes. It is rec-
Pins ommended to connect capacitors, with good high
Depending on the MCU pin count, the package frequency characteristics, between the power
may feature separate VAREF and VSSA analog and ground lines, placing 0.1µF and optionally, if
power supply pins. These pins supply power to the needed 10pF capacitors as close as possible to
A/D converter cell and function as the high and low the ST7 power supply pins and a 1 to 10µF ca-
reference voltages for the conversion. pacitor close to the power source (see Figure
97).
Separation of the digital and analog power pins al-
low board designers to improve A/D performance. – The analog and digital power supplies should be
Conversion accuracy can be impacted by voltage connected in a star network. Do not use a resis-
drops and noise in the event of heavily loaded or tor, as VAREF is used as a reference voltage by
badly decoupled power supply lines (see Section the A/D converter and any resistance would
12.12.2 General PCB Design Guidelines). cause a voltage drop and a loss of accuracy.
12.12.2 General PCB Design Guidelines – Properly place components and route the signal
traces on the PCB to shield the analog inputs.
To obtain best results, some general design and Analog signals paths should run over the analog
layout rules should be followed when designing ground plane and be as short as possible. Isolate
the application PCB to shield the noise-sensitive, analog signals from digital signals that may
analog physical interface from noise-generating switch while the analog inputs are being sampled
CMOS logic signals. by the A/D converter. Do not toggle digital out-
– Use separate digital and analog planes. The an- puts on the same I/O port as the A/D input being
alog ground plane should be connected to the converted.
digital ground plane via a single point on the
PCB.
Figure 97. Power Supply Filtering

ST72XXX
1 to 10μF 0.1μF VSS

ST7
DIGITAL NOISE
FILTERING
VDD
VDD

POWER
SUPPLY
0.1μF VAREF
SOURCE

EXTERNAL
NOISE
FILTERING VSSA

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10-BIT ADC CHARACTERISTICS (Cont’d)

12.12.3 ADC Accuracy

Conditions: VDD=5V 1)
Symbol Parameter Conditions Typ Max2) Unit
1) 3 4
|ET| Total unadjusted error
1) 2 3
|EO| Offset error
1) 0.5 3 LSB
|EG| Gain Error
1) 1 2
|ED| Differential linearity error CPU in run mode @ fADC 2 MHz.
|EL| Integral linearity error 1) CPU in run mode @ fADC 2 MHz. 1 2
Notes:
1. ADC Accuracy vs. Negative Injection Current: Injecting negative current may reduce the accuracy of the conversion
being performed on another analog input.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 12.8 does not affect the ADC
accuracy.
2. Data based on characterization results, monitored in production to guarantee 99.73% within ± max value from -40°C
to 125°C (± 3σ distribution limits).

Figure 98. ADC Accuracy Characteristics

Digital Result ADCDR EG

(1) Example of an actual transfer curve
1023
(2) The ideal transfer curve
1022 V –V (3) End point correlation line
AREF SSA
1LSB = --------------------------------------------
1021 IDEAL 1024
(2)
ET=Total Unadjusted Error: maximum deviation
ET between the actual and the ideal transfer curves.
7 (3) EO=Offset Error: deviation between the first actual
(1) transition and the first ideal one.
6
EG=Gain Error: deviation between the last ideal
5 transition and the last actual one.
EO EL ED=Differential Linearity Error: maximum deviation
4 between actual steps and the ideal one.
3 EL=Integral Linearity Error: maximum deviation
ED between any actual transition and the end point
2 correlation line.
1 LSBIDEAL
1
Vin (LSBIDEAL)
0
1 2 3 4 5 6 7 1021 1022 1023 1024
VSSA VAREF

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ST72325xx

13 PACKAGE CHARACTERISTICS

13.1 PACKAGE MECHANICAL DATA

Figure 99. 64-Pin Low Profile Quad Flat Package (14x14)

D A mm inches1)
A2
Dim.
D1 Min Typ Max Min Typ Max
A1 A 1.60 0.0630
A1 0.05 0.15 0.0020 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
b b 0.30 0.37 0.45 0.0118 0.0146 0.0177
c 0.09 0.20 0.0035 0.0079
D 16.00 0.6299
e
D1 14.00 0.5512
E1 E
E 16.00 0.6299
E1 14.00 0.5512
e 0.80 0.0315
θ 0° 3.5° 7° 0° 3.5° 7°
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L
L1 1.00 0.0394
L1
c Number of Pins

h N 64
Note 1. Values in inches are converted from mm
and rounded to 4 decimal digits.

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 ST72325xx

Figure 100. 64-Pin Low Profile Quad Flat Package (10 x10)

mm inches1)
Dim.
D A
Min Typ Max Min Typ Max
D1 A2 A 1.60 0.0630

A1
A1 0.05 0.15 0.0020 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
b c 0.09 0.20 0.0035 0.0079
D 12.00 0.4724
E1 E D1 10.00 0.3937
e
E 12.00 0.4724
E1 10.00 0.3937
e 0.50 0.0197

c
θ 0° 3.5° 7° 0° 3.5° 7°
L1
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
θ
L L1 1.00 0.0394
Number of Pins
N 64
Note 1. Values in inches are converted from mm
and rounded to 4 decimal digits.

Figure 101. 48-Pin Low Profile Quad Flat Package

mm inches1)
Dim.
Min Typ Max Min Typ Max
D A A 1.60 0.0630
D1 A2 A1 0.05 0.15 0.0020 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
A1
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
b C 0.09 0.20 0.0035 0.0079
D 9.00 0.3543
D1 7.00 0.2756
E1 E e
E 9.00 0.3543
E1 7.00 0.2756
e 0.50 0.0197
c θ 0° 3.5° 7° 0° 3.5° 7°
L1
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L
θ L1 1.00 0.0394
Number of Pins
N 48
Note 1. Values in inches are converted from mm and
rounded to 4 decimal digits.

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ST72325xx

Figure 102. 44-Pin Low Profile Quad Flat Package

mm inches1)
Dim.
Min Typ Max Min Typ Max
D A
D1 A2 A 1.60 0.0630

A1 A1 0.05 0.15 0.0020 0.0059

A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
b b 0.30 0.37 0.45 0.0118 0.0146 0.0177
C 0.09 0.20 0.0035 0.0079
e D 12.00 0.4724
E1 E
D1 10.00 0.3937
E 12.00 0.4724
E1 10.00 0.3937

c e 0.80 0.0315
L1
L θ 0° 3.5° 7° 0° 3.5° 7°
h
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 0.0394
Number of Pins
N 44
Note 1. Values in inches are converted from mm
and rounded to 4 decimal digits.

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 ST72325xx

PACKAGE MECHANICAL DATA (Cont’d)

Figure 103. 42-Pin Plastic Dual In-Line Package, Shrink 600-mil Width

mm inches1)
Dim.
Min Typ Max Min Typ Max
E A 5.08 0.2000

A1 0.51 0.0201
A2 A
A2 3.05 3.81 4.57 0.1201 0.1500 0.1799
A1 L c E1 b 0.38 0.46 0.56 0.0150 0.0181 0.0220
b2 b e eA
b2 0.89 1.02 1.14 0.0350 0.0402 0.0449
eB
D
E c 0.23 0.25 0.38 0.0091 0.0098 0.0150
D 36.58 36.83 37.08 1.4402 1.4500 1.4598
0.015
E 15.24 16.00 0.6000 0.6299
GAGE PLANE

E1 12.70 13.72 14.48 0.5000 0.5402 0.5701

e 1.78 0.0701
eA 15.24 0.6000
eC
eB
eB 18.54 0.7299
eC 1.52 0.0598
L 2.54 3.30 3.56 0.1000 0.1299 0.1402
Number of Pins
N 42
Note 1. Values in inches are converted from mm and
rounded to 4 decimal digits.

Figure 104. 32-Pin Plastic Dual In-Line Package, Shrink 400-mil Width

mm inches1)
Dim.
Min Typ Max Min Typ Max
A 3.56 3.76 5.08 0.1402 0.1480 0.2000
E eC
A1 0.51 0.0201

A2 A
A2 3.05 3.56 4.57 0.1201 0.1402 0.1799
b 0.36 0.46 0.58 0.0142 0.0181 0.0228
A1 b1 0.76 1.02 1.40 0.0299 0.0402 0.0551
L
E1
C eA C 0.20 0.25 0.36 0.0079 0.0098 0.0142
b2 b e eB
D
D 27.43 28.45 1.0799 1.1201
E 9.91 10.41 11.05 0.3902 0.4098 0.4350
E1 7.62 8.89 9.40 0.3000 0.3500 0.3701
e 1.78 0.0701
eA 10.16 0.4000
eB 12.70 0.5000
eC 1.40 0.0551
L 2.54 3.05 3.81 0.1000 0.1201 0.1500
Number of Pins
N 32
Note 1. Values in inches are converted from mm and
rounded to 4 decimal digits.

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ST72325xx

PACKAGE MECHANICAL DATA (Cont’d)

Figure
- 105. 32-Pin Low Profile Quad Flat Package

mm inches1)
Dim.
Min Typ Max Min Typ Max
D A A 1.60 0.0630
D1 A2 A1 0.05 0.15 0.0020 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
A1
b 0.30 0.37 0.45 0.0118 0.0146 0.0177
C 0.09 0.20 0.0035 0.0079
e
D 9.00 0.3543

E1 E
D1 7.00 0.2756
b
E 9.00 0.3543
E1 7.00 0.2756
e 0.80 0.0315

L1
c θ 0° 3.5° 7° 0° 3.5° 7°

L L 0.45 0.60 0.75 0.0177 0.0236 0.0295

h L1 1.00 0.0394
Number of Pins
N 32
Note 1. Values in inches are converted from mm
and rounded to 4 decimal digits.

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13.2 THERMAL CHARACTERISTICS

Symbol Ratings Value Unit
Package thermal resistance (junction to ambient)
LQFP64 10x10 50
LQFP48 7x7 80
RthJA LQFP44 10x10 52 °C/W
SDIP42 55
LQFP32 7x7 70
SDIP32 50
PD Power dissipation 1) 500 mW
TJmax Maximum junction temperature 2) 150 °C

Notes:
1. The maximum chip-junction temperature is based on technology characteristics.
2. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA.
The power dissipation of an application can be defined by the user with the formula: PD=PINT+PPORT where PINT is
the chip internal power (IDDxVDD) and PPORT is the port power dissipation depending on the ports used in the applica-
tion.

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13.3 SOLDERING INFORMATION

■ In order to meet environmental requirements, maximum ratings related to soldering conditions
ST offers these devices in ECOPACK® are also marked on the inner box label.
packages. These packages have a lead-free ■ ECOPACK is an ST trademark. ECOPACK®
second level interconnect. The category of specifications are available at www.st.com.
second level interconnect is marked on the
package and on the inner box label, in
compliance with JEDEC Standard JESD97. The

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 ST72325xx

14 ST72325 DEVICE CONFIGURATION AND ORDERING INFORMATION

Each device is available for production in user pro- shipped to customers with a default content, while
grammable versions (FLASH) as well as in factory ROM/FASTROM factory coded parts contain the
coded versions (ROM/FASTROM). code supplied by the customer. This implies that
ST72325 devices are ROM versions. ST72P325 FLASH devices have to be configured by the cus-
devices are Factory Advanced Service Technique tomer using the Option Bytes while the ROM/FAS-
ROM (FASTROM) versions: they are factory-pro- TROM devices are factory-configured.
grammed HDFlash devices. FLASH devices are

14.1 FLASH OPTION BYTES

STATIC OPTION BYTE 0 STATIC OPTION BYTE
7 0 17 0
Reserved

WDG VD OSCTYPE OSCRANGE

PLLOFF
FMP_R

RSTC
PKG0

PKG1
CSS
HALT

SW

1 0 1 0 2 1 0

Default 1 1 1 0 0 1 1 1 1 1 1 0 1 1 1 1

The option bytes allow the hardware configuration 1: CSS disabled

of the microcontroller to be selected. They have no
address in the memory map and can be accessed OPT4:3= VD[1:0] Voltage detection
only in programming mode (for example using a These option bits enable the voltage detection
standard ST7 programming tool). The default con- block (LVD, and AVD) with a selected threshold for
tent of the FLASH is fixed to FFh. To program the the LVD and AVD (EVD+AVD).
FLASH devices directly using ICP, FLASH devices
are shipped to customers with the internal RC Selected Low Voltage Detector VD1 VD0
clock source enabled. In masked ROM devices, LVD and AVD Off 1 1
the option bytes are fixed in hardware by the ROM
Lowest Threshold: (VDD~3V) 1 0
code (see option list).
Med. Threshold (VDD~3.5V) 0 1
OPTION BYTE 0
Highest Threshold (VDD~4V) 0 0
OPT7= WDG HALT Watchdog and HALT mode
This option bit determines if a RESET is generated Caution: If the medium or low thresholds are se-
when entering HALT mode while the Watchdog is lected, the detection may occur outside the speci-
active. fied operating voltage range. Below 3.8V, device
0: No Reset generation when entering Halt mode operation is not guaranteed. For details on the
1: Reset generation when entering Halt mode AVD and LVD threshold levels refer to section
12.3.2 on page 145
OPT6= WDG SW Hardware or software watchdog
This option bit selects the watchdog type. OPT2 = Reserved, must be kept at default value.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT1= PKG0 Package selection bit 0
This option bit is not used.
OPT5 = CSS Clock security system on/off
This option bit enables or disables the clock secu-
rity system function (CSS) which includes the
clock filter and the backup safe oscillator.
0: CSS enabled

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ST72325 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

OPT0= FMP_R Flash memory read-out protection OSCTYPE
Read-out protection, when selected, provides a Clock Source
protection against Program Memory content ex- 1 0
traction and against write access to Flash memo- Resonator Oscillator 0 0
ry.
Erasing the option bytes when the FMP_R option Reserved 0 1
is selected causes the whole user memory to be Internal RC Oscillator 1 0
erased first, and the device can be reprogrammed.
Refer to Section 4.3.1 and the ST7 Flash Pro- External Source 1 1
gramming Reference Manual for more details. current source corresponding to the frequency
0: Read-out protection enabled range of the used resonator. Otherwise, these bits
1: Read-out protection disabled are used to select the normal operating frequency
OPTION BYTE 1 range.
OPT7= PKG1 Package selection bit 1 OSCRANGE
This option bit selects the package. Typ. Freq. Range
2 1 0
Version Selected Package Flash size PKG 1
1~2MHz 0 0 0
R/AR LQFP64 32/48/60K 1
2~4MHz 0 0 1
C LQFP48(C) 32/48/60K 1
4~8MHz 0 1 0
J LQFP44/SDIP42 48/60K 0
8~16MHz 0 1 1
LQFP48(S)/LQFP44/
S/J 16/32K 1
SDIP42
K LQFP32/SDIP32 16/32K 0
OPT0 = PLLOFF PLL activation
This option bit activates the PLL which allows mul-
Note: On the chip, each I/O port has up to 8 pads. tiplication by two of the main input clock frequency.
Pads that are not bonded to external pins are The PLL is guaranteed only with an input frequen-
forced in input pull-up configuration after reset. cy between 2 and 4MHz, for this reason the PLL
The configuration of these pads must be kept at must not be used with the internal RC oscillator.
reset state to avoid added current consumption. 0: PLL x2 enabled
In LQFP48(C) devices (PA0, PA1, PB6, PB7, 1: PLL x2 disabled
PD6, PD7, PE3, PE5, PE6, PE7, PF3, PF5) are in CAUTION: the PLL can be enabled only if the
input floating configuration after reset. Refer to “OSC RANGE” (OPT3:1) bits are configured to “
Note 4 on page 16. 2~4MHz”. Otherwise, the device functionality is
not guaranteed.
OPT6 = RSTC RESET clock cycle selection
This option bit selects the number of CPU cycles
applied during the RESET phase and when exiting
HALT mode. For resonator oscillators, it is advised
to select 4096 due to the long crystal stabilization
time.
0: Reset phase with 4096 CPU cycles
1: Reset phase with 256 CPU cycles

OPT5:4 = OSCTYPE[1:0] Oscillator Type

These option bits select the ST7 main clock
source type.

OPT3:1 = OSCRANGE[2:0] Oscillator range

When the resonator oscillator type is selected,
these option bits select the resonator oscillator

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ST72325 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE

Customer code is made up of the ROM/FAS- Refer to application note AN1635 for information
TROM contents and the list of the selected options on the counter listing returned by ST after code
(if any). The ROM/FASTROM contents are to be has been transferred. The STMicroelectronics
sent on diskette, or by electronic means, with the Sales Organization will be pleased to provide de-
S19 hexadecimal file generated by the develop- tailed information on contractual points.
ment tool. All unused bytes must be set to FFh. Caution: The Readout Protection binary value is
The selected options are communicated to inverted between ROM and FLASH products. The
STMicroelectronics using the correctly completed option byte checksum will differ between ROM and
OPTION LIST appended. FLASH.

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ST72325xx

Figure 106. Ordering information scheme

Example: ST72 F 325 K 6 T 6

Family
ST7 microcontroller family

Memory type
F: Flash
Blank : ROM
P = FASTROM

Sub-family
325

No. of pins
K = 32
J = 44 or 42
S or C = 48
AR = 64 (LQFP64 10x10 package)
R = 64 (LQFP64 14x14 package)

Memory size
4 = 16K
6 = 32K
7 = 48K
9 = 60K

Package
T = LQFP
B = DIP

Temperature range
6 = -40 °C to 85 °C
3 = -40 °C to 125 °C

For a list of available options (e.g. memory size, package) and orderable part numbers or for further information
on any aspect of this device, please contact the ST Sales Office nearest to you.

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 ST72325xx

ST72325 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

ST72325 ROM MICROCONTROLLER OPTION LIST
(Last update: October 2008)
Customer: ........................................................................
Address: ........................................................................
........................................................................
Contact: ........................................................................
Phone No: ........................................................................
Reference/ROM Code:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The ROM code name is assigned by STMicroelectronics.
ROM code must be sent in .S19 format. .Hex extension cannot be processed.
Device Type/Memory Size/Package (check only one option):
------------------------------| --------------------------- | -------------------------- |
ROM device: 32K 16K
------------------------------| --------------------------- | -------------------------- |
LQFP32 7x7: | [] | [] |
SDIP32: | [] | [] |
LQFP48 7x7: | [] | [] |
LQFP44 10x10: | [] | [] |
SDIP42: | [] | [] |
------------------------------| --------------------------- | --------------------------- |
Die form: 32K 16K
------------------------------| ---------------------------- | --------------------------- |
| [] | [] |
Conditioning (check only one option):
------------------------------------------------------------------------ | -----------------------------------------------------
Packaged Product
------------------------------------------------------------------------ Die Product (dice tested at 25°C only)
| -----------------------------------------------------
[ ] Tape & Reel [ ] Tray | [ ] Tape & Reel
| [ ] Inked wafer
| [ ] Sawn wafer on sticky foil
Temp. Range (do not check for die product).
-------------------------------------------
Temp. Range
-------------------------------------------
[ ] -40°C to +85°C
[ ] -40°C to +125°C

Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ " (10 char. max)

Authorized characters are letters, digits, '.', '-', '/' and spaces only.

Clock Source Selection: [ ] Resonator: [ ] 1 to 2 MHz

[ ] 2 to 4 MHz
[ ] 4 to 8 MHz
[ ] 8 to 16 MHz
[ ] Internal RC
[ ] External Clock
PLL: [ ] Disabled [ ] Enabled

CSS: [ ] Disabled [ ] Enabled

LVD Reset: [ ] Disabled [ ] High threshold [ ] Med. threshold [ ] Low threshold

Reset Delay: [ ] 256 Cycles [ ] 4096 Cycles
Watchdog Selection: [ ] Software Activation [ ] Hardware Activation
Watchdog Reset on Halt: [ ] Reset [ ] No Reset
Readout Protection: [ ] Disabled [ ] Enabled

Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Please download the latest version of this option list from:

http://www.st.com/mcu > downloads > ST7 microcontrollers > Option list

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DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

ST72P325 FASTROM MICROCONTROLLER OPTION LIST
(Last update: October 2008)
Customer: ........................................................................
Address: ........................................................................
........................................................................
Contact: ........................................................................
Phone No: ........................................................................
Reference/ROM Code:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The ROM code name is assigned by STMicroelectronics.
ROM code must be sent in .S19 format. .Hex extension cannot be processed.
Device Type/Memory Size/Package (check only one option):
------------------------------| --------------------------- | -------------------------- | --------------------------- | -------------------------- |
FASTROM DEVICE: 60K 48K 32K 16K
------------------------------| --------------------------- | -------------------------- | --------------------------- | -------------------------- |
LQFP32 7x7: | | | [] | [] |
SDIP32: | | | [] | [] |
LQFP48 7x7 (S): | | | [] | [] |
LQFP44 10x10: | [] | [] | [] | [] |
SDIP42: | | | [] | [] |
LQFP64 10x10: | [] | | | |
LQFP64 14x14: | [] | | | |
------------------------------| --------------------------- | --------------------------- | --------------------------- | --------------------------- |
DIE FORM: 60K 48K 32K 32K
------------------------------| ---------------------------- | --------------------------- | ---------------------------- | --------------------------- |
| [] | [] | [] | [] |
Conditioning (check only one option):
------------------------------------------------------------------------ | -----------------------------------------------------
Packaged Product
------------------------------------------------------------------------ Die Product (dice tested at 25°C only)
| -----------------------------------------------------
[ ] Tape & Reel [ ] Tray | [ ] Tape & Reel
| [ ] Inked wafer
| [ ] Sawn wafer on sticky foil
Temp. Range (do not check for die product).
-------------------------------------------
Temp. Range
-------------------------------------------
[ ] 0°C to +70°C
[ ] -10°C to +85°C
[ ] -40°C to +85°C
[ ] -40°C to +105°C
[ ] -40°C to +125°C
Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ " (10 char. max)
Authorized characters are letters, digits, '.', '-', '/' and spaces only.

Clock Source Selection: [ ] Resonator: [ ] 1 to 2 MHz

[ ] 2 to 4 MHz
[ ] 4 to 8 MHz
[ ] 8 to 16 MHz
[ ] Internal RC
[ ] External Clock
PLL: [ ] Disabled [ ] Enabled

CSS: [ ] Disabled [ ] Enabled

LVD Reset: [ ] Disabled [ ] High threshold [ ] Med. threshold [ ] Low threshold

Reset Delay: [ ] 256 Cycles [ ] 4096 Cycles
Watchdog Selection: [ ] Software Activation [ ] Hardware Activation
Watchdog Reset on Halt: [ ] Reset [ ] No Reset
Readout Protection: [ ] Disabled [ ] Enabled

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14.3 DEVELOPMENT TOOLS

Development tools for the ST7 microcontrollers in- high-level language debugger, editor, project man-
clude a complete range of hardware systems and ager and integrated programming interface.
software tools from STMicroelectronics and third- 14.3.3 Programming tools
party tool suppliers. The range of tools includes
solutions to help you evaluate microcontroller pe- During the development cycle, the ST7-EMU3 se-
ripherals, develop and debug your application, and ries emulators and the RLink provide in-circuit
program your microcontrollers. programming capability for programming the Flash
microcontroller on your application board.
14.3.1 Starter kits
ST also provides a low-cost dedicated in-circuit
ST offers complete, affordable starter kits. Starter programmer, the ST7-STICK, as well as ST7
kits are complete, affordable hardware/software Socket Boards which provide all the sockets re-
tool packages that include features and samples quired for programming any of the devices in a
to help you quickly start developing your applica- specific ST7 sub-family on a platform that can be
tion. used with any tool with in-circuit programming ca-
14.3.2 Development and debugging tools pability for ST7.
Application development for ST7 is supported by For production programming of ST7 devices, ST’s
fully optimizing C Compilers and the ST7 Assem- third-party tool partners also provide a complete
bler-Linker toolchain, which are all seamlessly in- range of gang and automated programming solu-
tegrated in the ST7 integrated development envi- tions, which are ready to integrate into your pro-
ronments in order to facilitate the debugging and duction environment.
fine-tuning of your application. The Cosmic C Evaluation boards
Compiler is available in a free version that outputs
up to 16KBytes of code. Three different Evaluation boards are available:
■ ST7232x-EVAL ST72F321/324/521 evaluation
The range of hardware tools includes full-featured
ST7-EMU3 series emulators and the low-cost board, with ICC connector for programming
RLink in-circuit debugger/programmer. These capability. Provides direct connection to ST7-
tools are supported by the ST7 Toolset from DVP3 emulator. Supplied with daughter boards
STMicroelectronics, which includes the STVD7 in- (core module) for ST72F321, ST72324 &
tegrated development environment (IDE) with ST72F521.

Table 30. STMicroelectronics Development Tools

Emulation Programming
Supported ST7 DVP3 Series ST7 EMU3 series
Products Active Probe & ICC Socket Board
Emulator Connection kit Emulator
T.E.B.
ST7MDT20-T6A/ ST7MDT20M-
ST72F325AR ST7MDT20-DVP3 ST7MDT20M-TEB ST7SB20M/xx1
DVP EMU3
ST72325S, ST7MDT20-T48/ ST7MDT20J-
ST7MDT20-DVP3 ST7MDT20J-TEB ST7SB20J/xx1
ST72F325S DVP EMU3
ST72325J, ST7MDT20-T32/ ST7MDT20J-
ST7MDT20-DVP3 ST7MDT20J-TEB ST7SB20J/xx1
ST72F325J DVP EMU3
ST72325K, ST7MDT20-T44/ ST7MDT20J-
ST7MDT20-DVP3 ST7MDT20J-TEB ST7SB20J/xx1
ST72F325K DVP EMU3

Note 1: Add suffix /EU, /UK, /US for the power supply of your region.

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DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

Table 31. Suggested List of Socket Types
Device Socket Emulator Adapter
LQFP64 14 x14 CAB 3303262 CAB 3303351
LQFP64 10 x10 YAMAICHI IC149-064-*75-*5 YAMAICHI ICP-064-6
LQFP48 7 X7 CAB 3303238 CAB 3303333
LQFP44 10 X10 YAMAICHI IC149-044-*52-*5 YAMAICHI ICP-044-5
LQFP32 7 X 7 IRONWOOD SF-QFE32SA-L-01 IRONWOOD SK-UGA06/32A-01

14.3.4 Socket and Emulator Adapter Related Documentation

Information AN 978: ST7 Visual Develop Software Key Debug-
For information on the type of socket that is sup- ging Features
plied with the emulator, refer to the suggested list AN 1938: ST7 Visual Develop for ST7 Cosmic C
of sockets in Table 31. toolset users
Note: Before designing the board layout, it is rec- AN 1940: ST7 Visual Develop for ST7 Assembler
ommended to check the overall dimensions of the Linker toolset users
socket as they may be greater than the dimen-
sions of the device.
For footprint and other mechanical information
about these sockets and adapters, refer to the
manufacturer’s datasheet.

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 ST72325xx

14.4 ST7 APPLICATION NOTES

Table 32. ST7 Application Notes
IDENTIFICATION DESCRIPTION
APPLICATION EXAMPLES
AN1658 SERIAL NUMBERING IMPLEMENTATION
AN1720 MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS
AN1755 A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555
AN1756 CHOOSING A DALI IMPLEMENTATION STRATEGY WITH ST7DALI
A HIGH PRECISION, LOW COST, SINGLE SUPPLY ADC FOR POSITIVE AND NEGATIVE IN-
AN1812
PUT VOLTAGES
EXAMPLE DRIVERS
AN 969 SCI COMMUNICATION BETWEEN ST7 AND PC
AN 970 SPI COMMUNICATION BETWEEN ST7 AND EEPROM
AN 971 I²C COMMUNICATION BETWEEN ST7 AND M24CXX EEPROM
AN 972 ST7 SOFTWARE SPI MASTER COMMUNICATION
AN 973 SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
AN 974 REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE
AN 976 DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION
AN 979 DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
AN 980 ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
AN1017 USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER
AN1041 USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOÏD)
AN1042 ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT
AN1044 MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
AN1045 ST7 S/W IMPLEMENTATION OF I²C BUS MASTER
AN1046 UART EMULATION SOFTWARE
AN1047 MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS
AN1048 ST7 SOFTWARE LCD DRIVER
AN1078 PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE
AN1082 DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERALS REGISTERS
AN1083 ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE
AN1105 ST7 PCAN PERIPHERAL DRIVER
AN1129 PWM MANAGEMENT FOR BLDC MOTOR DRIVES USING THE ST72141
AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS
AN1130
WITH THE ST72141
AN1148 USING THE ST7263 FOR DESIGNING A USB MOUSE
AN1149 HANDLING SUSPEND MODE ON A USB MOUSE
AN1180 USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD
AN1276 BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER
AN1321 USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE
AN1325 USING THE ST7 USB LOW-SPEED FIRMWARE V4.X
AN1445 EMULATED 16-BIT SLAVE SPI
AN1475 DEVELOPING AN ST7265X MASS STORAGE APPLICATION
AN1504 STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER
AN1602 16-BIT TIMING OPERATIONS USING ST7262 OR ST7263B ST7 USB MCUS
AN1633 DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION IN ST7 NON-USB APPLICATIONS
AN1712 GENERATING A HIGH RESOLUTION SINEWAVE USING ST7 PWMART
AN1713 SMBUS SLAVE DRIVER FOR ST7 I2C PERIPHERALS
AN1753 SOFTWARE UART USING 12-BIT ART

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Table 32. ST7 Application Notes

IDENTIFICATION DESCRIPTION
AN1947 ST7MC PMAC SINE WAVE MOTOR CONTROL SOFTWARE LIBRARY
GENERAL PURPOSE
AN1476 LOW COST POWER SUPPLY FOR HOME APPLIANCES
AN1526 ST7FLITE0 QUICK REFERENCE NOTE
AN1709 EMC DESIGN FOR ST MICROCONTROLLERS
AN1752 ST72324 QUICK REFERENCE NOTE
PRODUCT EVALUATION
AN 910 PERFORMANCE BENCHMARKING
AN 990 ST7 BENEFITS VS INDUSTRY STANDARD
AN1077 OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS
AN1086 U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING
AN1103 IMPROVED B-EMF DETECTION FOR LOW SPEED, LOW VOLTAGE WITH ST72141
AN1150 BENCHMARK ST72 VS PC16
AN1151 PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876
AN1278 LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS
PRODUCT MIGRATION
AN1131 MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324
AN1322 MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B
AN1365 GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264
AN1604 HOW TO USE ST7MDT1-TRAIN WITH ST72F264
AN2200 GUIDELINES FOR MIGRATING ST7LITE1X APPLICATIONS TO ST7FLITE1XB
PRODUCT OPTIMIZATION
AN 982 USING ST7 WITH CERAMIC RESONATOR
AN1014 HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
AN1015 SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE
AN1040 MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES
AN1070 ST7 CHECKSUM SELF-CHECKING CAPABILITY
AN1181 ELECTROSTATIC DISCHARGE SENSITIVE MEASUREMENT
AN1324 CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS
AN1502 EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
AN1529 EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY
ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILLA-
AN1530
TOR
AN1605 USING AN ACTIVE RC TO WAKEUP THE ST7LITE0 FROM POWER SAVING MODE
AN1636 UNDERSTANDING AND MINIMIZING ADC CONVERSION ERRORS
AN1828 PIR (PASSIVE INFRARED) DETECTOR USING THE ST7FLITE05/09/SUPERLITE
AN1946 SENSORLESS BLDC MOTOR CONTROL AND BEMF SAMPLING METHODS WITH ST7MC
AN1953 PFC FOR ST7MC STARTER KIT
AN1971 ST7LITE0 MICROCONTROLLED BALLAST
PROGRAMMING AND TOOLS
AN 978 ST7 VISUAL DEVELOP SOFTWARE KEY DEBUGGING FEATURES
AN 983 KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE
AN 985 EXECUTING CODE IN ST7 RAM
AN 986 USING THE INDIRECT ADDRESSING MODE WITH ST7
AN 987 ST7 SERIAL TEST CONTROLLER PROGRAMMING
AN 988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN
AN1039 ST7 MATH UTILITY ROUTINES

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 ST72325xx

Table 32. ST7 Application Notes

IDENTIFICATION DESCRIPTION
AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER
AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO-
AN1179
GRAMMING)
AN1446 USING THE ST72521 EMULATOR TO DEBUG AN ST72324 TARGET APPLICATION
AN1477 EMULATED DATA EEPROM WITH XFLASH MEMORY
AN1527 DEVELOPING A USB SMARTCARD READER WITH ST7SCR
AN1575 ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
AN1576 IN-APPLICATION PROGRAMMING (IAP) DRIVERS FOR ST7 HDFLASH OR XFLASH MCUS
AN1577 DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION FOR ST7 USB APPLICATIONS
AN1601 SOFTWARE IMPLEMENTATION FOR ST7DALI-EVAL
AN1603 USING THE ST7 USB DEVICE FIRMWARE UPGRADE DEVELOPMENT KIT (DFU-DK)
AN1635 ST7 CUSTOMER ROM CODE RELEASE INFORMATION
AN1754 DATA LOGGING PROGRAM FOR TESTING ST7 APPLICATIONS VIA ICC
AN1796 FIELD UPDATES FOR FLASH BASED ST7 APPLICATIONS USING A PC COMM PORT
AN1900 HARDWARE IMPLEMENTATION FOR ST7DALI-EVAL
AN1904 ST7MC THREE-PHASE AC INDUCTION MOTOR CONTROL SOFTWARE LIBRARY
AN1905 ST7MC THREE-PHASE BLDC MOTOR CONTROL SOFTWARE LIBRARY
SYSTEM OPTIMIZATION
AN1711 SOFTWARE TECHNIQUES FOR COMPENSATING ST7 ADC ERRORS
AN1827 IMPLEMENTATION OF SIGMA-DELTA ADC WITH ST7FLITE05/09
AN2009 PWM MANAGEMENT FOR 3-PHASE BLDC MOTOR DRIVES USING THE ST7FMC
AN2030 BACK EMF DETECTION DURING PWM ON TIME BY ST7MC

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 ST72325xx

15 KNOWN LIMITATIONS

15.1 ALL DEVICES the semaphore. If it is '1' this means that the last
interrupt was missed and the interrupt routine is in-
15.1.1 Unexpected Reset Fetch voked with the call instruction.
If an interrupt request occurs while a “POP CC” in- To implement the workaround, the following soft-
struction is executed, the interrupt controller does ware sequence is to be followed for writing into the
not recognise the source of the interrupt and, by PxOR/PxDDR registers. The example is for for
default, passes the RESET vector address to the Port PF1 with falling edge interrupt sensitivity. The
CPU. software sequence is given for both cases (global
Workaround interrupt disabled/enabled).
To solve this issue, a “POP CC” instruction must Case 1: Writing to PxOR or PxDDR with Global In-
always be preceded by a “SIM” instruction. terrupts Enabled:
15.1.2 External interrupt missed LD A,#01
To avoid any risk if generating a parasitic interrupt, LD sema,A ; set the semaphore to '1'
the edge detector is automatically disabled for one LD A,PFDR
clock cycle during an access to either DDR and
OR. Any input signal edge during this period will AND A,#02
not be detected and will not generate an interrupt. LD X,A ; store the level before writing to
This case can typically occur if the application re- PxOR/PxDDR
freshes the port configuration registers at intervals LD A,#$90
during runtime. LD PFDDR,A ; Write to PFDDR
Workaround LD A,#$ff
The workaround is based on software checking LD PFOR,A ; Write to PFOR
the level on the interrupt pin before and after writ-
ing to the PxOR or PxDDR registers. If there is a LD A,PFDR
level change (depending on the sensitivity pro- AND A,#02
grammed for this pin) the interrupt routine is in-
voked using the call instruction with three extra LD Y,A ; store the level after writing to
PUSH instructions before executing the interrupt PxOR/PxDDR
routine (this is to make the call compatible with the LD A,X ; check for falling edge
IRET instruction at the end of the interrupt service cp A,#02
routine).
jrne OUT
But detection of the level change does not make
sure that edge occurs during the critical 1 cycle du- TNZ Y
ration and the interrupt has been missed. This may jrne OUT
lead to occurrence of same interrupt twice (one LD A,sema ; check the semaphore status if
hardware and another with software call). edge is detected
To avoid this, a semaphore is set to '1' before CP A,#01
checking the level change. The semaphore is
changed to level '0' inside the interrupt routine. jrne OUT
When a level change is detected, the semaphore call call_routine; call the interrupt routine
status is checked and if it is '1' this means that the
OUT:LD A,#00
last interrupt has been missed. In this case, the in-
terrupt routine is invoked with the call instruction. LD sema,A
.call_routine ; entry to call_routine
There is another possible case i.e. if writing to PUSH A
PxOR or PxDDR is done with global interrupts dis- PUSH X
abled (interrupt mask bit set). In this case, the
semaphore is changed to '1' when the level PUSH CC
change is detected. Detecting a missed interrupt is .ext1_rt ; entry to interrupt routine
done after the global interrupts are enabled (inter- LD A,#00
rupt mask bit reset) and by checking the status of

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 ST72325xx

LD sema,A
IRET 15.1.3 Clearing active interrupts outside
Case 2: Writing to PxOR or PxDDR with Global In- interrupt routine
terrupts Disabled: When an active interrupt request occurs at the
SIM ; set the interrupt mask same time as the related flag is being cleared, an
unwanted reset may occur.
LD A,PFDR
Note: clearing the related interrupt mask will not
AND A,#$02 generate an unwanted reset
LD X,A ; store the level before writing to Concurrent interrupt context
PxOR/PxDDR
The symptom does not occur when the interrupts
LD A,#$90 are handled normally, i.e.
LD PFDDR,A; Write into PFDDR when:
LD A,#$ff – The interrupt flag is cleared within its own inter-
LD PFOR,A ; Write to PFOR rupt routine
LD A,PFDR – The interrupt flag is cleared within any interrupt
AND A,#$02 routine
LD Y,A ; store the level after writing to PxOR/ – The interrupt flag is cleared in any part of the
PxDDR code while this interrupt is disabled
LD A,X ; check for falling edge If these conditions are not met, the symptom can
be avoided by implementing the following se-
cp A,#$02 quence:
jrne OUT Perform SIM and RIM operation before and after
TNZ Y resetting an active interrupt request.
jrne OUT Example:
LD A,#$01 SIM
LD sema,A ; set the semaphore to '1' if edge is reset interrupt flag
detected RIM
RIM ; reset the interrupt mask Nested interrupt context:
LD A,sema ; check the semaphore status The symptom does not occur when the interrupts
CP A,#$01 are handled normally, i.e.
jrne OUT when:
call call_routine; call the interrupt routine – The interrupt flag is cleared within its own inter-
RIM rupt routine
OUT: RIM – The interrupt flag is cleared within any interrupt
routine with higher or identical priority level
JP while_loop
– The interrupt flag is cleared in any part of the
.call_routine ; entry to call_routine code while this interrupt is disabled
PUSH A If these conditions are not met, the symptom can
PUSH X be avoided by implementing the following se-
PUSH CC quence:
.ext1_rt ; entry to interrupt routine PUSH CC
LD A,#$00 SIM
LD sema,A reset interrupt flag
IRET POP CC

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 ST72325xx

KNOWN LIMITATIONS (Cont’d)

15.1.4 SCI Wrong Break duration during a period, depending on the OLVL1 and
Description OLVL2 settings.
A single break character is sent by setting and re- 15.1.6 TIMD set simultaneously with OC
setting the SBK bit in the SCICR2 register. In interrupt
some cases, the break character may have a long- If the 16-bit timer is disabled at the same time the
er duration than expected: output compare event occurs then output compare
- 20 bits instead of 10 bits if M=0 flag gets locked and cannot be cleared before the
timer is enabled again.
- 22 bits instead of 11 bits if M=1.
Impact on the application
In the same way, as long as the SBK bit is set,
break characters are sent to the TDO pin. This If output compare interrupt is enabled, then the
may lead to generate one break more than expect- output compare flag cannot be cleared in the timer
ed. interrupt routine. Consequently the interrupt serv-
ice routine is called repeatedly.
Occurrence
Workaround
The occurrence of the problem is random and pro-
portional to the baudrate. With a transmit frequen- Disable the timer interrupt before disabling the tim-
cy of 19200 baud (fCPU=8MHz and SCI- er. Again while enabling, first enable the timer then
BRR=0xC9), the wrong break duration occurrence the timer interrupts.
is around 1%. Perform the following to disable the timer:
Workaround TACR1 or TBCR1 = 0x00h; // Disable the com-
If this wrong duration is not compliant with the pare interrupt
communication protocol in the application, soft- TACSR | or TBCSR | = 0x40; // Disable the timer
ware can request that an Idle line be generated Perform the following to enable the timer again:
before the break character. In this case, the break
duration is always correct assuming the applica- TACSR & or TBCSR &= ~0x40; // Enable the tim-
tion is not doing anything between the idle and the er
break. This can be ensured by temporarily disa- TACR1 or TBCR1 = 0x40; // Enable the compare
bling interrupts. interrupt
The exact sequence is: 15.1.7 I2C Multimaster
- Disable interrupts In multimaster configurations, if the ST7 I2C re-
- Reset and Set TE (IDLE request) ceives a START condition from another I2C mas-
ter after the START bit is set in the I2CCR register
- Set and Reset SBK (Break Request) and before the START condition is generated by
- Re-enable interrupts the ST7 I2C, it may ignore the START condition
15.1.5 16-bit Timer PWM Mode from the other I2C master. In this case, the ST7
master will receive a NACK from the other device.
In PWM mode, the first PWM pulse is missed after On reception of the NACK, ST7 can send a re-start
writing the value FFFCh in the OC1R register and Slave address to re-initiate communication
(OC1HR, OC1LR). It leads to either full or no PWM

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 ST72325xx

KNOWN LIMITATIONS (Cont’d)

15.1.8 Pull-up always active on PE2 Symbol Max Unit
The I/O port internal pull-up is always active on I/O |ET| 6
port E2. As a result, if PE2 is in output mode low
|EO| 5
level, current consumption in Halt/Active Halt
mode is increased. |EG| 4.5 LSB
15.1.9 ADC accuracy 16/32K Flash devices |ED| 2
The ADC accuracy in 16/32K Flash Devices devi- |EL| 3
ates from table in section 12.12.3 on page 173 as
follows:

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 ST72325xx

16 REVISION HISTORY
Table 33. Revision History
Date Revision Description of Changes
26-Sep-2005 1 Initial release
Modified LQFP48 pinout, added S device ordering information
Modified Note 4 on page 16 for unbonded pins in 48 pin C devices
Added caution about reset vector in unprogrammed Flash devices in Section 6.3.
Removed EMC protective circuitry in Figure 88 on page 163 (device works correctly without
04-Dec-2006 2
these components)
Modified SS min. setup time and added note 4 to section 12.11.1 on page 166
Modifed description PKG1 bit in “FLASH OPTION BYTES” on page 181
Added “TIMD set simultaneously with OC interrupt” on page 194
In Table 2 added note 5 for I/O Port E2 (PE2) output mode “pull-up always activated” and
added note 6 on connection of power and ground pins.
Deleted the sentence in Section 4.3.1 ‘Readout protection is not supported if LVD is enabled
04-Apr-2007 3
Added Package dimensions for LQFP64 14 x14 in Figure 122
Specified EMI data for LQFP64 in Section 12.7.2
Added ‘Pull-up always active on PE2’ in Section 15.1.8
Title of the document changed
Modified Table 1 on page 1
Modified “Starting the Conversion” on page 133
Modified tRET and NRW values in “FLASH Memory” on page 155
Modified “Absolute Maximum Ratings (Electrical Sensitivity)” on page 158
Values in inches rounded to 4 decimal digits (instead of 3) in “PACKAGE MECHANICAL DA-
07-Oct-2008 4 TA” on page 174
Removed reference to “Application with a Crystal or Ceramic Resonator for ROM (LQFP64
or any 48/60K ROM)” on page 151
Modified “PACKAGE CHARACTERISTICS” on page 174 (Section 13.3)
Modified “TIMD set simultaneously with OC interrupt” on page 194
Modified Section 14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUS-
TOMER CODE on page 183 (Figure 106 and option lists)

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 ST72325xx

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