MICROPROCESSOR

LABMANUAL
 MICROPROCESSORANDINTERFACINGLAB
LIST OF
EXPERIMENTSVI,SEM.(E
CE,CSE,IT,BME)

S.NO. NAME OFTHE EXPERIMENT Page No.

1 STUDY ARCHITECTURE OF 8085 & 8086 AND FAMILIARIZATION WITH 3

ITSHARDWARE,COMMANDS&OPERATIONOFMICROPROCESSORKIT.

2 WRITEAPROGRAMUSING8085&VERIFYFOR: 9
A. ADDITIONOFTWO8-BITNUMBERS.
B. ADDITIONOFTWO16-BITNUMBERS.(WITHCARRY)

3 WRITEAPROGRAMUSING8085&VERIFYFOR: 14
A. SUBTRACTIONOFTWO8-BITNUMBERS.(DISPLAYOFBARROW)
B. SUBTRACTIONOFTWO16-BITNUMBERS.(DISPLAYOFBARROW)

4 WRITEAPROGRAMUSING8085&TESTFORTYPICALDATA: 19
A. MULTIPLICATIONOFTWO8-BITNUMBERSBYBITROTATION
METHOD
B. DIVISIONOFTWO8-BITNUMBERSBYREPEATEDSUBTRACTION
METHOD

5 WRITEAPROGRAMUSING8086FORDIVISIONOFADEFINEDDOUBLE WORD 25
BY ANOTHER WORD & VERIFY.

6 WRITEAPROGRAMUSING8085FORFINDINGSQUARE-ROOTOFA NUMBER & 28

VERIFY.

7 WRITEAPROGRAMUSING8086FORCOPYING12BYTESOFDATAFROM 31
SOURCE TO DESTINATION & VERIFY.

8 WRITEAPROGRAMUSING8086FORARRANGINGANARRAYOF NUMBERS IN 34
DESCENDING ORDER & VERIFY.

9 WRITEAPROGRAMTOINTERFACEADC&DACWITH8085& DEMONSTRATE 38
GENERATION OF SQUARE WAVE.

10 WRITEAPROGRAMTOCONTROLTHEOPERATIONOFSTEEPERMOTOR 41
USING 8085 AND 8255 PPI.

11 WRITEAPROGRAMTOCONTROLTHETRAFFICLIGHTSYSTEMUSING 8085 44
AND 8255 PPI.

Page2
Page3
 EXPERIMENTNO.1(A)

AIM:STUDYOF8085-MICROPROCESSORKIT.

APPARATUS:8085microprocessorkit.
.
THEORY:
Intel8085isan8-bitmicroprocessor.Itis40-pinICpackagefabricatedonasingleLSIchip.Ituses a single
+5 V supply. Its clock speed is about 3 MHz. It consists of three main sections: -

1. ALU(Arithmeticandlogicunit):-

TheALUperformsthearithmeticandlogicaloperation,addition,subtraction,logicalAND,OR,EX- OR,
Complement, Increment, Decrement, shift, clear.
2. TimingandControlUnit:-

Itgenerates timingand control signals,which arenecessary for theexecutionofinstruction.

3. Registers:-
Theseare used for temporary storageof dataand instruction. INTEL8085 has following registers: -
i) One 8 bit accumulator
ii) Six 8 bit registers (B, C, D, E, H, L)
iii) One 16 bit stack pointer, SP
iv) One16bitprogramcounter,PC
v) Instruction register
vi) Status register
vii) Temporaryregisters

PCcontainstheaddressofnextinstruction. IR
holds the instruction until it is decoded. SP
holds the address of the stack top.
Accumulatorisused duringexecutionofprogramfortemporarystorageofdata.

Statusflagsareasfollows:-
i) Carry (CS)
ii) Zero (Z)
iii) Sign (S)
iv) Parity(P)
v) AuxiliaryCarry(AC)

PSW
This 8-bit program status word includes status flags and three undefined bits.

Data and Address bus

Databusis8-bitwideand8bitsofdatacanbetransmittedinparallel.Ithas16-bitwide address bus as
the memory addresses are of 16 bits.

Page4
CIRCUIT DIAGRAM(PINDIAGRAM):-

36 12
RST-IN AD0 13
1 AD1 14
X1 AD2 15
AD3 16
2 AD4 17
X2 AD5 18
5 AD6 19
6 SID AD7 21
TRAP A8 22
9 A9 23
8 RST5.5 A10 24
7 RST6.5 A11 25
RST7.5 A12 26
10 A13 27
INTR A14 28
11 A15
INTAS0 30
29 ALE 31
S1 WR 32
33 RDI 34
HOLD O/M 3
39 RST-OT 37
READY CLKO 4
35 SOD 38
HLDA

PINCONFIGURATION
A8-A15 (Output):-
Theseare address bus andused for the mostsignificant bits of memory address.
AD0-AD7(Input/Output):-
Thesearetimemultiplexedaddressdatabus.Theseareusedfortheleastsignificant8bitsof the
memory address during first clock cycle and then for data during second and third clock
cycle
ALE(Address Latch Enable)
Itgoeshighduringthe1stclockcycleofamachine.Itenablesthelower8bitsofaddressto be latched
either in the memory or external latch.
IO/M
Itisstatussignal,whenitgoeshigh;theaddressonaddressbusisforI/Odevice,otherwise for
memory.
So,S1
Thesearestatussignalstodistinguishvarioustypesofoperation
S1 So Operation
0 0 Halt
0 1 Write
1 0 Read
1 1 Fetch
RD (output)
Itisusedtocontrolreadoperation. Itis
WR (output)
used tocontrol write operation

Page5
HOLD(input)
Itisusedtoindicatethatanotherdeviceisrequestingtheuseofaddress&databus.
HLDA(output)
ItisacknowledgementsignalusedtoindicateHOLDrequesthasbeenreceived. When it
INTR
goes high, microprocessor suspends its normal sequence of operations.
(input)INTA
ItisinterruptacknowledgementsignalsentbymicroprocessorafterINTRisreceived.
(output)

RST 5.5,6.5,7.5 and TRAP

These are various interruptsignals. Among themTRAP ishaving highest priority
RESET IN (input)
It resets the PC to zero.
RESET OUT(output)
Itindicates thatCPU isbeing reset.
X1, X2 (input)
Thiscircuitry is requiredtoproduceasuitableclockfortheoperationof
microprocessor. .

Clk
Itisclockoutputforuser.Itsfrequencyissameatwhichprocessoroperates. It is
(output)SID
used for data line for serial input.
(input)SOD(
It is used for data line for serial output.
output)Vcc
+5 volts supply
Vss
Groundreference

Page6
Page7
 EXPERIMENTNO.1(B)

AIM: STUDY OF 8086 MICROPROCESSOR KIT.

APPARATUS:8086microprocessorkit.
.
THEORY:The8086isa16-bit,N-channel,HMOSmicroprocessor.ThetermHMOSisusedfor
high-speedMOS”.The8086uses20addresslinesand16datalines.Itcandirectlyaddressupto2 20=
1Mbytesofmemory.The16-bitdatawordisdividedintoalow-orderbyteandahigh-orderbyte.The 20
address lines are time multiplexed lines. The 16 low-order address lines are time multiplexed with
data, and the 4 high-order address lines are time multiplexed with status signals.

OPERATINGMODESOF8086
There are two modes of operation for Intel 8086, namely the minimum mode and the maximum
mode. When only one 8086 CPU is to be used in a microcomputer system the 8086 is used in the
minimum mode of operation. In this mode the CPU issues the control signals required by memory
and I/O devices. In case of maximum mode of operation control signalsareissuedbyIntel8288bus
controllerwhichisusedwith8086forthisverypurpose.WhenMN/MXishightheCPU operatesin the
minimum mode. When it is low the CPU operates in the maximum mode.

Pin Description For Minimum Mode

FortheminimummodeofoperationthepinMN/MXisconnectedto5Vd.csupply.Thedescription of the
pins from 24 to 31 for the minimum mode is as follows:

INTA(Output):Pinno.24Interruptacknowledge.Onreceivinginterruptsignaltheprocessorissues an
interrupt acknowledge signal. It is active LOW.
ALE(Output):Pinno.25Addresslatchenable.ItgoesHIGHduringT1.Themicroprocessorsends this
signal to latch the address into the Intel 8282/8283 latch.
DEN(Output):Pinno.26Dataenable.WhenIntel8286/8287octalbustransceiverisusedthis signalacts as
an output enable signal. It is active LOW.
DT/R(Output) : Pin no. 27 Data Transmit/Receive. When Intel 8286/8287 octal bus transceiver is
usedthissignalcontrolsthedirectionofdataflowthroughthetransceiver.WhenitisHighdataare sent out.
When it is LOW data are received.
M/IO(Output):Pinno.28.MemoryorI/Oaccess.WhenitisHIGHtheCPUwantstoaccess
memory. When it isLOWthe CPU wantsto access I/O device.
WR(Output):Pinno.29.Write.WhenitisLOWtheCPUperformsmemoryorI/OwriteOperation. HLDA
(Output) : Pin no. 30.HOLD acknowledge. It is issued by the processor when it receives HOLD
signal. It is active HIGH signal. When HOLD request is removed HLDA goes LOW.
HOLD(Output):Pinno.31.Hold.whenanotherdeviceinmicrocomputersystemwantstousethe
addressanddatabus,itsendsaHOLDrequesttoCPUthroughthispin.ItisanactiveHIGHsignal.

Page8
PinDescriptionForMaximumMode
ForthemaximummodeofoperationthepinMN/MXismadeLOW.Itisgrounded.The description of the
pins from 24 to 31 is as follows:
QS1,QS0(Output): Pinno.24,25InstructionQueuestatus.Logicaregivenbelow:
QS1 QS0
0 0 No operation
0 1 1stbyteofopcodefromqueue
1 0 Emptythequeue
1 1 Subsequentbytefromqueue

S0,S1,S2(Output) : Pin nos. 26,27,28.status signals. These signals are connected to the bus
controllerIntel8288.ThebuscontrollergeneratesmemoryandI/Oaccesscontrolsignals.Table for
status signals is :
S2 S1 S0
0 0 0 Interruptacknowledge
0 0 1 Read data fromI/O port
0 1 0 WritedataintoI/O port
0 1 1 Halt
1 0 0 Opcodefetch
1 0 1 Memoryread
1 1 0 Memorywrite
1 1 1 Passive state.

LOCK(Output):Pinno.29.ItisanactiveLOWsignal.WhenitisLOWallinterruptsaremasked and no
HOLD request is granted. In a multiprocessor system all other processors are informed by this
signal that they should not ask the CPU for relinquishing the bus control.

RQ / GT1, RQ / GT0(Bidirectional) : Pin no. 30,31. Local bus Priority control. Other
processorsasktheCPUthroughtheselinestoreleasethelocalbus. RQ/GT1hashigherpriority than RQ
/ GT0

Page9
 U1
16
AD0 15
22 AD1 14
19 READY AD2 13
21 CLK AD3 12
RESET AD4 11
18 AD5 10
INTR AD6 9
AD7 8
AD8 7
AD9 6
AD10 5
AD11 4
AD12 3
AD13 2
AD14 39
AD15 38
A16/S3 37
A17/S4 36
A18/S5 35
A19/S6
34
BHE/S7
26
S0 27
S1 28
31 S2
30 RQ/GT0 32
17 RQ/GT1 RD 29
23 NMI LOCK 25
33 TEST QS0 24
MX QS1
8086
PIN DIAGRAM OF 8086

Page10
 MPLAB(EE‐329‐F)

BLOCK DIAGRAM OF 8086:

REGISTERS OF 8086: The Intel 8086 contains the following registers:

a) GeneralPurposeRegister
b) PointerandIndexRegisters
c) SegmentRegisters
d) InstructionRegisters
e) Status Flags

Page11
 EXPERIMENTNO.2(A)

AIM : WRITE APROGRAM USING 8085 & VERIFY FOR :

(a) ADDITIONOFTWO8-BITNUMBERS.

APPARATUS:8085microprocessorkit,5Vpowersupply,Keyboard.

THEORY (Program)

Memory Machinecode Mnemonics Operands Commands

address
7000 21,01,75 LXI H,7501 Getaddressof1st
no. in HL pair
7003 7E MOV A,M MoveIstno.in
accumulator
7004 23 INX H HL points the
address 7502H
7005 86 ADD M Addthe2ndno.
7006 23 INX H HL points 7503H
7007 77 MOV M,A Storeresultin
7503H.
7008 CF RST 1 Terminate

CIRCUITDIAGRAM/BLOCKDIAGRAM:-

START

GetthefirstNo.

GetthesecondNo.

Add.Twonumbers

Storetheresult

END

Page12
PROCEDURE:-
SCIENTECH
ANSHUMAN Reset
S Exmem
Enter Enter Starting Address
ProgramAddress Next
WriteProgram WriteProgram
Execution Steps Execution Steps

Esc Reset
G GO
Enter-enter Starting Address
Prog. Address Fill
Enter Reset
S Exmem
Enter Result Address
Any key-2
Enter-2
RegisterName

INPUTDATA
7501- 13H
7502- 12H

OUTPUTDATA
7503- 25H
PRECAUTIONS:-

Makesure that allthe machine codes shouldbe as perspecified in the program.

Page13
 EXPERIMENTNO.2(B)

AIM: WRITE APROGRAMUSING 8085 & VERIFY FOR :

(b) ADDITION OF TWO 16-BIT NUMBERS(WITH CARRY).

APPARATUS:8085microprocessorkit,5Vpowersupply,Keyboard.

THEORY (Program)

Memory Label Machine Mnemonics Operands Commands

address code
7000 2A,01,76 LHLD 7601H Get1stno.inHLpairfrom
memory(7601)
7003 EB XCHG Exchange cont. of DE HL
7004 2A,03,76 LHLD 7603H Get2stno.inHLpairfrom
location 7603
7007 0E,00 MVI C,00H Clearreg.C.
7009 19 DAD D GetHL+DE&storeresultin HL

700A D2,12,70 JNC 7012(loop) Ifno carrymovetoloop/ifcarry

thenmove tonext step.
700D 0C INR C IncrementregC
700E 79 MOV A,C Movecarryfromreg.Ctoreg. A

7011 32,02,75 STA 7502 Storecarryat7502H

7012 loop 22,00,75 SHLD 7500 Store result in 7500H.
7015 CF RST1 Terminate

Page14
CIRCUITDIAGRAM/BLOCKDIAGRAM:-

START

GetthefirstNo.inHL

ExchangeDE HL

GetthesecondNo.inHL

Add.Twonumbers

No
Ifcarry

Yes

Incrementreg.C

MoveCtoA

StoreAccumulator

StoreHLresult
PROCEDURE:-
END SCIENTECH
ANSHUMAN Reset
S Exmem
Enter Enter Starting Address
ProgramAddress Next
WriteProgram WriteProgram
Execution Steps Execution Steps
Esc Reset
G GO
Enter-enter Starting Address
Prog. Address Fill
Enter Reset
S Exmem
Enter Result Address
Anykey-2
Enter-2RegisterName
Page15
INPUTDATA
7601 : 13H
7602 : 31H
7603 : 12H
7604 : 10H

OUTPUTDATA
7500:25H
7501:41H
7502:00H

PRECAUTIONS:-
Makesure that allthe machine codes shouldbe as perspecified in the program.

Question&Answer:

Q.lExplainMOVr,M?
Ans:Movethecontentofmemorytoregister.

Q.2 HowmanyT-stateareinMOVinstruction?
Ans: 4 T-state.

Q.3 ExplaintheaddressingmodeofMOVr,M?
Ans: Register indirect.

Q.4 HowmanymachinecyclesareinMOVinstruction?
Ans: 2 machine cycle.

Q.5 WhatisMOVM,r?
Ans:movethecontentofregistertomemory

Q.6 WhichflagisaffectedinMOVinstruction?
Ans: none

Q.7 What isMVIr,data?

Ans:moveimmediatedatatoregister

Q.8 HowmanyT-stateareinMVIinstruction?
Ans: seven T-states.

Q.9 ExplaintheaddressingmodeofMVIr,data?
Ans: immediate

Q.10 HowmanymachinecyclesareinMVIinstruction?
Ans: 3 machine cycles.

Page16
 EXPERIMENTNO.3(A)

AIM : WRITE APROGRAM USING 8085 & VERIFY FOR :

A. SUBTRACTIONOFTWO8-BITNUMBERS.(DISPLAYOFBARROW).

APPARATUS:8085microprocessorkit,5Vpowersupply,Keyboard.

THEORY(Program):

Memory Opcode Mnemonics Operands Comments

address
7000 21,01,75 LXI H,7501 Getaddressofistno.inHLpair
7003 7E MOV A,M MoveIstno.inaccumulator
7004 23 INX H HL points 7502H.
7005 96 SUB M Substract2ndno.fromIstno.
7006 23 INX H HL points 7503 H.
7007 77 MOV M, A Move contents of acc. tomemory
7008 CF RST1 Stop

CIRCUITDIAGRAM /BLOCKDIAGRAM:-

START

GetthefirstNo.

GetthesecondNo.

Subtractsecondnumber from
first number

Storetheresult

END

Page17
PROCEDURE:-
SCIENTECH
ANSHUMAN Reset
S Exmem
Enter Enter Starting Address
ProgramAddress Next
WriteProgram WriteProgram
Execution Steps Execution Steps

Esc Reset
G GO
Enter-enter Starting Address
Prog. Address Fill
Enter Reset
S Exmem
Enter Result Address
Any key-2
Enter-2
RegisterName

INPUTDATA
7501:20H
7502:10H

OUTPUTDATA
7503:10H

PRECAUTIONS:-

Makesure that allthe machine codes shouldbe as perspecified in the program.

Page18
 EXPERIMENTNO.3(B)

AIM :WRITE APROGRAM USING 8085 & VERIFY FOR :

B. SUBTRACTIONOFTWO16-BITNUMBERS.(DISPLAYOFBARROW)

APPARATUS:8085microprocessorkit,5Vpowersupply,Keyboard.

THEORY (Program):
Memory Machine Mnemonics Operands Comments
Address Code
7000 2A, 01,75 LHLD 7501 H Get 1st16bitno.inHLpair
7003 EB XCHG ExchangeHLpairwithDE.
7004 2A,03,75 LHLD 7503H Get2nd16bitno.inHLpair
7007 7B MOV A,E Getlowerbyteofistno.
7008 95 SUB L Subtractlowerbyteof2ndno.
7009 6F MOV L, A Store the result in reg. L
700A 7A MOV A,D GethigherbyteofIstno.

700B 96 SBB H Subtracthigherbyteof 2ndno.

with borrow
700C 67 MOV H,A Move fromacc. To H
700D,E,F 22,05,75 SHLD 7505H Store16bitresultat7505&7506
7010 CF RST 1 Terminate

Page19
CIRCUITDIAGRAM/BLOCKDIAGRAM:-

START

GetthelowerbyteoffirstNo.

GetthelowerbyteofsecondNo.

Sub.lowerbyteofsecondNo.
from lower byte of first No.

GetthehigherbyteoffirstNo.

Getthehigherbyteofsecond

Sub.higherbyteofsecondNo.and
borrow from the pervious sub.

Storetheresult

END
PROCEDURE:-
SCIENTECH
ANSHUMAN Reset
S Exmem
Enter Enter Starting Address
ProgramAddress Next
WriteProgram WriteProgram
Execution Steps Execution Steps

Esc Reset
G GO
Enter-enter Starting Address
Prog. Address Fill
Enter Reset
S Exmem
Enter Result Address
Anykey-2
Page20
Enter -2
Register Name
INPUTDATA
7501: 30H
7502: 40H
7503: 10H
7504: 20H

OUTPUTDATA

7505: 20H
7506: 20H

PRECAUTIONS:-
Makesure that allthe machine codes shouldbe as perspecified in the program.

Question&Answer:
Q.1 Explain LXI rp,data 16 ?
Ans:loadregisterpairimmediate.

Q.2 HowmanyT-stateareinLXIinstruction?
Ans:10T –states.

Q.3 ExplaintheaddressingmodeofLXIrp,data?
Ans: Immediate

Q.4 HowmanymachinecyclesareinLXIinstruction?
Ans:3 machine cycles.

Q.5 What is LDA addr

?Ans:loadaccumulatordirect.

Q.6 HowmanyT-stateareinLDAinstruction?
Ans:13 T –states.

Q.7 ExplaintheaddressingmodeofLDAaddr?
Ans: Direct

Q.8 HowmanymachinecyclesareinLDAinstruction?
Ans: 4

Q.9 WhatisSTAaddr?
Ans:storeaccumulatordirect

Q.10 HowmanyT-stateareinSTAinstruction?
Ans: 13

Page21
 EXPERIMENTNO.4(A)

AIM:WRITEAPROGRAMUSING8085FORMULTIPLICATIONOFTWO8-BITNUMBERS BY
BIT ROTATION METHOD & VERIFY.

APPARATUS:8085microprocessorkit,5Vpowersupply,Keyboard.

THEORY(Program)

Memory Label Machine Mnemonics Operands Comments

Address Code
7000 2A,01,75 LHLD 7501 H GetMultiplicand
in H-L pair.
7003 EB XCHG ExchangeHLpairwith
DEpair
7004 3A,03,75 LDA 7503 H Get2ndno. in acc.
7007 21,00,00 LXI H,0000 Initialproductin
HL=00
700A 0E,08 MVI C,08H Count=08 in reg .C
700C Loop 29 DAD H Shiftpartialproduct
left by 1 bit
700D 17 RAL Rotate multiplication
by1bit.Ismultiplier=
1?
700E D2,12,70 JNC Ahead(7012) No,gotoahead
7011 19 DAD D Product=Product+
Multiplicand
7012 Ahead 0D DCR C DecrementCount
7013 C2,0C,70 JNZ Loop(700C)
7016 22,04,75 SHLD 7504 Store result
7019 CF RST 1 Terminate

Page22
CIRCUITDIAGRAM/BLOCKDIAGRAM:-

START

GetMultiplicand,GetMultiplier

InitialvalueofProduct=00
Count =08

Shift Product left one Bit

ShiftMultiplierleftoneBit

NO IS
Carryfrom
Multiplier?

YES

Product=Product+Multiplicand

Count=Count-1

NO IS
Count=0?

YES
StoreProduct

END

Page23
PROCEDURE:-
SCIENTECH
ANSHUMAN Reset
S Exmem
Enter Enter Starting Address
ProgramAddress Next
WriteProgram WriteProgram
ExecutionSteps Execution Steps

Esc Reset
G GO
Enter-enter Starting Address
Prog. Address Fill
Enter Reset
S Exmem
Enter Result Address
Any key-2
Enter-2
RegisterName

INPUTDATA

7501- 25H
7502- 00H
7503- 05H

OUTPUTDATA

7504- B9H
7505- 00H

PRECAUTIONS:-

Makesure that allthe machine codes shouldbe as perspecified in the program.

Page24
 EXPERIMENTNO.4(B)

AIM:WRITEAPROGRAMUSING8085FORDIVISIONOFTWO8-BITNUMBERSBY REPEATED
SUBTRACTION METHOD & TEST FOR TYPICAL DATA.

APPARATUS: 8085 microprocessor kit,5Vpower supply, Key board.

THEORY(Program):

Memory Label Machine Mnemonics Operands Comments

Address Code
7000 3A,01,75 LDA Divisor(7501)
7003 47 MOV B,A Take divisor in reg,B
7004 3A,02,75 LDA Dividend(7502) Take dividend in reg,A
7007 0E,00 MVI C,00 Quotient=00
7009 B8 CMP B
700A DA,13,70 JC Loop(7013)
700D loop1 90 SUB B Dividend-divisor=>A
700E 0C INR C C=C+1
700F B8 CMP B Isdividend<divisor
7010 D2,0D,70 JNC Loop1(700D) If not,go back
7013 loop 32,03,75 STA Remainder(7503) Store Remainder
7016 79 MOV A,C
7017 32,04,75 STA Quotient(7504) Store Quotient
701A CF RST 1 Terminate.

Page25
CIRCUITDIAGRAM/BLOCKDIAGRAM:-
START

Get8-bitDividendinreg.A,Get 8-
bit Divisor in reg. B

Takequotientinreg.C=00

NO
IS
Dividend>
Divisor?

YES
Quotientisinreg.C
A=Dividend-Divisor

IncrementCounterby1 Reminderisinacc.

END

PROCEDURE:-
SCIENTECH
ANSHUMAN Reset
S Exmem
Enter Enter Starting Address
ProgramAddress Next
WriteProgram WriteProgram
Execution Steps Execution Steps
Esc Reset
G GO
Enter-enter Starting Address
Prog. Address Fill
Enter Reset
S Exmem
Enter Result Address
Any key-2
Enter-2
RegisterName
Page26
INPUTDATA
7501- Divisor
7502-Dividend

OUTPUTDATA
7503-Remainder
7504-Quotient
PRECAUTIONS:-
Makesure that allthe machine codes shouldbe as perspecified in the program.

Question&Answer

Q.1 ExplaintheaddressingmodeofSTAaddr?
Ans: Direct

Q.2 HowmanymachinecyclesareinSTAinstruction?
Ans: 4

Q.3 What is LHLD addr?

Ans:loadH-Lpairdirect.

Q.4 HowmanyT-stateareinLHLDinstruction?
Ans:24 sixteen T –states..

Q.5 ExplaintheaddressingmodeofLHLDaddr?
Ans: Direct

Q.6 HowmanymachinecyclesareinLHLDinstruction?
Ans: 5

Q.7 What is SHLD addr ?

Ans:storeH-Lpairdirect.

Q.8 HowmanyT-stateareinSHLDinstruction?
Ans: 16

Q.9 ExplaintheaddressingmodeofSHLDaddr?
Ans: Direct

Q.10 HowmanymachinecyclesareinSHLDinstruction?
Ans: 5.

Page27
 EXPERIMENTNO.5

AIM:WRITEAPROGRAMUSING8085FORFINDINGSQUARE-ROOTOFANUMBER

APPARATUS:8085microprocessorkit,5Vpowersupply,Keyboard.

THEORY(Program):

Memory Label Machine Mnemonics Operands Comments

Address Code
2000 0E,01 MVI C,01H Place01inreg.C
2002 06,01 MVI B,01H Placeoddnumber1inreg.B
2004 3E,36 MVI A,36 Loadaccumulatorwiththegiven
number
2006 Loop 90 SUB B Subtractoddnumberfromthe
accumulator
2007 CA,10,20 JZ Ahead(2010) Ifaccumulatorcontentsarezero,
gotoAhead
200A 0C INR C Incrementreg.C
200B 04 INR B Incrementoddnumber
200C 04 INR B Incrementoddnumber
200D C3,06,20 JMP Loop(2006) Repeat subtraction
2010 Ahead 79 MOV A,C MovethecontentsofCtoA
2011 32,50,20 STA 2050H Storetheresultinthememory
location 2050H.
2014 CF RST1 Stop

PROCEDURE:-
SCIENTECH
ANSHUMAN Reset
S Exmem
Enter Enter Starting Address
ProgramAddress Next
WriteProgram WriteProgram

Execution Steps Execution Steps

Esc Reset
G GO
Enter-enter Starting Address
Prog. Address Fill
Enter Reset

Page28
S Exmem
Enter Result Address
Anykey-2
Enter
Name
Register

CIRCUITDIAGRAM/BLOCKDIAGRAM:-

START

1. Place01in thesubtractioncounterregister
2. Placeoddnumbers1in anyoneofthe register

Loadtheaccumulatorwiththegiven

Subtractoddnumberfromthecontents of
accumulator

YES
Is
remainder=0
Or negative
NO Storetheresult

Incrementsubtractioncounter
register END

Oddnumber=oddno.+2

INPUTDATA

2500-10H
2501- 00H

OUTPUTDATA

2550- 04H

Page29
PRECAUTIONS:-

Makesure that allthe machine codes shouldbe as perspecified in the program.

Question&Answer;

Q.1 WhatisLDAXrp?
Ans:Loadaccumulatorindirect.

Q.2 HowmanyT-stateareinLDAXinstruction?
Ans:7

Q.3 Explain the addressing mode ofLDAX rp?

Ans: Register indirect .

Q.4 HowmanymachinecyclesareinLDAXinstruction?
Ans: 2

Q.5 WhatisSTAXrp?
Ans:Storeaccumulatorindirect

Q.6 HowmanyT-stateareinSTAXinstruction?
Ans: 7

Q.7 ExplaintheaddressingmodeofSTAXrp?
Ans: Register indirect.

Q.8 HowmanymachinecyclesareinSTAXinstruction?
Ans: 2

Q.9 What isXCHG?

Ans:ExchangethecontentsofH-LpairwithD-Epair

Q.10 HowmanyT-stateareinXCHGinstruction?
Ans: 4

Page30
 EXPERIMENTNO.6

AIM:WRITEAPROGRAMUSING8086FORDIVISIONOFADEFINEDDOUBLEWORD
BYANOTHERWORD & VERIFY.

APPARATUS:8086microprocessorkit,5Vpowersupply,Keyboard.

THEORY(Program)

Memory Machine Mnemonics Operands Comments

Address Code
1000 B8,78,56 MOV AX,5678H Move 5678 to AX
1003 BA,34,12 MOV DX,1234H Move 1234 to DX
1006 B9,25,25 MOV CX,2525 Move2525toCX
1009 F7,F1 DIV CX Divide AX&DX by CX
100b CD,A5 INT A5

CIRCUITDIAGRAM/BLOCKDIAGRAM:-,

START

GetLSBofDividend

GetMSBofDividend

GetDivisorinCX

Divide&Storeresult

END

Page31
PROCEDURE:-
SCIENTECH
ANSHUMAN Reset
S O
Enter Enter EB/AX
SRC-SEGMAddress
Enter Starting Address
ProgramAddress Next
WriteProgram WriteProgram

Execution Steps Execution Steps

Esc Reset
G GO
Enter-enter Starting Address
SRC-SEGMAdd Fill
Enter Reset
Prog. Address O
Enter EB/AX
S
Enter Result Address
Any key-2
Enter-2
RegisterName

INPUTDATA
AX :5678H
DX :1234H
CX: 2525H
OUTPUTDATA
AX: 7D77(Quotient)
DX:0145(Remainder)

PRECAUTIONS:-

Makesure that allthe machine codes shouldbe as perspecified in the program.

Page32
Question&Answer:

Q.lExplaintheaddressingmodeofXCHG? Ans:
Register

Q.2 HowmanymachinecyclesareinXCHGinstruction?
Ans: 1

Q.3 WhatisADDr?
Ans:Addregistertoaccumulator.

Q.4 How many T-state are in ADD instruction?

Ans: 4

Q.5 ExplaintheaddressingmodeofADD?
Ans: Register

Q.6 How many machine cycles are in ADD instruction?

Ans:2

Q.7 WhatisADCr?
Ans:Addregisterwithcarrytoaccumulator.

Q.8 HowmanyT-stateareinADCrinstruction?
Ans: 4

Q.9 ExplaintheaddressingmodeofADC?
Ans: Register

Q.10 HowmanymachinecyclesareinADCinstruction?
Ans: 1

Page33
 EXPERIMENTNO.7

AIM:WRITEAPROGRAMUSING8086FORCOPYING12BYTESOFDATAFROMSOURCE TO
DESTINATION & VERIFY.

APPARATUS:8086microprocessorkit,5Vpowersupply,Keyboard.

THEORY(Program)

Memory Label Machine Mnemonics Operands Comments

Address Code
0101 FC CLD CleardirectionflagDF
0102 BE,00,03 MOV SI,0300 SourceaddressinSI
0105 BF,02,02 MOV DI,0202 DestinationaddressinDI
0108 8B,0C MOV CX,[SI] CountinCX
010A 46 INC SI IncrementSI
010B 46 INC SI IncrementSI
010C BACK A4 MOV SB Move byte
010D E2,FD LOOP BACK JumptoBACKuntilCXbecomes zero

010F CC INT Interrupt program

Page34
CIRCUITDIAGRAM/BLOCKDIAGRAM:-

START

Getsourceaddress

Getdestinationaddress

GetCountinCX

IncrementinSI
IncrementinSI

Movebytes

NO IS
Count=0?

YES

END

INPUTDATA 030B : 0A
0300 : 0B 030C : 0B
0301 : 00 030D :0E
0302 : 03
0303 : 04
0304 : 05 OUTPUTDATA
0305 : 06 0202 : 03
0306 : 15 0203 : 04
0307 : 07 0204 : 05
0308 : 12 0205 : 06
0309 : 08 0206 : 15
030A :09 0207 : 07
Page35
 0208 : 12 020B : 0A
0209 : 08 020C : 0B
020A 09 020D :0E

PRECAUTIONS:-

Makesure that allthe machine codes shouldbe as perspecified in the program.

Question&Answer:

Q.1 ExplainADIdata?
Ans:Addimmediatedatatoaccumulator

Q.2 HowmanyT-statesareinADIinstruction?
Ans: 7

Q.3 Explain the addressing mode of ADI?

Ans: Immediate

Q.4 HowmanymachinecyclesareinADIinstruction?
Ans: 2

Q5ExplainDADrp?
Ans:AddregisterpairtoHLpair.

Q.6 How many T-states are in DAD instruction?

Ans: 10

Q.7 ExplaintheaddressingmodeofDAD.
Ans: Register

Q.8 HowmanymachinecyclesareinDADinstruction?
Ans: 3

Q.9 ExplainDAA.
Ans:Decimaladjustaccumulator

Q.10 WhatisINXrp?
Ans:Incrementregisterpair

Page36
 EXPERIMENTNO.8

AIM:WRITEAPROGRAMUSING8086FORARRANGINGANARRAYOFNUMBERSIN
DESCENDING ORDER & VERIFY.

APPARATUS:8086microprocessorkit,5Vpowersupply,Keyboard.

THEORY(Program)

Memory Label Machine Mnemonics Operands Comments

Address Code
0200 BE,00,03 MOV SI,0300 InitializeSIReg.withMemory
Location. 0300.
0203 8B,1C MOV BX,[SI] BXhasno.ofbytes
0205 4B DEC BX Decrementtheno.ofbytesbyone
0206 (3) 8B 0C MOV CX (SI) Move no. of bytes in CX
0208 49 DEC CX Decrementtheno.ofbytesbyone
0209 BE,02,03 MOV SI,0303 Initialize SIreg.withthestarting
addressofstring
020C (2) 8A,04 MOV AL,[SI] Movefirstdatabyteofstringinto AL

020E 46 INC SI Point atthenext bytes of the string

020F 3A,04 COMP AL,[SI] Com.thetwobytesofstring.
0211 73,06 JAE (1) Iftwobytesareequalor1stbyteis
above that the second byte branch
to (1)
0213 86,04 XCHG AL,[SI] Else
0215 4E DEC SI Secondbyteislessthanfirstbyte and
swap the two bytes.
0216 88,04 MOV [SI],AL
0218 46 INC SI Point at next location of string
0219 (1) E2,F1 LOOP (2) Loop if CX is not zero
021B 4B DEC BX
021C BE,00,03 MOV SI,0300
021F 75,E5 JNZ (3)
0221 F4 HLT Halt.

LABMANUAL(VSEMECE) Page37
CIRCUITDIAGRAM/BLOCKDIAGRAM:-

START

Initializereg.SI(mem.Location)

Setthe counterBX

DecrementthecounterBX

Movecount in CX

DecrementCX

Initializereg.SI(StartingLocation)

Getfirstno.inAL

IncrementSI

IsfirstNo. Yes
<nextNo

No

Swapthetwobytes

No IS
Count=0?

DecrementCount

Comparerestofno.

No IS END
Count=0?
Page38
PROCEDURE:-
SCIENTECH
ANSHUMAN Reset
S Exmem
Enter Enter Starting Address
ProgramAddress Next
WriteProgram WriteProgram
Execution Steps Execution Steps

Esc Reset
G GO
Enter-enter Starting Address
Prog. Address Fill
Enter Reset
S Exmem
Enter Result Address
Any key-2
Enter-2
RegisterName

INPUTDATA
0300 : 05
0301 : 00
0302 : 20
0303 : 25
0304 : 28
0305 : 15
0306 : 07

OUTPUTDATA
0302 : 28
0303 : 25
0304 : 20
0305 : 15
0306 : 07

PRECAUTIONS:-

Makesure that allthe machine codes shouldbe as perspecified in the program.

Page39
Question&Answer:

1. Whatismicroprocessor?
Ans Itisaprogramcontrolledsemiconductordevice(IC),whichfetches,decodesandexecute
instructions.

2. Whatarethe basicunitsof microprocessor?

Ans ThebasicunitsorblocksofmicroprocessorareALU,anarrayofregistersandcontrolunit.

3. Whatisabus?
Ans Busisagroupofconductinglinesthatcarriesdata,addressandcontrolsignals.

4. Whydatabusisbi-directional?
Ans The microprocessor is to fetch (read) the data from memory or input device for processing and
afterprocessingithastostore(write)thedatatomemoryoroutputdevices.Hencethedatabusis bi-
directional.

5. Whydatabusis bi-directional?
Ans Theaddressisanidentificationnumberusedbythemicroprocessortoidentifyoraccessamemory location
or input/output device. It is an output signal from the processor. Hence the address bus is
unidirectional.

6. Definemachinecycle?
AnsMachinecycleisdefinedasthetimerequiredtocompleteoneoperationofaccessingmemory
input/output, or acknowledging an external request. This cycle may consists of three to six T-
states.

7. Define T-state?
Ans T-state is defined as one subdivision of operation performed in one clock period. These
subdivisionsareinternalstatessynchronizedwiththesystemclock,andeachT-stateisprecisely equal
to one clock period.

8. Whatisaninstructioncycle?
Ans The sequence of operations that a processor has to carry out while executing the instruction is
calledinstructioncycle.Eachinstructioncycleofprocessorcontainsanumberofmachinecycles.

9. Whatisfetchandexecute cycle?
Ans Theinstructioncycleisdividedintofetchandexecutecycles.Thefetchcycleisexecutedtofetch the
opcode from memory. The execute cycle is executed to decode the instruction and to perform the
work instructed by the instruction.

10. List the flags of 8085?

Ans Therearefiveflagsin8085.Theyaresignflag,zeroflag,auxiliarycarryflag,parityflagandcarry flag.

Page40
 EXPERIMENTNO.9

AIM:WRITEAPROGRAMTOINTERFACEADC&DACWITH8085&DEMONSTRATE
GENERATION OF SQUARE WAVE.

APPARATUS:8085microprocessorkit,5Vpowersupply,Keyboard.

DESCRIPTION:A D/A converter chip DAC 0800 has been provided on the board of M85-07 to
enable the user to have analog output. This can be used for generating various waveforms or for any
closedloopapplications.ThechiphasbeenusedinI/Omappedmodeandhasanaddressof(A0-A7),
i.e any of A0 to A7 can be used as an address. This chip has been designed to give an output of 0 to 8
Volts. The output of DAC 0800 is coming at Pin No.13 of connector CN11.

THEORY(Program)

Memory Label MachineCode Mnemonics Operands Comments

Address
2000 CD 4DOF CALL LECHO CLEAR LCD DISPLAY
2003 060E MVI B,0EH
2005 21 1F 20 LXI H,WAVE
2008 CD 47 17 CALL PRINTF DISPLAYMESGAE
200B DAC 3E 00 MVI A,00H
200D D3 38 OUT 38H
200F CD 31 0F CALL DELAY1
2012 0614 MVI B,14H
2014 CD 47 17 CALL PRINTF DISPLAYMESSAGE
2017 3EFF MVI A,FFH
2019 D3A0 OUT 0A0H
201B CD 31 0F CALL DELAY1
201E C3 0B 20 JMP DAC LOOP
2021 52 41 4D 50 20 WAVE OUTPUT AT
2026 50 49 4E 20 4E PIN NO. 2 CONN. C9

Page41
CIRCUITDIAGRAM/BLOCKDIAGRAM:-

START

ClearLCD

A00andsent to outport

Delay called

AFFand sent to outport

DealyCalled

PROCEDURE:-
SCIENTECH
ANSHUMAN Reset
S Exmem
Enter Enter Starting Address
ProgramAddress Next
WriteProgram WriteProgram
Execution Steps Execution Steps

Esc Reset
G GO
Enter-enter Starting Address
Prog. Address Fill
Enter Reset
S Exmem
Enter Result Address
Any key-2
Enter-2
RegisterName

RESULT:Waveformobserved on theCROfromPin No. 2of connector 9.

PRECAUTIONS:-

Makesure that allthe machine codes shouldbe as perspecified in the program.

Page42
Question&Answer:

1. What is ALE?
Ans TheALE(Addresslatchenable)isasignalusedtodemultiplextheaddressanddatalinesusingan external
latch. It is used to enable the external latch.

2. Where is the READY signal used?

Ans READYisaninputsignaltotheprocessor,usedbythememoryorinput/outputdevicestoget extra
time for data transfer or to introduce wait states in the bus cycles.

3. Givesomeexamplesofportdevicesusedin8085microprocessorbasedsystem? Ans
The various port devices used in 8085 are 8212,8155,8156,8255,8355,8755.

4. Whatistheneedfortiming diagram?
Ans Thetimingdiagramprovidesinformationregardingthestatusofvarioussignals,whenamachine cycle
is executed. The knowledge of timing diagram is essential for system designer to select matched
peripheral devices like memories, latches, ports etc from a microprocessor system.

5. Whatoperationisperformedduring firstT-stateofeverymachinecyclein8085?
Ans In8085,duringthefirstT-stateofeverymachinecyclethelowbyteaddressislatchedintoan external
latch using ALE signal.

6. Whatisinterruptacknowledgecycle?
Ans Theinterruptacknowledgecycleisamachinecycleexecutedby8085processortogettheaddress of the
interrupt service routine in order to service the interrupt device.

7. Whatisvectoredandnon-vectored interrupt?
Ans When an interrupt is accepted, if the processor control branches to a specific address defined by
themanufacturerthentheinterruptiscalledvectoredinterrupt.InNon-vectoredinterruptthereis no
specific address for storing the interrupt service routine. Hence the interrupted device should
give the address of the interrupt service routine.

8. Listthesoftwareandhardwareinterruptsof8085?
Ans Softwareinterrupts:RST0,RST1,RST2,RST3,RST4,RST5,RST6,RST7
Hardware interrupts : TRAP,RST 7.5,RST 6.5,RST 5.5, INTR.

9. What is TRAP?
Ans TheTRAPisanon-maskableinterruptof8085.Itisnotdisabledbyprocessorresetorafter
recognition of interrupt.

10. Howclocksignalsaregeneratedin8085andwhatisthefrequencyoftheinternalclock?
Ans The8085hastheclockgenerationcircuitonthechipbutanexternalquartzcrystalorLCcircuitor RC circuit
should be connected at the pins X1 andX2. The maximum internal clock frequency of 8085 is
3.03MHz.

Page43
 EXPERIMENTNo.10

AIM:-Tostudythesteppermotorandtoexecutemicroprocessorcomputerbasedcontrolofthesame by
changing number of steps, the direction of rotation and speed.

APPARATUSUSED:-StepperMotorKit,µPKit,InterfaceCordandConnectingLeads.

THEORY:-The stepper motor is a special type of motor which is designed to rotate through a specific
angle called step for each electrical pulse received from its control unit. It is used in digitally controlled
position control system in open loop mode. The input command is in form of a train of pulses to turn the
shaft through a specified angle. the main unit is designed to interface with µP 8085 kit. The stepper motor
controller card remains active while the pulse sequencegenerator disabled as given plug is connected with
µp interface socket . Following programme enables the stepper motor to run with µp 8085 kit. For two
phase four winding stepper motor only four LSB signals are required.

CIRCUITDIAGRAM:-

DIRECTION 12V

PROCEDURE:-
Connect the stepper motor with µp 8085 kit as shown in fig. pressEXMEM key to enter the address
asgiven then press NEXT to enter data .

ADDRESS DATA
2000 3E 80 MVI A,80 Initialize port A as output port.
2002 D303 OUT 03 OB
2004 3E F9 Start MVI AFA
2006 D300 OUT 00 Outputcodeforstepo.
2008 CD3020calldelay delaybetweentwosteps.
200B 3EF5MVIA,F6 LocationreserveforcurrentDelay
200D D3OOOUT OO Outputcodeforstep1.
Page44
200F CD 3020Call delay delaybetweentwosteps.
2012 3EF6MVI A, F5
2014 D3 OOOUTOO Outputcodeforstep2.
2016 CD 3020calls delay between two steps.
2019 3EFA MVIA,F9.
201B D3 OOOUT OO Output code for step 3.
201D CD3020call delay delaybetweentwosteps.
2020 C3 04 20 JMP STARTStart.

Press FILL key to store data in memory area. This will complete the pulse sequence generation. To delay
programme route, first press EXMEM to start, a dot sign will appear in address field then enter the start
address. Press NEXT to enter data.

ADDRESSDATA
2030 110000 LXID 0000 Generatesadelay.
2033 CDBC03 CALL DELAY
2036 11 00 00 LXI D 00 00Generates a delay.
2039 CDBC03 CALL DELAY
203C C9 RET

Press FILL to save data.to execute the programme press the key GO .The above programme is to rotatethe
motor at a particular as defined by the given address. Changing the following contents will change the
motor speed.

ADDRESS DATA
2030 11 00 20AND 2036TO SIMILAR 11 0020
CHANGE 110010 TO 110010
CHANGE 110005 TO 110005
CHANGE 110003 TO 110003.

The motor direction depends upon codes FA, F6 ,F5 AND F9.Change in following codes will change the
motor direction.

ADDRESS DATA
2005 3EF9 TO 3EFA
200C 3EF5 TO 3EF6
2012 3EF6 TO 3EF5
2019 3EFA TO 3EF9.

RESULT:-Thesteppermotorrunsasperfedprogramme.

PRECAUTION:-
1. Maketheconnectionofmotorwithµpkitproperly.
2. Donotchangethemotordirectionathighspeed.
Page45
Question&Answer:

1. Definestack?
Ans Stackis a sequence of RAMmemorylocations defined by the programmer.

2. Whatisprogramcounter?Howitisusefulinprogramexecution?
Ans Theprogramcounterkeepstrackofprogramexecution.Toexecuteaprogramthestartingaddress of the
program is loaded in program counter. The PC sends out an address to fetch a byte of instruction
from memory and increments its content automatically.

3. Defineopcodeandoperand?
Ans Opcode(operationcode)isthepartofaninstructionthatidentifiesaspecificoperation.Operandis a part
of instruction that represents a value on which the instruction acts.

4. Howthe8085processordifferentiatesamemoryaccessandI/Oaccess?
Ans ThememoryaccessandI/OaccessisdifferentiatedusingIO/Msignal.The8085processorasserts IO/M
low for memory operation and high for I/O operations.

5. Whenthe 8085processorchecksfor an interrupt?

Ans InthesecondT-stateofthelastmachinecycleofeveryinstruction,the8085processorchecks whether
an interrupt request is made or not.

6. Whyinterfacingisneededfor I/O devices?

Ans Generally I/O devices are slow devices. Therefore the speed of I/O devices does not match with
thespeedofmicroprocessor.AndsoaninterfaceisprovidedbetweensystembusandI/Odevices.

7. WhatisinterruptI/O?
Ans IftheI/OdeviceinitiatethedatatransferthroughinterruptthentheI/Oiscalledinterruptdriven I/O.

8. Whatisaport?
Ans TheportisabufferedI/O,whichisusedtoholdthedatatransmittedfromthemicroprocessorto I/O
devices and vice versa.

9. Whatis theneed forinterrupt controller?

Ans Theinterruptcontrollerisemployedtoexpandtheinterruptinputs.Itcanhandletheinterrupt request
from various devices and allow one by one to the processor.

10. What is synchronous data transfer scheme?

Ans Forsynchronousdatatransferscheme,theprocessordoesnotcheckthereadinessofthedevice after
commands have been issued for read/write operation. For this scheme the processor will
request the device to get ready and then read/write to the device immediately after the request.

Page46
 EXPERIMENTNO.11

AIM:WRITEAPROGRAMTOCONTROLTHETRAFFICLIGHTSYSTEMUSING8085& 8255 PPI.

APPARATUS:8085microprocessorkit,5Vpowersupply,Keyboard.

DESCRIPTION:ThisProgramcontrolslightofonesquare.Bychangingthedelaybetweentwo signals one

can change the speed of traffic. 8255 Port Address.
PortA-00H
PortB-01H
PortC-02H
ControlWord03H

THEORY(Program)

Memory Label Machine Mnemonics Operands Comments

Address Code
2000 3E80 MVI A,80H InitPA&PBasoutput
2002 D3 03 OUT 03H
2004 3E11 MVI A,11H Stopallfourends
2006 D3 00 OUT 00H
2008 D3 02 OUT 02H
200A CD 50 20 CALL DELAY1
200D LOOP 3E44 MVI A,44H GOSTRsignalofNorth&South, STOP
signal of East &West
200F OUT 00H
2011 CALL DELAY1
2014 MVI A,22H Alertsignalfortraffic
2016 OUT 00H
2018 CALL DELAY2
201B MVI A,99H GO LEFT signal of North & South
201D OUT 00H
201F CALL DELAY1
2022 MVI A,22H Alertsignalfortraffic
2024 OUT 00H
2026 CALL DELAY2
2029 MVI A,11H STOPsignalofNorth&South
202B OUT 00H
202D MVI A,44H GOSTRsignalofEast&West
202F OUT 02H
2031 CALL DELAY1
2034 MVI A,22H Alertsignalfortraffic

Page47
 2036 OUT 02H
2038 CALL DELAY2

Memory Label MachineCode Mnemonics Operands Comments

Address
203B MVI A,99H GOLeftsignalofEast& West

203D OUT 02H

203F CALL DELAY1
2042 MVI A,22H Alertsignalfortraffic
2044 OUT 02H
2046 CALL DELAY2
2049 MVI A,11H STOP signal of East &West
204B OUT 02H
204D JMP LOOP Jumptoloop
2050 DELAY1: MVI B,25H Delayof10sec.
2052 LP3: MVI C,0FFH
2054 LP2: MVI D,0FFH
2056 LP1: DCR D
2057 JNZ LP1
205A DCR C
205B JNZ LP2
205E DCR B
205F JNZ LP3
2062 RET
2063 DELAY2: MVI B,05H Delayof2sec
2065 LP6: MVI C,0FFH
2067 LP5: MVI D,0FFH
2069 LP4: DCR D
206A JNZ LP4
206D DCR C
206E JNZ LP5
2071 DCR B
2072 JNZ LP6
2075 RET

PROCEDURE:-
SCIENTECH
ANSHUMAN Reset
S Exmem
Enter Enter Starting Address
ProgramAddress Next
WriteProgram WriteProgram

Page48
 Execution Steps Execution Steps

Esc Reset
G GO
Enter-enter Starting Address
Prog. Address Fill
Enter Reset
S Exmem
Enter Result Address
Any key-2
Enter-2
RegisterName

RESULT:TrafficSignalTimingobservedforfourlane.

PRECAUTIONS:-

Makesure that allthe machine codes shouldbe as perspecified in the program.

Question&Answer:

1. Whatisasynchronousdatatransferscheme?
Ans In asynchronous data transfer scheme, first the processor sends a request to the device for
read/writeoperation.Thentheprocessorkeepsonpollingthestatusofthedevice.Oncethedevice is ready,
the processor executes a data transfer instruction to complete the process.

2. Whataretheinternaldevicesof8255?
Ans Theinternaldevicesof8255areport-A,port-B,port-C.Theportscanbeprogrammedforeither input or
output function in different operating modes.

3. WhatisUSART?
Ans The device which can be programmed to perform Synchronous or Asynchronous serial
communicationiscalledUSART(UniversalSynchronousAsynchronousReceiverTransmitter). Eg:
INTEL 8251

4. What is scanning in keyboard and what is scan time?

AnsTheprocessofsendingazerotoeachrowofakeyboardmatrixandreadingthecolumnsforkey
actuationiscalledscanning.Thescantimeisthetimetakenbytheprocessortoscanalltherows one by
one starting from first row and coming back to the first row again.

5. Whatisprogrammableperipheraldevice?
Ans If the function performed by the peripheral device can be altered or changed by a program
instruction then the peripheral device is called programmable device. It have control register. The
devicecanbeprogrammedbysendingcontrolwordintheprescribedformattothecontrolregister.

6. Whatisbaudrate?
Page49
Ans Thebaudrateistherateatwhichtheserialdataaretransmitted.Baudrateisdefinedas(Thetime for a bit
cell). In some systems one bit cell has one data bit, then the baud rate and bits/sec are same.

7. Whatare the tasks involved in keyboard interface?

Ans The tasks involved in keyboard interfacing are sensing a key actuation, Debouncing the key and
generating key codes ( Decoding the key). These tasks are performed software if the keyboard is
interfacedthroughportsandtheyareperformedbyhardwareifthekeyboardisinterfacesthrough 8279.

8. Howakeyboardmatrixisformedinkeyboardinterfaceusing8279?
Ans Thereturnlines,RL0toRL7of8279areusedtoformthecolumnsofkeyboardmatrix.Indecoded scan lines
SL0 t0SL3 of 8279 are used to form the rows of keyboard matrix. In encoded scan mode, the
output lines of external decoder are used as rows of keyboard matrix.

9. WhatisGPIB?
Ans GPIBistheGeneralPurposeinterfaceBus.Itisusedtointerfacethetestinstrumentstothesystem
controller.

10. Advantagesofdifferentialdatatransfer?
Ans 1.Communication at high datarateinrealworldenvironment.
2. Differentialdatatransmissionofferssuperiorperformance.
3. Differential signals can help induced noise signals.

Page50