CEA - Computer Engineering

COMPORGA – COMPUTER ORGANIZATION AND ARCHITECTURE

MODULE 3: INSTRUCTION SET

ARCHITECTURE
TOPIC: Learning Objective
In this module, we consider the basic principles involved
● To define instruction set
in instruction set architecture and design. The main goal
of this module is to discuss the (main) memory unit from ● To understand memory
the programmer’s point of view. In particular, we focus
locations and memory
on the way information is stored in and retrieved out of
addressing modes
the memory.

Resources Needed
MODULE STRUCTURE: ● Access to the Internet

I. Instruction Set Architecture ● Computer or mobile

II. Memory Locations and Operations device
III. Addressing Mode
IV. ISA Design
a. CISC
b. RISC
V. ISA Metrics

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COMPORGA – COMPUTER ORGANIZATION AND ARCHITECTURE

I. INSTRUCTION SET ARCHITECTURE

Instruction Set - A part of the processor that is visible to the programmer or compiler writer. It
serves as the boundary between software and hardware

The instruction set provides commands to the processor, to tell it what it

needs to do.

The instruction set consists of addressing modes, instructions, native data

types, registers, memory architecture, interrupt, exception handling, and
external I/O.

The ISA of a processor can be described using 5 categories:

• Operand Storage in the CPU

Where are the operands kept other than in memory?
• Number of explicit named operands
How many operands are named in a typical instruction.
• Operand location
Can any ALU instruction operand be located in memory? Or must all
operands be kept internally in the CPU?
• Operations
What operations are provided in the ISA.
• Type and size of operands
What is the type and size of each operand and how is it specified?

Components of ISA
• Storage Cell – Registers, memory, etc.
• Machine Instruction - Set of possible operations
• Instruction Format – Size and meaning of fields within the instruction set

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COMPORGA – COMPUTER ORGANIZATION AND ARCHITECTURE

II. MEMORY LOCATIONS AND OPERATIONS

The (main) memory can be modeled as an array of millions of adjacent cells, each
capable of storing a binary digit (bit), having value of 1 or 0. These cells are
organized in the form of groups of fixed number, say n, of cells that can be dealt
with as an atomic entity. An entity consisting of 8 bits is called a byte. In many
systems, the entity consisting of n bits that can be stored and retrieved in and out of
the memory using one basic memory operation is called a word (the smallest
addressable entity). Typical size of a word ranges from 16 to 64 bits. It is, however,
customary to express the size of the memory in terms of bytes. For example, the size
of a typical memory of a personal computer is 256 Mbytes, that is, 256 x 2 20 = 228
bytes.

In order to be able to move a word in and out of the memory, a distinct address has
to be assigned to each word. This address will be used to determine the location in
the memory in which a given word is to be stored. This is called a memory write
operation. Similarly, the address will be used to determine the memory location from
which a word is to be retrieved from the memory. This is called a memory read
operation. The number of bits, l, needed to distinctly address M words in a memory is
given by l = log2 M. For example, if the size of the memory is 64 M (read as 64
megawords), then the number of bits in the address is log2 (64 x 2 20) = log2 (226) =26
bits. Alternatively, if the number of bits in the address is l, then the maximum memory
size (in terms of the number of words that can be addressed using these l bits) is M =
2l .

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As mentioned above, there are two basic memory operations. These are the
memory write and memory read operations. During a memory write operation a
word is stored into a memory location whose address is specified. During a memory
read operation a word is read from a memory location whose address is specified.
Typically, memory read and memory write operations are performed by the central
processing unit (CPU)

Three basic steps are needed in order for the CPU to perform a write operation into a
specified memory location:

1. The word to be stored into the memory location is first loaded by the CPU into
a specified register, called the memory data register (MDR).

2. The address of the location into which the word is to be stored is loaded by
the CPU into a specified register, called the memory address register (MAR).

3. A signal, called write, is issued by the CPU indicating that the word stored in
the MDR is to be stored in the memory location whose address in loaded in
the MAR.

The figure above illustrates the operation of writing the word given by 7E (in hex) into
the memory location whose address is 2005. Part a of the figure shows the status of
the registers and memory locations involved in the write operation before the
execution of the operation. Part b of the figure shows the status after the execution

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of the operation. It is worth mentioning that the MDR and the MAR are registers used
exclusively by the CPU and are not accessible to the programmer.

Similar to the write operation, three basic steps are needed in order to perform a
memory read operation:

1. The address of the location from which the word is to be read is loaded into
the MAR.
2. A signal, called read, is issued by the CPU indicating that the word whose
address is in the MAR is to be read into the MDR.
3. After some time, corresponding to the memory delay in reading the
specified word, the required word will be loaded by the memory into the
MDR ready for use by the CPU.

The figure above illustrates the operation of reading the word stored in the memory
location whose address is 2010. Part a of the figure shows the status of the registers
and memory locations involved in the read operation before the execution of the
operation. Part b of the figure shows the status after the read operation.

Watch https://www.youtube.com/watch?v=jFDMZpkUWCw to view the process of

read and write.

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III. ADDRESSING MODE

Information involved in any operation performed by the CPU needs to be

addressed. In computer terminology, such information is called the operand.
Therefore, any instruction issued by the processor must carry at least two types of
information. These are the operation to be performed, encoded in what is called
the op-code field, and the address information of the operand on which the
operation is to be performed, encoded in what is called the address field.

Classification of Instructions:

Types of Addressing Mode

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IV. ISA DESIGN

A. Complex Instruction Set Computers (CISC)

• The primary goal of CISC architecture is to complete a task in as few lines of

assembly as possible
• Processor Hardware that is capable of understanding and executing a series
of operations
• Uses COMPLEX INSTRUCTION

ADVANTAGE:
- compiler has to do very little work to translate a high-leve
language statement into assembly
- very little RAM is required to store instructions
DISADVANTAGE:
- Complex instructions
- High cycles per second

B. Reduced Instruction Set Computers (RISC)

• RISC utilizes simple addressing modes and fixed length instructions for
pipelining
• Used in portable devices due to its power efficiency
• RISC is a type of microprocessor architecture that uses highly-optimized set of
instructions.

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ADVANTAGE:
- Use simple instructions that can be executed within one clock
cycle
- Speed
DISADVANTAGE:
- More RAM is needed to store the assembly level instructions
- The compiler must also perform more work to convert a high-level
language statement into code of this form.

V. ISA METRICS

The design of ISA follows certain characteristics as follows:

• Aesthetics
• Regularity
• Primitives not solutions
• Completeness
• Streamlined
• Ease of Compilation
• Ease of Implementation
• Scalability

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Task 3.1 ISA METRICS

Given the different ISA metrics, select 3 and discuss briefly what does it mean in
designing ISA.