PIC16F73/74/76/77

PIC16F73/74/76/77 (Rev. C0 Silicon) Data Sheet Errata

The PIC16F73/74/76/77 parts you have received conform functionally to the Device Data Sheet (DS30325B), except for the anomalies described below. None. Date Codes that pertain to Rev. C0 Silicon: PIC16F73/74 PIC16F76/77 0220 and later 0304 and later

Clarifications/Corrections to the Data Sheet:

In the Device Data Sheet (DS30325B), the following clarifications and corrections should be noted.

1. Module: Core
The typical and maximum supply currents (parameter D010A) specified for extended voltage devices have been changed. The IDD specifications differ from the Device Data Sheet only for devices operating at a VDD of 3.0V and a FOSC of 32 kHz with the WDT disabled. The changes in the specification are shown in bold in Table 1.

TABLE 1:
Param Sym. No. D010A IDD

DC SPECIFICATION CHANGES FROM DATA SHEET

Characteristic/ Device Supply Current PIC16LF73/74/76/77 New Specification Min Typ 25 Max 48 Data Sheet Specification Min Typ 20 Max 48 A LP osc configuration, FOSC = 32 kHz, VDD = 3.0V, WDT disabled Units Notes

2003 Microchip Technology Inc.

DS80165A-page 1

PIC16F73/74/76/77
2. Module: Pinout Correction
The MLF (now known as QFN) package pinout locations for pins RA4 and RA5 were incorrectly stated in Table 1-2 of the Device Data Sheet. The correct pinout locations are indicated in bold in Table 2.

TABLE 2:
Pin Name

PIC16F73 AND PIC16F76 PINOUT DESCRIPTION

DIP SSOP SOIC Pin# MLF Pin# I/O/P Type Buffer Type Description

. . . RA4/T0CKI RA4 T0CKI RA5/SS/AN4 RA5 SS AN4 . . . Legend: I = input = Not used O = output TTL = TTL input I/O = input/output ST = Schmitt Trigger input P = power 6 3 I/O I 7 4 I/O I I TTL Digital I/O. SPI slave select input. Analog input 4. ST Digital I/O Open drain when configured as output. Timer0 external clock input.

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PIC16F73/74/76/77
3. Module: Pinout Correction
The PIC16F73/74/76/77 device family does not offer low-voltage programming. The Device Data Sheet incorrectly lists RB3 as providing the PGM function required for low-voltage programming. References to the PGM function in Tables 1-2 and Table 1-3 of the Device Data Sheet have been removed. Table 3 and Table 4 show the corrections for the PIC16F73/76 and PIC16F74/77 devices respectively, The text shown in bold has been removed. References to the PGM function in the Pin Diagrams on pages 2 and 3, and Figures 1-1 and 1-2 (pages 6 and 7) in the Data Sheet have also been removed. A reference to the PGM function listed in the Data Sheet Index has also been removed.

TABLE 3:
Pin Name

PIC16F73 AND PIC16F76 PINOUT DESCRIPTION

DIP SSOP SOIC Pin# MLF Pin# I/O/P Type Buffer Type Description

. . . RB3/PGM RB3 PGM . . .

24

21 I/O I/O

TTL Digital I/O. Low voltage ICSP programming enable pin.

TABLE 4:
Pin Name . . . RB3/PGM RB3 PGM . . .

PIC16F74 AND PIC16F77 PINOUT DESCRIPTION

DIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type Description

36

39

11 I/O I/O

TTL Digital I/O. Low voltage ICSP programming enable pin.

2003 Microchip Technology Inc.

DS80165A-page 3

PIC16F73/74/76/77
4. Module: Packaging (Pinout and Product Identification)
PIC16F74 and PIC16F77 devices are now offered in a 44-pin, micro lead frame package (commonly known as QFN). This provides near chip scale package size. This option is in addition to the 28-pin QFN packages already available for the PIC16F73 and PIC16F76 devices. The 44-pin QFN package has been added to the product line since the original publication of the Device Data Sheet. The addition of this option requires the following additions to the Device Data Sheet (DS30325B). Referenced figures and tables follow this text. 1. The Pin Diagrams on pages 2-3 of the Data Sheet are amended with the addition of the 44-pin QFN pinout shown in Figure 1. 2. Table 1.3 of Section 1.0 (Device Overview) is replaced with an updated version which adds a column for QFN pin assignments. All new information is indicated in bold. 3. Section 17.1 (Package Marking Information) is amended to include a marking template and example for 44-pin QFN devices. These are shown in Figure 2. 4. Section 17.2 (Package Details) is amended to include the mechanical drawing of the 44-pin QFN package, following the existing drawings. This is shown in Figure 3. 5. In the PIC16F7X Product Identification System (page 171), the ML line item in the Package options section should now read (change in bold): ML = QFN For the sake of completeness, it is also noted that the package designation MLF is now replaced by QFN in all occurrences throughout the Device Data Sheet. MLF should be considered an obsoleted term.

FIGURE 1:

PINOUT DIAGRAM FOR PIC16F74/77, 44-PIN QFN PACKAGE

RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 RC0/T1CKI 44 43 42 41 40 39 38 37 36 35 34

44-Pin QFN

RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD VDD RB0/INT0 RB1 RB2

1 2 3 4 5 6 7 8 9 10 11

PIC16F74 PIC16F77

33 32 31 30 29 28 27 26 25 24 23

OSC2/CLKO OSC1/CLKI VSS VSS VDD VDD RE2/AN7/CS RE1/AN6/WR RE0/AN5/RD RA5/AN4/SS RA4/T0CKI

22 21 20 19 18 17 16 15 14 13 12 RA3/AN3/VREF+ RA2/AN2/VREFRA1/AN1 RA0/AN0 MCLR/VPP RB7/PGD RB6/PGC RB5 RB4 NC RB3

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2003 Microchip Technology Inc.

PIC16F73/74/76/77
FIGURE 2: PACKAGE MARKING TEMPLATE FOR PIC16F74/77, 44-PIN QFN 44-Lead QFN Example

XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN

PIC16F77 -I/ML 0310017

2003 Microchip Technology Inc.

DS80165A-page 5

PIC16F73/74/76/77
TABLE 1-3:
Pin Name OSC1/CLKI OSC1

PIC16F74/77 PINOUT DESCRIPTION

DIP Pin# 13 PLCC Pin# 14 QFN Pin# 32 QFP Pin# 30 I/O/P Type I Buffer Type Description

CLKI

ST/CMOS(4) Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode. Otherwise CMOS. External clock source input. Always associated with pin function OSC1 (see OSC1/CLKI, OSC2/CLKO pins). Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. Master Clear (input) or programming voltage (output). Master Clear (Reset) input. This pin is an active low RESET to the device. Programming voltage input. PORTA is a bidirectional I/O port.

OSC2/CLKO OSC2

14

15

33

31

CLKO

MCLR/VPP MCLR VPP RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2/VREFRA2 AN2 VREFRA3/AN3/VREF+ RA3 AN3 VREF+ RA4/T0CKI RA4 T0CKI RA5/SS/AN4 RA5 SS AN4 Legend: Note 1: 2: 3: 4:

18

18

I/P

ST

19

19 I/O I

TTL Digital I/O. Analog input 0. TTL I/O I Digital I/O. Analog input 1. TTL I/O I I Digital I/O. Analog input 2. A/D reference voltage (Low) input. TTL I/O I I Digital I/O. Analog input 3. A/D reference voltage (High) input. ST I/O I Digital I/O Open drain when configured as output. Timer0 external clock input. TTL I/O I I Digital I/O. SPI slave select input. Analog input 4.

20

20

21

21

22

22

23

23

24

24

I = input O = output I/O = input/output P = power = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as an external interrupt. This buffer is a Schmitt Trigger input when used in Serial Programming mode. This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.

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PIC16F73/74/76/77
TABLE 1-3:
Pin Name

PIC16F74/77 PINOUT DESCRIPTION (CONTINUED)

DIP Pin# PLCC Pin# QFN Pin# QFP Pin# I/O/P Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.

RB0/INT RB0 INT RB1 RB2 RB3 RB4 RB5 RB6/PGC RB6 PGC RB7/PGD RB7 PGD RC0/T1OSO/T1CKI RC0 T1OSO T1CKI RC1/T1OSI/CCP2 RC1 T1OSI CCP2 RC2/CCP1 RC2 CCP1 RC3/SCK/SCL RC3 SCK SCL RC4/SDI/SDA RC4 SDI SDA RC5/SDO RC5 SDO RC6/TX/CK RC6 TX CK RC7/RX/DT RC7 RX DT Legend: Note 1: 2: 3: 4:

33

36

8 I/O I

TTL/ST(1) Digital I/O. External interrupt. TTL TTL TTL TTL TTL TTL/ST(2) I/O I/O Digital I/O. In-circuit debugger and ICSP programming clock. TTL/ST(2) I/O I/O Digital I/O. In-circuit debugger and ICSP programming data. PORTC is a bidirectional I/O port. ST I/O O I Digital I/O. Timer1 oscillator output. Timer1 external clock input. ST I/O I I/O Digital I/O. Timer1 oscillator input. Capture2 input, Compare2 output, PWM2 output. ST I/O I/O Digital I/O. Capture1 input/Compare1 output/PWM1 output. ST I/O I/O I/O Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode. ST I/O I I/O Digital I/O. SPI data in. I2C data I/O. ST I/O O Digital I/O. SPI data out. ST I/O O I/O Digital I/O. USART asynchronous transmit. USART 1 synchronous clock. ST I/O I I/O Digital I/O. USART asynchronous receive. USART synchronous data. Digital I/O. Digital I/O. Digital I/O. Digital I/O. Digital I/O.

34 35 36 37 38 39

37 38 39 41 42 43

10 11 12 14 15 16

9 10 11 14 15 16

I/O I/O I/O I/O I/O

40

44

17

17

15

16

34

32

16

18

35

35

17

19

36

36

18

20

37

37

23

25

42

42

24

26

43

43

25

27

44

44

26

29

I = input O = output I/O = input/output P = power = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as an external interrupt. This buffer is a Schmitt Trigger input when used in Serial Programming mode. This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.

2003 Microchip Technology Inc.

DS80165A-page 7

PIC16F73/74/76/77
TABLE 1-3:
Pin Name

PIC16F74/77 PINOUT DESCRIPTION (CONTINUED)

DIP Pin# PLCC Pin# QFN Pin# QFP Pin# I/O/P Type Buffer Type Description PORTD is a bidirectional I/O port or parallel slave port when interfacing to a microprocessor bus.

RD0/PSP0 RD0 PSP0 RD1/PSP1 RD1 PSP1 RD2/PSP2 RD2 PSP2 RD3/PSP3 RD3 PSP3 RD4/PSP4 RD4 PSP4 RD5/PSP5 RD5 PSP5 RD6/PSP6 RD6 PSP6 RD7/PSP7 RD7 PSP7 RE0/RD/AN5 RE0 RD AN5 RE1/WR/AN6 RE1 WR AN6 RE2/CS/AN7 RE2 CS AN7 VSS VDD NC Legend: Note 1: 2: 3: 4:

19

21

38

38 I/O I/O

ST/TTL(3) Digital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port data. PORTE is a bidirectional I/O port. ST/TTL(3) I/O I I Digital I/O. Read control for parallel slave port. Analog input 5. ST/TTL(3) I/O I I Digital I/O. Write control for parallel slave port. Analog input 6. ST/TTL(3) I/O I I Digital I/O. Chip select control for parallel slave port. Analog input 7. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. These pins are not internally connected. These pins should be left unconnected.

20

22

39

39

21

23

40

40

22

24

41

41

27

30

28

31

29

32

30

33

25

25

10

26

26

10

11

27

27

12,31 11,32

13,34 12,35 1,17, 28,40

6, 30, 31 7, 8, 28, 29 13

6,29 7,28 12,13, 33,34

P P

I = input O = output I/O = input/output P = power = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as an external interrupt. This buffer is a Schmitt Trigger input when used in Serial Programming mode. This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.

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2003 Microchip Technology Inc.

PIC16F73/74/76/77
FIGURE 3: 44-PIN QFN PACKAGE (DRAWING 1, PACKAGING) 44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN)
E EXPOSED METAL PAD

p D

D2

2 1 n OPTIONAL PIN 1 INDEX ON TOP MARKING PIN 1 INDEX ON EXPOSED PAD E2 L

TOP VIEW

BOTTOM VIEW

A A1 A3

Number of Pins Pitch Overall Height Standoff Base Thickness Overall Width Exposed Pad Width Overall Length Exposed Pad Length Lead Width Lead Length

Units Dimension Limits n p A A1 A3 E E2 D D2 B L

MIN

.031 .000

.262 .262 .012 .014

INCHES NOM 44 .026 BSC .035 .001 .010 REF .315 BSC .268 .315 BSC .268 .013 .016

MAX

MIN

.039 .002

.274 .274 .013 .018

MILLIMETERS* NOM 44 0.65 BSC 0.90 0.80 0.02 0 0.25 REF 8.00 BSC 6.65 6.80 8.00 BSC 6.65 6.80 0.30 0.33 0.35 0.40

MAX

1.00 0.05

6.95 6.95 0.35 0.45

*Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC equivalent: M0-220
Drawing No. C04-103

2003 Microchip Technology Inc.

DS80165A-page 9

PIC16F73/74/76/77
REVISION HISTORY
Rev A Document (8/2003) First revision of this document. Device Data Sheet Clarification issues 1 (Core), 2 (Pinout Correction), 3 (Pinout Correction) and 4 (Packaging).

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2003 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable.

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchips products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.

Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Accuron, Application Maestro, dsPICDEM, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, InCircuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Companys quality system processes and procedures are QS-9000 compliant for its PICmicro 8-bit MCUs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchips quality system for the design and manufacture of development systems is ISO 9001 certified.

2003 Microchip Technology Inc.

DS80165A-page 11

WORLDWIDE SALES AND SERVICE

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07/28/03

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DS80165A-page 12

2003 Microchip Technology Inc.