Computer Organization and Architecture

CS 202

Module -1 Part -2

Memory Locations, Addresses, and Operations

Addressing Modes
 Memory Location, Addresses, and
Operation
n bits
first word
Memory consists of
second word
many millions of
storage cells, each of
which can store 1 bit.
•
Data is usually •
•
accessed in n-bit
i th word
groups called word.
n is called word length.
•
•
•
last word

Figure 2.5. Memory words.

Memory Location, Addresses, and
Operation
 32-bit word length example
32 bits

b 31 b 30 b1 b0

•
•
•
Sign bit: b 31= 0 for positive numbers
b 31= 1 for negative numbers
(a) A signed integer

8 bits 8 bits 8 bits 8 bits

ASCII ASCII ASCII ASCII

character character character character

(b) Four characters

 Accessing numbers, characters and strings
 Number
 By its word address as it usually occupies one word
 Character
 By byte address
 Strings
 They are of variable length
 Beginning of the string by giving the beginning byte
address which contains first character
 Successive bytes contains successive characters
 Termination?
Either by a special control character
Or a separate memory word location/ register containing
a number indicating the string length www.bookspar.com | Website for
students | VTU NOTES
 Memory Location, Addresses, and
Operation

 To retrieve information from memory, either for one

word or one byte (8-bit), addresses for each location
are needed.
 A k-bit address memory has 2k memory locations,
namely 0 – 2k-1, called memory space.
 24-bit addr memory: 224 = 16,777,216 = 16M (1M=220)
 32-bit addr memory: 232 = 4G (1G=230)
 1K(kilo)=210
 1T(tera)=240
 Memory Location, Addresses, and Operation
• It is impractical to assign distinct addresses to individual bit
locations in the memory.
• The most practical assignment is to have successive addresses
refer to successive byte locations in the memory is called byte-
addressable memory.
• Word alignment - Words are said to be aligned in memory if they
begin at a byte address that is a multiple of the number of bytes
in a word.
• Byte locations have addresses - 0,1, 2, 3, etc …
• word length is 16 bits, the successive words are located at
addresses - 0, 2, 4, 6, etc…
• word length is 32 bits, the successive words are located at
addresses - 0, 4, 8,12, etc…
Big-Endian and Little-Endian Assignments
Endianness: ordering of bytes within a larger object, eg how a word
is stored in memory
Eg: 68000 is a big endian processor
Big-Endian and Little-Endian Assignments
Big-Endian: lower byte addresses are used for the most significant bytes
of the word
Little-Endian: opposite ordering. lower byte addresses are used for the
least significant bytes of the word
 Problems
1. A memory has 32-bit address and byte-addressable,
what is the size of the memory (in bytes)?
2. A memory has 24-bit address and word-addressable
with a word length of 32 bits, what is the size of the
memory (in bytes)?
3. A memory has 16-bit address and byte addressable.
Word length is 32 bits. How many words can we store
in such a memory?
Note: A memory with k-bit address
a) byte-addressable  2k bytes
b) word-addressable  2k words
 Answers
1. 32-bit address, byte addressable memory
No of bytes = 232 = 230 x 22
= 4G bytes (1G = 230)
2. 24-bit address, word addressable, 1Word =32 bits (4 bytes)
No of words = 224 = 220 x 24
No of bytes = No of words x (bytes/word)
= 220 x 24 x 22 (1 word = 4 bytes)
= 64M bytes (1M = 220)
3. 16-bit address, byte addressable, 1Word =32 bits (4 bytes)
No of words = No of bytes / (bytes/word)
= 216 / 22 = 210 x 26 / 22 (1 word = 4 bytes)
= 16 K words (1K = 210)
Memory Operations

 Load (or Read or Fetch)

 Copy the content
 Memory content doesn’t change
 Address  MAR, read frm mem, content  MDR
 Registers can be used
 Store (or Write)
 Overwrite the content in memory
 Address  MAR and Data  MDR, write to mem
 Registers can be used
Instruction and Instruction Sequencing

 Data transfers between the memory and the processor

registers

 Arithmetic and logic operations on data

 Program sequencing and control

 I/O transfers
 Register Transfer Notation

 Identify a location by a symbolic name standing for its

hardware binary address (LOC, R0,…)
 Contents of a location are denoted by placing square
brackets around the name of the location
 R1← [LOC]
 R3 ← [R1] + [R2]
 Register Transfer Notation (RTN)
 Assembly Language Notation

 Represent machine instructions and programs

 Move R1, LOC => R1← [LOC]
 ADD R1, R2, R3 => R1 ← [R2] + [R3]
CPU Organizations

 Single Accumulator Organisation

 Result usually goes to the Accumulator
 Accumulator has to be saved to memory quite often
 General Register Organisation
 Registers hold operands thus reduce memory traffic
 Register bookkeeping
 Stack Organisation
 Operands and result are always in the stack
 Instruction cycle

Instruction cycle consists of following phases:

Fetching an instruction from memory.

Decoding the instruction.
Reading the effective address from memory in case of the
instruction having an indirect address.
Execution of the instruction.
 Instruction Format
Instruction Format
An instruction consists of bits and these bits are grouped upto
make fields.

Fields in instruction format :

• Opcode - which tells about the operation to be performed.
• Address field - designating a memory address or a processor
register.
• Mode field - specifying the way the operand or effective address
is determined.
 Instruction Formats

 Three-Address Instructions
(operation destn, src1, src2)
 ADD R1, R2, R3 ; R1 ← R2 + R3
 Two-Address Instructions
(operation destn, src)
 ADD R1, R2 ; R1 ← R1 + R2
 One-Address Instructions
( in arithmetic operations, accumulator is implicit)
 ADD B ; AC ← AC + M[B]
 LOAD A ; AC ← M[A]
 PUSH X ; TOS ← M[X]
 Zero-Address Instructions
(all operands are implied to be in a pushdown stack)
 ADD ; TOS ← TOS + (TOS – 1) (stack grows up)
(This operation has effect of popping the two top numbers from
stack, adding the numbers, and pushing the sum into the
stack)
Instruction Formats
Eg: Evaluate (A+B)(C+D) store result in X
 Three-Address
1. ADD R1, A, B ; R1 ← M[A] + M[B]
2. ADD R2, C, D ; R2 ← M[C] + M[D]
3. MUL X, R1, R2 ; M[X] ← R1  R2
Instruction Formats

Eg: Evaluate (A+B)(C+D) store result in X

 Two-Address
1. MOV R1, A ; R1 ← M[A]
2. ADD R1, B ; R1 ← R1 + M[B]
3. MOV R2, C ; R2 ← M[C]
4. ADD R2, D ; R2 ← R2 + M[D]
5. MUL R1, R2 ; R1 ← R1  R2
6. MOV X, R1 ; M[X] ← R1
Instruction Formats

Eg: Evaluate (A+B)(C+D) store result in X

 One-Address
1. LOAD A ; AC ← M[A]
2. ADD B ; AC ← AC + M[B]
3. STORE T ; M[T] ← AC
4. LOAD C ; AC ← M[C]
5. ADD D ; AC ← AC + M[D]
6. MUL T ; AC ← AC  M[T]
7. STORE X ; M[X] ← AC
 Instruction Formats

Eg: Evaluate (A+B)(C+D) store result in X

 Zero-Address
1. PUSH A ; TOS ← A
2. PUSH B ; TOS ← B
3. ADD ; TOS ← (A + B)
4. PUSH C ; TOS ← C
5. PUSH D ; TOS ← D
6. ADD ; TOS ← (C + D)
7. MUL ; TOS ← (C+D)(A+B)
8. POP X ; M[X] ← TOS
 Using Registers
• Registers are faster
• Shorter instructions
• The number of registers is smaller
(e.g. 32 registers need 5 bits)
• Potential speedup
• Minimize the frequency with which data is
moved back and forth between the memory and
processor registers.
 Addressing Modes
• Opcode field - specifies the operation to be performed.
• Operand - data on which the operation is to be performed.
• operand(data) may be in accumulator, general purpose register or at some
specified memory location
• Addressing mode -The way the operands are chosen during
program execution is dependent on the addressing mode of
the instruction.
• The addressing mode specifies a rule for interpreting or
modifying the address field of the instruction before the
operand is actually referenced.
 Effective Address - is the actual location of an operand of an
instruction.
Types of Addressing Modes

 Immediate mode
 Register mode
 Absolute/ Direct mode
 Indirect mode
 Index mode
 Base with index
 Base with index and offset
 Relative mode
 Auto - increment mode
 Auto - decrement mode
 Immediate Addressing

• Operand is part of instruction

• Operand = Value,
• EA = address of data in memory (in instruction area)
• e.g. MOV R1, #5 ; R1 ← 5
–Move 5 to register R1
–5 is operand
• No memory reference to fetch data
• Fast
• Limited range

Example
MOV R1,
#5R1
5 
 Register Addressing
• Operand is held in register, whose name (address)
given in instructn in address field
• EA = Ri (register address)
• Limited number of registers
• Very small address field needed
– Shorter instructions
– Faster instruction fetch and execution
• No memory access
• Very limited address space
Eg : MOV R1, R2
ADD R1, R2
Register Addressing Diagram

Example
MOV R1, R2

R1

R2 = 3

R3 = 5
 Direct /Absolute Addressing

• Address field contains address of operand (memory location)

• Effective address EA = A (memory address)
eg: MOV R1, A
• Single memory reference to access data
• No additional calculations to work out effective address
• Limited address space

29
Direct /Absolute Addressing
Example
MOV R1, A

A = 101

100
101 0 1 0 4
102
103
104 1 1 0 A
 Indirect Addressing (1/2)
• Memory cell pointed to by address field contains the address of
(pointer to) the operand
• EA =[A]
–Look in A, find an address (content of A) and look in memory
at that address location for operand
– In C programming, E=*D, D is a Pointer Variable
–Can be compiled into commands
MOV R1, D
MOV E, (R1)
– using indirect addressing => MOV E, (D)
• Large address space
• 2n where n = word length
• May be nested, multilevel, cascaded, e.g. EA = (((A)))
• Multiple memory accesses ,Hence slower
Indirect Addressing Diagram

Example
MOV R1, (A)

A = 101

100
101 0 1 0 4
102
103
104 1 1 0 A
 Register Indirect Addressing
• Operand is in register or memory cell pointed to by contents of
register Ri
• EA = [Ri]
• Large address space (2n)
• One fewer memory access than indirect addressing
Register Indirect Addressing Diagram

Example
MOV R1,
(R2)
R1

R2 = 3

R3 = 5
Indexed / Displacement Addressing
Indexing and Arrays
Index mode – the effective address of the operand is
generated by adding a constant value to the contents of a
register.
 X( Ri ) ; EA = [ Ri ] + X
Ri  Index register
X  constant given either as an explicit number or as a
symbolic name representing a numerical value.
 Effective address= start address + displacement
 (Index register holds address of a new location and value
of X defines an offset (displacement))
 Good for accessing arrays
 Indexed / Displacement Addressing
Indexed Address
EA = Index Register value + Relative Addr

Example
MOV R2, 3(R1)
3

100
R1 = 100
101
102
103 1 1 0 A
104
 Indexing and Arrays…
 Index mode facilitates access to an operand whose location is
defined relative to a reference point within the data structure in
which the operand appears.
 Several variations:
 X( Ri ) ; EA = [ Ri ] + X (Index)
EA is the sum of two values; one is given explicitly in the
instruction, and the other is stored in a register.
 ( Ri, Rj ) ; EA = [ Ri ] + [ Rj ] (Base with Index)
a A second register (base register) may be used to contain the
offset X. EA is the sum of the contents of registers Ri and Rj.
 X( Ri, Rj ) ; EA = X + [ Ri ] + [ Rj ] (Base with Index and
offset)
EA is sum of constant X and contents of registers Ri and Rj .
It is useful in accessing multiple components inside each item
in a record, where the beginning of an item is specified by
(Ri, Rj) part of addressing mode (3D arrays).
 Relative Addressing (PC-Relative)

 Effective address is determined by Index mode using the

program counter in place of the general-purpose register.
 Can be used to access data operands. But, mostly used to
specify the target address in branch instructions
 X( PC ) ; EA = [ PC ] + X (X is a signed number)
eg. Branch>0 LOOP
branch target location (LOOP) is computed by specifying it
as an offset from the current value of PC
 Branch target may be either before or after the branch
instruction, the offset is given as a singed number.
 Relative Addressing (PC-Relative)
 Relative Address
 EA = PCvalue + Relative Addr

0
1
PC= 2 2
Example
MOV R1, 100(PC) +

100
X = 100
101
102 1 1 0 A
103
104
 Autoincrement mode
the effective address of the operand is the contents of a
register specified in the instruction.
After accessing the operand, the contents of this register are
automatically incremented to point to the next item in a list.
( Ri )+  EA = [ Ri ] ;
Increment Ri
The increment is 1 for byte-sized operands, 2 for 16-bit
operands, and 4 for 32-bit operands.
 Example
ADD (R1)+, 3 ; M[R1]←M[R1]+3, R1 ←R1+1
 Autodecrement mode

 contents of a register specified in the instruction is

automatically decremented and used as effective address of
the operand.

- (Ri)  Decrement Ri ;
EA = [ Ri ];
 Addressing Modes
 The different ways in which the location of an operand is specified in an instruction
are referred to as addressing modes.
Instruction Execution and Straight-Line Sequencing

Assumptions:
- One memory operand
per instruction
- 32-bit word length
- Memory is byte
addressable
- Full memory address
can be directly specified
in a single-word instruction

Two-phase procedure:
- Instruction fetch
- Instruction execute
Branching
Branching
 Condition Codes

Condition-code bits are also called status bits or flag bits.

Condition code flags => bits are set or cleared as a result of an operation
performed in the ALU.
Condition code register / status register:
Bit V (overflow) is set to 1 if the exclusive-OR of the last two carries (Cn and
Cn-1) is equal to 1, else V=0. This is the condition for an overflow when
negative numbers are in 2's complement.
eg (In 8-bit ALU, V=1 if the output is greater than +127 or less than -128)
Bit Z (zero) is set to 1 if the output of the ALU contains all 0's, else Z=0.
Bit N (negative) is set to 1 if the highest-order bit Fn-1 is 1, else N=0.
Bit C (carry) is set to 1 if the end carry Cn is 1, else C=0.
Different instructions affect different flags
Condition Codes
Conditional Branch Instructions

 Example: A: 11110000

 A: 1 1 1 1 0 0 0 0 +(−B): 1 1 1 0 1 1 0 0
 B: 0 0 0 1 0 1 0 0 11011100

C=1 Z=0
N=1
V=0