288-Pin DDR4 RDIMM Core

Product Description

DDR4 SDRAM RDIMM Core

Product Description
This specification defines the electrical and mechanical requirements for 288-pin, 1.2V
(VDD) double data rate, synchronous DRAM, registered dual in-line memory modules
(DDR4 SDRAM RDIMMs). The very low profile RDIMM (VLP RDIMM), MiniRDIMM,
and VLP MiniRDIMM are also defined by this specification. These DDR4 RDIMMs are
intended for use as main memory when installed in servers. Some specifications are
part number-specific; refer to the module data sheet addendum of the specific Micron
part number (MPN) for the complete specification.

Features
• DDR4 functionality and operations supported as defined in the component data
sheet
• 288-pin RDIMM
• Supports ECC error detection and correction
• On-board I2C temperature sensor with integrated serial presence-detect (SPD) EE-
PROM
• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
• Low-power auto self refresh (LPASR)
• On-die V REFDQ generation and calibration
• Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS)
• Selectable BC4 or BL8 on-the-fly (OTF)
• Gold edge contacts
• Halogen-free
• Fly-by topology
• Terminated control, command, and address bus

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Products and specifications discussed herein are subject to change by Micron without notice.
 288-Pin DDR4 RDIMM Core
Product Description

Table 1: Product Family Attributes

Parameter Options Notes

DIMM organization x72 ECC
DIMM dimensions (nominal) 133.35mm x 31.25mm Refer to Module Dimensions
133.35 x 18.75mm (VLP UDIMM)
80.0mm x 31.25mm (MiniUDIMM)
80.0mm x 18.75mm (VLP MiniUDIMM)
Pin count 288
DDR4 SDRAM densities supported 4Gb, 8Gb, 16Gb, 32Gb, 64Gb
Capacity 8GB-256GB
DDR4 SDRAM width x4, x8
Data transfer rate PC4-2133 to PC4-3200 Refer to Key Timing Parameters
Serial presence detect, thermal sensor 512-byte
(SPD/TS)
Voltage options (nominal) 1.2V VDD
2.5V VPP
2.5V VDDSPD This supply is separate from the VDD
power plane
Interface 1.2V signaling
Operating temperature TOPER = 0 to 95°C Refer to Thermal Characteristics

Table 2: Key Timing Parameters – Non 3DS-Based DIMMs

DBI Disabled - Data Rate (MT/s) CL

24 22 21 20, 19 18, 17 16, 15 14, 13 12, 11 10

Speed DBI Enabled - Data Rate (MT/s) CL tRCD tRP tRC

Grade PC4- 28 26 25 23, 22 21, 20 19, 18 16, 15 14, 13 12 (ns) (ns) (ns)
-3G2 3200 3200, 3200, 2933 2666 2400 2133 1866 1600 1333 13.75 13.75 45.75
2933 2933
-2G9 2933 – 2933 2933 2666 2400 2133 1866 1600 1333 14.32 14.32 46.32
(13.75)1 (13.75)1 (45.75)1
-2G6 2666 – – – 2666 2400 2133 1866 1600 1333 14.25 14.25 46.25
(13.75)1 (13.75)1 (45.75)1

Note: 1. Down-bin timing; refer to component data sheet Speed Bin Tables for details.

Table 3: Key Timing Parameters – 3DS-Based DIMMs

Speed Data Rate (MT/s) CL tRCD tRP tRC

Grade PC4- 28 26 25 24 22 20 18 16 14 13 (ns) (ns) (ns)

-3S2 3200 3200, 3200, 2933 2933, 2666, 2400, 2133 1866 1600 1600 13.75 13.75 45.75
2933 2933 2666 2400 2133

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 288-Pin DDR4 RDIMM Core
Product Description

Table 3: Key Timing Parameters – 3DS-Based DIMMs (Continued)

Speed Data Rate (MT/s) CL tRCD tRP tRC

Grade PC4- 28 26 25 24 22 20 18 16 14 13 (ns) (ns) (ns)

-2S9 2933 – – 2933 2933, 2666, 2400, 2133 1866 1600 – 14.32 14.32 46.32
2666 2400 2133 (14.06)1 (14.06)1 (46.06)1
-2S6 2666 – – – 2666 2666 2400 2133 1866 1600 – 14.25 14.25 46.25
(14.06)1 (14.06)1 (46.06)1

Note: 1. Down-bin timing; refer to component data sheet Speed Bin Tables for details.

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 288-Pin DDR4 RDIMM Core
Product Description

Important Notes and Warnings

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including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-
ment if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi-
cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-
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automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-
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 288-Pin DDR4 RDIMM Core
Pin Assignments - RDIMM/MiniRDIMM

Pin Assignments - RDIMM/MiniRDIMM

The pin assignment table below is a comprehensive list of all possible pin assignments
for DDR4 RDIMM modules. See the Functional Block Diagram for pins specific to this
module.

Table 4: Pin Assignments - RDIMM

288-Pin DDR4 RDIMM Front 288-Pin DDR4 RDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 NC 37 VSS 73 VDD 109 VSS 145 NC 181 DQ29 217 VDD 253 DQ41
2 VSS 38 DQ24 74 CK0_t 110 DQS14_t/ 146 VREFCA 182 VSS 218 CK1_t 254 VSS
TDQS14_t
3 DQ4 39 VSS 75 CK0_c 111 DQS14_c/ 147 VSS 183 DQ25 219 CK1_c 255 DQS5_c
TDQS14_c
4 VSS 40 DQS12_t/ 76 VDD 112 VSS 148 DQ5 184 VSS 220 VDD 256 DQS5_t
TDQS12_t
5 DQ0 41 DQS12_c/ 77 VTT 113 DQ46 149 VSS 185 DQS3_c 221 VTT 257 VSS
TDQS12_c
6 VSS 42 VSS 78 EVENT_n 114 VSS 150 DQ1 186 DQS3_t 222 PARITY 258 DQ47
7 DQS9_t/ 43 DQ30 79 A0 115 DQ42 151 VSS 187 VSS 223 VDD 259 VSS
TDQS9_t
8 DQS09_c/ 44 VSS 80 VDD 116 VSS 152 DQS0_c 188 DQ31 224 BA1 260 DQ43
TDQS9_c
9 VSS 45 DQ26 81 BA0 117 DQ52 153 DQS0_t 189 VSS 225 A10/ 261 VSS
AP
10 DQ6 46 VSS 82 RAS_n/ 118 VSS 154 VSS 190 DQ27 226 VDD 262 DQ53
A16
11 VSS 47 CB4 83 VDD 119 DQ48 155 DQ7 191 VSS 227 NC 263 VSS
12 DQ2 48 VSS 84 CS0_n 120 VSS 156 VSS 192 CB5 228 WE_n/ 264 DQ49
A14
13 VSS 49 CB0 85 VDD 121 DQS15_t/ 157 DQ3 193 VSS 229 VDD 265 VSS
TDQS15_t
14 DQ12 50 VSS 86 CAS_n/ 122 DQS15_c/ 158 VSS 194 CB1 230 NC 266 DQS6_c
A15 TDQS15_c
15 VSS 51 DQS17_t/ 87 ODT0 123 VSS 159 DQ13 195 VSS 231 VDD 267 DQS6_t
TDQS17_t
16 DQ8 52 DQS17_c/ 88 VDD 124 DQ54 160 VSS 196 DQS8_c 232 A13 268 VSS
TDQS17_c
17 VSS 53 VSS 89 CS1_n/ 125 VSS 161 DQ9 197 DQS8_t 233 VDD 269 DQ55
NC
18 DQS10_t/ 54 CB6 90 VDD 126 DQ50 162 VSS 198 VSS 234 A17 270 VSS
TDQS10_t
19 DQS10_c/ 55 VSS 91 ODT1/ 127 VSS 163 DQS1_c 199 CB7 235 NC/ 271 DQ51
TDQS10_c NC C2
20 VSS 56 CB2 92 VDD 128 DQ60 164 DQS1_t 200 VSS 236 VDD 272 VSS
21 DQ14 57 VSS 93 CS2_n/ 129 VSS 165 VSS 201 CB3 237 CS3_n/ 273 DQ61
C0 C1, NC
22 VSS 58 RESET_n 94 VSS 130 DQ56 166 DQ15 202 VSS 238 SA2 274 VSS
23 DQ10 59 VDD 95 DQ36 131 VSS 167 VSS 203 CKE1/ 239 VSS 275 DQ57
NC
24 VSS 60 CKE0 96 VSS 132 DQS16_t/ 168 DQ11 204 VDD 240 DQ37 276 VSS
TDQS16_t

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 288-Pin DDR4 RDIMM Core
Pin Assignments - RDIMM/MiniRDIMM

Table 4: Pin Assignments - RDIMM (Continued)

288-Pin DDR4 RDIMM Front 288-Pin DDR4 RDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
25 DQ20 61 VDD 97 DQ32 133 DQS16_c/ 169 VSS 205 NC 241 VSS 277 DQS7_c
TDQS16_c
26 VSS 62 ACT_n 98 VSS 134 VSS 170 DQ21 206 VDD 242 DQ33 278 DQS7_t
27 DQ16 63 BG0 99 DQS13_t/ 135 DQ62 171 VSS 207 BG1 243 VSS 279 VSS
TDQ13_t
28 VSS 64 VDD 100 DQS13_c/ 136 VSS 172 DQ17 208 ALERT_n 244 DQS4_c 280 DQ63
TDQS13_c
29 DQS11_t/ 65 A12/BC_n 101 VSS 137 DQ58 173 VSS 209 VDD 245 DQS4_t 281 VSS
TDQS11_t
30 DQS11_c/ 66 A9 102 DQ38 138 VSS 174 DQS2_c 210 A11 246 VSS 282 DQ59
TDQS11_c
31 VSS 67 VDD 103 VSS 139 SA0 175 DQS2_t 211 A7 247 DQ39 283 VSS
32 DQ22 68 A8 104 DQ34 140 SA1 176 VSS 212 VDD 248 VSS 284 VDDSPD
33 VSS 69 A6 105 VSS 141 SCL 177 DQ23 213 A5 249 DQ35 285 SDA
34 DQ18 70 VDD 106 DQ44 142 VPP 178 VSS 214 A4 250 VSS 286 VPP
35 VSS 71 A3 107 VSS 143 VPP 179 DQ19 215 VDD 251 DQ45 287 VPP
36 DQ28 72 A1 108 DQ40 144 NC 180 VSS 216 A2 252 VSS 288 VPP

The pin assignment table below is a comprehensive list of all possible pin assignments
for DDR4 MiniRDIMM modules. See the Functional Block Diagram for pins specific to
this module.

Table 5: Pin Assignments - MiniRDIMM

288-Pin DDR4 MiniRDIMM Front 288-Pin DDR4 MiniRDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 NC 37 VSS 73 A1 109 DQ41 145 VREFCA 181 VSS 217 RFU 253 DQ45
2 NC 38 DQ24 74 VDD 110 VSS 146 NC 182 DQ28 218 VDD 254 VSS
3 RFU 39 VSS 75 CK0_t 111 DQS5_c 147 RFU 183 VSS 219 CK1_t 255 DQS14_t/
DM5_n
4 VSS 40 DQ25 76 CK0_c 112 DQS5_t 148 VSS 184 DQ29 220 CK1_c 256 DQS14_c
5 DQ0 41 VSS 77 VDD 113 VSS 149 DQ4 185 VSS 221 VDD 257 VSS
6 VSS 42 DQS3_c 78 RFU 114 DQ42 150 VSS 186 DQS12_t/ 222 RFU 258 DQ46
DM3_n
7 DQ1 43 DQS3_t 79 VTT 115 VSS 151 DQ5 187 DQS12_c 223 VTT 259 VSS
8 VSS 44 VSS 80 EVENT_n 116 DQ43 152 VSS 188 VSS 224 PARITY 260 DQ47
9 DQS0_c 45 DQ26 81 VDD 117 VSS 153 DQS9_t/ 189 DQ30 225 VDD 261 VSS
DM0_n
10 DQS0_t 46 VSS 82 A0 118 DQ48 154 DQS9_c 190 VSS 226 BA1 262 DQ52
11 VSS 47 DQ27 83 BA0 119 VSS 155 VSS 191 DQ31 227 A10/ 263 VSS
AP
12 DQ2 48 VSS 84 VDD 120 DQ49 156 DQ6 192 VSS 228 VDD 264 DQ53
13 VSS 49 CB0 85 RAS_n/ 121 VSS 157 VSS 193 CB4 229 WE_n/ 265 VSS
A16 A14
14 DQ3 50 VSS 86 CS0_n 122 DQS6_c 158 DQ7 194 VSS 230 CAS_n/ 266 DQS15_t/
A15 DM6_n
15 VSS 51 CB1 87 VDD 123 DQS6_t 159 VSS 195 CB5 231 VDD 267 DQS15_c

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 288-Pin DDR4 RDIMM Core
Pin Assignments - RDIMM/MiniRDIMM

Table 5: Pin Assignments - MiniRDIMM (Continued)

288-Pin DDR4 MiniRDIMM Front 288-Pin DDR4 MiniRDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
16 DQ8 52 VSS 88 ODT0 124 VSS 160 DQ12 196 VSS 232 A13 268 VSS
17 VSS 53 DQS8_c 89 CS1_n/ 125 DQ50 161 VSS 197 DQS17_t/ 233 A17/ 269 DQ54
NC DM8_n NC
18 DQ9 54 DQS8_t 90 VDD 126 VSS 162 DQ13 198 DQS17_c 234 VDD 270 VSS
19 VSS 55 VSS 91 ODT1/ 127 DQ51 163 VSS 199 VSS 235 NC/CS3_n/ 271 DQ55
NC C1
20 DQS1_c 56 CB2 92 CS2_n/C0/ 128 VSS 164 DQS10_t/ 200 CB6 236 NC/ 272 VSS
NC DM1_n C2
21 DQS1_t 57 VSS 93 VDD 129 DQ56 165 DQS10_c 201 VSS 237 VDD 273 DQ60
22 VSS 58 CB3 94 RFU 130 VSS 166 VSS 202 CB7 238 RFU 274 VSS
23 DQ10 59 VSS 95 VSS 131 DQ57 167 DQ14 203 VSS 239 VSS 275 DQ61
24 VSS 60 ALERT_n 96 DQ32 132 VSS 168 VSS 204 RESET_n 240 DQ36 276 VSS
25 DQ11 61 CKE0 97 VSS 133 DQS7_c 169 DQ15 205 RFU 241 VSS 277 DQS16_t/
DM7_n
26 VSS 62 VDD 98 DQ33 134 DQS7_t 170 VSS 206 VDD 242 DQ37 278 DQS16_c
27 DQ16 63 ACT_n 99 VSS 135 VSS 171 DQ20 207 CKE1/ 243 VSS 279 VSS
NC
28 VSS 64 BG0 100 DQS4_c 136 DQ58 172 VSS 208 BG1 244 DQS13_t/ 280 DQ62
DM4_n
29 DQ17 65 VDD 101 DQS4_t 137 VSS 173 DQ21 209 VDD 245 DQS13_c 281 VSS
30 VSS 66 A12/BC_n 102 VSS 138 DQ59 174 VSS 210 A11 246 VSS 282 DQ63
31 DQS2_c 67 A9 103 DQ34 139 VSS 175 DQS11_t/ 211 A7 247 DQ38 283 VSS
DM2_n
32 DQS2_t 68 VDD 104 VSS 140 SA0 176 DQS11_c 212 VDD 248 VSS 284 SA1
33 VSS 69 A8 105 DQ35 141 VDDSPD 177 VSS 213 A5 249 DQ39 285 SA2
34 DQ18 70 A6 106 VSS 142 SDA 178 DQ22 214 A4 250 VSS 286 SCL
35 VSS 71 VDD 107 DQ40 143 VPP 179 VSS 215 VDD 251 DQ44 287 VPP
36 DQ19 72 A3 108 VSS 144 VPP 180 DQ23 216 A2 252 VSS 288 VPP

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 288-Pin DDR4 RDIMM Core
Pin Descriptions

Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for DDR4
modules. All pins listed may not be supported on this module. See the Functional Block
Diagram located in the module MPN data sheet addendum for pins specific to the mod-
ule.

Table 6: Pin Descriptions

Symbol Type Description

Ax Input Address inputs: Provide the row address for ACTIVATE commands and the column address for
READ/WRITE commands in order to select one location out of the memory array in the respec-
tive bank (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, and RAS_n/A16 have additional functions;
see individual entries in this table). The address inputs also provide the op-code during the
MODE REGISTER SET command. A17 is only defined for x4 SDRAM.
A10/AP Input Auto precharge: A10 is sampled during READ and WRITE commands to determine whether an
auto precharge should be performed on the accessed bank after a READ or WRITE operation
(HIGH = auto precharge; LOW = no auto precharge). A10 is sampled during a PRECHARGE com-
mand to determine whether the precharge applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by the bank group and bank
addresses.
A12/BC_n Input Burst chop: A12/BC_n is sampled during READ and WRITE commands to determine if burst
chop (on-the-fly) will be performed (HIGH = no burst chop; LOW = burst chopped). See Com-
mand Truth Table in the DDR4 component data sheet.
ACT_n Input Command input: ACT_n defines the ACTIVATE command being entered along with CS_n. The
input into RAS_n/A16, CAS_n/A15, and WE_n/A14 are considered as row address A16, A15, and
A14. See Command Truth Table.
BAx Input Bank address inputs: Define the bank (with a bank group) to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be
accessed during a MODE REGISTER SET command.
BGx Input Bank group address inputs: Define the bank group to which a REFRESH, ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be
accessed during a MODE REGISTER SET command. BG[1:0] are used in the x4 and x8 configura-
tions. x16-based SDRAM only has BG0.
C0, C1, C2 Input Chip ID: These inputs are used only when devices are stacked; that is, 2H, 4H, and 8H stacks for
(RDIMM/LRDIMM on- x4 and x8 configurations using through-silicon vias (TSVs). These pins are not used in the x16
ly) configuration. Some DDR4 modules support a traditional DDP package, which uses CS1_n,
CKE1, and ODT1 to control the second die. All other stack configurations, such as a 4H or 8H,
are assumed to be single-load (master/slave) type configurations where C0, C1, and C2 are used
as chip ID selects in conjunction with a single CS_n, CKE, and ODT. Chip ID is considered part of
the command code.
CKx_t Input Clock: Differential clock inputs. All address, command, and control input signals are sampled
CKx_c on the crossing of the positive edge of CK_t and the negative edge of CK_c.
CKEx Input Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals, device
input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and
SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is
asynchronous for self refresh exit. After VREFCA has become stable during the power-on and ini-
tialization sequence, it must be maintained during all operations (including SELF REFRESH). CKE
must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK_t,
CK_c, ODT, RESET_n, and CKE) are disabled during power-down. Input buffers (excluding CKE
and RESET_n) are disabled during self refresh.
CSx_n Input Chip select: All commands are masked when CS_n is registered HIGH. CS_n provides external
rank selection on systems with multiple ranks. CS_n is considered part of the command code
(CS2_n and CS3_n are not used on UDIMMs).

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 288-Pin DDR4 RDIMM Core
Pin Descriptions

Table 6: Pin Descriptions (Continued)

Symbol Type Description

ODTx Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the
DDR4 SDRAM. When enabled, ODT (RTT) is applied only to each DQ, DQS_t, DQS_c, DM_n/
DBI_n/TDQS_t, and TDQS_c signal for x4 and x8 configurations (when the TDQS function is ena-
bled via the mode register). For the x16 configuration, RTT is applied to each DQ, DQSU_t,
DQSU_c, DQSL_t, DQSL_c, UDM_n, and LDM_n signal. The ODT pin will be ignored if the mode
registers are programmed to disable RTT.
PARITY Input Parity for command and address: This function can be enabled or disabled via the mode
register. When enabled in MR5, the DRAM calculates parity with ACT_n, RAS_n/A16, CAS_n/A15,
WE_n/A14, BG[1:0], BA[1:0], A[16:0]. Input parity should be maintained at the rising edge of the
clock and at the same time as command and address with CS_n LOW.
RAS_n/A16 Input Command inputs: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n) define the com-
CAS_n/A15 mand and/or address being entered and have multiple functions. For example, for activation
WE_n/A14 with ACT_n LOW, these are addresses like A16, A15, and A14, but for a non-activation com-
mand with ACT_n HIGH, these are command pins for READ, WRITE, and other commands de-
fined in Command Truth Table.
RESET_n CMOS Input Active LOW asynchronous reset: Reset is active when RESET_n is LOW and inactive when RE-
SET_n is HIGH. RESET_n must be HIGH during normal operation.
Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address range
SAx Input
on the I2C bus.
Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communication to
SCL Input
and from the temperature sensor/SPD EEPROM on the I2C bus.
DQx, CBx I/O Data input/output and check bit input/output: Bidirectional data bus. DQ represents
DQ[3:0], DQ[7:0], and DQ[15:0] for the x4, x8, and x16 configurations, respectively. If cyclic re-
dundancy checksum (CRC) is enabled via the mode register, the CRC code is added at the end of
the data burst. Any one or all of DQ0, DQ1, DQ2, or DQ3 may be used for monitoring of inter-
nal VREF level during test via mode register setting MR[4] A[4] = HIGH; training times change
when enabled.
DM_n/DBI_n/ I/O Input data mask and data bus inversion: DM_n is an input mask signal for write data. Input
TDQS_t (DMU_n, data is masked when DM_n is sampled LOW coincident with that input data during a write ac-
DBIU_n), (DML_n/ cess. DM_n is sampled on both edges of DQS. DM is multiplexed with the DBI function by the
DBIl_n) mode register A10, A11, and A12 settings in MR5. For a x8 device, the function of DM or TDQS
is enabled by the mode register A11 setting in MR1. DBI_n is an input/output identifying
whether to store/output the true or inverted data. If DBI_n is LOW, the data will be stored/
output after inversion inside the DDR4 device and not inverted if DBI_n is HIGH. TDQS is only
supported in x8 SDRAM configurations (TDQS is not valid for UDIMMs).
SDA I/O Serial Data: Bidirectional signal used to transfer data in or out of the EEPROM or EEPROM/TS
combo device.
DQS_t I/O Data strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
DQS_c tered-aligned with write data. For x16 configurations, DQSL corresponds to the data on
DQSU_t DQ[7:0], and DQSU corresponds to the data on DQ[15:8]. For the x4 and x8 configurations, DQS
DQSU_c corresponds to the data on DQ[3:0] and DQ[7:0], respectively. DDR4 SDRAM supports a differen-
DQSL_t tial data strobe only and does not support a single-ended data strobe.
DQSL_c
ALERT_n Output Alert output: Possesses functions such as CRC error flag and command and address parity error
flag as output signal. If a CRC error occurs, ALERT_n goes LOW for the period time interval and
returns HIGH. If an error occurs during a command address parity check, ALERT_n goes LOW un-
til the on-going DRAM internal recovery transaction is complete. During connectivity test mode,
this pin functions as an input. Use of this signal is system-dependent. If not connected as signal,
ALERT_n pin must be connected to VDD on DIMMs.
EVENT_n Output Temperature event: The EVENT_n pin is asserted by the temperature sensor when critical tem-
perature thresholds have been exceeded. This pin has no function (NF) on modules without
temperature sensors.

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 288-Pin DDR4 RDIMM Core
Pin Descriptions

Table 6: Pin Descriptions (Continued)

Symbol Type Description

TDQS_t Output Termination data strobe: When enabled via the mode register, the DRAM device enables the
TDQS_c same RTT termination resistance on TDQS_t and TDQS_c that is applied to DQS_t and DQS_c.
When the TDQS function is disabled via the mode register, the DM/TDQS_t pin provides the da-
(x8 DRAM-based ta mask (DM) function, and the TDQS_c pin is not used. The TDQS function must be disabled in
RDIMM only) the mode register for both the x4 and x16 configurations. The DM function is supported only in
x8 and x16 configurations. DM, DBI, and TDQS are a shared pin and are enabled/disabled by
mode register settings. For more information about TDQS, see the DDR4 DRAM component da-
ta sheet (TDQS_t and TDQS_c are not valid for UDIMMs).
VDD Supply Module power supply: 1.2V (TYP).
VPP Supply DRAM activating power supply: 2.5V –0.125V/+0.250V.
VREFCA Supply Reference voltage for control, command, and address pins.
VSS Supply Ground.
VTT Supply Power supply for termination of address, command, and control VDD/2.
VDDSPD Supply Power supply used to power the I2C bus for SPD.
RFU – Reserved for future use.
NC – No connect: No internal electrical connection is present.
NF – No function: May have internal connection present, but has no function.

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 288-Pin DDR4 RDIMM Core
General Description

General Description
High-speed DDR4 SDRAM modules use DDR4 SDRAM devices with two or four internal
memory bank groups. DDR4 SDRAM modules utilizing 4- and 8-bit-wide DDR4 SDRAM
devices have four internal bank groups consisting of four memory banks each, provid-
ing a total of 16 banks. 16-bit-wide DDR4 SDRAM devices have two internal bank
groups consisting of four memory banks each, providing a total of eight banks. DDR4
SDRAM modules benefit from the DDR4 SDRAM's use of an 8n-prefetch architecture
with an interface designed to transfer two data words per clock cycle at the I/O pins. A
single READ or WRITE operation for the DDR4 SDRAM effectively consists of a single
8n-bit-wide, four-clock data transfer at the internal DRAM core and eight correspond-
ing n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
DDR4 modules use two sets of differential signals: DQS_t and DQS_c to capture data
and CK_t and CK_c to capture commands, addresses, and control signals. Differential
clocks and data strobes ensure exceptional noise immunity for these signals and pro-
vide precise crossing points to capture input signals.

Fly-By Topology
DDR4 modules use faster clock speeds than earlier DDR technologies, making signal
quality more important than ever. For improved signal quality, the clock, control, com-
mand, and address buses have been routed in a fly-by topology, where each clock, con-
trol, command, and address pin on each DRAM is connected to a single trace and ter-
minated (rather than a tree structure, where the termination is off the module near the
connector). Inherent to fly-by topology, the timing skew between the clock and DQS sig-
nals can be accounted for by using the write-leveling feature of DDR4.

Module Manufacturing Location

Micron Technology manufactures modules at sites worldwide. Customers may receive
modules from any of the manufacturing locations listed below.

Table 7: DRAM Module Manufacturing Locations

Manufacturing Site Location Country of Origin Specified on Label

Boise, USA USA
Aguadilla, Puerto Rico Puerto Rico
Xian, China China
Singapore Singapore

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 288-Pin DDR4 RDIMM Core
Address Mapping to DRAM

Address Mapping to DRAM

Address Mirroring
To achieve optimum routing of the address bus on DDR4 multirank modules, the ad-
dress bus will be wired as shown in the table below, or mirrored. For quad-rank mod-
ules, ranks 1 and 3 are mirrored, and ranks 0 and 2 are non-mirrored. Highlighted ad-
dress pins have no secondary functions allowing for normal operation when cross-
wired. Data is still read from the same address it was written. However, LOAD MODE
operations require a specific address. This requires the controller to accommodate for a
rank that is mirrored. Systems may reference DDR4 SPD to determine whether the
module has mirroring implemented or not. See the JEDEC DDR4 SPD specification for
more details.

Table 8: Address Mirroring

Edge Connector Pin DRAM Pin, Non-Mirrored DRAM Pin, Mirrored

A0 A0 A0
A1 A1 A1
A2 A2 A2
A3 A3 A4
A4 A4 A3
A5 A5 A6
A6 A6 A5
A7 A7 A8
A8 A8 A7
A9 A9 A9
A10 A10 A10
A11 A11 A13
A13 A13 A11
A12 A12 A12
A14 A14 A14
A15 A15 A15
A16 A16 A16
A17 A17 A17
BA0 BA0 BA1
BA1 BA1 BA0
BG0 BG0 BG1
BG1 BG1 BG0

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 288-Pin DDR4 RDIMM Core
Thermal Sensor with SPD EEPROM Operation

Thermal Sensor with SPD EEPROM Operation

Thermal Sensor Operations
The integrated thermal sensor continuously monitors the temperature of the module
PCB directly below the device and updates the temperature data register. Temperature
data may be read from the bus host at any time, which provides the host real-time feed-
back of the module's temperature. Multiple programmable and read-only temperature
registers can be used to create a custom temperature-sensing solution based on system
requirements and JEDEC JC-42.2.
Note: Thermal sensor is only applicable on x72 ECC DIMMs.

EVENT_n Pin
The thermal sensor also adds the EVENT_n pin (open-drain), which requires a pull-up
to V DDSPD. EVENT_n is a thermal sensor output used to flag critical events that can be
set up in the sensor’s configuration registers. EVENT_n is not used by the serial pres-
ence-detect (SPD) EEPROM.
EVENT_n has three defined modes of operation: interrupt, comparator, and TCRIT. In
interrupt mode, the EVENT_n pin remains asserted until it is released by writing a 1 to
the clear event bit in the status register. In comparator mode, the EVENT_n pin clears
itself when the error condition is removed. Comparator mode is always used when the
temperature is compared against the TCRIT limit. In TCRIT only mode, the EVENT_n
pin is only asserted if the measured temperature exceeds the TCRIT limit; it then re-
mains asserted until the temperature drops below the TCRIT limit minus the TCRIT
hysteresis.
Note: EVENT_n is NF on DIMMs without thermal sensor.

SPD EEPROM Operation

DDR4 SDRAM modules incorporate SPD. The SPD data is stored in a 512-byte, JEDEC
JC-42.4-compliant EEPROM that is segregated into four 128-byte, write-protectable
blocks. The SPD content is aligned with these blocks as shown in the table below.
Block Range Description
0 0–127 000h–07Fh Configuration and DRAM parameters
1 128–255 080h–0FFh Module parameters
2 256–319 100h–13Fh Reserved (all bytes coded as 00h)
320–383 140h–17Fh Manufacturing information
3 384–511 180h–1FFh End-user programmable

The first 384 bytes are programmed by Micron to comply with JEDEC standard JC-45,
"Appendix X: Serial Presence Detect (SPD) for DDR4 SDRAM Modules." The remaining
128 bytes of storage are available for use by the customer.
The EEPROM resides on a two-wire I2C serial interface and is not integrated with the
memory bus in any manner. It operates as a slave device in the I2C bus protocol, with all
operations synchronized by the serial clock. Transfer rates of up to 1 MHz are achieva-
ble at 2.5V (NOM).

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 288-Pin DDR4 RDIMM Core
Registering Clock Driver Operation

Micron implements reversible software write protection on DDR4 SDRAM-based mod-

ules. This prevents the lower 384 bytes (bytes 0 to 383) from being inadvertently pro-
grammed or corrupted. The upper 128 bytes remain available for customer use and are
unprotected.

Registering Clock Driver Operation

Registered DDR4 SDRAM modules use a registering clock driver device consisting of a
register and a phase-lock loop (PLL). The device complies with the JEDEC DDR4 RCD
specification.
To reduce the electrical load on the host memory controller's command, address, and
control bus, Micron's RDIMMs use a DDR4 registering clock driver (RCD). The RCD
presents a single load to the controller while redriving signals to the DDR4 SDRAM de-
vices, which helps enable higher densities and increase signal integrity. The RCD also
provides a low-jitter, low-skew PLL that redistributes a differential clock pair to multiple
differential pairs of clock outputs.

Control Words
The RCD device(s) used on DDR4 RDIMMs, LRDIMMs, and NVDIMMs contain configu-
ration registers known as control words, which the host uses to configure the RCD
based on criteria determined by the module design. Control words can be set by the
host controller through either the DRAM address and control bus or the I2C bus inter-
face. The RCD I 2C bus interface resides on the same I2C bus interface as the module
temperature sensor and EEPROM.

Parity Operations
The RCD includes a parity-checking function that can be enabled or disabled in control
word RC0E. The RCD receives a parity bit at the DPAR input from the memory control-
ler and compares it with the data received on the qualified command and address in-
puts; it indicates on its open-drain ALERT_n pin whether a parity error has occurred. If
parity checking is enabled, the RCD forwards commands to the SDRAM when no parity
error has occurred. If the parity error function is disabled, the RCD forwards sampled
commands to the SDRAM regardless of whether a parity error has occurred. Parity is al-
so checked during control word WRITE operations unless parity checking is disabled.

Rank Addressing
The chip select pins (CS_n) on Micron's modules are used to select a specific rank of
DRAM. The RDIMM is capable of selecting ranks in one of three different operating
modes, dependent on setting DA[1:0] bits in the DIMM configuration control word lo-
cated within the RCD. Direct DualCS mode is utilized for single- or dual-rank modules.
For quad-rank modules, either direct or encoded QuadCS mode is used.

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 288-Pin DDR4 RDIMM Core
Electrical Specifications

Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other condi-
tions outside those indicated in each device's data sheet is not implied. Exposure to ab-
solute maximum rating conditions for extended periods may adversely affect reliability.

Table 9: Absolute Maximum Ratings

Symbol Parameter Min Max Units Notes

VDD VDD supply voltage relative to VSS –0.4 1.5 V 1
VDDQ VDDQ supply voltage relative to VSS –0.4 1.5 V 1
VPP Voltage on VPP pin relative to VSS –0.4 3.0 V 2
VIN, VOUT Voltage on any pin relative to VSS –0.4 1.5 V

Table 10: Operating Conditions

Symbol Parameter Min Nom Max Units Notes

VDD VDD supply voltage 1.14 1.20 1.26 V 1
VPP DRAM activating power supply 2.375 2.5 2.75 V 2
VREFCA(DC) Input reference voltage – 0.49 × VDD 0.5 × VDD 0.51 × VDD V 3
command/address bus
IVTT Termination reference current from VTT –750 – 750 mA
VTT Termination reference voltage (DC) – 0.49 × VDD - 0.5 × VDD 0.51 × VDD + V 4
command/address bus 20mV 20mV
IIN Input leakage current; any input excluding ZQ; 0V < –5 – 5 µA 5, 8
VIN < 1.1V
IZQ Input leakage current; ZQ –50 – 10 µA 6
IOZpd Output leakage current; VOUT = VDD; DQ is High-Z – – 10 µA 7
IOZpu Output leakage current; VOUT = VSS; DQ is High-Z; –50 – – µA 7
ODT is disabled with ODT input HIGH
IVREFCA VREFCA leakage; VREFCA = VDD/2 (after DRAM is ini- –4.5 – 4.5 µA 8
tialized)

Notes: 1. VDDQ balls on DRAM are tied to VDD.

2. VPP must be greater than or equal to VDD at all times.
3. VREFCA must not be greater than 0.6 × VDD. When VDD is less than 500mV, VREF may be
less than or equal to 300mV.
4. VTT termination voltages in excess of specification limit adversely affect command and
address signals' voltage margins and reduce timing margins.
5. Command and address inputs are terminated to VDD/2 in the registering clock driver. In-
put current is dependent on termination resistance set in the registering clock driver.
6. Tied to ground. Not connected to edge connector.
7. Multiply by the number of module ranks and then by the number of die per package.
8. RCD input current.

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 288-Pin DDR4 RDIMM Core
Electrical Specifications

Table 11: Thermal Characteristics

Symbol Parameter/Condition Value Units Notes

TC Commercial operating case temperature 0 to 85 °C 1, 2, 3
TC >85 to 95 °C 1, 2, 3, 4
TC Industrial operating case temperature -40 to 85 °C 1, 2, 3
TC >85 to 95 °C 1, 2, 3, 4
TOPER Normal operating temperature range 0 to 85 °C 5, 7, 8
TOPER Extended temperature operating range (optional) >85 to 95 °C 5, 8
TSTG Non-operating storage temperature –55 to 100 °C 6
RHSTG Non-operating storage relative humidity (non-condensing) 5 to 95 %
NA Change rate of storage temperature 20 °C/hour

Notes: 1. Maximum operating case temperature; TC is measured in the center of the package.
2. A thermal solution must be designed to ensure the DRAM device does not exceed the
maximum TC during operation.
3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC dur-
ing operation.
4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2X refresh, which is a 3.9µs
interval refresh rate.
5. The refresh rate must double when 85°C < TOPER ≤ 95°C.
6. Storage temperature is defined as the temperature of the top/center of the DRAM and
does not reflect the storage temperatures of shipping trays.
7. The normal temperature range specifies the temperatures at which all DRAM specifica-
tions will be supported. During operation, the DRAM case temperature must be main-
tained between 0°C and 85°C under all operating conditions for the commercial offer-
ring; The industrial temperature offering allows the case temperature to go below 0°C
to -40°C
8. For additional information, refer to technical note TN-00-08: "Thermal Applications"
available at micron.com.

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 288-Pin DDR4 RDIMM Core
DRAM Operating Conditions

DRAM Operating Conditions

Recommended AC operating conditions are given in the DDR4 component data sheets.
Component specifications are available at micron.com. Module speed grades correlate
with component speed grades, as shown below.

Table 12: Module and Component Speed Grades

DDR4 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade Component Speed Grade
-3G2 -062E
-3S2 -062H (3DS)
-2G9 -068
-2S9 -068H (3DS)
-2G6 -075
-2S6 -075H (3DS)

Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully de-
signed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level. Mi-
cron encourages designers to simulate the signal characteristics of the system's memo-
ry bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the edge connector of the module, not at the DRAM.
Designers must account for any system voltage drops at anticipated power levels to en-
sure the required supply voltage is maintained.

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 288-Pin DDR4 RDIMM Core
Thermal Sensor with SPD EEPROM Operating Conditions

Thermal Sensor with SPD EEPROM Operating Conditions

The thermal sensor continuously monitors the module's temperature and can be read
back at any time over the I2C bus shared with the serial presence-detect (SPD) EE-
PROM. Refer to JEDEC JC-42.4 EE1004 and TSE2004 device specifications for complete
details.
Note: Integrated thermal sensor only applicable to x72 ECC DIMMs. The following
AC/DC operating condition specifications apply both to devices that do contain the in-
tegrated thermal sensor and devices that do not include the thermal sensor.

SPD Data
For the latest SPD data, refer to Micron's SPD page: micron.com/SPD.

Table 13: Thermal Sensor with SPD EEPROM DC Operating Conditions

Parameter/Condition Symbol Min Nom Max Units

Supply voltage VDDSPD 1.7 2.5 3.3 V
Input low voltage: Logic 0; All inputs VIL –0.5 – VDDSPD × 0.3 V
Input high voltage: Logic 1; All inputs VIH VDDSPD × 0.7 – VDDSPD + 0.5 V
Output low voltage: 3mA sink current VDDSPD > 2V VOL – – 0.4 V
Input leakage current: (SCL, SDA) VIN = VDDSPD or VSSSPD ILI – – ±5 µA
Output leakage current: VOUT = VDDSPD or VSSSPD, SDA in High-Z ILO – – ±5 µA

Notes: 1. Table is provided as a general reference. Consult JEDEC JC-42.4 TSE2004 device specifica-
tions for complete details.
2. Operation at tSCL > 100 kHz may require VDDSPD ≤ 2.2.
3. All voltages referenced to VDDSPD.

Table 14: Thermal Sensor with SPD EEPROM AC Operating Conditions

Parameter/Condition Symbol Min Max Units

Clock frequency fSCL 10 1000 kHz
Clock pulse width HIGH time tHIGH 260 – ns
Clock pulse width LOW time tLOW 500 – ns
Detect clock LOW timeout tTIMEOUT 25 35 ms
SDA rise time tR – 120 ns
SDA fall time tF – 120 ns
Data-in setup time tSU:DAT 50 – ns
Data-in hold time tHD:DI 0 – ns
Data out hold time tHD:DAT 0 350 ns
Start condition setup time tSU:STA 260 – ns
Start condition hold time tHD:STA 260 – ns
Stop condition setup time tSU:STO 260 – ns
Time the bus must be free before a new transi- tBUF 500 – ns
tion can start
Write time tW – 5 ms

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 288-Pin DDR4 RDIMM Core
Thermal Sensor with SPD EEPROM Operating Conditions

Table 14: Thermal Sensor with SPD EEPROM AC Operating Conditions (Continued)

Parameter/Condition Symbol Min Max Units

Warm power cycle time off tPOFF 1 – ms
Time from power-on to first command tINIT 10 – ms

Notes: 1. Table is provided as a general reference. Consult JEDEC JC-42.4 TSE2004 device specifica-
tions for complete details.
2. Operation at fSCL > 100 kHz may require VDDSPD ≤ 2.2.

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 288-Pin DDR4 RDIMM Core
Registering Clock Driver Specifications

Registering Clock Driver Specifications

Table 15: Registering Clock Driver Electrical Characteristics

DDR4 RCD01 devices or equivalent
Parameter Symbol Pins Min Nom Max Units
DC supply voltage VDD – 1.14 1.2 1.26 V
DC reference voltage VREF VREFCA 0.49 × VDD 0.5 × VDD 0.51 × VDD V
DC termination VTT – VREF - 40mV VREF VREF + 40mV V
voltage
High-level input VIH. CMOS DRST_n 0.65 × VDD – VDD V
voltage
Low-level input VIL. CMOS 0 – 0.35 × VDD V
voltage
DRST_n pulse width tIN- – 1.0 – – µs
IT_Pow-
er_stable
AC high-level output VOH(AC) All outputs except VTT + (0.15 × VDD) – – V
voltage ALERT_n
AC low-level output VOL(AC) – – VTT + (0.15 × VDD) V
voltage
AC differential out- VOHdiff(AC) Yn_t - Yn_c, BCK_t - – 0.3 × VDD – mV
put high measure- BCK_c
ment level (for out-
put slew rate)
AC differential out- VOLdiff(AC) – –0.3 × VDD – mV
put low measure-
ment level (for out-
put slew rate)

Note: 1. Timing and switching specifications for the register listed are critical for proper opera-
tion of DDR4 SDRAM RDIMMs. These are meant to be a subset of the parameters for the
specific device used on the module. See the JEDEC RCD01 specification for complete op-
erating electrical characteristics. Registering clock driver parametric values are specified
for device default control word settings, unless otherwise stated. The RC0A control
word setting does not affect parametric values.

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 288-Pin DDR4 RDIMM Core
Module Dimensions

Module Dimensions

Figure 1: 288-Pin DDR4 RDIMM

Front view
133.35 ± 0.15

See MPN-specific data sheet addendum for component placement 31.25 ± 0.15
1.50
TYP

Pin 1 4.30
0.85 0.60 TYP
TYP TYP Pin 144
1.4
MAX
Back view

See MPN-specific data sheet addendum for component placement 3.0 (4X) TYP

14.6
TYP
8.0
TYP
0.5 TYP
Pin 288 Pin 145
5.95 TYP
1.4 ± 0.1
56.1 64.6
TYP TYP
Max Component thickness
same if mounted on both sides

Notes: 1. All dimensions are in millimeters; MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to JEDEC MO-309.

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 288-Pin DDR4 RDIMM Core
Module Dimensions

Figure 2: 288-Pin DDR4 VLP RDIMM

Front view
133.35 ± 0.15

See MPN-specific data sheet addendum for component placement 18.75 ± 0.15
1.50 TYP

1.4
MAX
Pin 1 4.30 Pin 144
0.85 0.60 TYP
TYP TYP

Back view

14.6 See MPN-specific data sheet addendum for component placement 3.0 2X TYP
TYP
8.0
TYP
0.5 TYP 1.4 ± 0.1
Pin 288 Pin 145 Max Component thickness
5.95 TYP
56.1 64.6 same if mounted on both sides
TYP TYP

Notes: 1. All dimensions are in millimeters; MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to JEDEC MO-309.

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 288-Pin DDR4 RDIMM Core
Module Dimensions

Figure 3: 288-Pin DDR4 MiniRDIMM

Front view
80.0 ± 0.15

30.0 ± 0.15
See MPN-specific data sheet addendum for component placement

1.25
MAX

PIN 1 PIN 144 0.5 TYP

0.35 TYP 1.0 TYP 0.5 TYP

Back view

1.4 ± 0.1
Max component thickness
same if mounted on both sides
See MPN-specific data sheet addendum for component placement
3.0 TYP (2X)

9.0
TYP
3.85 TYP

PIN 288 2.5 PIN 145

2.6 (0.102) TYP
TYP
32.0 TYP 39.0 TYP

Notes: 1. All dimensions are in millimeters; MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to JEDEC MO-314.

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 288-Pin DDR4 RDIMM Core
Module Dimensions

Figure 4: 288-Pin DDR4 VLP MiniRDIMM

Front view
80.0 ± 0.15

See MPN-specific data sheet addendum for component placement 18.75 ± 0.15

PIN 1 PIN 144 0.5 TYP

0.35 1.0 0.5
TYP TYP TYP
1.25
MAX
Back view

See MPN-specific data sheet addendum for component placement 3.0 TYP (2X)

9.0
TYP
3.85 TYP 1.4 ± 0.1
Max component thickness
PIN 288 2.5 PIN 145 same if mounted on both sides
2.6 TYP
TYP
32.0 39.0
TYP TYP

Notes: 1. All dimensions are in millimeters; MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to JEDEC MO-314.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000

www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.

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