® TDA7427

AM-FM RADIO FREQUENCY SYNTHESIZER

AND IF COUNTER

ON-CHIP REFERENCE OSCILLATOR AND

PROGRAMMABLE IF COUNTER
VHF INPUT AND PRECOUNTER FOR FRE-
QUENCIES UP TO 290MHz (SUITABLE FOR
DAB APPLICATION)
HF INPUT FOR FREQUENCIES UP TO
64MHz (SHORT WAVE BAND) DIP20 SO20
IN-LOCK DETECTOR FOR SEARCH/STOP
STATION FUNCTION
STAND-BY MODE FOR LOW POWER CON- ORDERING NUMBERS: TDA7427(DIP20)
SUMPTION TDA7427D (SO20)
HIGH CURRENT SOURCE FOR 0.5ms
LOCK-IN TIME
DIGITAL PORT EXTENSION WITH TWO
OUTPUTS FOR FLEXIBILITY IN APPLICA-
TION with an additional IF counting system that per-
FULLY PROGRAMMABLE BY I2C BUS forms all the functions needed in a complete PLL
radio tuning system for conventional and high
speed RDS tuners. The device has dedicated out-
DESCRIPTION puts for IN-LOCK detection and Search/Stop sta-
The TDA7427 is a PLL frequency synthesizer tion.

BLOCK DIAGRAM

13
DOUT1/INLOCK
16 2
FM_IN LP_HC
SWITCH PRECOUNTER 5 BIT PROG. 3
AM/FM :32/33 CNT INLOCK
SWITCH LP_AM
14 DETECTOR 1
HFREF LP1/LP2 LP_FM

SWITCH SWITCH
17 SWM/DIR SWM/DIR
AM_IN
PHASE CHARGE - 20
LPOUT
COMP PUMP +
11 BIT PROG VDD1
CNT
5
OSCIN REF 16 BIT PROG
6
OSCOUT OSCILLATOR CNT 4
VREF

8
SCL I2C BUS 18
9 GNDan/GNDdig
SDA INTERFACE

19
VDD2 14 BIT PROG TEST POWER ON
TIMER CONTROL
15 CNT LOGIC RESET
VDD1

10
IF_AM
11-21 BIT PROG CNT PORT EXTENSION
11
IF_FM

12 7
D95AU418B SSTOP DOUT3

November 1999 1/21

TDA7427

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit
VDD1 Supply Voltage - 0.3 to + 7 V
VDD2 Supply Voltage - 0.3 to + 11 V
Ptot Total Power Dissipation 300 mW
o
Tstg Storage Temperature - 55 to + 150 C
o
Tamb Ambient Temperature -40 to + 85 C

PIN CONNECTION

LP_FM 1 20 LPOUT
LP_HC 2 19 VDD2
LP_AM 3 18 GND
VREF 4 17 AM_IN
OSCIN 5 16 FM_IN
OSCOUT 6 15 VDD1
DOUT3 7 14 HFREF
SCL 8 13 DOUT1/INLOCK
SDA 9 12 SSTOP
IF_AM 10 11 IF_FM
D95AU373B

THERMAL DATA
Symbol Parameter DIP20 SO20 Unit
o
Rth j-amb Thermal Resistance Junction-Ambient max 100 150 C/W

2/21
 TDA7427

PIN DESCRIPTION (TDA7427/D)

PIN SYMBOL DESCRIPTION INPUT/OUTPUT

1 LP_FM Filter OPAMP input, charge pump output (FM mode)
Filter OPAMP input, charge pump output (high current
2 LP_HC
mode)
3 LP_AM Filter OPAMP input, charge pump output (AM mode)
4 VREF OPAMP reference voltage
5 OSCIN Oscillator reference clock input
6 OSCOUT Oscillator output
7 DOUT3 Open collector output
8 SCL I2C bus clock input Input
9 SDA I2C bus data I/O Input/output
10 IF_AM IF counter input (AM mode) Analog input
11 IF_FM IF counter input (FM mode) Analog input
12 SSTOP IF counter result output Output
13* DOUT1 Digital output Push-pull output
13* INLOCK Inlock detector output Output
14 HFREF HF reference
15 VDD1 Positive power supply 5V Supply
16 FM_IN High frequency input FM Analog input
17 AM_IN High frequency input AM Analog input
18 GND Analog digital ground Supply
19 VDD2 Positive power supply 10V Supply
20 LPOUT Filter input, change pump output
* Pin function is userdefined by software

3/21
TDA7427

ELECTRICAL CHARACTERISTICS (Tamb = 25°C; VDD1 = 5V; VDD2 = 10V; fOSC = 4MHz; unless other-
wise specified).
Symbol Parameter Test Condition Min. Typ. Max. Unit
VDD1 Supply Voltage 4.5 5.0 5.5 V
VDD2 Supply Voltage 9.0 11.0 V
IDD1 Supply Current no output load 2 4 6 mA
IDD2 Supply Current PLL locked 1 2 3 mA
IDD1 STB Supply Current Standby mode 1 µA
RF INPUT (AM_IN, FM_IN)
fiAM Input Frequency AM Vi = 100mVrms sinusoidal 0.5 64 MHz
fiFM Input Frequency FM Vi = 100mVrms sinusoidal 30 200 MHz
ViMIN Min Input Voltage AM 0.5 to 16MHz range sinusoidal 30 mVrms
ViMAX Max Input Voltage AM 0.6 to 16MHz range sinusoidal 600 mVrms
ViMIN Min Input Voltage FM 70 to 120MHz range sinusoidal 30 mVrms
ViMAX Max Input Voltage FM 70 to 120MHz range sinusoidal 600 mVrms
Zin Input Impedance FM input 3 4 5 KΩ
Zin Input Impedance AM input 3 4 5 KΩ
IF COUNTER (IF_AM, IF_FM)
fiAM Input Frequency range AM Vi = 100mVrms 0.400 11 MHz
fiAM Input Frequency range FM Vi = 100mVrms 10 11 MHz
ViMIN Min Input Voltage AM IF pin fin = 455kHz 30 mVrms
ViMIN Min Input Voltage FM IF pin fin = 10.7MHz 30 mVrms
ViMAX Max Input Voltage AM IF pin fin = 455kHz 600 mVrms
ViMAX Max Input Voltage FM IF pin fin = 10.7MHz 600 mVrms
Zin Input Inpedance FM IF pin 3 4 5 KΩ
Zin Input Inpedance AM IF pin 3 4 5 KΩ
BUS INTERFACE
Tj Noise Suppression Time 50 ns
Constant on SCL, SDA Input
fSCL SCL Clock Frequency 400 kHz
tAA SCL Low to SDA Data Valid 300 ns
tbuf Time the bus must be free for 4.7 µs
the new transmission
tHD-START START Condition hold time 4.0 µs
tLOW Clock Low Period 4.7 µs
tHIGH Clock High Period 4.0 µs
tSU-SDA Start Condition Setup Time 4.7 µs
tHD-DATA Data Input Hold Time 1 µs
tSU-DATA Data Input Setup Time 250 ns
tR SDA & SCL Rise Time 1 µs
tF SDA & SCL Full Time 0.3 µs
tSU-STOP Stop Condition Setup Time 4.7 µs
tDH DATA OUT Time 300 ns

4/21
 TDA7427

ELECTRICAL CHARACTERISTICS (continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit
VIL Input Low Voltage 1 V
VIH Input High Voltage 3 V
IIN Input Current -5 +5 µA
VOUT Output Voltage SDA IO = 1.6mA 0.15 0.4 V
acknowledge
OSCILLATOR
tbu Build Up Time fout = 4MHz 100 ms
Cin Internal Capacitance 20 pF
COUT Internal Capacitance fosc = 4MHz 20 pF
Zin Input Impedance fosc = 4MHz 100 KΩ
Vin Input Voltage (for Slave Mode) fIN = 4 to 13MHz (Sinus) 300 VDD mVpp
capacitance coupling
fin Max Input frequency (for Slave VIN = 600mVPP (Sinus) 30 MHz
Mode)
LOOP FILTER (LP_FM, LP_AM, LP_HC, LP_OUT)
IIN Input Leakage Current (*) VIN = GND; PDout = Tristate (1) -1 0.1 1 µA
IIN Input Leakage Current (*) VIN = VDD1; PDout = Tristate (1) -1 0.1 1 µA
VOL Output Voltage Low IOUT = -0.2mA 0 0.5 V
VOH Output Voltage High IOUT = 0.2mA 9.5 10 V
IOUT Output Current Sink 10 30 mA
IOUT Output Current Source VOUT = 0.5 to 9.5V 10 30 mA
DOUT1/SSTOP (push-pull outputs)
VOL Output Voltage Low IOUT = -0.1mA 0.1 0.2 V
VOH Output Voltage High IOUT = 0.1mA VDD1*0.2 4.9 V
DOUT3 (open collector output)
IOUT Output leakage Current VOUT = 10V -1 0.1 1 mA
VOL Output Voltage Low IOUT = -1mA 0.2 0.5 V
IOUT Output Current Sink VOUT = 0.5 to 9.5V 3 5 mA
1) PD = Phase Detector
(*) LP_FM and LP_HC pins only

5/21
TDA7427

GENERAL DESCRIPTION To minimize the noise induced by the digital part

This circuit contains a frequency synthesiser and of the system, a separate power supply supplies
a loop filter for use in FM/AM radio tuning sys- the internal loop filter amplifier. The loop gain can
tems. Only a VCO is required to build a complete be set for different conditions by setting the cur-
PLL system. For auto search/stop operation an IF rent values of the charge/pump generator.
counter system is available.
For FM and SW AM application, the counter IF COUNTER SYSTEM
works in a two-stage configuration. The first stage
is a swallow counter with a two modulus (:32/33) Two separate inputs are available for AM and FM
precounter. The second stage is an 11-bit pro- IF signals. The level of integration is adjustable
grammable counter. by six different measuring cycle times.
For LW and MW application, a 16-bit programma- The tolerance of the accepted count value is ad-
ble counter is available. justable, to reach an optimum compromise for
The circuit receives the scaling factors for the pro- search speed and precision of the evaluation.
grammable counters and the values of the refer- For the FM range the center frequency of the
ence frequencies via a I2C bus interface. measured count value is adjustable in 32 steps,
The reference frequency is generated by an inter- to get the possibility of fitting the IF filter toler-
nal XTAL oscillator followed by the reference di- ance. In the AM range an IF frequency of 448 to
vider. The device can operate with XTAL oscilla- 479KHz ( 10.684 to 10.715MHz for AM up-con-
tor between 4 and 13MHz either in master mode version) with 1KHz steps is available.
and in slave mode.
The reference and step frequencies are free se- PLL FREQUENCY SYNTHESIZER
lectable. (XTAL frequency divided by an integer
value). The outputs signals of the phase detector Input Amplifiers
are switching the programmable current sources. The signals applied on AM and FM inputs are am-
The loop filter integrates their currents to a DC plified to get a logic level in order to drive the fre-
voltage. quency dividers.
The typical input impedance for FM and AM in-
Values of the current sources are programmable puts is 4kΩ.
by 6 bits also received via the I2C bus.

Table 1. Address Organization

MSB LSB
FUNCTION SUBAD BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PLL CHARGE PUMP 00H LPIN1/2 CURRH B1 B0 A3 A2 A1 A0

PLL COUNTER 01H PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

PLL COUNTER 02H PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8

PLL REF COUNTER 03H RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0

PLL REF COUNTER 04H RC15 RC14 RC13 RC12 RC11 RC10 RC9 RC8

PLL LOCK DETECT 05H LDENA INLOCK D3 D2 D1 D0 PM1 PM0

IFC REF COUNTER 06H IRC7 IRC6 IRC5 IRC4 IRC3 IRC2 IRC1 IRC0

IFC REF COUNTER 07H IFCM1 IFCM0 IRC13 IRC12 IRC11 IRC10 IRC9 IRC8

IFC CONTROL 08H IFENA - - - - EW2 EW1 EW0

IFC CONTROL 09H IFS2 IFS1 IFS0 CF4 CF3 CF2 CF1 CF0

OSC ADJUST 0AH - - - OSC4 OSC3 OSC2 OSC1 OSC0

PORT EXTENSION 0BH - - - - - DOUT3 - DOUT1

6/21
 TDA7427

Figure 1. FM and AM (SW) operation (swallow mode)

REGISTER
OSC IN R0 ...R15 fref ∆ϕ
PD TO CHARGE
PREDIVIDER fsyn PUMP
:R

REGISTER
PC0 ...PC4

COUNTER
AM IN A
REGISTER
PC5 ... P15

PRESCALER COUNTER
M/M+1 :B

FM IN
D95AU375A

Table 2. Control Register Functions.

REGISTER NAME FUNCTION

PC Programmable counter for VCO frequency
RC Reference counter PLL
IRC Reference counter IF
IFCM IF counter mode selector
EW Frequency error window IF counter
IFENA Enable IFRC
CF Center frequency IF counter
IFS Sampling time IF counter
PM Stby, FM, AM, AM swallow mode selector
D Programmable delay and phase error for lock detector
LPIN1/2 Loop filter input select
PLLSTOP PLL stop
A Charge pump high current
B Charge pump low current
LDENA Lock detector enable
CURRH Set current high
OSC Oscillator adjust
DOUT1 Push pull output 5V
DOUT3 Open collector output
INLOCK Lock detector output

7/21
TDA7427

Figure 2. AM direct mode operation for SW, MW and LW

PREDIVIDER
OSC IN :R fref ∆ϕ
PHASE
TO CHARGE
DETECTOR
REGISTER PUMP
fsyn
RC0 ... RC15

AM IN REGISTER
PC0 ... PC15

PRESCALER
:C
FM IN

D95AU376A

DIVIDER FROM VCO FREQUENCY TO Dividing range calculation :

REFERENCE FREQUENCY
fVCO = [ 33 ⋅ A + (B + 1 - A) ⋅ 32 ] ⋅ fREF
This divider provides a low frequency fSYN which fVCO = (32 ⋅ B + A + 32) ⋅ fREF
phase is compared with the reference frequency
fREF. It is controlled by the registers PC0 to PC4 Important: for correct operation A ≤ 32, B ≥ A, with
and PC5 to PC15 A and B variable values of the dividers).

OPERATING MODES - AM direct mode: the AM signal is applied di-

Four operating modes are available fo PLL; they rectly to the 16 bit static divider ’C’. (PC0 to
are user programmable with the Mode PM regis- PC15)
ters (see table):
fOSC = (R + 1) ⋅ f REF
PM0 PM1 Operating Mode Dividing range:
0 0 Standby
1 0 AM (swallow)
fVCO = (C + 1) ⋅ fREF
0 1 AM (direct)
1 1 FM THREE STATE PHASE COMPARATOR
The phase comparator generates a phase error
signal according to phase difference between
fSYN and fREF. This phase error signal drives the
- Standby mode: in this mode all device func-
charge pump current generator (fig. 3)
tions are stopped. This allows low current
consumption without loss of information in all
registers. The pin LP-OUT is forced to 0V, CHARGE PUMP CURRENT GENERATOR
and all data registers are set to EFH. The os-
cillator keeps running. This stage generates signed pulses of current.
The phase error signal decides the duration and
polarity of those pulses.
- FM and AM (SW) Swallow Mode (SW):
in this mode the FM or AM signal is applied to The current absolute values are programmable by
a 32/33 prescaler, which is controlled by a 5 A0, A1, A2 registers for high current and B0, B1,
bit divider ’A’.The 5 bit register (PC0 to PC4) registers for low current.
controls this divider. In parallel the output of
the prescaler is connected to a 11 bit divider LOW NOISE CMOS OP-AMP
’B’. (PC5 to PC15).
An internal voltage divider at pin VREF connects
fOSC = (R+1)⋅ fREF the positive input of the low noise Op-Amp. The
charge pump output connects the negative input.
This internal amplifier in cooperation with external
components can provide an active filter.
8/21
 TDA7427

Figure 3. Phase comparator waveforms

Figure 4. IF Counter internal block diagram

IFENA
EW-REGISTER

IF-AM
11-21 BIT COUNTER ZD

CF-REGISTER UP/DOWN COUNTER

IF-FM

OSC 14 BIT COUNTER 3 BIT COUNTER

DECODE SSTOP

IFC-REGISTER IFS-REGISTER
D95AU377A

9/21
TDA7427

The negative input is switchable to three input mode a 1KHz signal is generated. This is followed
pins ( LPIN 1, LPIN 2 and LPIN 3) to increase the by an asynchronous divider to generate different
flexibility in application. This feature allows two sampling times (see fig. 4).
separate active filters for different applications
A logical "1" in the LPIN 1/2 register activates Intermediate Frequency Main Counter
pin LPIN 1, otherwise pin LPIN 2 is active. While This counter is a 11/21 bits synchronous autore-
the high current mode is activated LPIN 3 is load down-counter. Four bits are programmable
switched on. to have the possibility for an adjust to the fre-
quency of the CF filter. The counter length is
INLOCK DETECTOR automatically adjusted to the chosen sampling
time and the counter mode (AM, FM, AM-UPC).
The charge pump can be switched in low current At the start the counter will be loaded with a de-
mode either via software or automatically by the fined value which is an equivalent to the divider
inlock detector by setting bit LDENA to "1". value (tsample ⋅ fIF).
The charge pump is forced in low current mode If a correct frequency is applied to the IF counter
when a phase difference of 10-40 nsec is frequency inputs IF-AM IF-FM, at the end of the
reached. sampling time the main counter is changing its
A phase difference larger then the programmed state from 0 H to 1FFFFFH.
values will switch the charge pump immediately in This is detected by a control logic. The frequency
the high current mode. range inside which a successful count results is
detected is adjustable by bits EW 0,1,2.
Programmable delays are available for inlock de-
tection.
Adjustment of the Measurement Sequence
Time
IF COUNTER SYSTEM (AM/FM/AM - UPC MODES) The precision of the measurements is adjustable
The if counter works in modes controlled by IFCM by controlling the discrimination window .
register (see table): This is adjustable by programming the control
registers EW0...EW2.
IFCM1 IFCM0 FUNCTION The measurement time per cycle is adjustable by
0 0 NOT USED setting the Register IFS0 - IFS2.
0 1 FM MODE
1 0 AM MODE Adjust of the Frequency Value
The center frequency of the discrimination win-
10.7MHz AM UP
1 1 dow is adjustable by the control register "CF0" to
CONVERSION MODE
"CF4". (see data byte specification).
Typical input impedance for IF inputs is 4KΩ.
A sample timer to generate the gate signal for the Port Extension and additional functions
main counter is build with a 14-bit programmable One digital open collector output and one digital
counter to have the possibility to use any crystal push-pull output are available in application
oscillator frequency. In FM mode 6.25KHz in AM mode. This digital ports are controlled by the data
bits DOUT1 and DOUT3.
Figure 5. I2C Bus timing diagram
tHIGH tR tLOW tR

SCL
tSU-STA tHD-DAT tSUBTOP
tSD-DAT
tHD-STA

SDA IN

tAA tDH ttxt

SDA OUT
D95AU378

10/21
 TDA7427

I2C BUS INTERFACE DESCRIPTION ter will release the bus after sending 8 bit of data.
During the 9th clock cycle the receiver will pull the
The TDA7427 supports the I2C bus protocol. This SDA line to LOW level to indicate it has receive
protocol defines any device that sends data into the eight bits of data correctly.
the bus as a transmitter and the receiving device
as the receiver. The device that controls the
transfer is the master and the device being con- Data transfer
trolled is the slave. The master always initiates During data transfer the TDA7427 samples the
data transfer and provides the clock to transmit or SDA line on the leading edge of the SCL clock.
receive operations. Therefore, for proper device operation the SDA
line must be stable during the SCL LOW to HIGH
Data Transition transition.
Data transition on the SDA line must only occur
when the clock SCL is low. SDA transitions while Device Addressing
SCL is high will be interpreted as START or To start the communication between two devices,
STOP condition. the bus master must initiate a start instruction se-
quence, followed by an eight bit word correspond-
Start Condition ing to the address of the device it is addressing.
A start condition is defined by a HIGH to LOW The most significant 6 bits of the slave address
transition of the SDA line while SCL is at a stable are the device type identifier.
HIGH level. This START condition must precede The TDA7427 frequency synthesizer device type
any command and initiate a data transfer onto the is fixed as "110001"
bus. The TDA7427 continuously monitors the The next significant bit is used to address a par-
SDA and SCL lines for a valid START and will not ticular device of the previous defined type con-
response to any command if this condition has nected to the bus. The state of the hardwired A0
not been met. pin defines the state of this address bit. So up to
two devices could be connected on the same bus.
The last bit of the instruction defines the type of
Stop Condition operation to be performed:
A STOP condition is defined by a LOW to HIGH
transition of the SDA while the SCL line is at a stable - When set to "1", a read operation is selected
HIGH level. This condition terminate the communica- - When set to "0", a write operation is selected
tion between the devices and forces the bus interface
of the TDA7427 into the initial condition. The chip selection is accomplished by setting the
bit of the chip address to the corresponding status
Acknowledge of the A0 input.
All TDA7427 connected to the bus will compare
Indicates a successful data transfer. The transmit- their own hardwired address with the slave ad-

Figure 6. Application with two loop filters

FM VCO

+10V AM VCO
10µF 100nF AM-FM
IF
1nF 10nF
VDD1 3.9K 100nF 3.3nF
10nF 10nF
VDD2 IF_AM IF_FM FM_IN AM_IN 820Ω
19 10 11 16 17 Utun
SCL 20
8 LPOUT 1nF
CONTROLLER
SDA
9
1
LP_FM 27K FM:50KHz
6.8nF
TDA7427 2
LP_HC 15K
VDD1
+5V 15 LP_AM 100K
3
100nF 10µF
68nF
AM:1KHz
VREF 6.8nF
4
INLOCK/DOUT1
100nF 13
SSTOP
12
5 6 14 7
OSCIN OSCOUT HFREF DOUT3
4MHz
10nF
D95AU379B

11/21
TDA7427

dress being transmitted. following words transmitted to the TDA7427 will

After this comparison, the TDA7427 will generate be considered as Data. The internal address will
an "acknowledge" on the SDA line and will per- be automatically incremented. After each word re-
form either a read or write operation according to ceipt the TDA7427 will answer with an "acknow-
the state of R/W bit. ledge".

Write Operation SOFTWARE SPECIFICATION

Following a START condition the master sends a I2C Protocol
slave address word with the R/W bit set to "0". The interface protocol comprises:
The TDA7427 will "acknowledge" after this first A start condition (s)
transmission and wait for a second word (the
word address field). A chip address byte (the LSB determines
This 8 bit address field provides an access to any read/write transmission)
of the 8 internal addresses. Upon receipt of the A sub-address byte.
word address the TDA7427 slave device will re- A sequence of data (N-bytes + acknowledge)
spond with an "acknowledge". At this time, all the A stop condition (P)

CHIP ADDRESS SUBADDRESS DATA 1 to DATA n

MSB LSB MSB LSB MSB LSB

S 1 1 0 0 0 1 0 R/W ACK T T T I A3 A2 A1 A0 ACK DATA ACK P

ACK = Acknowledge
S = Start
P = Stop
I = Auto Increment
T = used for testing (in application mode they have to be " 0")
MAX CLOCK SPEED 400kbits/s

CHIP ADDRESS
MSB LSB
1 1 0 0 0 1 0 0

SUBADDRESS
MSB LSB FUNCTION
T3 T2 T1 I A3 A2 A1 A0
0 0 0 0 Charge pump control
0 0 0 1 PLL counter 1 (LSB)
0 0 1 0 PLL counter 2 (MSB)
0 0 1 1 PLL reference counter 1 (LSB)
0 1 0 0 PLL reference counter 2 (MSB)
0 1 0 1 PLL lockdetector control and PLL mode select
0 1 1 0 IFC reference counter 1 (LSB)
0 1 1 1 IFC reference counter 2 (MSB) and IFC mode select
1 0 0 0 IF counter control 1
1 0 0 1 IF counter control 2
1 0 1 0 Oscillator adjust
1 0 1 1 Port extension
0 page mode off
1 page mode enabled
T1, T2, T3 used for testing, in application mode they have to be "0"

12/21
 TDA7427

Data Byte Specification

CHARGE PUMP CONTROL

MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 High current = 0mA
0 0 0 1 High current = 0.5mA
0 0 1 0 High current = 1.0mA
0 0 1 1 High current = 1.5mA
0 1 0 0 High current = 2.0mA
0 1 0 1 High current = 2.5mA
0 1 1 0 High current = 3.0mA
0 1 1 1 High current = 3.5mA
1 0 0 0 High current = 4.0mA
1 0 0 1 High current = 4.5mA
1 0 1 0 High current = 5.0mA
1 0 1 1 High current = 5.5mA
1 1 0 0 High current = 6.0mA
1 1 0 1 High current = 6.5mA
1 1 1 0 High current = 7.0mA
1 1 1 1 High current = 7.5mA
0 0 Low current = 0µA
0 1 Low current = 50µA
1 0 Low current = 100µA
1 1 Low current = 150µA
0 Select low Current
1 Select high Current
1 Select loop filter LP_FM
0 Select loop filter LP_AM
LPIN1/2 CURRH B1 B0 A3 A2 A1 A0 Subaddress = 00H

PLL COUNTER 1 (LSB)

MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 LSB = 0
0 0 0 0 0 0 0 1 LSB = 1
0 0 0 0 0 0 1 0 LSB = 2

1 1 1 1 1 1 0 0 LSB = 252
1 1 1 1 1 1 0 1 LSB = 253
1 1 1 1 1 1 1 0 LSB = 254
1 1 1 1 1 1 1 1 LSB = 255
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Bit name Subaddress = 01H

13/21
TDA7427

PLL COUNTER 2 (MSB)

MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 MSB = 0
0 0 0 0 0 0 0 1 MSB = 256
0 0 0 0 0 0 1 0 MSB = 512

1 1 1 1 1 1 0 0 MSB = 64768
1 1 1 1 1 1 0 1 MSB = 65024
1 1 1 1 1 1 1 0 MSB = 65280
1 1 1 1 1 1 1 1 MSB = 65536
PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 Bit name Subddress = 02H
Swallow mode: fvco/fsyn = LSB + MSB + 32
Direct mode: fvco/fsyn = LSB + MSB + 1

PLL REFERENCE COUNTER 1 (LSB)

MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 LSB = 0
0 0 0 0 0 0 0 1 LSB = 1
0 0 0 0 0 0 1 0 LSB = 2

1 1 1 1 1 1 0 0 LSB = 252
1 1 1 1 1 1 0 1 LSB = 253
1 1 1 1 1 1 1 0 LSB = 254
1 1 1 1 1 1 1 1 LSB = 255
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 Bit name Subaddress =03H

PLL REFERENCE COUNTER 2 (MSB)

MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 MSB = 0
0 0 0 0 0 0 0 1 MSB = 256
0 0 0 0 0 0 1 0 MSB = 512

1 1 1 1 1 1 0 0 MSB = 64768
1 1 1 1 1 1 0 1 MSB = 65024
1 1 1 1 1 1 1 0 MSB = 65280
1 1 1 1 1 1 1 1 MSB = 65536
RC15 RC14 RC13 RC12 RC11 RC10 RC9 RC8 Bit name Subddress = 04H
fOSC/fREF = LSB + MSB + 1

14/21
 TDA7427

LOCK DETECTOR & PLL MODE CONTROL

MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
0 0 PLL standby mode
0 1 PLL AM swallow mode
1 0 PLL AM direct mode
1 1 PLL FM mode
0 0 PD phase difference threshold 10ns
0 1 PD phase difference threshold 20ns
1 0 PD phase difference threshold 30ns
1 1 PD phase difference threshold 40ns
0 0 Not used in application mode
0 1 Activation delay = 4 ⋅ fref
1 0 Activation delay = 6 ⋅ fref
1 1 Activation delay = 8 ⋅ fref
0 Digital output 1 at pin "dout1/inlock"
1 Inlock information at pin "dout1/inlock"
0 No lock detector controlled chargepump
1 Lock detector controlled chargepump
LDENA INLOCK D3 D2 D1 D0 PM1 PM0 Bit name Subaddress = 05H

IF COUNTER REFERENCE CONTROL 1 (LSB)

MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 LSB = 0
0 0 0 0 0 0 0 1 LSB = 1
0 0 0 0 0 0 1 0 LSB = 2

1 1 1 1 1 1 0 0 LSB = 252
1 1 1 1 1 1 0 1 LSB = 253
1 1 1 1 1 1 1 0 LSB = 254
1 1 1 1 1 1 1 1 LSB = 255
IRC7 IRC6 IRC5 IRC4 IRC3 IRC2 IRC1 IRC0 Bit name Subaddress = 06H

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TDA7427

IF COUNTER REFERENCE CONTROL 2 (MSB) AND IF COUNTER MODE SELECT

MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 MSB = 0
0 0 0 0 0 0 0 1 MSB = 256
0 0 0 0 0 0 1 0 MSB = 512

1 1 1 1 0 1 MSB = 15616
1 1 1 1 1 0 MSB = 15872
1 1 1 1 1 1 MSB = 16128
0 0 NOT USED IN APPLICATION MODE
0 1 IF counter FM mode
1 0 IF counter AM mode
1 1 IF counter AM 10.7MHz upconversion mode
IFCM1 IFCM0 IRC13 IRC12 IRC11 IRC10 IRC9 IRC8 Bit name Subaddress = 07H
fosc/ftim = LSB + MSB + 1

IF COUNTER CONTROL 1
MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 don’t use
0 0 1 don’t use
0 1 1 EW delta f = ±6.25kHz (FM); ±1kHz (AM; AM-UPC)
1 0 0 EW delta f = ±12.5kHz (FM); ±2kHz (AM; AM-UPC)
1 0 1 EW delta f = ±25kHz (FM); ±4kHz (AM; AM-UPC)
1 1 0 EW delta f = ±50Hz (FM); ±8kHz (AM; AM-UPC)
EW delta f = ±100kHz (FM); ±16kHz (AM; AM-
1 1 1
UPC)
X X X X don’t use
0 IF counter disabled / stand by
1 IF counter enabled
FENA FR3 FR2 FR1 FR0 EW2 EW1 EW0 Bit name Subaddress = 08H

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 TDA7427

IF COUNTER CONTROL 2
MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 fcenter = 10.60000MHz (FM) 448KHz (AM) 10.688MHz (AM UPC)
0 0 0 0 1 fcenter = 10.60625MHz (FM) 449KHz (AM) 10.689MHz (AM UPC)
0 0 0 1 0 fcenter = 10.61250MHz (FM) 450KHz (AM) 10.690MHz (AM UPC)
0 0 0 1 1 fcenter = 10.61875MHz (FM) 451KHz (AM) 10.691MHz (AM UPC)
0 0 1 0 0 fcenter = 10.62500MHz (FM) 452KHz (AM) 10.692MHz (AM UPC)
0 0 1 0 1 fcenter = 10.63125MHz (FM) 453KHz (AM) 10.693MHz (AM UPC)
0 0 1 1 0 fcenter = 10.63750MHz (FM) 454KHz (AM) 10.694MHz (AM UPC)
0 0 1 1 1 fcenter = 10.64375MHz (FM) 455KHz (AM) 10.695MHz (AM UPC)
0 1 0 0 0 fcenter = 10.65000MHz (FM) 456KHz (AM) 10.696MHz (AM UPC)
0 1 0 0 1 fcenter = 10.65625MHz (FM) 457KHz (AM) 10.697MHz (AM UPC)
0 1 0 1 0 fcenter = 10.66250MHz (FM) 458KHz (AM) 10.698MHz (AM UPC)
0 1 0 1 1 fcenter = 10.66875MHz (FM) 459KHz (AM) 10.699MHz (AM UPC)
0 1 1 0 0 fcenter = 10.67500MHz (FM) 460KHz (AM) 10.700MHz (AM UPC)
0 1 1 0 1 fcenter = 10.68125MHz (FM) 461KHz (AM) 10.701MHz (AM UPC)
0 1 1 1 0 fcenter = 10.68750MHz (FM) 462KHz (AM) 10.702MHz (AM UPC)
0 1 1 1 1 fcenter = 10.69375MHz (FM) 463KHz (AM) 10.703MHz (AM UPC)
1 0 0 0 0 fcenter = 10.70000MHz (FM) 464KHz (AM) 10.704MHz (AM UPC)
1 0 0 0 1 fcenter = 10.70625MHz (FM) 465KHz (AM) 10.705MHz (AM UPC)
1 0 0 1 0 fcenter = 10.71250MHz (FM) 466KHz (AM) 10.706MHz (AM UPC)
1 0 0 1 1 fcenter = 10.71875MHz (FM) 467KHz (AM) 10.707MHz (AM UPC)
1 0 1 0 0 fcenter = 10.72500MHz (FM) 468KHz (AM) 10.708MHz (AM UPC)
1 0 1 0 1 fcenter = 10.73125MHz (FM) 469KHz (AM) 10.709MHz (AM UPC)
1 0 1 1 0 fcenter = 10.73750MHz (FM) 470KHz (AM) 10.710MHz (AM UPC)
1 0 1 1 1 fcenter = 10.74375MHz (FM) 471KHz (AM) 10.711MHz (AM UPC)
1 1 0 0 0 fcenter = 10.75000MHz (FM) 472KHz (AM) 10.712MHz (AM UPC)
1 1 0 0 1 fcenter = 10.75625MHz (FM) 473KHz (AM) 10.713MHz (AM UPC)
1 1 0 1 0 fcenter = 10.76250MHz (FM) 474KHz (AM) 10.714MHz (AM UPC)
1 1 0 1 1 fcenter = 10.76875MHz (FM) 475KHz (AM) 10.715MHz (AM UPC)
1 1 1 0 0 fcenter = 10.77500MHz (FM) 476KHz (AM) 10.716MHz (AM UPC)
1 1 1 0 1 fcenter = 10.78125MHz (FM) 477KHz (AM) 10.717MHz (AM UPC)
1 1 1 1 0 fcenter = 10.78750MHz (FM) 478KHz (AM) 10.718MHz (AM UPC)
1 1 1 1 1 fcenter = 10.79375MHz (FM) 479KHz (AM) 10.719MHz (AM UPC)
1 1 1 tsample = 160µs (FM mode); 1ms (AM; AM-UPC)
1 1 0 tsample = 320µs (FM mode); 2ms (AM; AM-UPC)
1 0 1 tsample = 640µs (FM mode); 4ms (AM; AM-UPC)
1 0 0 tsample = 1.280ms (FM mode); 8ms (AM; AM-UPC)
0 1 1 tsample = 2.560ms (FM mode); 16ms (AM; AM-UPC)
0 1 0 tsample = 5.120ms (FM mode); 32ms (AM; AM-UPC)
0 0 1 tsample = 10.240ms (FM mode); 64ms (AM; AM-UPC)
0 0 0 tsample = 20.480ms (FM mode); 128ms (AM; AM-UPC)
IFS2 IFS1 IFS0 CF4 CF3 CF2 CF1 CF0 bit same Subaddress = 09H

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TDA7427

OSCILLATOR ADJUST
MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
X X X 0 0 0 0 0 Cload 1,2 = 3pF
X X X 0 0 0 0 1 Cload 1,2 = 4.25pF
X X X 0 0 0 1 0 Cload 1,2 = 5.5pF
X X X 0 0 0 1 1 Cload 1,2 = 6.75pF
X X X 0 0 1 0 0 Cload 1,2 = 8pF
X X X 0 0 1 0 1 Cload 1,2 = 9.25pF
X X X 0 0 1 1 0 Cload 1,2 = 10.5pF
X X X 0 0 1 1 1 Cload 1,2 = 11.75pF
X X X 0 1 0 0 0 Cload 1,2 = 13pF
X X X 0 1 0 0 1 Cload 1,2 = 14.25pF
X X X 0 1 0 1 0 Cload 1,2 = 15.5pF
X X X 0 1 0 1 1 Cload 1,2 = 16.75pF
X X X 0 1 1 0 0 Cload 1,2 = 18pF
X X X 0 1 1 0 1 Cload 1,2 = 19.25pF
X X X 0 1 1 1 0 Cload 1,2 = 20.5pF
X X X 0 1 1 1 1 Cload 1,2 = 21.75pF
X X X 1 0 0 0 0 Cload 1,2 = 23pF
X X X 1 0 0 0 1 Cload 1,2 = 24.25pF
X X X 1 0 0 1 0 Cload 1,2 = 25.5pF
X X X 1 0 0 1 1 Cload 1,2 = 26.75pF
X X X 1 0 1 0 0 Cload 1,2 = 28pF
X X X 1 0 1 0 1 Cload 1,2 = 29.25pF
X X X 1 0 1 1 0 Cload 1,2 = 30.5pF
X X X 1 0 1 1 1 Cload 1,2 = 31.75pF
X X X 1 1 0 0 0 Cload 1,2 = 33pF
X X X 1 1 0 0 1 Cload 1,2 = 34.25pF
X X X 1 1 0 1 0 Cload 1,2 = 35.5pF
X X X 1 1 0 1 1 Cload 1,2 = 36.75pF
X X X 1 1 1 0 0 Cload 1,2 = 38pF
X X X 1 1 1 0 1 Cload 1,2 = 39.25pF
X X X 1 1 1 1 0 Cload 1,2 = 40.5pF
X X X 1 1 1 1 1 Cload 1,2 = 41.75pF
- - - OSC4 OSC3 OSC2 OSC1 OSC0 Bit name Subaddress = 0AH

PORT EXTENSION CONTROL

MSB LSB FUNCTION
D7 D6 D2 D0
0 CMOS push-pull DOUT1 low
1 CMOS push-pull DOUT1 high
0 NPN opencollector DOUT3 inactive
1 NPN opencollector DOUT3 active
0 0 always "0" in application mode
- - DOUT3 DOUT1 Bit name Subaddress = 0BH

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 TDA7427

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX. MECHANICAL DATA

a1 0.254 0.010

B 1.39 1.65 0.055 0.065

b 0.45 0.018

b1 0.25 0.010

D 25.4 1.000

E 8.5 0.335

e 2.54 0.100

e3 22.86 0.900

F 7.1 0.280

I 3.93 0.155

L 3.3 0.130
DIP20
Z 1.34 0.053

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TDA7427

mm inch
DIM. OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN. TYP. MAX.

A 2.35 2.65 0.093 0.104

A1 0.1 0.3 0.004 0.012

B 0.33 0.51 0.013 0.020

C 0.23 0.32 0.009 0.013

D 12.6 13 0.496 0.512

E 7.4 7.6 0.291 0.299

e 1.27 0.050

H 10 10.65 0.394 0.419

h 0.25 0.75 0.010 0.030

L 0.4 1.27 0.016 0.050

SO20
K 0˚ (min.)8˚ (max.)

L
h x 45˚

B e K A1 C
H

20 11

1 0
1

SO20MEC

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 TDA7427

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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