SH79F642B

Single-phase Energy Metering IC integrated LCD driver and enhanced 8051 Microcontroller

1. Features
 8051 compatible Pipe-lined instruction based on the  5 channels 10-bit Analog to Digital Converter
single-chip 8-bit micro-controller (ADC) with built-in compare function
 Flash ROM: 64K Bytes  EUART0,EUART1 (built-in IR), EUART2
 EEPROM: 2K Bytes  Built-in Calendar clock
 RAM: internal 256 Bytes and external 2816 Bytes  Two 12-bit PWM timers
LCD RAM：32 Bytes  LCD driver:
 Operation voltage: 2.2V - 3.8V - 4 COM x 32 SEG (1/4 duty 1/3 bias)
 Oscillator (Code option): - 6 COM x 30 SEG (1/6 duty 1/3 bias)
- fOSC=32.768kHz - 8 COM x 28 SEG (1/8 duty 1/4 bias)
- Build in PLL : PLL= 8.192MHz - 8 levels contrast software programmable
 46 CMOS general purpose I/O ports  Built-in low power detection (LPD)
 Built-in pull-up resistor for I/O  Built-in low voltage reset (LVR) function (enabled
 Three 16-bit timer / counters: T0, T1 & T2 by code option)
 Powerful interrupt sources: LVR voltage: 2.3V
- Timer0, Timer1, Timer2  Built-in Watch Dog Timer (WDT)
- External interrupt 1, 2, 3  Warm-up timer for power-on reset
- EUART0, EUART1, EUART2  CPU Machine cycle: 1 oscillator clock
- RTC, LPD  Support Low power operation modes:
- ADC, EMU, PWM - IDLE Mode
 Energy Metering - Power-Down Mode
Active/ reactive/ apparent Energy Metering and voltage/  Low-power Comsumption
current rms metering  Package: LQFP64(10*10) / LQFP64 (7*7)
Accuracy of 0.1% for active energy over a dynamic
range of 2000:1.
Accuracy of 0.5% for reactive energy over a dynamic
range of 1000:1.
Less than 0.5% error for voltage/ current rms
2. General Description
The SH79F642B is a low-cost,high-performance single-phase energy metering SOC chip, and integrated single-phase
energy metering, LCD driver, Calendar clock and enhanced 8051 microcontroller.
SH79F642B embedded energy metering module, to measure active, reactive and apparent energy, as well as voltage/
current rms. And then to monitor the voltage sag of the power line and zero-crossing features.
The SH79F642B is a fast 8051 compatible micro-controller with a redesigned CPU of no wasted clock and memory cycles.
Typically, it will be faster and exhibit better performance than the traditional 8051 at the same oscillator frequency.
The SH79F642B retains most features of the standard 8051. These features include internal 256 bytes RAM, two 16-bit
timers / counters, three UART, and external interrupt INT1. In addition, the SH79F642B provides external 2816 bytes RAM (not
include LCD RAM), two 12-bit PWM outputs, external interrupt INT2&3, 16-bit timer/counter (Timer2) compatible with 8052. It
contains a 64K Bytes Flash memory block for program and data.
Some standard serial communication modes such as EUART、IR are supported in SH79F642B. Also the LCD driver,
ADC,PWM Timer and RTC are incorporated in SH79F642B.
For high reliability and low cost issues, the SH79F642B builds in PLL clock, LCD Driver, Watchdog Timer, Low Voltage
Reset function, and oscillator fail detection. SH79F642B also supports two power supply modes and two power saving modes
to reduce power consumption.

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 SH79F642B
3. Block Diagram

VDD
VBAT Reset circuit RST
Pipelined 8051 architecture
Power Watch Dog
VOUT

Low Voltage Reset

VIN Low Voltage Detect

Internal 256 bytes
external 2816 bytes
64K bytes LCD RAM 32bytes
Flash ROM

T0 Port 5 Configuration
Timer0 (16bit) P5.0 ~ P5.7
T1 I/Os
Timer1 (16bit)
T2
Timer2 (16bit)
T2EX Port 4 Configuration
P4.0 ~ P4.7
I/Os
INT0
INT1 Port 3 Configuration
INT2 External Interrupt P3.0~P3.6
I/Os
INT3
Port 2 Configuration
AN0 P2.0 ~ P2.7
I/Os
AN1
AN2 ADC
Port 1 Configuration
AN3 P1.0 ~ P1.7
I/Os
AN5
PWM0 Port 0 Configuration
PWM P0.0 ~ P0.7
PWM1 I/Os

PLL Oscillator RXD0/TXD0

EUART0,1/IR
EUART2 RXD1/TXD1
RXD2/TXD2
XTAL1
Oscillator
XTAL2

LCD driver COM1-4/6/8

CALOUT 4x32/6x30/8x28 SEG1-32
RTC

I1P 8 levels contrast

I1N software adjust
I2P
Energy
I2N TMS
Measurement
VP JTAG ports TDI
VN (for debug) TDO
VREF TCK

Regulator C
AVCC LDO

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 SH79F642B
4. Pin Configuration

P1.4//PWM0/SEG1//COM5
P0.6/SEG11/RXD2
P0.7/SEG12/TXD2

P1.5/SEG2/COM6
P1.7/SEG4/COM8

P1.6/SEG3/COM7
P0.5/SEG10/TCK

P0.3/SEG8/TMS

P0.2/SEG7/TDO
P0.4/SEG9/TDI

P1.3/COM4

P1.2/COM3

P1.1/COM2

P1.0/COM1
P0.0/SEG5
P0.1/SEG6
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SEG13/P4.0 49 32 P3.6/SEG32/TXD0

SEG14/P4.1 50 31 P3.5/SEG31/RXD0

SEG15/P4.2 51 30 P3.4/SEG30/TXD1/IOMUX

SEG16/P4.3 52 29 P3.3/SEG29/RXD1

SEG17/P4.4 53 28 P3.2/T2/CALOUT

SEG18/P4.5 54 27 P3.0/T2EX/T0
SEG19/P4.6 55 26 P2.7/INT2/T1/AN5
SEG20/P4.7 56 SH79F642B 25 P2.6/INT3/AN3
(LQFP64)
SEG21/P5.0 57 24 P2.5/QF/AN2
SEG22/P5.1 58 23 P2.4/PF/CALOUT2/AN1
SEG23/P5.2 59 22 P2.3/AN0/VIN
SEG24/P5.3 60 21 P2.2
SEG25/P5.4 61 20 P2.1
SEG26/P5.5 62 19 P2.0/RST
SEG27/PWM1/P5.6 63 18 NC

SEG28/INT1/P5.7 64 17 XTAL1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VDD
NC

DGND

AVCC

VBAT

VOUT
I2P

I1P
I2N

XTAL2
I1N

AGND
VREF

VN
VP

Pin Configuration Diagram

Note: The out most pin function has the highest priority, and the inner most pin function has the lowest priority (Refer to Pin
Configuration Diagram). This means when one pin is occupied by a higher priority function (if enabled) cannot be used as the
lower priority functional pin, even when the lower priority function is also enabled. Only until the higher priority function is
disabled by software, can the corresponding pin be released for the lower priority function use.

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 SH79F642B
Table 4.1 Pin Functions
Pin No. Pin Name Default function Pin No. Pin Name Default function
1 NC ------ 33 COM1/P1.0 P1.0
2 VREF ------ 34 COM2/P1.1 P1.1
3 VP ------ 35 COM3/P1.2 P1.2
4 VN ------ 36 COM4/P1.3 P1.3
COM5/SEG1/
5 I2P ------ 37 P1.4
PWM0/P1.4
6 I2N ------ 38 COM6/SEG2/ P1.5 P1.5
7 I1N ------ 39 COM7/SEG3/ P1.6 P1.6
8 I1P ------ 40 COM8/SEG4/ P1.7 P1.7
9 AGND ------ 41 SEG5/P0.0 P0.0
10 DGND ------ 42 SEG6/P0.1 P0.1
11 AVCC ------ 43 TDO/SEG7/P0.2 P0.2
12 VBAT ------ 44 TMS/SEG8/P0.3 P0.3
13 VDD ------ 45 TDI/SEG9/P0.4 P0.4
14 VOUT ------ 46 TCK/SEG10/P0.5 P0.5
15 C ------ 47 RXD2/SEG11/P0.6 P0.6
16 XTAL2 ------ 48 TXD2/SEG12/P0.7 P0.7
17 XTAL1 ------ 49 SEG13/P4.0 P4.0
18 NC ------ 50 SEG14/P4.1 P4.1
———— ————
19 P2.0/RST RST 51 SEG15/P4.2 P4.2
20 P2.1 P2.1 52 SEG16/P4.3 P4.3
21 P2.2 P2.2 53 SEG17/P4.4 P4.4
22 VIN/AN0/P2.3 VIN 54 SEG18/P4.5 P4.5
23 AN1/CALOUT2/PF/P2.4 P2.4 55 SEG19/P4.6 P4.6
24 AN2/QF/P2.5 P2.5 56 SEG20/P4.7 P4.7
25 AN3/INT3/P2.6 P2.6 57 SEG21/P5.0 P5.0
26 AN5/T1/INT2/P2.7 P2.7 58 SEG22/P5.1 P5.1
27 T0/T2EX/P3.0 P3.0 59 SEG23/P5.2 P5.2
28 CALOUT/T2/P3.2 P3.2 60 SEG24/P5.3 P5.3
29 RXD1/SEG29/P3.3 P3.3 61 SEG25/P5.4 P5.4
30 IOMUX/TXD1/SEG30/P3.4 P3.4 62 SEG26/P5.5 P5.5
31 RXD0/SEG31/P3.5 P3.5 63 SEG27/PWM1/P5.6 P5.6
32 TXD0/SEG32/P3.6 P3.6 64 SEG28/INT1/P5.7 P5.7

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 SH79F642B
5. Pin Description

Pin Name Type Description

PORT
P0.0 – P0.7 I/O 8-bit bi-directional I/O port
P1.0 – P1.7 I/O 8-bit bi-directional I/O port
P2.0 – P2.7 I/O 8-bit bi-directional I/O port
P3.0, P3.2 – P3.6 I/O 6-bit bi-directional I/O port
P4.0 – P4.7 I/O 8-bit bi-directional I/O port
P5.0 – P5.7 I/O 8-bit bi-directional I/O port
IOMUX O Multi-function pulse output port
Timer
T0 I Timer0 external input or compare output
T1 I Timer1 external input or compare output
T2 I/O Timer2 external input/ Baudrate clock output
T2EX I The external clock input pin for the capture timer
EUART
RXD0 I/O EUART0 data input/ output
TXD0 O EUART0 data output.
RXD1 I/O EUART1 data input/ output
TXD1 O EUART1 data output.
RXD2 I/O EUART2 data input/ output
TXD2 O EUART2 data output.
LCD controller
COM1 – COM8 O Common signal output for LCD display
SEG1 – SEG32 O Segment signal output for LCD display
ADC
AN0-AN3, AN5 I ADC input chanels
RTC
CALOUT O Compensation clock output
CALOUT2 O Compensation clock output2
PWM
PWM0 O PWM0 output
PWM1 O PWM1 output
EMU
I1P, I1N, I2P,
I Energy metering input
I2N, VP, VN
Extern reference voltage input/output，the external need to connect the 0.1uF and 1 uF
VREF I/O
capacitor to ground.
PF, QF O Active/ reactive power pulse output

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 SH79F642B
(Continued)
Pin Name Type Description
Interrupt & Reset & Clock & Power
INT1 - INT3 I External interrupt 1~3
———— A low on this pin for 10us longer will reset the device. An internal diffused 30kohm resistor
RST I
to VDD permits a power-on reset using only an external capacitor to GND.
XTAL1 I Oscillator input
XTAL2 O Oscillator output
DGND P Digital ground
VDD P Power
AGND P Analog ground
Digital power supply circuit,the external need to connect the 4.7uF capacitor to ground,the
C P
typical voltage 1.8V
VOUT P Power output pin（output VDD or VBAT by using a switch ）, digital circuit supply.
VBAT P Battery supply
Energy Metering Analog Power with built-in 2.8V LDO output. It requires an 1uF external
AVCC P
ceramic capacitor to GND.
Programmer
TDO (SEG7) O Debug interface: Test data out
TMS (SEG8) I Debug interface: Test mode select
TDI (SEG9) I Debug interface: Test data in
TCK (SEG10) I Debug interface: Test clock in
Note:
When P0.2-0.5 used as debug interface, other functions of P0.2-0.5 are blocked.
External Voltage detection Pin
VIN I External voltage detection input

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 SH79F642B
6. SFR Mapping
The SH79F642B provides 256 bytes of internal RAM to contain general-purpose data memory and Special Function
Register (SFR). The SFR of the SH79F642B fall into the following categories:

CPU core registers: ACC, B, PSW, SP, DPL, DPH

Enhanced C51 core registers: AUXC, DPL1, DPH1, INSCON, XPAGE

Power and clock control registers: PCON, SUSLO, CLKCON

LPD registers: LPDCON, LPDCON1, LDOCON

Flash registers: IB_OFFSET, XPAGE, IB_DATA, IB_CON1, IB_CON2, IB_CON3, IB_CON4,

IB_CON5

Data Memory register: XPAGE

Watch-dog registers: RSTSTAT

Interrupt system registers: IEN0, IEN1, IPH0, IPL0, IPH1, IPL1, EXF0

I/O port registers: P0, P1, P2, P3, P4, P0CR, P1CR, P2CR, P3CR, P4CR, P0PCR, P1PCR, P2PCR,
P3PCR, P4PCR, PXMOD, P5, P5CR, P5PCR,P2DRV,P3DRV

Timer registers: TCON1, TCON, TMOD, TL0, TH0, TL1, TH1, T2CON, T2MOD, EXF0,
TL2, TH2, RCAP2L, RCAP2H

EUART0 registers: PCON, SCON, SBUF, SADDR, SADEN, SBRTH, SBRTL, SFINE

EUART1 registers: SCON1, SBUF1, SADDR1, SADEN1, SBRTH1, SBRTL1, SFINE1

EUART2 registers: SCON2, SBUF2, SADDR2, SADEN2, SBRTH2, SBRTL2, SFINE2

IR registers: IRCON

ADC registers: ADCON, ADT, ADCH, ADDL, ADDH

LCD registers: LCDCON, LCDCON1, P0SS, P1SS, P3SS, P4SS, P5SS

PLL registers: CLKCON

RTC registers: SBSC, SEC, MIN, HR, DAY, MTH, YR, DOW, RTCDATH, RTCDATL, RTCALM,
A0SEC, A0MIN, A0HR, A0DAY, A0DOW, A1SEC, A1MIN, A1HR, RTCCON,
RTCWR, RTCPSW, RTCIE, RTCIF,RTCTMR

PWM registers: PWM0CON, PWM0PH, PWM0PL, PWM0DH, PWM0DL, PWM1CON, PWM1PH,

PWM1PL, PWM1DH, PWM1DL

EMU registers: EADR, EDTAH, EDTAM, EDTAL, EMUSR, EMUIE, EMUIF

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 SH79F642B

Table 6.1 C51 Core SFRs

POR/WDT/LVR
Mnem Addr Name Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Value
ACC E0H Accumulator 00000000 ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0
B F0H B Register 00000000 B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0
AUXC F1H C Register 00000000 C.7 C.6 C.5 C.4 C.3 C.2 C.1 C.0
PSW D0H Program Status Word 00000000 CY AC F0 RS1 RS0 OV F1 P
SP 81H Stack Pointer 00000111 SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0
DPL 82H Data Pointer1 Low byte 00000000 DPL0.7 DPL0.6 DPL0.5 DPL0.4 DPL0.3 DPL0.2 DPL0.1 DPL0.0
DPH 83H Data Pointer1 High byte 00000000 DPH0.7 DPH0.6 DPH0.5 DPH0.4 DPH0.3 DPH0.2 DPH0.1 DPH0.0
DPL1 84H Data Pointer 2 Low byte 00000000 DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0
DPH1 85H Data Pointer 2 High byte 00000000 DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0
INSCON 86H Data pointer select ----00-0 - - - - DIV MUL - DPS

Table 6.2 Data MPAGE SFR

POR/WDT/LVR
Mnem Addr Name Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Value
XPAGE F7h Memory Page 00000000 XPAGE.7 XPAGE.6 XPAGE.5 XPAGE.4 XPAGE.3 XPAGE.2 XPAGE.1 XPAGE.0

Table 6.3 Power and clock control SFRs

POR/WDT/LVR
Mnem Addr Name Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Value
PCON 87H Power Control 00000000 SMOD SSTAT SSTAT1 SSTAT2 GF1 GF0 PD IDL
SUSLO 8EH Suspend Mode Control 00000000 SUSLO.7 SUSLO.6 SUSLO.5 SUSLO.4 SUSLO.3 SUSLO.2 SUSLO.1 SUSLO.0
PASLO E7H Power select Control 00000000 PASLO.7 PASLO.6 PASLO.5 PASLO.4 PASLO.3 PASLO.2 PASLO.1 PASLO.0

Table 6.4 LPD control SFR

POR/WDT/LVR
Mnem Addr Name Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Value
LPDCON B3H LPD Control 100*00-* LPDEN FVIN LPDIF VOUTS FVDD LPDS - AUTOS
LPDCON1 BFH VOUT低电压检测控制寄存器 00---000 LPDEN LPDF - - - LPDS2 LPDS1 LPDS0

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 SH79F642B
LDOCON DFH 计量LDO电压控制寄存器 ***----- BGEN LDOEN1 LDOEN0 - - - - -
*note: LPDCON value will changed in deferent reset condition .
Table 6.5 Flash control SFRs
POR/WDT/LVR
Mnem Addr Name Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Value
Low byte offset of flash memory for IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF
IB_OFFSET FBH 00000000
programming SET.7 SET.6 SET.5 SET.4 SET.3 SET.2 SET.1 SET.0
Data Register for programming
IB_DATA FCH 00000000 IB_DATA.7 IB_DATA.6 IB_DATA.5 IB_DATA.4 IB_DATA.3 IB_DATA.2 IB_DATA.1 IB_DATA.0
flash memory

IB_CON1 F2H Flash Memory Control Register 1 00000000 IB_CON1.7 IB_CON1.6 IB_CON1.5 IB_CON1.4 IB_CON1.3 IB_CON1.2 IB_CON1.1 IB_CON1.0

IB_CON2 F3H Flash Memory Control Register 2 ----0000 - - - - IB_CON2.3 IB_CON2.2 IB_CON2.1 IB_CON2.0

IB_CON3 F4H Flash Memory Control Register 3 ----0000 - - - - IB_CON3.3 IB_CON3.2 IB_CON3.1 IB_CON3.0

IB_CON4 F5H Flash Memory Control Register 4 ----0000 - - - - IB_CON4.3 IB_CON4.2 IB_CON4.1 IB_CON4.0

IB_CON5 F6H Flash Memory Control Register 5 ----0000 - - - - IB_CON5.3 IB_CON5.2 IB_CON5.1 IB_CON5.0

Table 6.6 ISP control SFRs

POR/WDT/LVR
Mnem Addr Name Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Value
FLASHCO A7H Flash contol -------0 - - - - - - - FAC
N SFR

Table 6.7 WDT SFR

POR/WDT/LVR
Mnem Addr Name Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Value
RSTSTAT B1H Watchdog Timer Control *-***000 WDOF - PORF LVRF CLRF WDT.2 WDT.1 WDT.0

*note : RSTSTAT value will changed in deferent reset condition

Table 6.8 Clkcon SFR
POR/WDT/LVR
Mnem Addr Name Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Value
CLKCON B2H System Clock Select and Monitor 111-00-- 32K_SPDUP CLKS1 CLKS0 - PLLCON FS2 - -

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 SH79F642B
Table 6.9 Interrupt SFRs
POR/WDT/LVR
Mnem Addr Name Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Value
IEN0 A8H Interrupt Enable Control 0 0000000- EA EADTP ET2 ES0 ET1 EX1 ET0 -
IEN1 A9H Interrupt Enable Control 1 00000000 ELPD ES2 EPWM ES1 ERTC EX3 EX2 EEMU
IPL0 B8H Interrupt Priority Control Low 0 -000000- - PADTPL PT2L PS0L PT1L PX1L PT0L -
IPH0 B4H Interrupt Priority Control High 0 -000000- - PADTPH PT2H PS0H PT1H PX1H PT0H -
IPL1 B9H Interrupt Priority Control Low 1 00000000 PLPDL PES2L PPWML PS1L PRTCL PX3L PX2L PEMUL
IPH1 B5H Interrupt Priority Control High 1 00000000 PLPDH PES2H PPWMH PS1H PRTCH PX3H PX2H PEMUH

Table 6.10 Port SFRs

POR/WDT/LVR
Mnem Addr Name Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Value
P0 80H 8-bit Port 0 00000000 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
P1 90H 8-bit Port 1 00000000 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
P2 A0H 8-bit Port 2 00000000 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
P3 B0H 8-bit Port 3 -00000-0 - P3.6 P3.5 P3.4 P3.3 P3.2 - P3.0
P4 C0H 8-bit Port 4 00000000 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0
P5 CFH 8-bit Port 5 00000000 P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0
P0CR E1H Port0 input/output direction control 00000000 P0CR.7 P0CR.6 P0CR.5 P0CR.4 P0CR.3 P0CR.2 P0CR.1 P0CR.0
P1CR E2H Port1 input/output direction control 00000000 P1CR.7 P1CR.6 P1CR.5 P1CR.4 P1CR.3 P1CR.2 P1CR.1 P1CR.0
P2CR E3H Port2 input/output direction control 00000000 P2CR.7 P2CR.6 P2CR.5 P2CR.4 P2CR.3 P2CR.2 P2CR.1 P2CR.0
P3CR E4H Port3 input/output direction control 10000010 - P3CR.6 P3CR.5 P3CR.4 P3CR.3 P3CR.2 - P3CR.0
P4CR E5H Port4 input/output direction control 00000000 P4CR.7 P4CR.6 P4CR.5 P4CR.4 P4CR.3 P4CR.2 P4CR.1 P4CR.0
P5CR E6H Port5 input/output direction control 00000000 P5CR.7 P5CR.6 P5CR.5 P5CR.4 P5CR.3 P5CR.2 P5CR.1 P5CR.0
P0PCR E9H Internal pull-high enable for Port0 00000000 P0PCR.7 P0PCR.6 P0PCR.5 P0PCR.4 P0PCR.3 P0PCR.2 P0PCR.1 P0PCR.0
P1PCR EAH Internal pull-high enable for Port1 00000000 P1PCR.7 P1PCR.6 P1PCR.5 P1PCR.4 P1PCR.3 P1PCR.2 P1PCR.1 P1PCR.0
P2PCR EBH Internal pull-high enable for Port2 00000--0 P2PCR.7 P2PCR.6 P2PCR.5 P2PCR.4 P2PCR.3 P2PCR.2 P2PCR.1 P2PCR.0
P3PCR ECH Internal pull-high enable for Port3 -00000-0 - P3PCR.6 P3PCR.5 P3PCR.4 P3PCR.3 P3PCR.2 - P3PCR.0
P4PCR EDH Internal pull-high enable for Port4 00000000 P4PCR.7 P4PCR.6 P4PCR.5 P4PCR.4 P4PCR.3 P4PCR.2 P4PCR.1 P4PCR.0
P5PCR EEH Internal pull-high enable for Port5 00000000 P5PCR.7 P5PCR.6 P5PCR.5 P5PCR.4 P5PCR.3 P5PCR.2 P5PCR.1 P5PCR.0
PXMOD EFH Port mode select --00000- - - CAL2EN IOMUX1 IOMUX0 P2OS.2 P2OS.1 -
P2DRV F9H Drive ability for P2 select 00000000 P2DRV.7 P2DRV.6 P2DRV.5 P2DRV.4 P2DRV.3 P2DRV.2 P2DRV.1 P2DRV.0

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 SH79F642B
P3DRV FAH Drive ability for P3 select 00000000 P3DRV.7 P3DRV.6 P3DRV.5 P3DRV.4 P3DRV.3 P3DRV.2 P3DRV.1 P3DRV.0

note: Bit1,bit7 of P3CR are reserved bits, and always be 1

Table 6.11 Timer SFRs
POR/WDT/LVR
Mnem Addr Name Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Value
TCON 88H Timer/Counter 0 Control 000000-- TF1 TR1 TF0 TR0 IE1 IT1 - -
-------- --------
TMOD 89H Timer/Counter 0 Mode 00000000 GATE1 M11 M10 GATE0 M01 M00
C/T 1 C/T 0
TL0 8AH Timer/Counter 0 Low Byte 00000000 TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0
TH0 8CH Timer/Counter 0 High Byte 00000000 TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0
TL1 8BH Timer/Counter1 Low Byte 00000000 TL1.7 TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.1
TH1 8DH Timer/Counter 1 High Byte 00000000 TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.1
-------- ------------
T2CON C8H Timer/Counter 2 Control 00--0000 TF2 EXF2 - - EXEN2 TR2 C/T 2 CP/R L 2
T2MOD C9H Timer/Counter 2 Mode 0-----00 TCLKP2 - - - - - T2OE DCEN
Timer/Counter 2 Reload/Caprure
RCAP2L CAH 00000000 RCAP2L.7 RCAP2L.6 RCAP2L.5 RCAP2L.4 RCAP2L.3 RCAP2L.2 RCAP2L.1 RCAP2L.0
Low Byte
RCAP2H CBH Timer/Counter 2 Reload/Caprure 00000000 RCAP2H.7 RCAP2H.6 RCAP2H.5 RCAP2H.4 RCAP2H.3 RCAP2H.2 RCAP2H.1 RCAP2H.0
High Byte
TL2 CCH Timer/Counter 2 Low Byte 00000000 TL2.7 TL2.6 TL2.5 TL2.4 TL2.3 TL2.2 TL2.1 TL2.0
TH2 CDH Timer/Counter 2 High Byte 00000000 TH2.7 TH2.6 TH2.5 TH2.4 TH2.3 TH2.2 TH2.1 TH2.0
TCON1 CEH Timer/Counter 0 Control -00-0000 - TCLKS1 TCLKS0 - TCLKP1 TCLKP0 TC1 TC0

Table 6.12 EUART0 SFRs

POR/WDT/LVR
Mnem Addr Name Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Value
PCON 87H Power & Serial Control 00000000 SMOD SSTAT SSTAT1 SSTAT2 GF1 GF0 PD IDL
SCON 98H Serial Control 00000000 SM0/FE SM1/RXOV SM2/TXCOL REN TB8 RB8 TI RI
SBUF 99H Serial Data Buffer 00000000 SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0
SADDR 9AH Slave Address 00000000 SADDR.7 SADDR.6 SADDR.5 SADDR.4 SADDR.3 SADDR.2 SADDR.1 SADDR.0
SADEN 9BH Slave Address Mask 00000000 SADEN.7 SADEN.6 SADEN.5 SADEN.4 SADEN.3 SADEN.2 SADEN.1 SADEN.0
SBRTH 9CH Baud rate high byte 00000000 SBRTEN SBRT0.14 SBRT0.13 SBRT0.12 SBRT0.11 SBRT0.10 SBRT0.9 SBRT0.8
SBRTL 9DH Baud rate low byte 00000000 SBRT0.7 SBRT0.6 SBRT0.5 SBRT0.4 SBRT0.3 SBRT0.2 SBRT0.1 SBRT0.0
SFINE 9EH Baud rate fine tuning for EUART0\1 00000000 SFINE1.3 SFINE1.2 SFINE1.1 SFINE1.0 SFINE.3 SFINE.2 SFINE.1 SFINE.0

11
 SH79F642B
Table 6.13 EUART1 SFRs
POR/WDT/LVR
Mnem Addr Name Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Value
PCON 87H Power & serial Control 00000000 SMOD SSTAT SSTAT1 SSTAT2 GF1 GF0 PD IDL
SCON1 D8H Serial Control 00000000 SM10/FE1 SM11/RXOV SM12/TXCO REN1 TB81 RB81 TI1 RI1
1 L1
SBUF1 D9H Serial Data Buffer 00000000 SBUF1.7 SBUF1.6 SBUF1.5 SBUF1.4 SBUF1.3 SBUF1.2 SBUF1.1 SBUF1.0
SADDR1 DAH Slave Address 00000000 SADDR1.7 SADDR1.6 SADDR1.5 SADDR1.4 SADDR1.3 SADDR1.2 SADDR1.1 SADDR1.0
SADEN1 DBH Slave Address Mask 00000000 SADEN1.7 SADEN1.6 SADEN1.5 SADEN1.4 SADEN1.3 SADEN1.2 SADEN1.1 SADEN1.0
SBRTH1 DCH Baud rate high byte 00000000 SBRTEN1 SBRT1.14 SBRT1.13 SBRT1.12 SBRT1.11 SBRT1.10 SBRT1.9 SBRT1.8
SBRTL1 DDH Baud rate low byte 00000000 SBRT1.7 SBRT1.6 SBRT1.5 SBRT1.4 SBRT1.3 SBRT1.2 SBRT1.1 SBRT1.0
SFINE 9EH Baud rate fine tuning for EUART0\1 00000000 SFINE1.3 SFINE1.2 SFINE1.1 SFINE1.0 SFINE.3 SFINE.2 SFINE.1 SFINE.0

Table 6.14 EUART2 SFRs

POR/WDT/LVR
Mnem Addr Name Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Value
SCON2 F8H Serial Control 00000000 SM20/FE2 SM21/RXOV SM22/TXCO REN2 TB82 RB82 TI2 RI2
2 L2
SBUF2 BAH Serial Data Buffer 00000000 SBUF2.7 SBUF2.6 SBUF2.5 SBUF2.4 SBUF2.3 SBUF2.2 SBUF2.1 SBUF2.0
SADDR2 BBH Slave Address 00000000 SADDR2.7 SADDR2.6 SADDR2.5 SADDR2.4 SADDR2.3 SADDR2.2 SADDR2.1 SADDR2.0
SADEN2 BCH Slave Address Mask 00000000 SADEN2.7 SADEN2.6 SADEN2.5 SADEN2.4 SADEN2.3 SADEN2.2 SADEN2.1 SADEN2.0
SBRTH2 BDH Baud rate high byte 00000000 SBRTEN2 SBRT2.14 SBRT2.13 SBRT2.12 SBRT2.11 SBRT2.10 SBRT2.9 SBRT2.8
SBRTL2 BEH Baud rate low byte 00000000 SBRT2.7 SBRT2.6 SBRT2.5 SBRT2.4 SBRT2.3 SBRT2.2 SBRT2.1 SBRT2.0
SFINE2 DEH Baud rate fine tuning for EUART2 ----0000 - - - - SFINE2.3 SFINE2.2 SFINE2.1 SFINE2.0

Table 6.15 IR SFR

POR/WDT/LVR
Mnem Addr Name Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Value
IRCON A1H IR control 00000000 IRON IRF6 IRF5 IRF4 IRF3 IRF2 IRF1 IRF0

12
 SH79F642B
Table 6.16 ADC SFRs
POR/WDT/LVR
Mnem Addr Name Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Value
----------------
ADCON C1H ADC control 00000000 ADON ADCIF EC EADC SCH2 SCH1 SCH0 GO/DON E
ADT C2H ADC clock control 000-0000 TADC2 TADC1 TADC0 - TS3 TS2 TS1 TS0
ADCH AFH ADC channel control --0-0000 - - CH5 - CH3 CH2 CH1 CH0
ADDL 91H ADC data low byte ------00 - - - - - - A1 A0
ADDH 92H ADC data high byte 00000000 A9 A8 A7 A6 A5 A4 A3 A2

Table 6.17 LCD SFRs

POR/WDT/LVR
Mnem Addr Name Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Value
LCDCON1 A2H LCD contrast control 0-00-000 FCMOD FCCTL1 FCCTL0 - MOD2 MOD1 MOD0

LCDCON A3H LCD control 0-000000 LCDON - DUTY1 DUTY0 BIAS CONTR2 CONTR1 CONTR0
P0SS AAH P0 or Segment Select 00000000 P0S7 P0S6 P0S5 P0S4 P0S3 P0S2 P0S1 P0S0
P1SS ABH P1 or Segment Select 0000---0 P1S7 P1S6 P1S5 P1S4 - - - COMS
P3SS ACH P3 or Segment Select -0000--- - P3S6 P3S5 P3S4 P3S3 - - -
P4SS ADH P4 or Segment Select 00000000 P4S7 P4S6 P4S5 P4S4 P4S3 P4S2 P4S1 P4S0
P5SS AEH P5 or Segment Select 00000000 P5S7 P5S6 P5S5 P5S4 P5S3 P5S2 P5S1 P5S0

13
 SH79F642B
Table 6.18 RTC SFRs
POR/WDT/LVR
Mnem Addr Name Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Value
SBSC FFA0H Sub second REG ******** SBSC7 SBSC6 SBSC5 SBSC4 SBSC3 SBSC2 SBSC1 SBSC0
SEC FFA1H Second REG -******* - SEC6 SEC5 SEC4 SEC3 SEC2 SEC1 SEC0
MIN FFA2H Minute REG ******** - MIN6 MIN5 MIN4 MIN3 MIN2 MIN1 MIN0
HR FFA3H Hour REG --****** - - HR5 HR4 HR3 HR2 HR1 HR0
DAY FFA4H Date REG --****** - - DAY5 DAY4 DAY3 DAY2 DAY1 DAY0
MTH FFA5H Month REG ---***** - - - MTH4 MTH3 MTH2 MTH1 MTH0
YR FFA6H Year REG ******** YR7 YR6 YR5 YR4 YR3 YR2 YR1 YR0
DOW FFA7H Day REG -----*** - - - - - DOW2 DOW1 DOW0

RTCDATH FFA8H RTC compensation value (E) high -******* - - E13 E12 E11 E10 E9 E8
byte
RTC compensation value (E) low
RTCDATL FFA9H ******** E7 E6 E5 E4 E3 E2 E1 E0
byte
RTCALM FFAAH RTC alarmer control ******** ALM1C2 ALM1C1 ALM1C0 ALM0C4 ALM0C3 ALM0C2 ALM0C1 ALM0C0
A0SEC FFABH Alarmer0 Second REG -******* - A0SEC6 A0SEC5 A0SEC4 A0SEC3 A0SEC2 A0SEC1 A0SEC0
A0MIN FFACH Alarmer0 Minute REG -******* - A0MIN6 A0MIN5 A0MIN4 A0MIN3 A0MIN2 A0MIN1 A0MIN0
A0HR FFADH Alarmer0 Hour REG --****** - - A0HR5 A0HR4 A0HR3 A0HR2 A0HR1 A0HR0
A0DAY FFAEH Alarmer0 Date REG --****** - - A0DAY5 A0DAY4 A0DAY3 A0DAY2 A0DAY1 A0DAY0
A0DOW FFAFH Alarmer0 Day REG -----*** - - - - - A0DOW2 A0DOW1 A0DOW0
A1SEC FFB0H Alarmer1 Second REG -******* - A1SEC6 A1SEC5 A1SEC4 A1SEC3 A1SEC2 A1SEC1 A1SEC0
A1MIN FFB1H Alarmer1 Minute REG -******* - A1MIN6 A1MIN5 A1MIN4 A1MIN3 A1MIN2 A1MIN1 A1MIN0
A1HR FFB2H Alarmer1 Hour REG --****** - - A1HR5 A1HR4 A1HR3 A1HR2 A1HR1 A1HR0
RTCCON FFB3H RTC control 0***0*** RTCRD ITEN ITS1 ITS0 OUTEN OUTS OUTF1 OUTF0
RTCWR FFB4H Writtern protect for RTC 00000000 RTCWR7 RTCWR6 RTCWR5 RTCWR4 RTCWR3 RTCWR2 RTCWR1 RTCWR0

RTCPSW FFB5H Writtern protect security code for 00000000 PSW7 PSW6 PSW5 PSW4 PSW3 PSW2 PSW1 PSW0
RTC
RTCIE FFB6H RTC interrupt control 0000000- IT0IE DAYIE HRIE MINIE SECIE ALM1IE ALM0IE -
RTCIF FFB7H RTC interrupt flag *******- IT0IF DAYIF HRIF MINIF SECIF ALM1IF ALM0IF -

RTCECL FFB8H RTC bias at room temperature low uuuuuuuu EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0
byte
RTC bias at room temperature high
RTCECH FFB9H uuuuuuuu EC15 EC14 EC13 EC12 EC11 EC10 EC9 EC8
byte

14
 SH79F642B
RTCTMR FFBAH RTC Timer uuuuuuuu RTCT7 RTCT6 RTCT5 RTCT4 RTCT3 RTCT2 RTCT1 RTCT0

Note: u：Reset does not affect the current value；*：Power on reset value is random number, and other forms of reset is u.
Table 6.19 EMU SFRs
POR/WDT/LVR
Mnem Addr Name Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Value
EADR D1H EMU Address Register 00000000 RW EADR.6 EADR.5 EADR.4 EADR.3 EADR.2 EADR.1 EADR.0
EDTAH D2H EMU Data Register high byte 00000000 EDTAH.7 EDTAH.6 EDTAH.5 EDTAH.4 EDTAH.3 EDTAH.2 EDTAH.1 EDTAH.0
EDTAM D3H EMU Data Register mid byte 00000000 EDTAM.7 EDTAM.6 EDTAM.5 EDTAM.4 EDTAM.3 EDTAM.2 EDTAM.1 EDTAM.0
EDTAL D4H EMU Data Register low byte 00000000 EDTAL.7 EDTAL.6 EDTAL.5 EDTAL.4 EDTAL.3 EDTAL.2 EDTAL.1 EDTAL.0
EMUSR D5H EMU Status/Control Register ******** DSPEN EMUCLK1 EMUCLK0 SAGF NoQLd NoPLd REVQ REVP
EMUIE D6H EMU interrupt enable Register 00000000 QFEN PFEN DSPIE QFIE PFIE SUMIE SAGIE ZXIE
EMUIF D7H EMU interrupt request Register --00000000 - - DSPIF QFIF PFIF SUMIF SAGIF ZXIF

注意：*：EMUSR initial value will vary according to the different types of reset.
Table 6.20 External Interrupt SFRs
POR/WDT/LVR
Mnem Addr Name Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Value
EXF0 E8H External interrupt 0 flag --000000 - EMUF IT31 IT30 IT21 IT20 IE3 IE2

TCON 88H Timer/Counter 2 Control 00000-- TF1 TR1 TF0 TR0 IE1 IT1 - -

Table 6.21 PWM SFRs

POR/WDT/LVR
Mnem Addr Name Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Value
PWM0CON C3H PWM0 conotrol 0000-000 PWM0EN PWM0S PWM0CK1 PWM0CK0 - PWM0IE PWM0IF PWM0SS
PWM1CON 93H PWM1 conotrol 0000-000 PWM1EN PWM1S PWM1CK1 PWM1CK0 - PWM1IE PWM1IF PWM1SS
PWM0PH C7H PWM0 period high 4bit ----0000 - - - - PWM0P.11 PWM0P.10 PWM0P.9 PWM0P.8
PWM0PL C6H PWM0 period low 8bit 00000000 PWM0P.7 PWM0P.6 PWM0P.5 PWM0P.4 PWM0P.3 PWM0P.2 PWM0P.1 PWM0P.0
PWM0DH C5H PWM0 duty high 4bit ----0000 - - - - PWM0D.11 PWM0D.10 PWM0D.9 PWM0D.8
PWM0DL C4H PWM0 duty low 8bit 00000000 PWM0D.7 PWM0D.6 PWM0D.5 PWM0D.4 PWM0D.3 PWM0D.2 PWM0D.1 PWM0D.0
PWM1PH 97H PWM1 period high 4bit ----0000 - - - - PWM1P.11 PWM1P.10 PWM1P.9 PWM1P.8
PWM1PL 96H PWM1 period low 8bit 00000000 PWM1P.7 PWM1P.6 PWM1P.5 PWM1P.4 PWM1P.3 PWM1P.2 PWM1P.1 PWM1P.0

15
 SH79F642B
PWM1DH 95H PWM1 duty high 4bit ----0000 - - - - PWM1D.11 PWM1D.10 PWM1D.9 PWM1D.8
PWM1DL 94H PWM1 duty low 8bit 00000000 PWM1D.7 PWM1D.6 PWM1D.5 PWM1D.4 PWM1D.3 PWM1D.2 PWM1D.1 PWM1D.0

Note: -：Reserved bit.

16
 SH79F642B
Single-phase Energy Metering IC integrated LCD driver and enhanced 8051 Microcontroller

SFR mapping figure

Bit
Non Bit Addressable
Addressable

0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

F8h SCON2 P2DRV P3DRV IB_OFFSET IB_DATA (Reserved) FFh
F0h B AUXC IB_CON1 IB_CON2 IB_CON3 IB_CON4 IB_CON5 XPAGE F7h
E8h EXF0 P0PCR P1PCR P2PCR P3PCR P4PCR P5PCR PXMOD EFh
E0h ACC P0CR P1CR P2CR P3CR P4CR P5CR PASLO E7h
D8h SCON1 SBUF1 SADDR1 SADEN1 SBRT1H SBRT1L SFINE2 LDOCON DFh
D0h PSW EADR EDTAH EDTAM EDTAL EMUSR EMUIE EMUIF D7h
C8h T2CON T2MOD RCAP2L RCAP2H TL2 TH2 TCON1 P5 CFh
C0h P4 ADCON ADT PWM0CON PWM0DL PWM0DH PWM0PL PWM0PH C7h

B8h IPL0 IPL1 SBUF2 SADDR2 SADEN2 SBRT2H SBRT2L LPDCON1 BFh

B0h P3 RSTSTAT CLKCON LPDCON IPH0 IPH1 OSCLO B7h

A8h IEN0 IEN1 P0SS P1SS P3SS P4SS P5SS ADCH AFh
A0h P2 IRCON LCDCON1 LCDCON ISPLO ISPCON FLASHCON A7h
98h SCON SBUF SADDR SADEN SBRTH SBRTL SFINE 9Fh
90h P1 ADDL ADDH PWM1CON PWM1DL PWM1DH PWM1PL PWM1PH 97h
88h TCON TMOD TL0 TL1 TH0 TH1 SUSLO 8Fh
80h P0 SP DPL DPH DPL1 DPH1 INSCON PCON 87h
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

Non Bit Addressable

0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
FFF8h - - - - - - - - FFFFh
FFF0h - - - - - - FFF7h
FFE8h - FFEFh
FFE0h - FFE7h
FFD8h - - - - - FFDFh
FFD0h - - - - - FFD7h
FFC8h - - - - - - FFCFh
FFC0h - - - - - - - - FFC7h
FFB8h RTCECL RTCECH RTCTMR - - - - - FFBFh
FFB0h A1SEC A1MIN A1HR RTCCON RTCWR RTCPSW RTCIE RTCIF FFB7h
FFA8h RTCDATH RTCDATL RTCALM A0SEC A0MIN A0HR A0DAY A0DOW FFAFh
FFA0h SBSC SEC MIN HR DAY MTH YR DOW FFA7h

17 V1.0
 SH79F642B
FF98h - - - - - - - - FF9Fh
FF90h - - - - - - FF97h
FF88h - - - - - - - - FF8Fh
FF80h - - - - - - FF87h
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
note: The unused addresses of SFR are not available.
SFR Reset Value
SFR Name Reset Value
ACC 00000000b
B 00000000b
AUXC 00000000b
PSW 00000000b
SP 00000111b
DPL 00000000b
DPH 00000000b
DPL1 00000000b
DPH1 00000000b
INSCON 00000000b

18
 SH79F642B

7. Normal Function
7.1 Instruction Extension
7.1.1 CPU Core SFR
Feature
CPU core registers: ACC, B, PSW, SP, DPL, DPH
Accumulator
ACC is the Accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the Accumulator
simply as A.

B Register
The B register is used during multiply and divide operations. For other instructions it can be treated as another scratch pad
register.

Stack Pointer (SP)

The Stack Pointer Register is 8 bits wide, It is incremented before data is stored during PUSH, CALL executions and it is
decremented after data is out of stack during POP, RET,RETI executions. The stack may reside anywhere in on-chip internal
RAM（00H-FFH）. On reset, the Stack Pointer is initialized to 07H causing the stack to begin at location 08H.

Program Status Word Register (PSW)

The PSW register contains program status information.

Table 7.1 PSW Register

D0H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PSW CY AC F0 RS1 RS0 OV F1 P
R/W R/W R/W R/W R/W R/W R/W R/W R
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit
Bit Mnemonic Description
Number
Carry flag bit
7 CY 0: no carry or borrow in an arithmetic or logic operation
1: a carry or borrow in an arithmetic or logic operation
Auxiliary Carry flag bit
6 AC 0: an auxiliary carry or borrow in an arithmetic or logic operation
1: an auxiliary carry or borrow in an arithmetic or logic operation
F0 flag bit
5 F0
Available to the user for general purposes
R0-R7 Register bank select bits
00: Bank 0 (Address to 00H-07H)
4-3 RS[1:0] 01: Bank 1 (Address to 08H-0FH)
10: Bank 2 (Address to 10H-17H)
11: Bank 3 (Address to 18H-1FH)
Overflow flag bit
2 OV 0: no overflow happen
1: an overflow happen
F1 flag bit
1 F1 Available to the user for general purposes

Parity flag bit

0 P 0: an even number of ``one'' bits in the Accumulator
1: an odd number of ``one'' bits in the Accumulator

19
 SH79F642B
Data Pointer Register (DPTR)
DPTR consists of a high byte (DPH) and a low byte (DPL). Its intended function is to hold a 16-bit address, but it may be
manipulated as a 16-bit register or as two independent 8-bit registers.

7.1.2 Enhanced CPU core SFRs

 Extended 'MUL' and 'DIV' instructions: 16bit*8bit, 16bit/8bit
 Dual Data Pointer
 Enhanced CPU core registers: AUXC, DPL1, DPH1, INSCON

The SH79F642B has modified 'MUL' and 'DIV' instructions. These instructions support 16 bit operand. A new register - the
register is applied to hold the upper part of the operand/result.

The AUXC register is used during 16 bit operand multiply and divide operations. For other instructions it can be treated as
another scratch pad register.

After reset, the CPU is in standard mode, which means that the 'MUL' and 'DIV' instructions are operating like the standard
8051 instructions. To enable the 16 bit mode operation, the corresponding enable bit in the INSCON register must be set.

Result
Operation
A B AUXC
INSCON.2 = 0; 8 bit mode (A)*(B) Low Byte High Byte ---
MUL
INSCON.2 = 1; 16 bit mode (AUXC A)* (B) Low Byte Middle Byte High Byte
INSCON.3 = 0; 8 bit mode (A) / (B) Quotient Low Byte Remainder ---
DIV
INSCON.3 = 1; 16 bit mode (AUXC A) / (B) Quotient Low Byte Remainder Quotient High Byte

Dual Data Pointer

Using two data pointers can accelerate data memory moves. The standard data pointer is called DPTR and the new data
pointer is called DPTR1.

DPTR1 is the same with DPTR, which consists of a high byte (DPH1) and a low byte (DPL1). Its intended function is to hold a
16-bit address, but it may be manipulated as a 16-bit register or as two independent 8-bit registers.

The DPS bit in INSCON register is used to choose the active pointer. The user can switch data pointers by toggling the DPS bit.
And all DPTR-related instructions will use the currently selected data pointer.
7.1.3 Register
Table 7.2 Data Pointer Select Register
86H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
INSCON - - - - DIV MUL - DPS
R/W - - - - R/W R/W - R/W
Reset Value
- - - - 0 0 - 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

16 bit / 8 bit Divide Selection Bit
3 DIV 0: 8 bit Divide
1: 16 bit Divide
16 bit / 8 bit Multiply Selection Bit
2 MUL 0: 8 bit Multiply
1: 16 bit Multiply
Data Pointer Selection Bit
0 DPS 0: Data pointer
1: Data pointer1

20
 SH79F642B
7.2 RAM
7.2.1 Features
SH79F642B provides both internal RAM and external RAM for random data storage. The internal data memory is mapped
into four separated segments:
1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly addressable.
2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable only.
3. The Special Function Registers (SFR, addresses 80h to FFh) are directly addressable only.
4. The expanded RAM bytes are indirectly accessed by MOVX instructions.

The Upper 128 bytes occupy the same address space as SFR, but they are physically separate from SFR space. When an
instruction accesses an internal location above address 7Fh, the CPU can distinguish whether to access the upper 128 bytes
data RAM or to access SFR by different addressing mode of the instruction.
Note: the unused address is unavailable in SFR.

The SH79F642B provides 256 bytes RAM in internal data space, additional 2816 bytes RAM in external data space for
increasing data handling requirement, high level language support and LCD RAM (B00h – B26h) configuration.

The Internal and External RAM configuration

B1FH
LCD RAM

AFFH

External RAM 0FFH 0FFH

Special
Upper 128 bytes
Function
Internal Ram
Register
indirect accesses
direct accesses
80H 80H
7FH
Lower 128 bytes
Internal Ram
direct or indirect accesses
000H 00H

The SH79F642B provides traditional method for accessing of external RAM. Use MOVX A, @Ri or MOVX @Ri, A; to
access external low 256 bytes RAM; MOVX A, @DPTR or MOVX @DPTR, A to access external 64K bytes RAM.
In SH79F642B, the user can also use XPAGE register to access external RAM only with MOVXA, @Ri or MOVX @Ri, A
instructions. The user can use XPAGE to represent the high byte address of RAM above 256 Bytes.

In flash SSP mode, the XPAGE can also be used as sector selector (Refer to SSP Function)

21
 SH79F642B
7.2.2 Register
Table 7.3 Data memory page Register
F7H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
XPAGE XPAGE.7 XPAGE.6 XPAGE.5 XPAGE.4 XPAGE.3 XPAGE.2 XPAGE.1 XPAGE.0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

7-0 XPAGE 7-0 RAM Page Selector

22
 SH79F642B
7.3 Flash Program Memory
7.3.1 Features
 The program memory consists 64 * 1KB sectors, total 64KB
 Programming and erase can be done over the full operation voltage range
 Support 4 code protection mode
 Write, read and erase operation are all supported by In-Circuit Programming (ICP)
 Support overall/sector erase and programming
 Minimum program/erase cycles: Program block : 10,000
EEPROM-like block : 100,000
 Minimum years data retention: 20
 Low power consumption
FFFFH

07FFH
EEPROM Like Data Block Program Memory Block
0000H 0000H

Information Block Program Memory Block

The SH79F642B embeds 64K flash program memory for program code. The flash program memory provides electrical erase
and programming and supports In-Circuit Programming (ICP) mode and Self-Sector Programming (SSP) mode. Every sector is
1024 bytes.
The SH79F642B also embeds 2048 bytes EEPROM-like memory block for storing user data. Every sector is 256 bytes. It has
8 sectors.
Flash operation definition:
In-Circuit Programming (ICP): Through the Flash programmer to wipe the Flash memory, read and write operations.
Self-Sector Programming (SSP) mode: User Program code run in Program Memory to wipe the Flash memory, read and write
operations. But it can not erase the sector which contains program itself.
Flash Memory Supports the Following Operations:
(1) Code Protection Control Mode
SH79F642B code protection function provides a high-performance security measures for the user. It provided 4 protection
modes in .

Code protection mode 0: encrypt the programmer, allow/forbid any programmer write/read operations (not including overall
erase), the uint is 4K (4 sectors), and can protect them respectively.
Code protection mode 1: encrypt the MOVC instruction, allow/forbid through MOVC instructions to read operation in other
sectors, or through SSP mode to erased/write operation, the uint is 4K (4 sectors), and can protect
them respectively.
Code protection mode 2: SSP function allow/forbid control, when selected, chip’s SSP operation (erase or write, not include
read)for code block is forbid, but not for EEPROM-like.
Code protection mode 3: customer password protection, can set password by customer, the password is 6 bytes. If this function
is enable, it means that entering this password first before the programmer or simulator tool do any

23
 SH79F642B
operation (read, write, erase or simulate)for the chip, if the password is right, then the chip allows the
programmer or simulator tool to do the corresponding operation, otherwise it gives error, and don’t
perform the corresponding operation.
The user must use one of the following two ways to complete code protection control mode Settings:
I. Flash programmer in ICP mode is set to corresponding protection bit to enter the protected mode.
II. The SSP mode does not support code protection control mode programming.
(2) Overall Erase
Regardless of the state of the code protection control mode, the overall erase operation will erase all programs, code options,
the code protection bit, but they will not erase EEPROM-like memory block.
The user must use the following way to complete the overall erase:
I. Flash programmer in ICP mode send overall erase instruction to run overall erase.
II. The SSP mode does not support overall erase mode.
(3) Sector Erase
Sector erase operations will erase the content of selected sector. The user program (SSP) and Flash programmer can perform
this operation.
For user programs to perform the operation, code protection mode 1 and mode 2 in the selected sector must be forbidden.
For Flash programmer to perform the operation, code protection mode 0 in the selected sector must be forbidden. If code
protection mode 3 is enable, user must enter the correct password.
The user must use one of the following two ways to complete sector erase:
1. Flash programmer in ICP mode send sector erase instruction to run sector erase.
2. Through the SSP function send sector erase instruction to run sector erase (see chapter SSP).

(4) EEPROM-like Memory Block Erase

EEPROM-like memory block erase operations will erase the content in EEPROM-like memory block. The user program (SSP)
and Flash programmer can perform this operation.
The user must use one of the following two ways to complete EEPROM-like memory block erase:
1. Flash programmer in ICP mode send EEPROM-like memory block erase instruction to run EEPROM-like memory block
erase.
2. Through the SSP function send EEPROM-like memory block erase instruction to run EEPROM-like memory block erase
(see chapter SSP).

(5) Write/Read Code

Write/read code operation can read or write code from flash memory block. The user program (SSP) and Flash programmer
can perform this operation.

For user programs to perform the reading operation, code protection mode 1 in the selected sector must be forbidden.
Regardless of the security bit Settings or not, the user program can read/write the sector which contains program itself (the unit
is 1K ).
For Flash programmer to perform the writting operation, code protection mode 1 and mode 2 in the selected sector must be
forbidden.

Note: If only enable code protection control mode 1, the user program can’t write other sectors, but it can write the sector which
contains program itself (the unit is 1K ).
If use the programmer to perform the operation, code protection mode 0 in the selected sector must be forbidden.

The user must use one of the following two ways to complete Write/Read Code:
1. Flash programmer in ICP mode send write or read code instruction to run write or read code.
2. Through the SSP function send write or read code instruction to run write or read code;
Through MOVC instruction to perform write or read code.

(6) Write/Read EEPROM-like Memory Block

EEPROM-like memory block operation can read or write data from EEPROM-like memory block. The user program (SSP) and
Flash programmer can perform this operation.
The user must use one of the following two ways to complete write/read EEPROM-like memory block:
1. Flash programmer in ICP mode send write/read EEPROM-like memory block instruction to run write/read EEPROM-like
memory block.
2. Through the SSP function send write/read EEPROM-like memory block instruction to run write EEPROM-like memory
block;
Through MOVC instruction to perform reading EEPROM-like operation.

24
 SH79F642B
Flash Memory Block Operation Summary
Operation ICP SSP
Code Protection support not support

Sector Erase support (no security bit) support (no security bit)

Overall Erase support not support

EEPROM-like memory block
support support
erase

Write/Read support (no security bit) support (no security bit)

Read/write EEPROM-like
support support
memory block

7.3.2 Flash Operation in ICP Mode

ICP mode is performed without removing the micro-controller from the system. In ICP mode, the user system must be
power-off, and the programmer can refresh the program memory through ICP programming interface. The ICP programming
interface consists of 6 wires (VDD, GND, TCK, TDI, TMS, TDO).
At first the four JTAG pins (TDO, TDI, TCK, TMS) are used to enter the programming mode. Only after the four pins are inputted
the specified waveform, the CPU will enter the programming mode. For more detail description please refers to the FLASH
Programmer’s user guide.
In ICP mode，all the flash operations are completed by the programmer through 6-wire interface. Since the program timing is
very sensitive, 6 jumpers are needed (VDD, GND, TDO, TDI, TCK, TMS) to separate the program pins from the application
circuit as the following diagram.

Flash
Programmer
MCU
VDD
TMS
TCK

TDI
TDO
GND

To Application
Circuit

Jumper

The recommended steps are as following:

(1) The jumpers must be open to separate the programming pins from the application circuit before programming.
(2) Connect the programming interface with programmer and begin programming.
(3) Disconnect programmer and short these jumpers after programming is complete.

Note:Pin C must connect the 4.7uF capacitor to ground.otherwise the programming will be abnormal.

25
 SH79F642B
7.4 SSP Function
The SH79F642B provides SSP (Self Sector Programming) function, each sector can be sector erased or programmed by
the user’s code if the selected sector is not be protected. But once sector has been programmed, it cannot be reprogrammed
before sector erase.
The SH79F642B build in a complex control flow to prevent the code from carelessly modification. If the dedicated
conditions are not met (IB_CON2~5), the SSP will be terminated.

7.4.1 Registers
1）Sector select Register for erase/programming and Offset register for Programming
This register is used to select the block code of the sector to be erased/programmed, and coordinates IB_OFFSET register
to indicate the address offset of the byte to be programmed in sector.
For program memory, one sector is 1024 bytes, register is defined as follows:
Table 7.4 Offset register for programming
F7H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
XPAGE XPAGE.7 XPAGE.6 XPAGE.5 XPAGE.4 XPAGE.3 XPAGE.2 XPAGE.1 XPAGE.0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

7-2 XPAGE[7-2] Sector of the flash memory to be programmed, 000000 means sector 0, and so on
1-0 XPAGE[1-0] High Address of Offset of the flash memory sector to be programmed

Table 7.5 Offset of flash memory for programming

FBH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF
IB_OFFSET
SET.7 SET.6 SET.5 SET.4 SET.3 SET.2 SET.1 SET.0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

7-0 IB_OFFSET Low Address of Offset of the flash memory sector to be programmed
XPAGE[1:0] and IB_OFFSET[7:0] are 10bits in total, can indicate the offset of all 1024 bytes in 1 program memory block.

EEPROM-like sectors, one sector is 256 bytes, in total 8 sectors, register is defined as follows:
Table 7.6 Sector select Register for erase/programming
F7H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
XPAGE XPAGE.7 XPAGE.6 XPAGE.5 XPAGE.4 XPAGE.3 XPAGE.2 XPAGE.1 XPAGE.0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

7-3 XPAGE[7:3] No significance at the time erase/programming sector
Erased/programmed sector select bit
2-0 XPAGE[2:0]
000：sector 0

26
 SH79F642B
001：sector 1
…
111: sector 7
Use “MOVC A, @A+DPTR” or “MOVC A, @A+PC” to access EEPROM-like sectors.
Note: Need to set FAC bit in FLASHCON register.

Table 7.7Offset register for Programming

FBH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF
IB_OFFSET
SET.7 SET.6 SET.5 SET.4 SET.3 SET.2 SET.1 SET.0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

7-0 IB_OFFSET[7:0] Erased/programmed block unit address
IB_OFFSET[7:0] are 8bits in total, can indicate the offset of all 256 bytes in 1 block.

2)Data Register for Programming

Table 7.8 Data Register for Programming
FCH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IB_DATA IB_DATA.7 IB_DATA.6 IB_DATA.5 IB_DATA.4 IB_DATA.3 IB_DATA.2 IB_DATA.1 IB_DATA.0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

7-0 IB_DATA[7:0] Data to be programmed

3)Type select Register

Table 7.9 SSP Type select Register
F2H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IB_CON1 IB_CON1.7 IB_CON1.6 IB_CON1.5 IB_CON1.4 IB_CON1.3 IB_CON1.2 IB_CON1.1 IB_CON1.0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

SSP Type select
7-0 IB_CON1[7:0] 0xE6: Sector Erase
0x6E: Sector Programming

27
 SH79F642B
4)SSP Flow Control Register
Table 7.10 SSP Flow Control Register1
F3H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IB_CON2 - - - - IB_CON2.3 IB_CON2.2 IB_CON2.1 IB_CON2.0
R/W - - - - R/W R/W R/W R/W
Reset Value
- - - - 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

3-0 IB_CON2[3:0] Must be 05H, else Flash Programming will terminate

Table 7.11 SSP Flow Control Register2

F4H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IB_CON3 - - - - IB_CON3.3 IB_CON3.2 IB_CON3.1 IB_CON3.0
R/W - - - - R/W R/W R/W R/W
Reset Value
- - - - 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

3-0 IB_CON3[3:0] Must be 0AH else Flash Programming will terminate

Table 7.12 SSP Flow Control Register3

F5H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IB_CON4 - - - - IB_CON4.3 IB_CON4.2 IB_CON4.1 IB_CON4.0
R/W - - - - R/W R/W R/W R/W
Reset Value
- - - - 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

3-0 IB_CON4[3:0] Must be 09H, else Flash Programming will terminate

Table 7.13 SSP Flow Control Register4

F6H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IB_CON5 - - - - IB_CON5.3 IB_CON5.2 IB_CON5.1 IB_CON5.0
R/W - - - - R/W R/W R/W R/W
Reset Value
- - - - 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

3-0 IB_CON5[3:0] Must be 06H, else Flash Programming will terminate

28
 SH79F642B
7.4.2 Flash Control Flow

Set IB_OFFSET
Set XPAGE
Set IB_DATA
Set IB_CON1

S0

IB_CON2[3:0]≠5H Set IB_CON2[3:0]=5H

IB_CON2≠5H
S1

IB_CON3≠AH IB_CON2≠5H

Set IB_CON3 = AH
ELSE
S2 IB_CON3≠AH

Set IB_CON4 = 9H

IB_CON4 ≠9H
Reset
IB_CON1-5 S3

Set IB_CON5 = 6H

S4

Sector Erase IB_CON1 = E6H

& IB_CON2[3:0] = 5H
& IB_CON3 = AH
& IB_CON4 = 9H
& IB_CON5 = 6H

IB_CON1 = 6EH
& IB_CON2[3:0] = 5H
& IB_CON3 = AH
& IB_CON4 = 9H
& IB_CON5 = 6H

Programming

29
 SH79F642B
7.4.3 SSP Programming Notice
To successfully complete SSP programming, the user’s software must following the steps below:

A. For Code/Data Programming: note: need to close code protection mode 1 and mode 2
1. Disable interrupt;
2. Fill in the XPAGE, IB_OFFSET for the corresponding address;
3. Fill in IB_DATA if programming is wanted;
4. Fill in IB_CON1-5 sequentially;
5. Add 4 nops for more stable operation;
6. Code/Data programming, CPU will be in IDLE mode; Exit IDLE mode automatically after programming;
7. Go to Step 2 if more data are to be programmed;
8. Clear XPAGE; enable interrupt if necessary.

B. For Sector Erase: note: need to close code protection mode 1 and mode 2
1. Disable interrupt;
2. Fill in the XPAGE for the corresponding sector;
3. Fill in IB_CON1-5 sequentially;
4. Add 4 NOPs for more stable operation;
5. Sector Erase, CPU will be in IDLE mode; Exit IDLE mode automatically after programming;
6. Go to step 2 if more sectors are to be erased;
7. Clear XPAGE; enable interrupt if necessary.

C. For Code Reading:

Just Use “MOVC A, @A+DPTR” or “MOVC A, @A+PC”.

D. For EEPROM-Like:
Steps is same as code programming, the differences are:
1. Set FAC bit in FLASHCON register before programming or erase EEPROM-Like;
2. One sector of EEPROM-Like is 256 bytes, not 1024 bytes.

Note:The FAC bit must be cleared if not need to operate EEPROM-Like.

7.4.4 Readable identification code

Each SH79F642B chip were cured a 40bits readable identification code after the factory. Its value is a random value between
0~0xFFFFFFFFFF and unable to be erased, and can be read by program or programming tools.
When read readable identification code, set the FAC bit first and then evaluate“0127BH~127FH”to DPTR, clear A, and then
use “MOVC A，@A+DPTR”to read.

Note: The FAC bit must be cleared after reading readable identification code, otherwise it will effect the instruction execution
of user’s program .

FLASHCON register description is as follows:

Table7.14 Flash Access Control Register
A7H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
FLASHCON - - - - - - - FAC
R/W - - - - - - - R/W
Reset Value
- - - - - - - 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

FAC: Flash access control
0 FAC 0: MOVC or SSP access main memory
1: MOVC or SSP access EEPROM-like

30
 SH79F642B

7.5 System Clock and Oscillator

7.5.1 Features
Only support 1 oscillator type: 32.768kHz crystal
Built-in 8.192MHz phase locked loop (PLL) oscillator
Built-in 32.768kHz speed up circuit
Built-in system clock prescaler
7.5.2 Clock definition

The SH79F642B have several internal clocks defined as below:

OSCCLK: the oscillator clock is 32.768kHz crystal.
fOSC is defined as the OSCCLK frequency. tOSC is defined as the OSCCLK period.
PLLCLK: the PLL oscillator clock. fPLL is defined as the PLLCLK frequency. tPLL is defined as the PLLCLK period.
WDTCLK: the internal 2kHz WDT RC clock. fWDT is defined as the WDTCLK frequency. tWDT is defined as the WDTCLK
period.
OSCSCLK: the input of system clock prescaler. It can be OSCCLK or PLL clock. fOSCS is defined as the OSCSCLK
frequency. tOSCS is defined as the OSCSCLK period.
SYSCLK: system clock, the output of system clock prescaler. It is the CPU instruction clock. fSYS is defined as the SYSCLK
frequency. tSYS is defined as the SYSCLK period.

7.5.3 Description
SH79F642B Only support 1 oscillator type: 32.768kHz crystal. The oscillator generates the basic clock pulse that provides
the system clock to supply CPU and on-chip peripherals.
A phase locked loop (PLL) oscillator is built in SH79F642B, which can provide up to 8.192MHz oscillator clock. PLLCON
control register can decide whether PLL oscillator is enabled or disabled.

31
 SH79F642B
7.5.4 Registers
Table 7.15 System Clock Control register
B2H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CLKCON 32K_SPDUP CLKS1 CLKS0 - PLLCON FS2 - -
R/W R/W R/W R/W - R/W R/W - -
Reset Value
1 1 1 - 0 0 - -
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

32.768kHz oscillator speed up mode control bit
0: 32.768kHz oscillator normal mode, cleared by software.
1: 32.768kHz oscillator speed up mode, set by hardware or software.
This control bit is set by hardware automatically in all kinds of RESET such as
Power on reset, watch dog reset etc. to speed up the 32.768kHz Oscillator
7 32K_SPDUP oscillating, shorten the 32.768kHz oscillator start-oscillating time.
And this bit also can be set or cleared by software if necessary. Such as set
before entering Power-down mode and cleared when Power-down mode wakes
up.
It should be noticed that turning off 32.768kHz oscillator speed up (clear this bit)
could reduce the system power consumption.
SYSCLK Prescaler Register
00: fSYS = fOSCS
01: fSYS = fOSCS / 2
6-5 CLKS [1: 0]
10: fSYS = fOSCS / 4
11: fSYS = fOSCS / 12
If 32.768kHz oscillator is selected as OSCSCLK, these control bits is invalid.
PLL Oscillator On control Register
3 PLLCON 0: Cleared to turn off PLL oscillator.
1: Set to turn on PLL oscillator.
Frequency Select Register
2 FS2 0: 32.768kHz is selected as OSCSCLK.
1: PLLCLK is selected as OSCSCLK.
Note:
To select PLLCLK as OSCSCLK, the steps below must be done in sequence:
1. Set PLLCON =1 and turn on the PLL oscillator
2. Wait at least 2ms
3. Set FS=1 to select PLLCLK as OSCSCLK

32
 SH79F642B
7.5.5 Oscillator Type
32768Hz crystal&internal PLL :
C1
XTAL1
32.768
kHz
XTAL2
C2

Crystal Oscillator
Recommend Type Manufacturer
Frequency C1 C2
DT 38 (φ3x8) KDS
32.768kHz 5~12.5pF 5~12.5pF Shenzhen DGJB
φ3x8 – 32.768kHz
Electronic Co.,Ltd.

Notes:
(1) Capacitor values are used for design guidance only!
(2) These capacitors were tested with the crystals listed above for basic start-up and operation. They are not optimized.
(3) Be careful for the stray capacitance on PCB board, the user should test the performance of the oscillator over the expected
VDD and the temperature range for the application.
Before selecting crystal/ceramic, the user should consult the crystal/ceramic manufacturer for appropriate value of external
component to get best performance, visit http://www.sinowealth.comfor more recommended manufactures

33
 SH79F642B
7.6 I/O Port
7.6.1 Features

 46 bi-directional I/O ports

 Share with alternative functions
The SH79F642B has 6 groups of 46 bi-directional I/O ports. The PORT data is put in Px register. The PORT control register
(PxCRy) controls the PORT as input or output. Each I/O port has an internal pull-high resistor, which is controlled by PxPCRy
when the PORT is used as input (x=0~5,y=0~7).
SH79F642B I/O ports are supplied by VOUT.
For SH79F642B, some I/O pins can share with alternative functions. There exists a priority rule in CPU to avoid these
functions be conflict when all the functions are enabled. (Refer to Port Share Section for details)

7.6.2 Registers
Table 7.16 Port Control Register
E1H- E6H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P0CR (E1H) P0CR.7 P0CR.6 P0CR.5 P0CR.4 P0CR.3 P0CR.2 P0CR.1 P0CR.0
P1CR (E2H) P1CR.7 P1CR.6 P1CR.5 P1CR.4 P1CR.3 P1CR.2 P1CR.1 P1CR.0
P2CR (E3H) P2CR.7 P2CR.6 P2CR.5 P2CR.4 P2CR.3 P2CR.2 P2CR.1 P2CR.0
P3CR (E4H) - P3CR.6 P3CR.5 P3CR.4 P3CR.3 P3CR.2 - P3CR.0
P4CR (E5H) P4CR.7 P4CR.6 P4CR.5 P4CR.4 P4CR.3 P4CR.2 P4CR.1 P4CR.0
P5CR (E6H) P5CR.7 P5CR.6 P5CR.5 P5CR.4 P5CR.3 P5CR.2 P5CR.1 P5CR.0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

Port input/output direction control Register
PxCR.y
7-0 0: input mode (default)
x=0~5, y=0~7
1: output mode
Note: 7&1 bits of P3CR are reserved and always remain ‘1’.

Table7.17 Port Pull up Resistor Control Register

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P0PCR (E9H) P0PCR.7 P0PCR.6 P0PCR.5 P0PCR.4 P0PCR.3 P0PCR.2 P0PCR.1 P0PCR.0
P1PCR (EAH) P1PCR.7 P1PCR.6 P1PCR.5 P1PCR.4 P1PCR.3 P1PCR.2 P1PCR.1 P1PCR.0
P2PCR (EBH) P2PCR.7 P2PCR.6 P2PCR.5 P2PCR.4 P2PCR.3 P2PCR.2 P2PCR.1 P2PCR.0
P3PCR (ECH) - P3PCR.6 P3PCR.5 P3PCR.4 P3PCR.3 P3PCR.2 - P3PCR.0
P4PCR (EDH) P4PCR.7 P4PCR.6 P4PCR.5 P4PCR.4 P4PCR.3 P4PCR.2 P4PCR.1 P4PCR.0
P5PCR (EEH) P5PCR.7 P5PCR.6 P5PCR.5 P5PCR.4 P5PCR.3 P5PCR.2 P5PCR.1 P5PCR.0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

Input Port internal pull-high resistor enable/disable control
PxPCR.y
7-0 0: internal pull-high resistor disabled (default)
X=0- 5,y=0-7
1: internal pull-high resistor enabled

34
 SH79F642B
Table 7.18 Port Data Register
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P0 (80H) P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
P1 (90H) P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
P2 (A0H) P2.7 P2.6 P2.5 P2.4 P2.3 P2.2* P2.1* P2.0
P3 (B0H) - P3.6 P3.5 P3.4 P3.3 P3.2 - P3.0
P4 (C0H) P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0
P5 (CFH) P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

Px.y Port Data Register
7-0
x=0~5, y=0~7
Note: Port 2.1 and 2.2 are N-channel open drain I/O. The port voltage shouldn’t be over VDD + 0.3V.

Table7.19 Port2 Output Mode Select Register

EFH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PXMOD - - CAL2EN IOMUX1 IOMUX0 P2OS.2 P2OS.1 -
R/W - - R/W R/W R/W R/W R/W -
Reset Value
- - 0 0 0 0 0 -
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

Port 2.4 output mode select
0: output mode of the pin is set to GPIO (default)
5 CAL2EN
1: output mode of the pin is set to RTC pulse output
(Output enable register of RTC should be opened)
Port 3.4 output mode select
00: output mode of the pin is set to GPIO (default)
01: output mode of the pin is set to PF pulse output
4-3 IOMUX[1:0]
10: output mode of the pin is set to QF pulse output
11: output mode of the pin is set to RTC pulse output
(Output enable registers of PF/QF/RTC should be opened)
Port 2 output mode select
P2OS.x
2-1 0: output mode of the pin is set to N-channel open drain type (default)
x =2-1
1: output mode of the pin is set to CMOS push-pull type

Table 7.20 Drive ability of P2/P3 Select Register

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P2DRV(F9H) P2DRV.7 P2DRV.6 P2DRV.5 P2DRV.4 P2DRV.3 P2DRV.2 P2DRV.1 P2DRV.0
P3DRV(FAH) P3DRV.7 P3DRV.6 P3DRV.5 P3DRV.4 P3DRV.3 P3DRV.2 P3DRV.1 P3DRV.0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value
0 0 0 0 0 0 0 0
(POR/WDT/LVR/PIN)

35
 SH79F642B
Bit Number Bit Mnemonic Description
Port 2,3 output mode select
PxDRV.y 0：output drive ability of the pin is set to normal mode
2-1
x =2-3, y = 0-7 1：output drive ability of the pin is set to weak mode
(Drive current value is shown in IOH2, IOL2)

7.6.3 Port Diagram

SFEN

PxPCRy
Output Mode Input Mode

VDD VDD 0 = ON
PxCRy (Pull-up)
1 = OFF

Write I/O Pad

Data Bus Data

Register

Read Port Data Register

Read
Read Data Register/Pad Selection

0: From Pad
1: From data register
0 = OFF
1 = ON

Second
Function

Read Port Pad

Note:
1) The input source of reading input port operation is from input pin directly.
2) The input source of reading output port operation has two paths, one is from the port data Register, and the other is from the
output pin directly. The read Instruction distinguishes which path is selected.
3) The read-modify-write instruction is for the reading of the data register in output mode, and the other instructions are for
reading of the output pin directly.
4) The destination of writing Input / Output port operation is the data register.

36
 SH79F642B
7.6.4 Port Share
The 46 bi-directional I/O ports can also share second or third special function. But the share priority should obey the Outer
Most Inner Lest rule:
The out most pin function in Pin Configuration has the highest priority, and the inner most pin function has the lowest priority.
This means when one pin is occupied by a higher priority function (if enabled), it cannot be used as the lower priority
functional pin , even the lower priority function is also enabled. Only until the higher priority function is closed by hardware or
software, can the corresponding pin be released for the lower priority function use. Also the function that need pull up resister
is also controlled by the same rule.
When port share function is enabled, the user can modify PxCR, PxPCR(x=0~5), but these operations will have no effect on
the port status until the share functions was disabled.
When port share function is enabled, any read or write operation to port will only affect the data register while the port pin
keeps unchanged until all the share functions are disabled.
If the second function enables analog module such as ADC, the read instruction of pin will only return 0, regardless of the
actual pin voltage level or I/O status.

Port 0:
LCD Segment 5-12 (P0.0 – P0.7)
-RXD2(P0.6): EUART 2 data input
-TXD2(P0.7): EUART 2 data output
Table 7.21 PORT0 Share Table
Pin No. Priority Function Enable bit
1 TXD2 When Write to SBUF2 Register
Pin 48 2 SEG12 P0SS.7=1
3 P0.7 Above condition is not met
1 RXD2 Set REN2 bit in SCON2 Register, (Auto Pull up)
Pin 47 2 SEG11 P0SS.6=1
3 P0.6 Above condition is not met
1 SEG5~SEG10 P0SS.x=1 (x=0~5)
Pin 41~46
2 P0.0~P0.5 P0SS.x=0 (x=0~5)

Port 1:
LCD COM1-8 (P1.0-P1.7)
LCD Segment 1-4 (P1.4 – P1.7)
PWM0(P1.4): PWM0 output
Table 7.22 PORT1 Share Table
Pin No. Priority Function Enable bit
1 PWM0 PWM0CON Register PWM0EN=1, and P1SS.4=0
2 COM5 P1SS.4 = 1, PWM0EN=0, LCDCON DUTY[1:0]=01
Pin37
3 SEG1 P1SS.4=1 ,PWM0EN=0,
4 P1.4 Above condition is not met
1 SEG2 P1SS.5 = 1
Pin38 2 COM6 P1SS.5 = 1, LCDCON DUTY[1:0]=01
3 P1.5 Above condition is not met
1 SEG3 P1SS.6= 1
Pin39 2 COM7 P1SS.6 = 1, LCDCON DUTY[1:0]=1X
3 P1.6 P1SS.6 = 0
1 SEG4 P1SS.7= 1
Pin40 2 COM8 P1SS.7 = 1, LCDCON DUTY[1:0]=1X
3 P1.7 P1SS.7 = 0
1 COM1~4 P1SS Register COMS=1
Pin33~36
2 P1.0~P1.3 P1SS Register COMS=0

37
 SH79F642B
Port 2:
———
-RST (P2.0)：RESET pin
-AN0 (P2.3): ADCinput channel 0
-AN1 (P2.4): ADCinput channe 1
-AN2 (P2.5): ADCinput channe 2
-AN3 (P2.6): ADCinput channe 3
-AN5 (P2.7): ADCinput channe 5
-INT2(P2.7): external interrupt 2
-INT3(P2.6): external interrupt 3
-T1 (P2.7): Timer 1 external input
- PF(P2.4): active energy pulse output
- QF(P2.5): reactive energy pulse output
-CALIN2(P2.4): RTC calibration input
-VIN (P2.3): external voltage input
Table 7.23 PORT 2 Share Table
Pin No. Priority Function Enable bit
———
1 RST Code option
Pin19
2 P2.0 Code option
1 VIN Code option
Pin22 2 AN0 CH0=1& ADON=1&SCH [2:0] = 000
3 P2.3 CH0=0
1 AN1 CH1=1& ADON=1&SCH [2:0] = 001
2 CALOUT2 CAL2EN=1&OUTEN in register RTCCON is set ‘1’
Pin23
3 PF PFEN in EMUIE is set ‘1’
4 P2.4 CH1=0 & PFEN=0
1 AN2 CH2=1&ADON=1&SCH [2:0] = 010
Pin24 2 QF QFEN in EMUIE is set ‘1’
3 P2.5 CH2=0
1 AN3 CH3=1&ADON=1&SCH [2:0] = 011

Pin25 EX3=1&P2CR=0x40
2 INT3
( set pull up in program)
3 P2.6 Above condition is not met
1 AN5 CH5=1& ADON=1&SCH [2:0] = 101
--------
TR1=1&C/T----1----=1 (auto pull up)；
2 T1
Pin26 or C/T 1 =0&TC1=1.
EX2=1&P2CR=0x80;
3 INT2
（set pull up in program）
4 P2.7 Above condition is not met

38
 SH79F642B
Port 3:
-RXD0(P3.5): EUART 0 data input
-TXD0(P3.6): EUART 0 data output
-RXD1 (P3.3): EUART 1 data input
-TXD1 (P3.4): EUART 1 data output
-T0 (P3.0): TIMER0 external input or compare output
-T2 (P3.2): TIMER0 2 external input / BaudRate clock output
-T2EX(P3.0): The external clock input pin for the capture timer
-CALOUT (P3.2): RTC compensation output
-LCD Segment 29~32
- IOMUX(P3.4): Multi-function pulse output
Table 7.24 PORT 3 Share Table
Pin No. Priority Function Enable bit
--------
TR0=1&C/T----
0----
=1(auto pull up)；
1 T0
Or C/T 0 =0&TC0=1
In mode0,2,3 EXEN2=1
Pin27
Or in mode 1 DCEN=1
2 T2EX Or in mode 1 DCEN=0& EXEN2=0
(auto pull up)
3 P3.0 Above condition is not met
1 CALOUT OUTEN=1 in RTCCON register
Pin28 2 T2 TR2=1& T2OE=1(auto pull up)
3 P3.2 Above condition is not met
1 RXD1 REN1=1 (auto pull up)
Pin29 2 SEG29 P3SS.3=1
3 P3.3 Above condition is not met
IOMUX[1:0]=01&PFEN=1 or IOMUX[1:0]=10&QFEN=1
1 IOMUX
Or IOMUX[1:0]=11& OUTEN=1 in RTCCON

Pin30 2 TXD1 Write to SBUF1 register

3 SEG30 P3SS.4=1
4 P3.4 Above condition is not met
1 RXD0 REN=1 (auto pull up)
Pin31 2 SEG31 P3SS.5=1
3 P3.5 Above condition is not met
1 TXD0 Write to SBUF register
Pin32 2 SEG32 P3SS.6=1
3 P3.6 Above condition is not met

39
 SH79F642B
Port 4:
LCD Segment 13-20 (P4.0 – P4.7)
Table 7.25 PORT 4 Share Table
Pin No. Priority Function Enable bit
1 SEG13~SEG20 P4SS.x=1(x=0~7)
Pin49~56
2 P4.0~P4.7 P4SS.x=0(x=0~7)

Port 5:
- LCD Segment 21-28 (P5.0 – P5.7)
- PWM1(P5.6): PWM1 output
- INT1(P5.7): External interrupt 1
Table 7.26 PORT 5 Share Table
Pin No. Priority Function Enable bit
1 SEG21~SEG26 P5SS.x=1(x=0~5)
Pin57~62
2 P5.0~P5.5 P5SS.x=0(x=0~5)
1 SEG27 P5SS.6=1
Pin63 2 PWM1 PWM1EN=1&P5SS.6=0
3 P5.6 PWM1EN=0,&P5SS.6=0
1 SEG28 P5SS.7=1
P5SS.7=0, EX1=1&set Port5.7 to input mode
Pin64 2 INT1
(set pull up in program)
3 P5.7 P5SS.7=0&EX1=0

40
 SH79F642B
7.7 TIMER
7.7.1 Features
The SH79F642B has three independent 16-bit timers, Timer 0, Timer 1 and Timer 2.
Timer 0 is compatible to traditional 8051.
Timer1 is compatible to traditional 8051.
Timer2 is compatible to traditional 8052. Auto-reload mode with up or down counter and programmable output function.
Timer 0/1 is also buildup with compare output function.
Timer 0/1 clock source selection
Timer 0/1 clock source divided by
7.7.2 Timer0/1
Each regular two data registers (THx, and TLx acts as (for x = 0, 1)) can be used as a 16-bit register access. They are
controlled by the registers TCON and TMOD. The ET0 of IEN0 register and ET1 position 1 allows the Timer 0 and Timer 1
interrupt. (Refer to the interrupt section).
Timer x mode（x = 0, 1）
Counter / Timer Mode register (TMOD) way to select the bit Mx1-Mx0, select the timer works.
Mode 0: 13-bit counter / timer
Timer 'x 13 counter / timers in Mode 0. THx register store 13-bit counter / timer 8 and TLx is stored 5 (TLx.4-TLx.0). Of TLx
three (TLx.7-TLx.5) is uncertain, and should be ignored when read. When the 13-bit timer register increments, overflow, the
———
system set up timer overflow flag TFx. If the timer x interrupt is enabled, will generate an interrupt. C/ Tx selects the counter /
timer clock source.
——— ———
If the C/ Tx = 1, Timer x input pins (Tx) level from high to low transition, so that the timer x data register plus 1. C/ Tx = 0,
select the system clock timer x is the clock source.
————
When the GATEx = 0, or GATEx = 1 and the input signal INTx effective TRx is set to open the timer. GATEx set to 1 allows
———— ————
the timer to INTx by the external input signal, control, ease of measurement INTx positive pulse width. TRx position not to force
a reset timer, which means that if TRx is set, the timer register will start counting the last the TRx clear the value of 0:00.
Therefore, before enabling the timer, set the initial value of the timer register.
The register TCON1 TCLKSx (x = 0,1) select the system clock or 32.768kHz/8 as timer x (x = 0,1) of the clock source can be
configured as a timer application.
Configurable in TCLKPx (x = 0, 1) select the system clock or system clock 1/12 as the timer x (x = 0, 1) the clock source
register TCON1.
When the timer application, configuration the register TCON1 in TC0 / 1 so that the timer 0/1 overflow T0/T1 pin automatically
flip. If TC0 / 1 is set to 1, the T0/T1 pin is automatically set as an output.

System Clock
1/12
32.768KHz/8
TCLKPx Overflow
=0
TCLKSx
C/Tx TLx THx Interrupt
TFx
=1 (5bits) (8bits) Request
Tx Overflow
0:Switch Off Flag
GATEx 1:Switch On Tx
INTx + C/Tx=0 and TCx=1
&
TRx The Block Diagram of mode0 of Timerx ( x=0,1 )

Note: INT0 is not valid

Mode 1: 16-bit counter / timer
In addition to the 16-bit timer / counter, a run and the way of the way consistent. Open and configure the counter / timer also
as a way to mode 0.

41
 SH79F642B

System Clock
1/12
32.768KHz/8
Overflow
TCLKPx
=0
TCLKSx
C/Tx TLx THx Interrupt
TFx
=1 (8bits) (8bits) Request
Tx Overflow
0:Switch Off Flag
GATEx 1:Switch On Tx
INTx + C/Tx=0 and TCx=1
&
TRx The Block Diagram of mode1 of Timerx ( x=0,1 )

Note: INT0 is not valid

Mode 2: 8-bit auto-reload counter / timer
Mode 2, Timer x is 8-bit auto-reload counter / timer. TLx store the count value of THx, store the reload value. When in TLx
counter overflows to 0x00, set from the timer overflow flag TFx, the values of the registers THx reload register TLx. If the timer
interrupt is enabled, when TFx set will generate an interrupt. The reload value in THx will not change. Allows the timer to the
correct count before the start, TLx must be initialized to the desired value.
In addition to auto-reload function, mode 2 counter / timer enable and configuration mode 1 and 0 is the same.
When the timer application that can be configured the register TCON1 TCLKSx (x = 0, 1) bits select the system clock or
32.768kHz/8 timer x (x = 0, 1) the clock source.
Configurable in TCLKPx (x = 0, 1) select the system clock or system clock 1/12 as the timer x (x = 0, 1) the clock source
register TCON1.
When the timer application, configuration the register TCON1 in TC0 / 1 so that the timer 0/1 overflow T0/T1 pin
automatically flip. If TC0 / 1 is set to 1, the T0/T1 pin is automatically set as an output.

TH0
(8bits)
System Clock
1/12
Reload
32.768KHz/8
TCLKPx
TCLKSx =0
overflow
C/Tx TL0 Interrupt
TFx
(8bits) Request
Tx =1
Overflow
Flag
0:Switch Off
GATEx 1:Switch On Tx
INTx + C/Tx=0 and TCx=1
&
TRx The Block Diagram of mode2 of Timerx (x=0,1)

Note: INT0 is not valid

Mode 3: Two 8-bit counter / timer (only Timer 0)
In Mode 3, Timer 0 is used as two independent 8-bit counter / timer, TL0 and TH0 control.The TL0 use the Timer 0 control (in
TCON) and status (in TMOD) bits: TR0, C/T0GATE0 and TF0. The TL0 use the system or 32.768kHz clock or an external,input
signal as a clock source.
TH0 can only be used as the timer clock source from the system clock. The TH0 by Timer 1 control bit TR1 control is enabled,
the overflow Timer 1 overflow flag TF1 set, Control Timer 1 interrupt.

42
 SH79F642B
Timer 0 in Mode 3, Timer 1 can operate in modes 0, 1 or 2, but not at 1 TF1 flag and generate an interrupt. TH1 and TL1 can
only be used as a timer function, the clock source from the system clock, bit invalid GATE1. T1 input pin pull-up resistor is not
valid. Timer 1 enabled or not, because the control of TR1 Timer 0 occupied. Timer is enabled, the one in the way 0, 1 or 2:00 in
Mode 3 is turned off.
Register TCON1 the TCLKS0 select the system clock or 32.768kHz/8 as the timer clock source can be configured as a timer
application.Can be configured to register TCON1 the TCLKP0 select the system clock or system clock 1/12 as the clock source
of timer 0.
When the timer application, configuration the register TCON1 in TC0 overflow of Timer 0 T0 pin automatically flip. If TC0 is set
to 1, the T0 pin is automatically set as an output.

System Clock
1/12
32.768kHz/8
=0
TCLKP0 Overflow
C/T0 TL0 Interrupt
TCLKS0 TF0
(8bits) Request
=1
T0
Overflow
0:Switch Off Flag
GATE0 1:Switch On
T0
& C/T0=0 and TC0=1
TR0

System Clock
1/12 TH0 Overflow Interrupt
TF1
(8bits) Request
32.768kHz/8
TCLKP0 0:Switch Off Overflow
TCLKS0 1:Switch On Flag
TR1

The Block Diagram of mode3 of Timer0

.

43
 SH79F642B
Registers
Table 7.27 Timer / Counter x control register (x = 0,1)
88H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

Timer x overflow flag
TFx 0: Timer x overflow, can be cleared by software.
7,5
x = 0, 1 1: Timer x overflow is set by hardware; by software set to 1 will cause the timer
interrupt
Timer x to start, stop control bit
TRx 0: stop the timer x
6,4
x = 0, 1 1: Start the timer x
IEx External interrupt x request flag
3,1
x =0, 1
ITx External interrupt x trigger mode select bits
2,0
x = 0,1

Table 7.28 Timer / counter MODE register (x = 0,1)

89H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
——— ———
TMOD GATE1 C/T1 M11 M10 GATE0 C/T0 M01 M00
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

GATEx Timer x Gate Control bits
7,3 0 : Timer x is enabled whenever TRx control bit is set
x = 0, 1 1 : Timer x is enabled only while INTx pin is high and TRx control bit is set
———
Timer x Timer / Counter mode selected bits
6,2 C/ Tx 0 : Timer Mode,
x = 0, 1 1 : Counter Mode
Timer x Timer mode selected bits
5-4 Mx [1:0] 00 : Mode 0, 13-bit up counter / timer, bit7~5 of TLx is ignored.
01 : Mode 1, 16-bit up counter / timer
1-0 x = 0, 1 10 : Mode 2, 8-bit auto-reload up counter/timer
11 : Mode 3 (only for Timer0), two 8-bit up timer.

Table 7.29 Timer / counter data register

8AH-8DH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TL0(8AH) TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0
TH0(8CH) TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0
TL1(8BH) TL1.7 TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.0
TH1(8DH) TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

TLx.y , THx.y
7-0 Timer x low & high byte counter
x=0-1, y=0-7

44
 SH79F642B

Table 7.30 Timer / counter control register

CEH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TCON1 - TCLKS1 TCLKS0 - TCLKP1 TCLKP0 TC1 TC0
W/R - W/R W/R - W/R W/R W/R W/R
Reset value
- 0 0 - 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

Timer x Clock Source Control bit
TCLKSx
0: the system clock source as the clock of timer x
6-5 x=0,1
1: Select the clock source of 32.768kHz/8 as the timer x
Timer x clock source prescaler control bits
TCLKPx
0: Select the system clock 1/12 as the timer x clock source
3-2 x=0,1 1: Select the system clock as the clock source of timer x
More output function allows bit
TCx
0: Disable the timer x output compare function
1-0 x=0,1
1: Enable the timer x output compare function

45
 SH79F642B

7.7.3 Timer2
The Timer 2 in the SH79F642B is the standard C52 Timer 2.It is implemented as a 16-bit register accessed as two
cascaded Data Registers: TH2 and TL2. It is controlled by the register TCON2 and TMOD2. The Timer 2 interrupt can be
enabled by setting ET2 bit in IEN0 register (See Interrupt section).
For Timer2 operation, C/T2 selects system clock (timer operation) or external pin T2 (counter operation) as the timer clock
input. Setting TR2 allows Timer 2/Counter 2 Data Register to increment by the selected input.
TCLKP2 in T2MOD selects system clock or 1/12 system clock as the Timer 2 clock source.

Timer 2 Modes
Timer 2 has three kinds of work: Capture / Reload with increment or decrement the counter of the auto-reload mode and
programmable clock output. CP/RL2 combination of selection of these ways.
Timer 2 Modes select

———
C/T2 T2OE DCEN TR2 CP/RL2 mode
X 0 X 1 1 0 16 bit capture
X 0 0 1 0
1 16 bit auto-reload timer
X 0 1 1 0
0 1 X 1 X 3 Programmable clock-output only
1 1 X 1 X X Not suggest to use this mode
X X X 0 X X Timer2 stop, the T2EX path still enable

Mode 0: 16 bit Capture

In the capture mode, two options are selected by bit EXEN2 in T2CON.
If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which will set TF2 on overflow to generate an interrupt if IET2 is enabled.
If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transition at external input T2EX also causes the current value
in TH2 and TL2 to be captured into RCAP2H and RCAP2L respectively, In addition, the transition at T2EX causes bit EXF2 in
T2CON to be set. The EXF2 bit, like TF2, can also generate an interrupt if IET2 is enabled.

System clock
1/12

=0 Increment Mode
TCLKP2 C/T2
TL2 TH2 TF2
T2 =1
0:Switch Off Overflow flag
TR2 1:Switch On

CP / RL2 Interrupt
& + Request
EXEN2 RCAP2L RCAP2H
0:Switch Off
1:Switch On
T2EX
EXF2

External falling
Block Diagram of 16 bit Capcture mode (Mode 0) of Timer2 edge flag

46
 SH79F642B
Mode 1: 16 bit auto-reload timer
Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by
DCEN (Down Counter Enable) bit in T2MOD. Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When
DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.

When DCEN=0, two options are selected by bit EXEN2 in T2CON.

If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer
registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L, which are pressed by software.
If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This
transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled.

System clock
1/12
Increment Mode
=0
TCLKP2 C/T2 TL2 TH2 TF2
=1
T2
Overflow
0:Switch Off Flag
TR2 1:Switch On
Interrupt
+ Request
RCAP2L RCAP2H

EXEN2
+ External Falling
0:Switch Off Edge flag
T2EX 1:Switch On
EXF2

The Block Diagram of Auto Relode Mode (Mode 1)of Timer2 (DCEN=0)

Setting the DCEN bit enables Timer 2 to count up or down. When DCEN = 1, the T2EX pin controls the direction of the
count, and EXEN2’s control is invalid.
A logical “1” at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also
causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively.
A logical “0” at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in
RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers.
The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this
operating mode, EXF2 does not flag an interrupt.

47
 SH79F642B

FFH FFH

System clock
1/12

=0 Interrupt
TCLKP2
Request
C/T2 TL2 TH2 TF2
T2 =1
Overflow
0:Switch Off Flag
TR2 1:Switch On
Toggle
RCAP2L RCAP2H
1.T2EX=1， Timer2 is up counter
T2EX 2.T2EX=0， Timer2 is down counter EXF2

The Block Diagram of Auto-Reload Mode ( Mode 1) of Timer2 (DCEN=1)

Mode 3: Programmable Clock output

In this mode the clock-out frequency depends on the system clock and the reload value of Timer 2 Capture registers (RCAP2H,
RCAP2L), as shown in the following equation.
1 System Clock
Clock Out Frequency = ×
2 × 2 65536 − [ RCAP 2 H , RCAP 2 L]
Timer 2 overflow will not generate an interrupt, so it is possible to use Timer 2 as a baud-rate generator and a clock output
simultaneously with the same frequency.

System clock
1/12 /2
=0
TCLKP2
C/ T2 TL2 TH2
=1

0:Switch Off
TR2 1:Switch On

C/ T2
RCAP2L RCAP2H

T2OE
0:Switch Off
T2 1:Switch On
/2

EXEN2
0:Switch Off
T2EX Timer2 Interrupt
1:Switch On Request
EXF2

The Block Diagram of Programmable Clock output ( Mode 3 ) of Timer2

48
 SH79F642B
Note:
(1) TF2 and EXF2 both can generate an interrupt and share the same interrupt vector address.
(2) TF2 and EXF2 can be set to ‘1’ in any conditions, and they can be cleared only by software or hardware reset.
(3) When EA = 1 and ET2 = 1, it generates the Timer 2 interrupt by setting TF2&EXF2=1.
(4) 4&5 bits in T2CON can’t be writtern other than ‘0’, otherwise T2 may not work.

49
 SH79F642B
Registers
Table 7.31 Timer 2 Control register
C8H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
——— ————
T2CON TF2 EXF2 - - EXEN2 TR2 C/T2 CP/RL2
R/W R/W R/W - - R/W R/W R/W R/W
Reset Value
0 0 - - 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

Timer 2 overflow flag
7 TF2 0 : Timer 2 no overflow, can be cleared by software
1 : Timer 2 overflow, set by hardware; set by software will cause a timer interrupt
External event input (falling edge) from T2EX pin detected flag bit.
6 EXF2 0 : No external event input (Must be cleared by software)
1 : Detected external event input (Set by hardware if EXEN2 = 1)
External event input (falling edge) from T2EX pin used as Reload/Capture trigger
enable/disable control bit
3 EXEN2 0 : Ignore events on T2EX pin for Timer 2 operation
1 : Cause a capture or reload when a negative edge on T2EX pin is detected,
when Timer 2 is not used to clock the EUART (T2EX always has a pull up resistor)
Timer2 start/stop control bit
2 TR2 0 : Stop Timer 2
1 : Start Timer 2
Timer 2 Timer / Counter mode selected bit
———
1 C/T2 0 : Timer Mode, T2 pin is used as I/O port
1 : Counter Mode, the internal pull-up resister is turned on
Capture/Reload mode selected bit
————
0 CP/RL2 0 : 16 bits timer/counter with reload function
1 : 16 bits timer/counter with capture function

50
 SH79F642B

Table 7.32 Timer 2 Mode Control register

C9H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
T2MOD TCLKP2 - - - - - T2OE DCEN
R/W R/W - - - - - R/W R/W
Reset Value
0 - - - - - 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

Frequency devision select:
7 TCLKP2 0 : Select 1/12 system clock as Timer 2 clock source.
1 : Select system clock as Timer 2 clock source.
Timer 2 Output Enable bit
1 T2OE 0 : Set P3.2/T2 as clock input or I/O port.
1 : Set P3.2/T2 as clock output (Baud-Rate generator mode)
Down Counter Enable bit
0 DCEN 0 : Disable Timer 2 as up/down counter, timer 2 is an up counter.
1 : Enable Timer 2 as up/down counter.

Table 7.33 Timer 2 Reload/Capture & Data Registers

CAH- CDH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RCAP2L(CAH) RCAP2L.7 RCAP2L.6 RCAP2L.5 RCAP2L.4 RCAP2L.3 RCAP2L.2 RCAP2L.1 RCAP2L.0
RCAP2H(CBH) RCAP2H.7 RCAP2H.6 RCAP2H.5 RCAP2H.4 RCAP2H.3 RCAP2H.2 RCAP2H.1 RCAP2H.0
TL2(CCH) TL2.7 TL2.6 TL2.5 TL2.4 TL2.3 TL2.2 TL2.1 TL2.0
TH2(CDH) TH2.7 TH2.6 TH2.5 TH2.4 TH2.3 TH2.2 TH2.1 TH2.0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value
（POR/WDT/LVR/ 0 0 0 0 0 0 0 0
PIN）

Bit Number Bit Mnemonic Description

RCAP2L.x Timer 2 Reload/ Capturer Data, x=0~7
7-0
RCAP2H.x
TL2.x Timer 2 Low & High byte counter, x=0~7
7-0
TH2.x

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 SH79F642B

7.8 Interrupt
7.8.1 Features
14 interrupt sources
4 interrupt priority levels
Program Over Range interrupt

Outline
SH79F642B 14 interrupt sources: 3 External interrupt (external interrupt 1/2/3), three timer interrupts (timer 0/1/2), 3 EUART
interrupts, ADC interrupt, The RTC interrupt ,PWM interrupt, LPD interrupt and EMU interrupt.

7.8.3 Interrupt Enable control

Each interrupt source can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt
enable registers IEN0 or IEN1. The IEN0 register also contains a global interrupt enable bit, EA, which can enable/disable all
interrupts at once. Generally, after reset, all interrupt enable bits are set to 0, which means that the corresponding interrupts are
disabled.

Table 7.34 Primary Interrupt Enable Register

A8H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IEN0 EA EADTP ET2 ES0 ET1 EX1 ET0 -
W/R W/R W/R W/R W/R W/R W/R W/R -
Reset value
0 0 0 0 0 0 0 -
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

All Interrupt Enable bit
7 EA 0: Disable all interrupts
1: Enable all interrupts
ADC Interrupt Enable bit
6 EADTP 0: Disable ADC interrupt
1: Enable ADC interrupt
Timer2 overflow interrupt enable bit
5 ET2 0: Disable Timer2 overflow interrupt
1: Enable Timer2 overflow interrupt
EUART0 Interrupt Enable bit
4 ES0 0: Disable EUART0 interrupt
1: Enable EUART0 interrupt
Timer 1 overflow Interrupt Enable bit
3 ET1 0: Disable Timer 1 overflow interrupt
1: Enable Timer 1 overflow interrupt
External Interrupt 1 Enable bit
2 EX1 0: Disable External Interrupt 1
1: Enable External Interrupt 1
Timer 0 overflow Interrupt Enable bit
1 ET0 0: Disable Timer 0 overflow interrupt
1: Enable Timer 0 overflow interrupt
0 - Reserved

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 SH79F642B
Table 7.35 Primary Interrupt Enable Register\
A9H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IEN1 ELPD ES2 EPWM ES1 ERTC EX3 EX2 EEMU
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

LPD Interrupt Enable bit
7 ELPD 0: Disable LPD interrupt
1: Enable LPD interrupt
EUART2 Interrupt Enable bit
6 ES2 0: Disable EUART2 interrupt
1: Enable EUART2 interrupt
PWM Interrupt Enable bit
5 EPWM 0: Disable PWM interrupt
1: Enable PWM interrupt
EUART1 Interrupt Enable bit
4 ES1 0: Disable EUART1 interrupt
1: Enable EUART1 interrupt
RTC Interrupt Enable bit
3 ERTC 0: Disable RTC interrupt
1: Enable RTC interrupt
External Interrupt 3 Enable bit
2 EX3 0: Disable External Interrupt 3
1: Enable External Interrupt 3
External Interrupt 2 Enable bit
1 EX2 0: Disable External Interrupt 2
1: Enable External Interrupt 2
Energy Metering Interrupt Enable bit
0 EEMU 0：Disable EMU interrupt
1：Enable EMU interrupt

53
 SH79F642B
7.8.4 Interrupt Flag
Each interrupt source has its own interrupt flag, when interrupt occurs, corresponding flag will be set by hardware, the interrupt
flag bits are listed in Table bellow.
when an interrupt is generated, the hardware will be set from the corresponding flag Individual interrupt flag bits are listed
in the interrupt summary table.
For external interrupt (INT1/2/3), when an external interrupt 1/2/3 is generated, if the interrupt was edge trigged, the
interrupt flag (IE0-1 in TCON, IE2-3 in EXF0) that generated this interrupt is cleared by hardware when the service routine is
vectored. If the interrupt was level trigged, then the requesting external source directly controls the request flag, rather than the
on-chip hardware.
An external interrupt source to generate an external interrupt INTx (x = 1,2,3), if the interrupt is edge triggered, the CPU in
response to interrupt, the interrupt flag (TCON register IE1, EXF0 register of the IE2 / 3) is hardware clear; interrupt is a low
level triggered external interrupt source to the direct control of the interrupt flag, rather than controlled by the on-chip hardware.
When the timer 0/1 counter overflow, the TCON register TFx (for x = 0, 1) will generate the interrupt flag, resulting in the
Timer 0/1 interrupt the CPU after the interrupt flag is automatically cleared by hardware.
The timer 2 interrupt is generated by the logical OR of flag TF2 and bit EXF2 in T2CON register, which is set by hardware.
None of these flags can be cleared by hardware when the service routine is vectored. In fact, the service routine may have to
determine whether it was TF2 or EXF2 that generated the interrupt, so the flag must be cleared by software.
T2CON register TF2 or EXF2 flag, generate timer interrupt, the CPU after the interrupt, the flag can not be hardware
automatically cleared. In fact, the interrupt service routine must decide whether an interrupt is generated by the TF2 or EXF2
flag must be cleared by software.
The EUART interrupt is generated by the logical OR of flag RI and TI in SCON register, which is set by hardware. Neither
of these flags can be cleared by hardware when the service routine is vectored. In fact, the service routine will normally have to
determine whether it was the receive interrupt flag or the transmission interrupt flag that generated the interrupt, so the flag
must be cleared by software.
SCON register sign of RI or TI is set to 1, resulting in EUARTx (x = 0, 1) interrupt the CPU after the interrupt flag is not by
hardware automatically cleared. In fact, the interrupt service routine must determine whether the received interrupt or an
interrupt flag must be cleared by software. EUART2 EUART1 share an interrupt address.
The ADC interrupt is generated by ADCIF bit in ADCON. If an interrupt is generated, the converted result in
ADCDH/ADCDL will be valid. If continuous compare function in ADC module is Enable, ADCIF will not be set at each
conversion, but set if converted result is larger than compare value. The flag must be cleared by software.
ADCON register ADCIF flag 1:00, resulting in the ADC interrupt. If the interrupt is generated, the ADDH / ADDL the, result
of the conversion is valid. Continuous comparison function of the ADC module is turned on if the result is greater than the
comparison value, conversion, if the conversion result is less than the comparison value, the ADCIF flag 0;, ADCIF flag ADCIF
interrupt flag must be performed by software cleared.
The RTC interrupt is generated by IT0IF or DAYIF or HRIF or MINIF or SECIF or ALM1IF or ALM0IF of flag in RTCIF.
These flags must be cleared by software.
RTCIF register IT0IF or DAYIF or HRIF or MINIF or SECIF or ALM1IF or ALM0IF flag=1, resulting in RTC interrupt. These
flags must be cleared by software.
The PWM interrupts are generated by PWM0IF in PWMxCON. The flags can be cleared by software.
PWMxCON (x = 0 ~ 1) the register PWMIFx flag 1, the PWM interrupt flag must be cleared by software.
The LPD interrupt is generated by LPDIF in LPDCON register. And the flag can only be cleared by hardware.
The LPDCON register LPDIF flag is set, LPD generate an interrupt. CPU in the response of the interrupt flag is hardware
automatically clears.
Setting the corresponding EMUIF register after a energy metering period, then AND with the EMUIE register, if the result
isn’t zero, the EXF0 register EMUF flag, resulting in the EMU interrupt. The flag must be cleared by software
Table 7.36 External Interrupt Flag Register
88H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

TFx Timer x overflow flag
7,5
x = 0, 1 0: Timer x overflow, can be cleared by software.

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 SH79F642B
1: Timer x overflow is set by hardware; by software set to 1 will cause the timer
interrupt
Timer x to start, stop control bit
TRx
6,4 0: stop the timer x
x = 0, 1
1: Start the timer x
External interrupt x request flag
IEx
3,1 0 : No interrupt pending
x = 0,1
1 : Interrupt is pending
External interrupt x trigger mode select bit
ITx
2,0 0 : Low Level trigger
x = 0,1
1 : Trigger on falling edge

Table 7.37 External Interrupt Flag Register

E8H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
EXF0 - EMUF IT31 IT30 IT21 IT20 IE3 IE2
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value
- 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

Energy Metering interrupt request flag
6 EMUF 0 = No interrupt pending
1 = Interrupt is pending
External interrupt 3 trigger mode
00 = Low Level trigger
5-4 IT3[1:0] 01 = Trigger on falling edge
10 = Trigger on rising edge
11 = Trigger on both edge
External interrupt 2 trigger mode
00 = Low Level trigger
3-2 IT2[1:0] 01 = Trigger on falling edge
10 = Trigger on rising edge
11 = Trigger on both edge
External interrupt 3 request flag
0 = No interrupt pending
1 IE3
1 = Interrupt is pending
IE3/2 is cleared by hardware
External interrupt 2 request flag
0 = No interrupt pending
0 IE2
1 = Interrupt is pending
IE3/2 is cleared by hardware

7.8.5 Interrupt Vector

When an interrupt occurs, the program counter is pushed onto the stack and the corresponding interrupt vector address is
loaded into the program counter. The interrupt vector addresses are listed in Interrupt Summary Table.
7.8.6 Interrupt Priority
Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt
priority control registers IPL0, IPH0, IPL1, and IPH1. The interrupt priority service is described below:
An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the
same or lower priority.
The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority
levels are received simultaneously, the request of higher priority level is serviced.

55
 SH79F642B
If requests of the same priority level are pending at the start of an instruction cycle, an internal polling sequence determines
which request is serviced.
Interrupt Priority Level
Priority bits
Interrupt Level Priority
IPHx IPLx
0 0 Level 0 (lowest priority)
0 1 Level 1
1 0 Level 2
1 1 Level 3 (highest priority)

Table 7.38 Interrupt priority control registers

B8H, B4H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IPL0 (B8H) - PADTPL PT2L PS0L PT1L PX1L PT0L -
IPH0 (B4H) - PADTPH PT2H PS0H PT1H PX1H PT0H -
W/R W/R W/R W/R W/R W/R W/R W/R -
Reset value
- 0 0 0 0 0 0 -
（POR/WDT/LVR/PIN）
B9H, B5H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IPL1 (B9H) PLPDL PS2L PPWML PS1L PHSECL PX3L PX2L PEMUL
IPH1 (B5H) PLPDH PS2H PPWMH PS1H PHSECH PX3H PX2H PEMUH
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

7-0 PxxxL/H Corresponding interrupt source xxx’s priority level select

7.8.7 Interrupt Handling

The interrupt flags are sampled and polled at the fetch cycle of each machine cycle. All interrupts are sampled at the rising
edge of the clock. If one of the flags was set, the CPU will find it and the interrupt system will generate a LCALL to the
appropriate service routine, provided this hardware-generated LCALL is not blocked by any of the following conditions:
An interrupt of equal or higher priority is already in progress.
The current cycle is not in the final cycle of the instruction in progress. This ensures that the instruction in progress is
completed before vectoring to any service routine.
The instruction in progress is RETI. This ensures that if the instruction in progress is RETI then at least one more
instruction except RETI will be executed before any interrupt is vectored to; this delay guarantees that the CPU can
observe the changes of the interrupt status.
Notes:
Since priority change normally needs 2 instructions, it is recommended to disable corresponding Interrupt Enable flag to avoid
interrupt between the these 2 instructions during the change of priority.
That if the flag is no longer active when the blocking condition is removed, the denied interrupt will not be serviced. Every polling
cycle interrogates only the valid interrupt requests.
The polling cycle/LCALL sequence is illustrated below

C1 C2 C3 C3~Cn Cn~Cn+7 Cn+8

Interrupt
Interrupt Interrupt Interrupt
Signal Long Call to
Pending service
Polled Generated Interrupt Vector Service

Interrupt
Latched

Figure2. Interrupt Response Timing

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 SH79F642B
The hardware-generated LCALL pushes the contents of the program counter onto the stack (but it does not save the PSW)
and reloads the program counter with corresponding address that depends on the source of the interrupt being vectored too, as
shown in Interrupt Summary table.
Interrupt service execution proceeds from that location until the RETI instruction is encountered. The RETI instruction
informs the processor that the interrupt routine is no longer in progress, then pops the top two bytes from the stack and reloads
the program counter. Execution of the interrupted program continues from the point where it was stopped. Note that the RETI
instruction is very important because it informs the processor that the program left the current interrupt service. A simple RET
instruction would also have returned execution to the interrupted program, but it would have left the interrupt control system
thinking an interrupt with this priority was still in progress. In this case, no interrupt of the same or lower priority level would be
acknowledged.

7.8.8 Interrupt Response Time

If an interrupt is recognized, its request flag is set in every machine cycle after recognize. The value will be polled by the
circuitry until the next machine cycle. The CPU will generate an interrupt at the third machine cycle. If the request is active and
conditions are right for it to be acknowledged, a hardware-generated LCALL to the requested service routine will be the next
instruction to be executed. Else the interrupt will pending. The call itself takes 7 machine cycles. Thus a minimum of 3+7
complete machine cycles will elapse between activation and external interrupt request and the beginning of execution of the
first instruction of the service routine.
A longer response time would be obtained if the request was blocked by one of the above three previously listed
conditions. If an interrupt of equal or higher priority is already in progress, the additional wait time obviously depends on the
nature of the other interrupt’s service routine.
If the instruction in progress is not in its final cycle, the additional wait time cannot be more than 20 machine cycles since
the longest instructions (DIV & MUL) are only 20 machine cycles long for 16 bit operation (or 11 machine cycles for 8 bit
operation); and if the instruction in progress is RETI or the additional wait time cannot be more than 8+20 machine cycles (a
maximum of one more cycle to complete the instruction in progress, plus maximal 20 machine cycles to complete the next
instruction, if the instruction is 16bit DIV or MUL). In addition, a LCALL instruction needs 7 machine cycles.
Thus a single interrupt system, the response time is always more than 10 machine cycles and less than 2+8+20+7
machine cycles.
7.8.9 External Interrupt inputs
The SH79F642B has 4 external interrupt inputs. External interrupt 1-3 each has one vector address. External interrupt 0/1
can be programmed to be level-triggered or edge-triggered by clearing or setting bit IT1 or IT0 in register TCON and register
EXF0. If ITn = 0(n=0~1), external interrupt 0/1 is triggered by a low level detected at the INT1 pin. If ITn =1(n=0~1), external
interrupt 0/1 is edge triggered. In this mode if consecutive samples of the INT1 pin show a high level in one cycle and a low level
in the next cycle, interrupt request flag in register EXF1 is set, causing an interrupt request. Since the external interrupt pins are
sampled once each machine cycle, an input high or low level should be held for at least one machine cycle to ensure proper
sampling.
If the external interrupt is edge-triggered, the external source has to hold the request pin high for at least one machine
cycle, and then hold it low for at least one machine cycle. This is to ensure that the transition is detected and that interrupt
request flag is set. Notice that IE0-3 is automatically cleared by CPU when the service routine is called.
External interrupt2-3 operates in the similar ways as external interrupt1 except have different registers and have more
selection of trigger.
If the external interrupt is level-triggered, the external source must hold the request active until the requested interrupt is
generated, which will take 2 machine cycles. If the external interrupt is still asserted when the interrupt service routine is
completed, another interrupt will be generated. It is not necessary to clear the interrupt flag Iex (x=1,2,3) when the interrupt is
level sensitive, it simply tracks the input pin level.
If an external interrupt is enabled when the SH79F642B is put into Power down or Idle mode, the interrupt occurrence will
cause the processor to wake up and resume operation. Refer to the Power management Section for details.

57
 SH79F642B

>1 machine Cycle

High-Level Threshold

Low-Level Threshold

>1 machine Cycle

Low-Level Threshold

>2 machine Cycle

Figure 3. External Interrupt Detection

58
 SH79F642B
7.8.10 Interrupt Summary
Source Vector Address Enable bits Flag bits Polling Priority C51
Reset 0000h - - 0 (Highest) -
Reserved 0003h - - - -
Timer0 000Bh ET0 TF0 3 1
INT1 0013h EX1 IE1 4 2
Timer1 001Bh ET1 TF1 5 3
EUART0 0023h ES RI+TI 6 4
Timer2 002Bh ET2 TF2+EXF2 7 5
ADC 0033h EADC ADCIF 8 6
EMU 003Bh EEMU EMUF 9 7
INT2 0043h EX2 IE2 10 8
INT3 004Bh EX3 IE3 11 9
RTC 0053h ERTC RTCIF 12 10
EUART1 005Bh ES1 RI1+TI1 13 11
PWM 0063h EPWM+PWMIE0/1 PWMIF0/1 14 12
EUART2 006Bh ES2 RI2+TI2 15 13
LPD 0073h ELPD LPDIF 16 14
Reserved 007Bh - - - -

59
 SH79F642B
8. Enhanced Function

8.1 LCD Driver

The LCD driver contains a controller, 4/6/8 common signal pads and 32 segment driver pads. Segment 1~32 and
COM1~COM8 can also be used as I/O port, it is controlled by the P0SS, P1SS, P3SS , P4SS & P5SS registers.
The 32 byte display data RAM is addressed at B00H-B1FH, which could be used as data memory if needed.
The SH79F642B uses normal display topologies with contrast adjustment and which supports both 1/4duty-1/3 or 1/4 bias
and 1/8duty-1/4bias. In addition, it supports FCM (Fast Charge Mode) to reduce power cost.
The LCD supply power VLCD equals to VDD.
When SH79F642B enters the Power-Down mode, the LCD RAM can still be stored safely.
During the Power on Reset or Pin Reset or LVR Reset or Watch-dog Reset, the LCD will be turned off.
When LCD is turned off, both common and segment will output low.

8.1.1 Resistance-type LCD model

The traditional resistance-type LCD display modes have the following characteristics:
- Register by CONTR [2:0] in LCDCON control 8 contrast adjustment;
- 1/4 duty cycle when the frame rate of 64Hz;
- Support for fast charging mode (Fast Charge Mode) in order to reduce power consumption.
The from LCDCON1 register MOD [2:0] bits control selectable LCD bias resistor (RLCD) for 60k or 450k/900k. Select the 60k
bias resistor can get a better display, but the current will be relatively large, not suitable for low power applications. The MOD
[2:0] bits in LCDON1 are set for 001/000 select 450k/900k bias resistor, although you can achieve low power consumption, but
the LCD display will become worse. The choice of 450k and 900k is controlled by LCDCON1 [2:0] bits.
Therefore, MCU provides the display mode: fast charge mode ,this mode can be given to juggle both low power and display.
Set the MOD [2:0] = 011/1xx can choose such a display, selected 60k bias resistor in the display data refresh time, provide
greater drive current, selected 450k/900k bias resistor during the data retention to provide a smaller drive current.
Fast charging display two charging modes: Mode A and Mode B by LCDCON1 register FCMOD bit to choose. From LCDCON1
register FCCTL [1:0] bits select the charging time LCD com cycle of 1/4, 1/8, 1/16 or 1/32.

V3
V2

V1
COM4 - SEGn 0
-V1
-V2

-V3
Fast Charge Mode A:
High current selected before
switching edge, period is
defined by FCCT[1:0] bits

Fast Charge Mode B:

High current selected while
switching edge, period is
defined by FCCT[1:0] bits

Fast Charge Mode Waveform

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 SH79F642B

COM4 one frame

V3
COM1 V2
COM3
V1
0

V3

COM2 COM2 V2

V1
0
COM1
V3

COM3 V2

V1
0

V3
V2
COM4
V1
0

V3
V2
SEGn
SEGn+1 V1

SEGn 0

V3
V2
SEGn+1
V1
0

V3
V2

V1
COM4 - SEGn 0
-V1
-V2

-V3
Fast Charge Mode A:
High current selected before
switching edge, period is
defined by FCCT[1:0] bits

Fast Charge Mode B:

High current selected while
switching edge, period is
defined by FCCT[1:0] bits

LCD waveform (1/4duty, 1/3bias)

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 SH79F642B

COM8 V4

V3

COM7 COM1 V2
COM6
V1
0
COM5
V4
COM4
COM3 V3

COM2 V2
COM1
COM2 V1

V4

V3

COM3 V2

V1

V4

V3

COM4 V2

SEGn V1

V4

V3

SEGn V2

V1

V4
V3
V2
V1
COM1- SEGn 0
- V1
- V2
- V3
-V4

LCD waveform (1/8duty, 1/4bias)

62
 SH79F642B
8.1.2 Registers
Table 8.1 LCD Control Register
A3H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
LCDCON LCDON - DUTY1 DUTY0 BIAS CONTR2 CONTR1 CONTR0
W/R W/R - W/R W/R W/R W/R W/R W/R
Reset Value
0 - 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

LCD on/off control bit
7 LCDON 0: Disable LCD driver (default)
1: Enable LCD drive
LCD duty selector:
00: 1/4 duty, 1/3 bias recommended
5-4 DUTY[1:0]
01: 1/6 duty, 1/3 bias recommended, P1.4&P1.5 is used as COM5&COM6
10: 1/8 duty, 1/4 bias recommended, P1.4~P1.7 is used as COM5~COM8
Bias selector:
3 BIAS 0: 1/3 bias
1: 1/4 bias
LCD contrast control:
000: VLCD=0.650 VOUT
001: VLCD=0.700 VOUT
010: VLCD=0.750 VOUT
2-0 CONTR[2:0] 011: VLCD=0.800 VOUT
100: VLCD=0.850 VOUT
101: VLCD=0.900 VOUT
110: VLCD=0.950 VOUT
111: VLCD=1.000 VOUT

Table 8.2 LCD Contrast Control Register

A2H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
LCDCON1 FCMOD - FCCTL1 FCCTL0 - MOD2 MOD1 MOD0
W/R W/R - W/R W/R - W/R W/R W/R
Reset Value
0 - 0 0 - 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

Fast charge up mode control:
7 FCMOD 0: fast charge up mode A
1: fast charge up mode B
Fast charge up time control :
00: 1/4 LCD com period
5-4 FCCTL[1:0] 01: 1/8 LCD com period
10: 1/16 LCD com period
11: 1/32 LCD com period
Drive mode selector:
000: Traditional mode, bias resistor is 900k
001: Traditional mode, bias resistor is 450k
2-0 MOD[2:0]
010: Traditional mode, bias resistor is 60k
011: fast charge up mode, bias resistor is switched between 60k and 450k automatic
1xx: fast charge up mode, bias resistor is switched between 60k and 900k automatic

63
 SH79F642B
Table 8.3 P0 fuction select register
AAH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P0SS P0S7 P0S6 P0S5 P0S4 P0S3 P0S2 P0S1 P0S0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

P0 mode control:
7-0 P0S[7:0] 0: P0.0-P0.7 as I/O
1: P0.0-P0.7 as Segment(SEG5 – SEG12)

Table 8.4 P1 fuction select register

ABH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P1SS P1S7 P1S6 P1S5 P1S4 - - - COMS
W/R W/R W/R W/R W/R - - - W/R
Reset Value
0 0 0 0 - - - 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

P1 mode control:
0: P1.4~P1.7 as I/O
7-4 P1S[7:4]
1: P1.4~P1.7 as Segment (SEG1 – SEG4) or COM (COM4-COM8), which is
controlled by DUTY[1:0]
P5 COM mode control:
0 COMS 0: P1.0~P1.3 as I/O
1: P1.0~P1.3 as Common (COM1 – COM4)

Table 8.5 P3 fuction select register

ACH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P3SS - P3S6 P3S5 P3S4 P3S3 - - -
W/R - W/R W/R W/R W/R - - -
Reset Value
- 0 0 0 0 - - -
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

P3 mode control:
7-4 P3S[6:3] 0: P3.3-P3.6 as I/O
1: P3.3-P3.6 as Segment (SEG29 – SEG32)

Table 8.6 P4 fuction select register

ADH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P4SS P4S7 P4S6 P4S5 P4S4 P4S3 P4S2 P4S1 P4S0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

64
 SH79F642B
P4 mode control:
7-0 P4S[7:0] 0: P4.0~P4.7 as I/O
1: P4.0~P4.7 as Segment(SEG13 – SEG20)

Table 8.7 P5 fuction select register

AEH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P5SS P5S7 P5S6 P5S5 P5S4 P5S3 P5S2 P5S1 P5S0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

P5 mode control:
7-4 P5S[7:0] 0: P5.0~P5.7 as I/O
1: P5.0~P5.7 as Segment(SEG21 – SEG28)

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 SH79F642B
8.1.3 LCD RAM config
Table 8.8 LCD 1/4 duty, 1/3 bias (COM1 – 4, SEG1 – 39)
7 6 5 4 3 2 1 0
Address
- - - - COM4 COM3 COM2 COM1
B00H - - - - SEG1 SEG1 SEG1 SEG1
B01H - - - - SEG2 SEG2 SEG2 SEG2
B02H - - - - SEG3 SEG3 SEG3 SEG3
B03H - - - - SEG4 SEG4 SEG4 SEG4
B04H - - SEG5 SEG5 SEG5 SEG5 SEG5 SEG5
B05H - - SEG6 SEG6 SEG6 SEG6 SEG6 SEG6
B06H SEG7 SEG7 SEG7 SEG7 SEG7 SEG7 SEG7 SEG7
B07H SEG8 SEG8 SEG8 SEG8 SEG8 SEG8 SEG8 SEG8
B08H SEG9 SEG9 SEG9 SEG9 SEG9 SEG9 SEG9 SEG9
B09H SEG10 SEG10 SEG10 SEG10 SEG10 SEG10 SEG10 SEG10
B0AH SEG11 SEG11 SEG11 SEG11 SEG11 SEG11 SEG11 SEG11
B0BH SEG12 SEG12 SEG12 SEG12 SEG12 SEG12 SEG12 SEG12
B0CH SEG13 SEG13 SEG13 SEG13 SEG13 SEG13 SEG13 SEG13
B0DH SEG14 SEG14 SEG14 SEG14 SEG14 SEG14 SEG14 SEG14
B0EH SEG15 SEG15 SEG15 SEG15 SEG15 SEG15 SEG15 SEG15
B0FH SEG16 SEG16 SEG16 SEG16 SEG16 SEG16 SEG16 SEG16
B10H SEG17 SEG17 SEG17 SEG17 SEG17 SEG17 SEG17 SEG17
B11H SEG18 SEG18 SEG18 SEG18 SEG18 SEG18 SEG18 SEG18
B12H SEG19 SEG19 SEG19 SEG19 SEG19 SEG19 SEG19 SEG19
B13H SEG20 SEG20 SEG20 SEG20 SEG20 SEG20 SEG20 SEG20
B14H SEG21 SEG21 SEG21 SEG21 SEG21 SEG21 SEG21 SEG21
B15H SEG22 SEG22 SEG22 SEG22 SEG22 SEG22 SEG22 SEG22
B16H SEG23 SEG23 SEG23 SEG23 SEG23 SEG23 SEG23 SEG23
B17H SEG24 SEG24 SEG24 SEG24 SEG24 SEG24 SEG24 SEG24
B18H SEG25 SEG25 SEG25 SEG25 SEG25 SEG25 SEG25 SEG25
B19H SEG26 SEG26 SEG26 SEG26 SEG26 SEG26 SEG26 SEG26
B1AH SEG27 SEG27 SEG27 SEG27 SEG27 SEG27 SEG27 SEG27
B1BH SEG28 SEG28 SEG28 SEG28 SEG28 SEG28 SEG28 SEG28
B1CH SEG29 SEG29 SEG29 SEG29 SEG29 SEG29 SEG29 SEG29
B1DH SEG30 SEG30 SEG30 SEG30 SEG30 SEG30 SEG30 SEG30
B1EH SEG31 SEG31 SEG31 SEG31 SEG31 SEG31 SEG31 SEG31
B1FH SEG32 SEG32 SEG32 SEG32 SEG32 SEG32 SEG32 SEG32

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 SH79F642B
8.2 EUART0
8.2.1 Features
 The SH79F642B has three enhanced EUARTs with own baud rate generator
 The baud rate generator is an 15 bit up-counting timer
 Enhancements over the standard 8051 the EUART include Framing Error detection and automatic address recognition
 The EUART can be operated in four modes
 The UART1 provide IR interface.

8.2.2 EUART0 Mode Description

The EUART can be operated in 4 modes. Users must initialize the SCON to selct BPS and mode before any communication can
take place.
In all of the 4 modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in
Mode 0 by the condition RI = 0 and REN = 1. This will generate a clock on the TxD pin and shift in 8 bits on the RxD pin.
Reception is initiated in the other modes by the incoming start bit if RI = 0 and REN = 1. The external transmitter will start the
communication by transmitting the start bit.

Table 8.9 EUART Mode Summary

Frame
SM0 SM1 Mode Type Baud Clock Start Bit Stop Bit 9th bit
Size
0 0 0 Sych fSYS/ (4 or 12) 8 bits NO NO None
0 1 1 Ansych Built-in BaudRate generator overflow rate/16 10 bits 1 1 None

1 0 2 Ansych fSYS/ (32 or 64) 11 bits 1 1 0, 1

1 1 3 Ansych Built-in BaudRate generator overflow rate/16 11 bits 1 1 0, 1

Mode 0: Synchronous Mode, Half duplex

This mode provides synchronous communication with external devices. In this mode serial data is transmitted and received on
the RxD line. TxD is used to output the shift clock. The TxD clock is provided by the SH79F642B whether the device is
transmitting or receiving. This mode is therefore a half duplex mode of serial communication. In this mode, 8 bits are transmitted
or received per frame. The LSB is transmitted/received first.
The baud rate is programmable to either 1/12 or 1/4 of the system clock. This baud rate is determined in the SM2 bit (SCON.5).
When this bit is set to 0, the serial port runs at 1/12 of the system clock. When set to 1, the serial port runs at 1/4 of the system
clock.
The functional block diagram is shown below. Data enters and exits the serial port on the RxD line. The TxD line is used to output
the SHIFT CLOCK. The SHIFT CLOCK is used to shift data into and out of the SH79F642B

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 SH79F642B
Transmit Shift Register

System Clock Internal

PARIN SOUT RXD
Data Bus
Write to
LOAD
SBUF
CLOCK
÷ 12 ÷4
TX START TX SHIFT

TX CLOCK TI
SM2 0 1 SERIAL Serial Port Interrupt
CONTROLLER RI
RX CLOCK
SHIFT
TXD
CLOCK

RI LOAD SBUF
RX START
REN
RX SHIFT
Read SBUF
CLOCK
PAROUT SBUF SBUF
RXD SIN

Receive Shift Register

Any instruction that uses SBUF as a destination register (“write to SBUF” signal) will start the transmission. The next system
clock tells the Tx control block to commence a transmission. The data shift occurs at the falling edge of the SHIFT CLOCK, and
the contents of the transmit shift register is shifted one position to the right. As data bits shift to the right, zeros come in from the
left. After transmission of all 8 bits in the transmit shift register, the Tx control block will deactivates SEND and sets TI (SCON.1)
at the rising edge of the next system clock.
Write to SBUF

RxD
D0 D1 D2 D3 D4 D5 D6 D7
TxD

TI

Send Timing of Mode 0

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 SH79F642B
Reception is initiated by the condition REN (SCON.4)= 1 and RI (SCON.0) = 0. The next system clock activates RECEIVE. The
data latch occurs at the rising edge of the SHIFT CLOCK, and the contents of the receive shift register are shifted one position to
the left. After the receiving of all 8 bits into the receive shift register, the RX control block will deactivates RECEIVE and sets RI
at the rising edge of the next system clock, and the reception will not be enabled till the RI is cleared by software.

RxD
D0 D1 D2 D3 D4 D5 D6 D7

TxD

RI

Receive Timing of Mode 0

Mode 1: 8-Bit EUART, Variable Baud Rate, Asynchronous Full-Duplex

This mode provides the 10 bits full duplex asynchronous communication. The 10 bits consist of a start bit (logical 0), 8 data bits
(LSB first), and a stop bit (logical 1). When receiving, the eight data bits are stored in SBUF and the stop bit goes into RB8
(SCON.2). The baud rate in this mode is variable. The serial receive and transmit baud rate can be programmed to be 1/16 of the
BaudRate generator overflow. The functional block diagram is shown below.

Transmit Shift Register

STOP
Internal
PARIN
Data Bus
Baud rate
Write to SBUF START SOUT TXD
Generator
LOAD
overflow CLOCK
From 7FFF to 0000
TX START TX SHIFT
÷ 16 TX CLOCK
TI
SERIAL
Serial Port Interrupt
CONTROLLER
÷16 RI

RX CLOCK
SAMPLE LOAD SBUF
Read SBUF
1-TO-0 RX START RX SHIFT
DETECTOR
CLOCK Internal
PAROUT SBUF
Data Bus
BIT
RXD SIN D8 RB8
DETECTOR

Receive Shift Register

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 SH79F642B
Transmission begins with a “write to SBUF” signal, and it actually commences at the next system clock following the next rollover
in the divide-by-16 counter (divide baud-rate by 16), thus, the bit times are synchronized to the divide-by-16 counter, not to the
“write to SUBF” signal. The start bit is firstly put out on TxD pin, then are the 8 bits of data. After all 8 bits of data in the transmit
shift register are transmitted, the stop bit is put out on the TxD pin, and the TI flag is set at the same time that the stop is send.

Write to SBUF

TxD
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop
Shift CLK

TI

Send Timing of Mode 1

Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data with the detection of a falling
edge on the RxD pin. For this purpose RxD is sampled at the rate of 16 times baud rate. When a falling edge is detected, the
divide-by-16 counter is immediately reset. This helps to align the bit boundaries with the rollovers of the divide-by-16
th th
counter.The 16 states of the counter divide each bit time into 16ths. The bit detector samples the value of RxD at the 7 , 8 and
9th counter states of each bit time. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for
noise rejection. If the first bit after the falling edge of RxD pin is not 0, which indicates an invalid start bit, and the reception is
immediately aborted. The receive circuits are reset and again waiting for a falling edge in the RxD line. If a valid start bit is
detected, then the rest of the bits are also detected and shifted into the shift register. After shifting in 8 data bits and the stop bit,
the SBUF and RB8 are loaded and RI are set if the following conditions are met:
1. RI must be 0
2. Either SM2 = 0, or the received stop bit = 1
If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set. Otherwise the received
frame may be lost.
At the time, the receiver goes back to looking for another falling edge on the RxD pin. And the user should clear RI by software for
further reception.
RxD
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop

Bit Sample

Shift CLK

RI

Receive Timing of Mode 1

70
 SH79F642B

Mode 2: 9-Bit EUART, Fixed Baud Rate, Asynchronous Full-Duplex

This mode provides the 11 bits full duplex asynchronous communication. The 11 bit consists of one start bit (logical 0), 8 data bits
(LSB first), a programmable 9th data bit, and a stop bit (logical 1). Mode 2 supports multiprocessor communications and
hardware address recognition (Refer to Multiprocessor Communication Section for details). When data is transmitted, the 9th
data bit (TB8 in SCON) can be assigned the value of 0 or 1, for example, the parity bit P in the PSW or used as data/address flag
th
in multiprocessor communications. When data is received, the 9 data bit goes into RB8 and the stop bit is not saved. The baud
rate is programmable to either 1/32 or 1/64 of the system working frequency, as determined by the SMOD bit in PCON. The
functional block diagram is shown below.

Transmit Shift Register

System Clock
TB8 D8
STOP
Internal
PARIN
÷2 Data Bus
Write to SBUF START SOUT TXD
LOAD
SMOD CLOCK
0 1
TX START TX SHIFT
÷ 32 TX CLOCK
TI
SERIAL
Serial Port Interrupt
CONTROLLER
÷ 32 RI

RX CLOCK
SAMPLE LOAD SBUF
1-TO-0 Read SBUF
RX START RX SHIFT
DETECTOR

CLOCK Internal
PAROUT SBUF
Data Bus
BIT
RXD SIN D8 RB8
DETECTOR

Receive Shift Register

th
Transmission begins with a “write to SBUF” signal, the “write to SBUF” signal also loads TB8 into the 9 bit position of the
transmit shift register. Transmission actually commences at the next system clock following the next rollover in the divide-by-16
counter (thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to SUBF” signal). The start bit is firstly
put out on TxD pin, then are the 9 bits of data. After all 9 bits of data in the transmit shift register are transmitted, the stop bit is put
out on the TxD pin, and the TI flag is set at the same time, this will be at the 11th rollover of the divide-by-16 counter after a write
to SBUF.
Write to SBUF

TxD
Start D0 D1 D2 D3 D4 D5 D6 D7 D8 Stop

Shift CLK

TI

Send Timing of Mode 2

71
 SH79F642B
Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data, with the detection of a falling
edge on the RxD pin. For this purpose RxD is sampled at the rate of 16 times baud rate. When a falling edge is detected, the
divide-by-16 counter is immediately reset. This helps to align the bit boundaries with the rollovers of the divide-by-16 counter.
The 16 states of the counter divide each bit time into 16ths. The bit detector samples the value of RxD at the 7th, 8th and 9th
counter state of each bit time. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise
rejection. If the first bit detected after the falling edge of RxD pin is not 0, which indicates an invalid start bit, and the reception is
immediately aborted. The receive circuits are reset and again looks for a falling edge in the RxD line. If a valid start bit is
detected, then the rest of the bits are also detected and shifted into the shift register.
After shifting in 9 data bits and the stop bit, the SBUF and RB8 are loaded and RI is set if the following conditions are met:
1. RI must be 0
th
2. Either SM2 = 0, or the received 9 bit = 1 and the received byte accords with Given Address
th
If these conditions are met, then the 9 bit goes to RB8, the 8 data bits go into SBUF and RI is set. Otherwise the received
frame may be lost.
At the time, the receiver goes back to looking for another falling edge on the RxD pin. And the user should clear RI by software for
further reception.
RxD
Start D0 D1 D2 D3 D4 D5 D6 D7 D8 Stop

Bit Sample

Shift CLK

RI

Receive Timing of Mode 2

Mode 3: 9-Bit EUART, Variable Baud Rate, Asynchronous Full-Duplex
Mode 3 uses transmission protocol of the Mode 2 and baud rate generation of the Mode 1.

Transmit Shift Register

STOP
TB8 D8
Internal
PARIN SOUT TXD
Baud rate Data Bus
Generator Write to SBUF START
LOAD
overflow
CLOCK
From 7FFF to 0000
TX START TX SHIFT
÷ 16 TX CLOCK
TI
SERIAL
Serial Port Interrupt
CONTROLLER
÷16 RI

RX CLOCK
SAMPLE LOAD SBUF
Read SBUF
1-TO-0 RX START RX SHIFT
DETECTOR
CLOCK Internal
PAROUT SBUF
Data Bus
BIT
RXD SIN D8 RB8
DETECTOR

Receive Shift Register

72
 SH79F642B
8.2.3 Baud rate Generator
EUART0, EUART1, EUART2 each carry a baudrate generator, It is essentially a 15-bit up counter.

Overflow To EUART
15-bit timer `
Fsys From 7FFFH to
0000H

SBRTEN=1
SBRTH[14:8],SBRTL[7:0]

Baudrate Generator for EUART

Fsys
The baudrate is SBRToverflowrate = , SBRT = [ SBRTH , SBRTL]
32768 − SBRT
so, the baud rate is calculated as follows in each mode.
In Mode 0, the baud rate is programmable system clock 1/12 or 1/4 determined by the SM2 bit. When SM2=0, t the serial port
runs at 1/12 of the system clock. When SM2 =1, the serial port runs at 1/4 of the system clock.

In mode 1 and 3, the baud rate can be fine fixed with accuracy of one system clock. The formula is shown below:
Fsys
BaudRate =
16 × (32768 - SBRT ) + SFINE
E.G. When Fsys=8MHz, to get 115200Hz baud rate，computing method of SBRT and SFINE as shown below：
8000000/16/115200 = 4.34
SBRT = 32768 – 4 = 32764
115200 = 8000000/(16×4 + SFINE)
SFINE = 5.4 ≈ 5
The method with fine register comes into a 115942Hz Baudrate with 0.64% error compared to 8.5% error of calculating in old
method.

In Mode 2, the baud rate is fixed for the system clock 1/32 or 1/64, determined by the SMOD bit (PCON.7). When the SMOD bit
to 0, EUART to 1/64 of the system clock is running. When SMOD bit is 1, EUART run the system clock 1/32.

f SYS
BaudRate = 2 SMOD × ( )
64

73
 SH79F642B
8.2.4 Multi-processor communication
Software address recognition
Modes 2 and 3 of the EUART have a special provision for multi-processor communication. In these modes, 9 data bits are
received. The 9th bit goes into RB8. Then a stop bit follows. The EUART can be programmed such that when the stop bit is
received, the EUART interrupt will be activated (i.e. the request flag RI is set) only if RB8 = 1. This feature is enabled by setting
the bit SM2 in SCON.
A way to use this feature in multiprocessor communications is as follows. lf the master processor wants to transmit a block of
data to one of the several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from
a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte.
With SM2 = 1, no other slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each
slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to
receive the data bytes that will be coming. After having received a complete message, the slave sets SM2 again. The slaves
that were not addressed leave their SM2 set and go on with their business, ignoring the incoming data bytes.

Note: In mode 0, SM2 is used to select baud rate doubling. In mode 1, SM2 can be used to check the validity of the stop bit. If
SM2 = 1 in mode 1, the receive interrupt will not be activated unless a valid stop bit is received.

Automatic (Hardware) address recognition

In Mode 2 & 3, setting the SM2 bit will configure EUART0 act as following: when a stop bit is received, EUART0 will
generate an interrupt only if the 9th bit that goes into RB8 is logic 1 (address byte) and the received data byte matches the
EUART0 slave address. Following the received address interrupt, the slave should clear its SM2 bit to enable interrupts on the
reception of the following data byte(s).
th
The 9-bit mode requires that the 9 information bit is a 1 to indicate that the received information is an address and not
data. When the master processor wants to transmit a block of data to one of the slaves, it first sends out the address of the
targeted slave (or slaves). All the slave processors should have their SM2 bit set high when waiting for an address byte, which
ensures that they will be interrupted only by the reception of an address byte. The Automatic address recognition feature further
ensures that only the addressed slave will be interrupted. The address comparison is done by hardware not software.
After being interrupted, the addressed slave clears the SM2 bit to receive data bytes. The un-addressed slaves will be
unaffected, as they will be still waiting for their address. Once the entire message is received, the addressed slave should set its
SM2 bit to ignore all transmissions until it receives the next address byte.

The Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by
invoking the Given Address. All of the slaves may be contacted by using the Broadcast address.
Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. The
slave address is an 8-bit value specified in the SADDR register. The SADEN register is actually a mask for the byte value in
SADDR. If a bit position in SADEN is 0, then the corresponding bit position in SADDR is don’t care. Only those bit positions in
SADDR whose corresponding bits in SADEN are 1 are used to obtain the Given Address. This gives the user flexibility to
address multiple slaves without changing the slave address in SADDR. Use of the Given Address allows multiple slaves to be
recognized while excluding others.
Slave 1 Slave 2
SADDR 10100100 10100111
SADEN (0 mask) 11111010 11111001
Given Address 10100x0x 10100xx1
Broadcast Address (OR) 1111111x 11111111

The Given address for slave 1 and 2 differ in the LSB. For slave 1, it is a don’t care, while for slave 2 it is 1. Thus to communicate
only with slave 1, the master must send an address with LSB = 0 (10100000). Similarly the bit 1 is 0 for slave 1 and don’t care for
slave 2. Hence to communicate only with slave 2 the master has to transmit an address with bit 1 = 1 (1010 0011). If the master
wishes to communicate with both slaves simultaneously, then the address must have bit 0 = 1 and bit 1 = 0. The bit 2 position is
don’t care for both the slaves. This allows two different addresses to select both slaves (1010 0001 and 1010 0101).

The master can communicate with all the slaves simultaneously with the Broadcast Address. This address is formed from the
logical OR of the SADDR and SADEN. The zeros in the result are defined as don’t cares. In most cases, the Broadcast Address
is FFh, this address will be acknowledged by all slaves.

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 SH79F642B
On reset, the SADDR and SADEN are initialized to 00h. This results in Given Address and Broadcast Address being set as
XXXXXXXX (all bits don’t care). This effectively removes the multiprocessor communications feature, since any selectivity is
disabled. This ensures that the EUART 0 will reply to any address, which it is backwards compatible with the 80C51
microcontrollers that do not support automatic address recognition. So the user may implement multiprocessor by software
address recognition mentioned above.

Error Detection
Error detection is available when the SSTAT bit in register PCON is set to logic 1.The SSTAT bit must be logic 1 to access any
of the status bits (FE, RXOV, and TXCOL). The SSTAT bit must be logic 0 to access the Mode Select bits (SM0, SM1, and
SM2).All the 3 bits should be cleared by software after they are set, even when the following frames received without any error
will not be cleared automatically.
Transmit collision
The Transmit Collision bit (TXCOL bit in register SCON) reads ‘1’ if RI is set 0 and user software writes data to the SBUF
register while a transmission is still in progress. If this occurs, the new data will be ignored and the transmit buffer will not be
written.

Receive Overrun
The Receive Overrun bit (RXOV in register SCON) reads ‘1’ if a new data byte is latched into the receive buffer before software
has read the previous byte. The previous data is lost when this happen.
Frame Error
The Frame Error bit (FE in register SCON) reads ‘1’ if an invalid (low) STOP bit is detected.
Break Detection
A break is detected when any 11 consecutive bits are sensed low. Since a break condition also satisfies the requirements for a
framing error, a break condition will also result in reporting a framing error. Once a break condition has been detected, the
EUART will go into an idle state and remain in this idle state until a valid stop bit (rising edge on RxD line) has been received.

8.2.5 EUART1/2
EUART1/2 has the same control & operation modes as EUART0. EUART1 provides IR interface.（Refer to IR section for
details）
8.2.6 Register
Table 8.10 Power Control register
87H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PCON SMOD SSTAT SSTAT1 SSTAT2 GF1 GF0 PD IDL
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

Baud rate doubler
If set in mode 1 & 3, the baud-rate of EUART is doubled if using timer 1 as
7 SMOD
baud-rate generator,
If set in mode 2, the baud-rate of EUART is doubled
SCON [7:5] function select bit
6 SSTAT 0 : SCON [7:5] operates as SM0, SM1, SM2
1 : SCON [7:5] operates as FE, RXOV, TXCOL
SCON1 [7:5] function select bit
5 SSTAT1 0 : SCON1 [7:5] operates as SM10, SM11, SM12
1 : SCON1 [7:5] operates as FE1, RXOV1, TXCOL1
SCON1 [7:5] function select bit
4 SSTAT2 0 : SCON2 [7:5] operates as SM20, SM21, SM22
1 : SCON2 [7:5] operates as FE2, RXOV2, TXCOL2
3-2 GF[1:0] General purpose flags for software use
1 PD Power-Down mode control bit
0 IDL Idle mode control bit

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 SH79F642B
Table 8.11 EUART0 Control & status Register
98H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SCON SM0/FE SM1/RXOV SM2/TXCOL REN TB8 RB8 TI RI
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

EUART Serial mode control bit, when SSTAT = 0
00: mode 0, Synchronous Mode, fixed baud rate
7-6 SM [0:1] 01: mode 1, 8 bit Asynchronous Mode, variable baud rate
10: mode 2, 9 bit Asynchronous Mode, fixed baud rate
11: mode 3, 9 bit Asynchronous Mode, variable baud rate
EUART Frame Error flag, when FE bit is read, SSTAT bit must be set 1
7 FE 0: No Frame Error, clear by software
1: Frame error occurs, set by hardware
EUART Receive Over flag, when RXOV bit is read, SSTAT bit must be set 1
6 RXOV 0: No Receive Over, clear by software
1: Receive over occurs, set by hardware
EUART0 Multi-processor communication enable bit (9th bit ‘1’ checker), when
SSTAT = 0
0: In Mode0, baud-rate is 1/12 of system clock
In Mode1, disable stop bit validation check, any stop bit will set RI to
generate interrupt
5 SM2
In Mode2 & 3, any byte will set RI to generate interrupt
1: In Mode0, baud-rate is 1/4 of system clock
In Mode1, Enable stop bit validation check, only valid stop bit (1) will set
RI to generate interrupt
In Mode2 & 3, only address byte (9th bit = 1) will set RI to generate interrupt
EUART Transmit Collision flag, when TXCOL bit is read, SSTAT bit must
be set 1
5 TXCOL
0 : No Transmit Collision, clear by software
1 : Transmit Collision occurs, set by hardware
EUART0 Receiver enable.
4 REN 0 : Receive Disable
1 : Receive Enable
3 TB8 the 9th bit to be transmitted in mode 2 & 3 of EUART0, set or clear by software
Transmitter bit 8 of EUART0
In mode 0, RB8 is not used.
2 RB8
In mode 1, if receive interrupt occurs, RB8 is the stop bit that was received.
In modes 2 & 3 it is the 9th bit that was received.
Transmit interrupt flag of EUART0
0: cleared by software
1 TI
1: Set by hardware at the end of the 8th bit time in Mode0, or at the beginning of
the stop bit in other modes
Receive interrupt flag of EUART0
0: cleared by software
0 RI
1: Set by hardware at the end of the 8th bit time in Mode0, or during the stop bit
time in other modes

Table 8.12 EUART0 Data buffer register

99H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SBUF SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0
R/W R/W R/W R/W R/W R/W R/W R/W R/W

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 SH79F642B
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

This SFR accesses two registers; a transmit shift register and a receive latch
register.
7-0 SBUF.7-0 A write of SBUF will send the byte to the transmit shift register and then initiate a
transmission
A read of SBUF returns the contents of the receive latch

Table 8.13 EUART0 Slave Address & Address Mask register

9AH-9BH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SADDR SADDR.7 SADDR.6 SADDR.5 SADDR.4 SADDR.3 SADDR.2 SADDR.1 SADDR.0
SADEN SADEN.7 SADEN.6 SADEN.5 SADEN.4 SADEN.3 SADEN.2 SADEN.1 SADEN.0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

7-0 SADDR.7-0 SFR SADDR defines the EUART’s slave address.
SFR SADEN is a bit mask to determine which bits of SADDR are checked against a
received address:
7-0 SADEN.7-0
0 : Corresponding bit in SADDR is a “don’t care”
1 : Corresponding bit in SADDR is checked against a received address

Table 8.14 EUART0 Baud rate generator

9CH,9DH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SBRTH (9CH) SBRTEN SBRT0.14 SBRT0.13 SBRT0.12 SBRT0.11 SBRT0.10 SBRT0.9 SBRT0.8
SBRTL (9DH) SBRT0.7 SBRT0.6 SBRT0.5 SBRT0.4 SBRT0.3 SBRT0.2 SBRT0.1 SBRT0.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset Value
（POR 0 0 0 0 0 0 0 0
/WDT/LVR/PIN）

Number Mnemonic Description

EUART0 Baud rate generator control:
7 SBRTEN 0：disable（default）
1：enable
6-0 SBRTH[6:0] EUART0 Baud rate generator counter high 7-bit
7-0 SBRTL[7:0] EUART0 Baud rate generator counter low 8-bit

Table 8.15 EUART0/1 baudrate generator fine register

9EH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFINE SFINE1.3 SFINE1.2 SFINE1.1 SFINE1.0 SFINE.3 SFINE.2 SFINE.1 SFINE.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset Value
（POR/WDT/LV 0 0 0 0 0 0 0 0
R/PIN）

Number Mnemonic Description

7-4 SFINE1[3:0] EUART1 baudrate generator fine data register

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3-0 SFINE[3:0] EUART0 baudrate generator fine data register

Table 8.16 EUART1 Control & status Register

D8H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SCON1 SM10/FE1 SM11/RXOV1 SM12/TXCOL1 REN1 TB81 RB81 TI1 RI1
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Number Mnemonic Description

EUART1 Serial mode control bit, when SSTAT1 = 0
00: mode 0, Synchronous Mode, fixed baud rate
7-6 SM10, SM11 01: mode 1, 8 bit Asynchronous Mode, variable baud rate
10: mode 2, 9 bit Asynchronous Mode, fixed baud rate
11: mode 3, 9 bit Asynchronous Mode, variable baud rate
EUART1 Frame Error flag, when FE1 bit is read, SSTAT1 bit must be set 1
7 FE1 0: No Frame Error, clear by software
1: Frame error occurs, set by hardware
EUART1 Receive Over flag, when RXOV1 bit is read, SSTAT1 bit must be set
1
6 RXOV1
0: No Receive Over, clear by software
1: Receive over occurs, set by hardware
EUART1 Multi-processor communication enable bit (9th bit ‘1’ checker),
when SSTAT1 = 0
0 : In mode 0, baud-rate is 1/12 of system clock
In mode 1, disable stop bit validation check, any stop bit will set RI1 to generate
interrupt
5 SM12
In mode 2 & 3, any byte will set RI1 to generate interrupt
1 : In mode 0, baud-rate is 1/4 of system clock
In mode 1, Enable stop bit validation check, only valid stop bit (1) will set RI1 to
generate interrupt
In mode 2 & 3, only address byte (9th bit = 1) will set RI1 to generate interrupt
EUART1 Transmit Collision flag, when TXCOL1 bit is read, SSTAT1 bit
must be set 1
5 TXCOL1
0 : No Transmit Collision, clear by software
1 : Transmit Collision occurs, set by hardware
EUART1 Receiver enable bit
4 REN1 0 : Receive Disable
1 : Receive Enable
The 9th bit to be transmitted in mode 2 & 3 of EUART1, set or cleared by
3 TB81
software
The 9th bit to be received in mode 1,2 & 3 of EUART
In mode 0, RB81 is not used
2 RB81
In mode 1, if receive interrupt occurs, RB81 is the stop bit that was received
In modes 2 & 3 it is the 9th bit that was received
Transmit interrupt flag of EUART1
0: cleared by software
1 TI1
1: Set by hardware at the end of the 8th bit time in Mode0, or at the beginning of
the stop bit in other modes
Receive interrupt flag of EUART1
0: cleared by software
0 RI1
1: Set by hardware at the end of the 8th bit time in Mode0, or during the stop bit
time in other modes

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 SH79F642B
Table 8.17 EUART1 Data buffer register
D9H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SBUF1 SBUF1.7 SBUF1.6 SBUF1.5 SBUF1.4 SBUF1.3 SBUF1.2 SBUF1.1 SBUF1.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Number Mnemonic Description

This SFR accesses two registers; a transmit shift register and a receive latch register.
7-0 SBUF1[7-0] A write of SBUF1 will send the byte to the transmit shift register and then initiate a transmission
A read of SBUF1 returns the contents of the receive latch.

Table 8.18 EUART1 Slave Address & Address Mask register

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SADDR1 (DAH) SADDR1.7 SADDR1.6 SADDR1.5 SADDR1.4 SADDR1.3 SADDR1.2 SADDR1.1 SADDR1.0
SADEN1 (DBH) SADEN1.7 SADEN1.6 SADEN1.5 SADEN1.4 SADEN1.3 SADEN1.2 SADEN1.1 SADEN1.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset Value
（POR 0 0 0 0 0 0 0 0
/WDT/LVR/PIN）

Number Mnemonic Description

7-0 SADDR1[7-0] SFR SADDR1 defines the EUART1’s slave address.
SFR SADEN1 is a bit mask to determine which bits of SADDR are checked against a
received address:
7-0 SADEN1[7-0]
0 : Corresponding bit in SADDR1 is a “don’t care”.
1 : Corresponding bit in SADDR1 is checked against a received address.

Table 8.19 EUART1 Baud rate generator

DCH-DDH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SBRTH1 (DCH) SBRT1EN SBRT1.14 SBRT1.13 SBRT1.12 SBRT1.11 SBRT1.10 SBRT1.9 SBRT1.8
SBRTL1 (DDH) SBRT1.7 SBRT1.6 SBRT1.5 SBRT1.4 SBRT1.3 SBRT1.2 SBRT1.1 SBRT1.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset Value
（POR 0 0 0 0 0 0 0 0
/WDT/LVR/PIN）

Number Mnemonic Description

EUART1 Baud rate generator control:
7 SBRT1EN 0：disable（default）
1：enable
6-0 SBRT1[14:8] EUART1 Baud rate generator counter high 7-bit
7-0 SBRT1[7:0] EUART1 Baud rate generator counter low 8-bit

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 SH79F642B
Table 8.20 EUART2 Control & status Register
F8H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SCON2 SM20/FE2 SM21/RXOV2 SM22/TXCOL2 REN2 TB82 RB82 TI2 RI2
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Number Mnemonic Description

EUART2 Serial mode control bit, when SSTAT2 = 0
00: mode 0, Synchronous Mode, fixed baud rate
7-6 SM20, SM21 01: mode 1, 8 bit Asynchronous Mode, variable baud rate
10: mode 2, 9 bit Asynchronous Mode, fixed baud rate
11: mode 3, 9 bit Asynchronous Mode, variable baud rate
EUART2 Frame Error flag, when FE2 bit is read, SSTAT2 bit must be set 1
7 FE2 0: No Frame Error, clear by software
1: Frame error occurs, set by hardware
EUART2 Receive Over flag, when RXOV2 bit is read, SSTAT2 bit must be set
1
6 RXOV2
0: No Receive Over, clear by software
1: Receive over occurs, set by hardware
EUART2 Multi-processor communication enable bit (9th bit ‘1’ checker), when
SSTAT2 = 0
0 : In mode 0, baud-rate is 1/12 of system clock
In mode 1, disable stop bit validation check, any stop bit will set RI2 to generate
interrupt
5 SM22
In mode 2 & 3, any byte will set RI2 to generate interrupt
1 : In mode 0, baud-rate is 1/4 of system clock
In mode 1, Enable stop bit validation check, only valid stop bit (1) will set RI2 to
generate interrupt
In mode 2 & 3, only address byte (9th bit = 1) will set RI2 to generate interrupt
EUART2 Transmit Collision flag, when TXCOL2 bit is read, SSTAT2 bit
must be set 1
5 TXCOL2
0 : No Transmit Collision, clear by software
1 : Transmit Collision occurs, set by hardware
EUART2 Receiver enable bit
4 REN2 0 : Receive Disable
1 : Receive Enable
The 9th bit to be transmitted in mode 2 & 3 of EUART2, set or cleared by
3 TB82
software
The 9th bit to be received in mode 1,2 & 3 of EUART2
In mode 0, RB82 is not used
2 RB82
In mode 1, if receive interrupt occurs, RB82 is the stop bit that was received
In modes 2 & 3 it is the 9th bit that was received
Transmit interrupt flag of EUART2
0: cleared by software
1 TI2
1: Set by hardware at the end of the 8th bit time in Mode0, or at the beginning of
the stop bit in other modes
Receive interrupt flag of EUART2
0: cleared by software
0 RI2
1: Set by hardware at the end of the 8th bit time in Mode0, or during the stop bit
time in other modes
Notes:
TI2&RI2 can only be cleared. “READ-MODIFY-WRITE” instructions (like logic operation instructions) aren’t allowed to the 2 bits

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 SH79F642B
Table 8.21 Data buffer register
BAH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SBUF2 SBUF2.7 SBUF2.6 SBUF2.5 SBUF2.4 SBUF2.3 SBUF2.2 SBUF2.1 SBUF2.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Number Mnemonic Description

This SFR accesses two registers; a transmit shift register and a receive latch register.
7-0 SBUF2[7-0] A write of SBUF1 will send the byte to the transmit shift register and then initiate a transmission
A read of SBUF1 returns the contents of the receive latch.

Table 8.22 EUART2 Slave Address & Address Mask register

BBH-BCH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SADDR2 (BBH) SADDR2.7 SADDR2.6 SADDR2.5 SADDR2.4 SADDR2.3 SADDR2.2 SADDR2.1 SADDR2.0
SADEN2 (BCH) SADEN2.7 SADEN2.6 SADEN2.5 SADEN2.4 SADEN2.3 SADEN2.2 SADEN2.1 SADEN2.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset Value
（POR 0 0 0 0 0 0 0 0
/WDT/LVR/PIN）

Number Mnemonic Description

7-0 SADDR2[7-0] SFR SADDR1 defines the EUART2’s slave address.
SFR SADEN1 is a bit mask to determine which bits of SADDR are checked against a
received address:
7-0 SADEN2[7-0]
0 : Corresponding bit in SADDR1 is a “don’t care”.
1 : Corresponding bit in SADDR1 is checked against a received address.

Table 8.23 EUART2 Baud rate generator

BDH-BEH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SBRTH2 (BDH) SBRT2EN SBRT2.14 SBRT2.13 SBRT2.12 SBRT2.11 SBRT2.10 SBRT2.9 SBRT2.8
SBRTL2 (BEH) SBRT2.7 SBRT2.6 SBRT2.5 SBRT2.4 SBRT2.3 SBRT2.2 SBRT2.1 SBRT2.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset Value
（POR 0 0 0 0 0 0 0 0
/WDT/LVR/PIN）

Number Mnemonic Description

EUART2 Baud rate generator control:
7 SBRT2EN 0：disable（default）
1：enable
6-0 SBRT2[14:8] EUART2 Baud rate generator counter high 7-bit
7-0 SBRT2[7:0] EUART2 Baud rate generator counter low 8-bit

Table 8.24 EUART2 baudrate generator fine register

DEH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFINE2 SFINE2.3 SFINE2.2 SFINE2.1 SFINE2.0
W/R W/R W/R W/R W/R
Reset Value
0 0 0 0
（POR/WDT/LVR/PIN）

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Number Mnemonic Description
3-0 SFINE2[3:0] EUART2 baudrate generator fine data register

8.3 Infrared interface

SH79F642B provide a IR interface ,which built-in EUART1 internal. Apart from the high-frequency carrier signal within the
EUART1 waveform other and EUART1-consistent. EUART1 and IR can not work simultaneously. IRF register determines the
carrier frequency. Each carrier is synchronized with the falling edge of with TXD1 signal. When the increase of IR carrier, in
order to EUART1 error reduced to the smallest, the baud rate is lower than 9600bps.

IRON

IRTXD TXD 1
Carrier
RXD Mux
EUART 1 TXD RXD 1

IRON

Fcarry

TXD

IRTXD

Table 8.25 IR control register

A1H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IRCON IRON IRF6 IRF5 IRF4 IRF3 IRF2 IRF1 IRF0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Number Mnemonic Description

IR control :
7 IRON 0: disable IR, EUART1 as normal EUART
1: enable IR, IR frequency load EUART1 TxD signal
IR Carrier frequency selector:
SYSCLK
6-0 IRF[6:0]
Fcarrier =
4 × ( IRF + 1)

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 SH79F642B
8.4 ADC
8.4.1 feature
 10-bit resolution
 Built-in reference voltage
 5 analog channel input

The SH79F642B include a single ended, 10-bit SAR Analog to Digital Converter (ADC) with build in Vref connected to the
VDD or AVREF. 5 ADC channels are share with one ADC module, each channel can be programmed to connect with the
————
analog input individually. Only one channel can be available at one time. GO/DONE signal is available to start convert, and
indicate end of convert. When onversion is completed, the data in AD convert data register will be updated and ADCIF bit in
ADCON register will be set to generate an interrupt if ADC Interrupt is enabled.
The ADC integrated a digital compare function to compare the value of analog input with the digital value in the AD
converter. If this function is enabled (EC =1 in ADCON register) when ADC module is enabled (ADON = 1 in ADCON register).
When the corresponding digital value of analog input is larger than the value in compare value register (ADDH/L), the ADC
————
interrupt will occur, otherwise no interrupt will be generated. The digital comparator can work continuously when GO/DONE bit
is set until software clear, which behaviors different with the ADC module.
The ADC module including digital compare module can wok in IDLE mode and the ADC interrupt will wake up the Idle
mode, but is disabled in POWER-DOWN mode.
Measurement of the battery voltage to the ADC, the internal first pass through the resistor divider (divider resistor value is
10k/10k). The ADC measurement is 1/2 the battery voltage, each LSB corresponding ( VDD/512 )mV.

8.4.2 ADC Diagram

SCH2,SCH0 CH3-CH0

000
AN0
001
AN1
010
10 bit AN2
SAR 011
AN3
ADC Input voltage 101
AN5
100
VBAT

110
Regulator

ADC Block Diagram

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 SH79F642B

8.4.3 Register
Table 8.26 ADC Control Register
C1H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
————
ADCON ADON ADCIF EC EADC SCH2 SCH1 SCH0 GO/DONE
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

ADC Enable bit
7 ADON 0: Disable the ADC module
1: Enable the ADC module
ADC Interrupt Flag bit
0 : No ADC interrupt, cleared by software.
6 ADCIF
1 : Set by hardware to indicate that the AD Convert has been completed, or analog
input is larger than ADDATH/ADDATL if compare is enabled
Compare Function Enable bit
5 EC 0 : Compare function disabled (default)
1 : Compare function enabled.
ADC interrupt enable
4 EADC 0 : Disable the ADC interrupt
1 : Enable the ADC interrupt
ADC channel Select
000: ADC channel AN0
001: ADC channel AN1
010: ADC channel AN2
3-1 SCH [2:0] 011: ADC channel AN3
100: Battery
101: ADC channel AN5
110: Internal VBG
111: Reserved
ADC status flag
———— 0: Automatically cleared by hardware when AD convert is completed. Clearing this bit during
0 GO/DONE converting time will stop current conversion. If Compare function is enabled, this bit will not
be cleared by hardware until software clear.
1: Set to start AD convert or digital compare.

Table 8.27 ADC Time Control Register

C2H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ADT TADC2 TADC1 TADC0 - TS3 TS2 TS1 TS0
R/W R/W R/W R/W - R/W R/W R/W R/W
Reset Value
0 0 0 - 0 0 0 0
（POR/WDT/LVR/PIN）
Bit Number Bit Mnemonic Description
TADC [2:0] – ADC Clock Period Select
000 = ADC Clock Period tAD = 2 tSYS
001 = ADC Clock Period tAD = 4 tSYS
010 = ADC Clock Period tAD = 6 tSYS
7-5 TADC [2:0] 011 = ADC Clock Period tAD = 8 tSYS
100 = ADC Clock Period tAD = 12 tSYS
101 = ADC Clock Period tAD = 16 tSYS
110 = ADC Clock Period tAD = 24 tSYS
111 = ADC Clock Period tAD = 32 tSYS
3-0 TS [3:0] Sample time select

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 SH79F642B
2 tAD ≤ Sample time = (TS [3:0]+1) * TAD < 15 TAD
Note:
(1) Make sure that tAD ≧ 1µs;
(2) The minimum sample time is 2 tAD, even TS[3:0] = 0000;
(3) The maximum sample time is 15 tAD , even TS[3:0] = 1111;
(4) Evaluate the series resistance connected with ADC input pin before set TS[3:0];
(5) Be sure that the series resistance connected with ADC input pin is no more than 10kΩ when 2 tAD sample time is selected;
(6) Total conversion time is: 12 tAD + sample time.

Table 8.28 ADC Channel Configure Register

AFH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ADCH - - CH5 - CH3 CH2 CH1 CH0
R/W - - R/W - R/W R/W R/W R/W
Reset Value
- - 0 - 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

Channel Configuration
3-0 CH[5], CH [3:0] 0: P2.7-P2.3 is I/O port
1: P2.7-P2.3 is ADC input port

Table 8.29 AD converter Data register (compare value register)

92H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ADDH A9 A8 A7 A6 A5 A4 A3 A2
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）
91H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ADDL - - - - - - A1 A0
R/W - - - - - - R/W R/W
Reset Value
- - - - - - 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

ADC data register:
7-0 Digital Value of sampled analog voltage, updated when conversion is completed
A9-A0
1-0 If ADC Compare function is enabled (EC = 1), this is the value to be compared
with the analog input

The Approach for AD Conversion:

1. Select the analog input channels and reference voltage.
2. Enable the ADC module with the selected analog channel.
————
3. Set GO/DONE = 1 to start the AD conversion.
————
4. Wait until GO/DONE = 0 or ADCIF = 1, if the ADC interrupt is enabled, the ADC interrupt will occur.
5. Acquire the converted data from ADDH/ADDL.
6. Repeat step 3-5 if another conversion is required.
The Approach for Digital Compare Function:
1. Select the analog input channels and reference voltage.
2. Set ADDH/ADDL to the compare value.
3. Set EC = 1 to enable compare function.

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 SH79F642B
4. Enable the ADC module with the selected analog channel.
————
5. Set GO/DONE = 1 to start the compare function.
6. If the analog input is lager than compare value set in ADDH/ADDL, the ADCIF will be set to 1. if the ADC interrupt is enabled,
the ADC interrupt will occur.
————
7. The compare function will continue work until the GO/DONE bit is cleared to 0.

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 SH79F642B
8.5 RTC (Real Timer Clock)
8.5.1 Features
 32.768kHz clock input with frequency compensation.
 Built-in high-precision frequency compensation circuit, compensation accuracy: 0.127PPM.
 Counter registers for: Half second, Second, Minute, Hour, Day, Day-of-week, Month, Year
 Day counter with automatic month and leap year adjustment
 Provides two Real Time Clock Alarms and a Timer.
 Provides the accurate seconed pulse output.

8.5.2 Functional Description

Time & Calendar function:
The RTC module provides clock indications in Half second, seconds, minutes, and hours; calendar indications in day-of-week,
day-of-month, month, and year(four-year calendar) with automatic adjustment for month and leap year. Reading the clock and
calendar registers return the current time and date. Writing to these registers set the time and date, and the counters will
continue to count from the new settings.
Calendar functions are provided by the day, day-of-week, month, and year counter registers. The roll over of the day counter is
automatically adjusted for the month and leap years.

Table 8.30 Cycle length of the time RTC

REGISTER COUNTING CYCLE CARRY TO NEXT UNIT COMMENT
SBSC 00-255 255 to 0 SBSC overflow, SEC plus 1
SEC 00 to 59 59 to 00 -
MIN 00 to 59 59 to 00 -
HR 00 to 23 23 to 00 -
01 to 31 31 to 01 MTH=1,3,5,7,8,10 and 12
01 to 30 30 to 01 MTH=4,6,9 and 11
DAY
01 to 29 29 to 01 MTH=2, YR=0 (leap year)
01 to 28 28 to 01 MTH=2, YR=1,2 and 3
MTH 01 to 12 12 to 01 -
YR 0 to 99 99 to 0 YR=0, leap year
DOW 0 to 6 6 to 0 -

SCBC’s value is equal to high 8 bit of 1 Hz frequency divider (source from 32.768KHz). Write 0x00 to SCBC will clear the high
8 bit register of divider. So SCBC also can be used for correcting time difference.

Read the calendar registers:

RTCCRD is used for reading time. When RTCRD = 0, the time register update by frequency 32768 Hz. When RTCRD = 1, the
newest time data update to register and stop refresh register until set RTCRD = 0 again.

Write the calendar registers;

Step 1: set RTCWD = 0x69. This step will stop the update of time registers and make this registers (include RTCPSW) writable.
Step 2: write data to time registers.
Step 3: set RTCPSW = 0x5a. This step will check the data you write. When the data is under rule of each register, write success
and clear RTCPSW. When the data is illegal, cancel write operation and set RTCPSW = 0x01.

Compensation:
A frequency compensation mechanism is built into this RTC module to allow adjustments to the RTC clock when a less
accurate 32.768kHz crystal is used. With the compensation mechanism, a more accurate real time could be made than the
frequency accuracy of the crystal that drives the module. The compensation value can be be set by application software, the
compensation cycle is 60s (high frequency compensaton second pulse’s compensaton cycle is 1s).1 LSB of compensaton
register can correct 0.127 PPM (1/60/32768/4) frequency error. There are 13 bit register ( two's complement ) use for
compensation, and higest bit reflect the polarity ( 0 means the crystal is too fast, 1 means the crystal is too slow). The
compensation range is -1024PPM to 1024PPM. The relation of frequency error (Err, Unit:S/D) and compensaton value (E) as
follow:
Err > 0 E(13:0) = Err * 11.574 / 0.127
Err < 0 E(13:0) = ~( |Err| * 11.574 / 0.127 ) + 1

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 SH79F642B
Alarm Function
Built-in 2 group alarm, one group include Second, Minute, Hour, Day, Day-of-week alarm register, the other one include
Second, Minute, Hour alarm register. When the time register data equal the alarm register, ALM0(1) be set to 1 and alarm
interrupt generate ( when alarm interrupt is enabled). At the same time, if OUTF[1:0] = 11, alarm 1 will output a 80ms(±1ms)
pulse in CALOUT.
ALMCON use to enable or disable each alarm register, There is no rule set to check the alarm register data, but the wrong data
may cause unexpected result. Therefore, take care in software programming.

Timer Function
Build-in 8 bit timer, the timer’s clock source can be choose by set ITS[1:0]. ITEN is a bit to control disable/enable timer function.
When the timer overflow, the timer register ( RTCTMR ) auto reload, set ITIF = 1, generate timer interrupt (if the interrupt is
enabled).

Interrupt Funtion
Provides second, minute, hour interrupt and alarm, timer interrupt. Each interrupt include interrupt control bit and interrupt flag
bit, the interrupt flag can be set 1 by hardware and clear by software.

I/O Pin
The RTC function uses 1 I/O pin: CALOUT. CALOUT is controlled by output control register OUTF, CALOUT output pin for:
compensated clock output after calibration, which can be programmed to output compensated 60-second clock or its original
32KHz clock, period changing signal. The output polarity can be set by OUTS.

8.5.3 Registers

Table 8.31 RTC subsecond register

FFA0H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SBSC SEC7 SEC6 SEC5 SEC4 SEC3 SEC2 SEC1 SEC0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value （POR） * * * * * * * *
Reset Value（WDT/LVR/PIN） u u u u u u u u

Bit Number Bit Mnemonic Description

RTC Subsecond Value
This register (bit0 ~ bit7) contains the current value of the high 8 bit of 1 Hz divider. This
7-0 SBSC[7:0] register (bit0 ~ bit7) can be read at any time without affecting the counter count. Writing to
this register (bit0 ~ bit7) loads the value to the subsecond counter and the counter continues
to count from this new value. The subsecond counter rolls over to 0 after reaching 255.
NOTE: * : means random value .

Table 8.32 Second Register

FFA1H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SEC - SEC6 SEC5 SEC4 SEC3 SEC2 SEC1 SEC0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value （POR） * * * * * * * *
Reset Value（WDT/LVR/PIN） u u u u u u u u

Bit Number Bit Mnemonic Description

This register (bit0 ~ bit6) contains the current value (BCD) of the second counter. This
register (bit0 ~ bit6) can be read at any time without affecting the counter count. Writing to
this register (bit0 ~ bit6) loads the value to the second counter and the counter continues to
6-0 SEC[6:0]
count from this new value. The second counter rolls over to 0 after reaching 59.
Writing a value other than 0 to 59 to this register has no effect.
Be sure not to write a data such as ‘0x, 1x, 2x, 3x, 4x (x=A~F)’ to this register.

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Table 8.33 Minute Register

FFA2H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MIN - MIN6 MIN5 MIN4 MIN3 MIN2 MIN1 MIN0
R/W - R/W R/W R/W R/W R/W R/W R/W
Reset Value （POR） * * * * * * * *
Reset Value（WDT/LVR/PIN） - u u u u u u u

Bit Number Bit Mnemonic Description

This read/write register contains the current value (BCD) of the minute counter. This
register can be read at any time without affecting the counter count. Writing to this register
loads the value to the minute counter and the counter continues to count from this new
6-0 MIN[6:0]
value. The minute counter rolls over to 0 after reaching 59. Writing a value other than 0 to
59 to this register has no effect.
Be sure not to write a data such as ‘0x, 1x, 2x, 3x, 4x (x=A~F)’ to this register.

Table 8.34 Hour Register

FFA3H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
HR - - HR5 HR4 HR3 HR2 HR1 HR0
R/W - - R/W R/W R/W R/W R/W R/W
Reset Value （POR） * * * * * * * *
Reset Value（WDT/LVR/PIN） - - u u u u u u

Bit Number Bit Mnemonic Description

This read/write register contains the current value (BCD) of the hour counter. This register
can be read at any time without affecting the counter count. Writing to this register loads the
value to the hour counter and the counter continues to count from this new value.
5-0 HR[5:0]
The hour counter rolls over to 0 after reaching 23. Writing a value other than 0 to 23 to this
register has no effect.
Be sure not to write a data such as ‘0x, 1x (x=A~F)’ to this register.

Table 8.35 Day Register

FFA4H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DAY - - DAY5 DAY4 DAY3 DAY2 DAY1 DAY0
R/W - - R/W R/W R/W R/W R/W R/W
Reset Value （POR） - - * * * * * *
Reset Value（WDT/LVR/PIN） - - u u u u u u

Bit Number Bit Mnemonic Description

This read/write register contains the current value (BCD) of the day-of-month counter. This
register can be read at any time without affecting the counter count. Writing to this register
loads the value to the day counter and the counter continues to count from this new value.
5-0 DAY[5:0] The day counter rolls over to 1 ($01) after reaching 28, 29 , 30 , or 31 , depending on the
value in the month and year registers.
Writing a value that is not valid for the month and year to this register has no effect.
Be sure not to write a data such as ‘1x, 2x (x=A~F)’ to this register.

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Table 8.36 Month Register
FFA5H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MTH - - - MTH4 MTH3 MTH2 MTH1 MTH0
R/W - - - R/W R/W R/W R/W R/W
Reset Value （POR） - - - * * * * *
Reset Value（WDT/LVR/PIN） - - - u u u u u

Bit Number Bit Mnemonic Description

This read/write register contains the current value (BCD) of the month counter. This register
can be read at any time without affecting the counter count. Writing to this register loads the
value to the month counter and the counter continues to count from this new value. The
4-0 MTH[4:0]
month counter rolls over to 1 after reaching 12 .
Writing a value other than 1 to 12 to this register has no effect.
Be sure not to write a data such as ‘x (x=A~F)’ to this register.

Table 8.37 Year Register

FFA6H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
YR YR7 YR6 YR5 YR4 YR3 YR2 YR1 YR0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value （POR） * * * * * * * *
Reset Value（WDT/LVR/PIN） u u u u u u u u

Bit Number Bit Mnemonic Description

This read/write register contains the current value (BCD) of the year counter. This register
can be read at any time without affecting the counter count. Writing to this register loads the
7-0 YR[7:0] value to the year counter and the counter continues to count from this new value.
The YR value rolls over to 0 after reaching 99.
Writing a value other than 0 to 99 to this register has no effect.

Table 8.38 Week Register

FFA7H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DOW - - - - - DOW2 DOW1 DOW0
R/W - - - - - R/W R/W R/W
Reset Value
- - - - - u u u
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

This read/write register contains the current value (BCD) of the day-of-week counter. This
register can be read at any time without affecting the counter count. Writing to this register
2-0 DOW[2:0] loads the value to the day-of-week counter and the counter continues to count from this
new value. The day-of-week counter value rolls over to 0 after reaching 6. Writing a value
other than 0 to 6 to this register has no effect.

Table 8.39 RTC Compensation Value Register( E )

FFA8H – FFA9H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RTCDATH(FFA8H) - - E13 E12 E11 E10 E9 E8
RTCDATL(FFA9H) E7 E6 E5 E4 E3 E2 E1 E0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
0 0 * * * * * *
Reset Value（POR）
0 0 * * * * * *

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Reset Value - - u u u u u u
（WDT/LVR/PIN） - - u u u u u u

Bit Number Bit Mnemonic Description

RTC Compensaton value ( E )
E[13:0] compensation value is the compensate clock number of RTC.
E < 0 : Cut down E clock in a compensate cycle;
7-0 E[13:0]
E > 0 : Add E clock in a compensate cycle.
E[13:0]: the binary complement means a signed value
NOTE: Reset will not change this register’s value.

Table 8.40 RTC Alarm Control Register

FFAAH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RTCALM ALM1C2 ALM1C1 ALM1C0 ALM0C4 ALM0C3 ALM0C2 ALM0C1 ALM0C0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value（POR） * * * * * * * *
Reset Value
u u u u u u u u
（WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

Alarm 1 Hour Enable bit
7 ALM1C2 0：A1HR is not used as comparison data for generating an alarm
1：A1HR is used as comparison data for generating an alarm
Alarm 1 Minute Enable bit
6 ALM1C1 0：A1MIN is not used as comparison data for generating an alarm
1：A1MIN is used as comparison data for generating an alarm
Alarm 1 Sec Enable bit
5 ALM1C0 0：A1SEC is not used as comparison data for generating an alarm
1：A1SEC is used as comparison data for generating an alarm
Alarm 0 Week Enable bit
4 ALM0C4 0：A0DOW is not used as comparison data for generating an alarm
1：A0DOW is used as comparison data for generating an alarm
Alarm 0 Day Enable bit
3 ALM0C3 0：A0DAY is not used as comparison data for generating an alarm
1：A0DAY is used as comparison data for generating an alarm
Alarm 0 Hour Enable bit
2 ALM0C2 0：A0HR is not used as comparison data for generating an alarm
1：A0HR is used as comparison data for generating an alarm
Alarm 0 minute Enable bit
1 ALM0C1 0：A0MIN is not used as comparison data for generating an alarm
1：A0MIN is used as comparison data for generating an alarm
Alarm 0 Second Enable bit
0 ALM0C0 0：A0SEC is not used as comparison data for generating an alarm
1：A0SEC is used as comparison data for generating an alarm

Table 8.41 Alarm 0 Second Register

FFABH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
A0SEC - A0SEC6 A0SEC5 A0SEC4 A0SEC3 A0SEC2 A0SEC1 A0SEC0
R/W - R/W R/W R/W R/W R/W R/W R/W
Reset Value（POR） - * * * * * * *
Reset Value
- u u u u u u u
（WDT/LVR/PIN）

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Bit Number Bit Mnemonic Description

Alarm 0 second register (BCD). When ALM0C0 = 1, second register (SEC) equal
6-0 A0SEC6-0 A0SEC and the other enabled alarm 0 registers meet the conditions too, generate an
alarm and set the flag bit of alarm interrupt to 1.

Table 8.42 Alarm 0 Minute Register

FFACH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
A0MIN - A0MIN6 A0MIN5 A0MIN4 A0MIN3 A0MIN2 A0MIN1 A0MIN0
R/W - R/W R/W R/W R/W R/W R/W R/W
Reset Value（POR） - * * * * * * *
Reset Value
- u u u u u u u
（WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

Alarm 0 minute register (BCD). When ALM0C1 = 1, minute register (MIN) equal
6-0 A0MIN6-0 A0MIN and the other enabled alarm 0 registers meet the conditions too, generate an
alarm and set the flag bit of alarm interrupt to 1.

Table 8.43 Alarm 0 Hour Register

FFADH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
A0HR - - A0HR5 A0HR4 A0HR3 A0HR2 A0HR1 A0HR0
R/W - - R/W R/W R/W R/W R/W R/W
Reset Value（POR） - - * * * * * *
Reset Value
- - u u u u u u
（WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

Alarm 0 hour register (BCD). When ALM0C2 = 1, hour register (HR) equal A0HR
5-0 A0HR5-0 and the other enabled alarm 0 registers meet the conditions too, generate an alarm
and set the flag bit of alarm interrupt to 1.

Table 8.44 Alarm 0 Day Register

FFAEH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
A0DAY - - A0DAY5 A0DAY4 A0DAY3 A0DAY2 A0DAY1 A0DAY0
R/W - - R/W R/W R/W R/W R/W R/W
Reset Value（POR） - - * * * * * *
Reset Value
- - u u u u u u
（WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

Alarm 0 day register (BCD). When ALM0C3 = 1, day register (DAY) equal A0DAY
5-0 DAY5-0 and the other enabled alarm 0 registers meet the conditions too, generate an alarm
and set the flag bit of alarm interrupt to 1.

Table 8.45 Alarm 0 Week Register

FFAFH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
A0DOW - - - - - A0DOW2 A0DOW1 A0DOW0
R/W - - - - - R/W R/W R/W
Reset Value（POR） - - - - - * * *
Reset Value
- - - - - u u u
（WDT/LVR/PIN）

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Bit Number Bit Mnemonic Description

Alarm 0 week register (BCD). When ALM0C4 = 1, week register (DOW) equal
2-0 DOW2-0 A0DOW and the other enabled alarm 0 registers meet the conditions too, generate
an alarm and set the flag bit of alarm interrupt to 1.

Table 8.46 Alarm 1 Second Register

FFB0H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
A1SEC - A1SEC6 A1SEC5 A1SEC4 A1SEC3 A1SEC2 A1SEC1 A1SEC0
R/W - R/W R/W R/W R/W R/W R/W R/W
Reset Value（POR） - * * * * * * *
Reset Value
- u u u u u u u
（WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

Alarm 1 second register (BCD). When ALM1C0 = 1, second register (SEC) equal
6-0 A1SEC6-0 A1SEC and the other enabled alarm 1 registers meet the conditions too, generate an
alarm and set the flag bit of alarm interrupt to 1.

Table 8.47 Alarm 1 Minute Register

FFB1H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
A1MIN - A1MIN6 A1MIN5 A1MIN4 A1MIN3 A1MIN2 A1MIN1 A1MIN0
R/W - R/W R/W R/W R/W R/W R/W R/W
Reset Value（POR） - * * * * * * *
Reset Value
- u u u u u u u
（WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

Alarm 1 minute register (BCD). When ALM1C1 = 1, minute register (MIN) equal
6-0 A1MIN6-0 A1MIN and the other enabled alarm 1 registers meet the conditions too, generate an
alarm and set the flag bit of alarm interrupt to 1.

Table 8.48 Alarm 1 Hour Register

FFB2H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
A1HR - - A1HR5 A1HR4 A1HR3 A1HR2 A1HR1 A1HR0
R/W - - R/W R/W R/W R/W R/W R/W
Reset Value（POR） - - * * * * * *
Reset Value
- - u u u u u u
（WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

Alarm 1 hour register (BCD). When ALM1C2 = 1, hour register (HR) equal A1MIN
5-0 A1HR5-0 and the other enabled alarm 1 registers meet the conditions too, generate an alarm
and set the flag bit of alarm interrupt to 1.

Table 8.49 RTC calibration control register

FFB3H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RTCCON RTCRD ITEN ITS1 ITS0 OUTEN OUTS OUTF1 OUTF0
R/W R/W R/W R/W R/W R/W R/W R/W R
Reset Value(POR) 0 * * * 0 * * *
Reset Value(WDT/LVR/PIN) 0 u u u 0 u u u

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Bit Number Bit Mnemonic Description

Time Registers Lock bit
7 RTCRD 0： RTC Time Registers update with RTC clock frequency
1： RTC Time Registers update to the latest data, then stop refresh
RTC Built-in Timer Enable bit
6 ITEN 0：Stop build-in timer
1：Start build-in timer
RTC Build-in Timer Clock Source Select bit
00：RTC clock source / 128
5-4 ITS[1:0] 01：Second ( original )
10：Minute
11： Hour
RTC Multi-function Output Enable bit
3 OUTEN 0： CALOUT use as normal I/O pin
1： CALOUT output RTC multi-function signal
RTC Multi-function Output’s Polarity Select bit
2 OUTS 0： Positive, active level is high level
1： Negative, active level is low level
Calibration Mode CALOUT Pin Output Frequency Select bit
00：CALOUT output 32.768khz clock
1-0 OUTF [1:0] 01：output compensated clock by low frequency
10：output compensated clock by high frequency
11：outout swithing impulse,if alarm happened, output 80ms impulse
Note :
1．When select second signal (high frequency compensated) output, PLL need enabled.
2．There is a delay ( less than 32us ) exist, when set RTCRD = 1. Because refresh the time register need time, and
when RTCRD is set to 1 success, the lock operation success.

Table 8.50 RTC Time Data Write-protect Register

FFB4H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RTCWR RTCWR7 RTCWR6 RTCWR5 RTCWR4 RTCWR3 RTCWR2 RTCWR1 RTCWR0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value（POR） 0 0 0 0 0 0 0 0
Reset Value 0 0 0 0 0 0 0 0
（WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

When RTCWD = 0x69, stop the update of time registers and make this registers (include
RTCPSW) writable. Then write data to time registers. At last, set RTCPSW = 0x5a, will
7-0 RTCWR7-0
check the data you write. When the data is under rule of each register, write success and
clear RTCPSW. When the data is illegal, cancel write operation and set RTCPSW = 0x01.

Table 8.51 RTC Time Writable Register

FFB5H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RTCPSW PSW7 PSW6 PSW5 PSW4 PSW3 PSW2 PSW1 PSW0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value（POR） 0 0 0 0 0 0 0 0
Reset Value 0 0 0 0 0 0 0 0
（WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

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 SH79F642B
Only RTCPSW = 0x5a, the calendar time register value update to the calendar time
counter,any other value can affect the calendar time counter.Finished writing
7-0 PSW7-0
value,whether the data is valid,the register only can be cleared by hardware.The
register can be written onle if RTCWR = 0x69.

Table 8.52 RTC Interrupt Enable Register

FFB6H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RTCIE IT0IE DAYIE HRIE MINIE SECIE ALM1IE ALM0IE -
R/W R/W R/W R/W R/W R/W R/W R/W -
Reset Value（POR） 0 0 0 0 0 0 0 -
Reset Value 0 0 0 0 0 0 0 -
（WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

Build-in Timer Interrupt Enable Control bit
7 IT0IE 0: Disable build-in timer interrupt
1: Enable build-in timer interrupt
Day Interrupt Enable Control bit
6 DAYIE 0: Disable Day interrupt
1: Enable Day interrupt
Hour Interrupt Enable Control bit
5 HRIE 0: Disable Hour iInterrupt
1: Enable Hour interrupt
Minute Interrupt Enable Control bit
4 MINIE 0: Disable Minute interrupt
1: Enable Minute interrupt
Second Interrupt Enable Control bit
3 SECIE 0: Disable Second interrupt
1: Enable Second interrupt
Alarm 1 Interrupt Enable Control bit
2 ALM1IE 0: Disable Alarm 1 interrupt
1: Enable Alarm 0 interrupt
Alarm 0 Interrupt Enable Control bit
1 ALM0IE 0: Disable Alarm 0 interrupt
1: Enable Alarm 0 interrupt

Table 8.53 RTC Interrupt Request Register

FFB7H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RTCIF IT0IF DAYIF HRIF MINIF SECIF ALM1IF ALM0IF -
R/W R/W R/W R/W R/W R/W R/W R/W -
Reset Value（POR） * * * * * * * -
Reset Value
u u u u u u u -
（WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

The Request Flag for Built-in Timer Interrupt
7 IT0IF 0: No request
1: Request
The Request Flag for Day Interrupt
6 DAYIF 0: No request
1: Request
The Request Flag for Hour Interrupt
5 HRIF 0: No request
1: Request

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The Request Flag for Minute Interrupt
4 MINIF 0: No request
1: Request
The Request Flag for Second Interrupt
3 SECIF 0: No request
1: Request
The Request Flag for Alarm 1 Interrupt
2 ALM1IF 0: No request
1: Request
The Request Flag forAlarm 0 Interrupt
1 ALM0IF 0: No request
1: Request

Table 8.54 RTC Room Temperature Error Register

FFB9H FFB8H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RTCECH(FFB9H) EC15 EC14 EC13 EC12 EC11 EC10 EC9 EC8
RTCECL(FFB8H) EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0
R/W R R R R R R R R
Reset Value
u u u u u u u u
（POR/WDT/LVR/PIN））

Bit Number Bit Mnemonic Description

RTC 25℃（77℉）Error Value ( EC Register)
15-0 EC[15:0] E[15:0] ( Two's complement ) is the frequency ( 32768Hz ) error under 25℃（77℉）,
1LSB ->0.1PPM

Table 8.55 RTC Build-in Timer Count Register

FFBAH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RTCTMR RTCT7 RTCT6 RTCT5 RTCT4 RTCT3 RTCT2 RTCT1 RTCT0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value
u u u u u u u u
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

7-0 RTCT[7-0] RTC Build-in Timer Counter
NOTE:
This Counter is down-couter.1 when set RTCTMR = 0/1, overflow will be happened in every count cycle.

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8.6 PWM Timer

8.6.1 Features
 Two 12-bit PWM output
 Provided interrupt function on period
 Selectable output polarity

The SH79F642B has two 12-bit PWM modules. The PWM module can provide the pulse width modulation waveform with the
period and the duty being controlled, individually. The PWMxEN (x = 0-1) is used to enable two PWM modules. The PWMxCON
(x = 0-1) is used to control the clock source, output mode and cycle interrupt of the PWM module output, and so on. The
PWMxPH/L (x = 0-1) is used to control the period cycle of the PWM module output. PWMxDH/L (x = 0-1) is used to control the
duty in the waveform of the PWM module output.

PWM Wave Output Control Block

PWMCON[PWMCK1:PWMCK0]
Generator Block
/1,/2,/4 or /8 PWMCON[PWMSS]
fsys Pre-Counter
PWMCON[PWMEN] PWMCON[PWMS]
Logic PWMCON[PWMS]
PWM Clock

0
12-bit Period 12-bit Duty PWM 1
Counter Counter Wave 1 PWM
'1' Match 0

PWMPH 8-bit buffer PWMDH 8-bit buffer

Writing signal of Writing signal of PWMCON[PWMEN]
PWMPH PWMDH

PWMPL PWMDL I/O Block

Period Time Base Block

Interrupt
PWMCON[PWMIE] PWMCON[PWMIF]
Control

Period Interrupt Block

Fig. 8.7.1 Sample Figure of PWMx Module

8.6.2 Registers
Table 8.56 PWMx control PWMxCON (x=0~1)
C3H, 93H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PWM0CON (C3H) PWM0EN PWM0S PWM0CK1 PWM0CK0 - PWM0IE PWM0IF PWM0SS
PWM1CON (93H) PWM1EN PWM1S PWM1CK1 PWM1CK0 - PWM1IE PWM1IF PWM1SS
W/R W/R W/R W/R W/R - W/R W/R W/R
Reset Value
0 0 0 0 - 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

PWMx enable bit：
7 PWMxEN 0: Disable PWMx
1: Enable PWMx
PWMx output normal mode of duty cycle
6 PWMxS 0: high active, PWMx output high during duty time, output low during remain period time
1: low active, PWMx output low during duty time, output high during remain period time

97
 SH79F642B
PWMx clock selector:
00: system clock/1
5~4 PWMxCK[1:0] 01: system clock/2
10: system clock/4
11: system clock/8
PWMx interrupt control ：
2 PWMxIE 0：Disable PWMx period interrupt
1：Enable PWMx period interrupt
PWMx interrupt flag
1 PWMxIF 0: no overflow
1: Set by hardware to indicate that the PWM period counter overflow.Cleared by software
PWMx output control
0 PWMxSS 0：PWMx output disable, as I/O or other fuction
1：PWMx output enable

Table 8.57 PWM0 period register PWM0PH/L

C7H, C6H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PWM0PH (C7H) - - - - PWM0P.11 PWM0P.10 PWM0P.9 PWM0P.8
PWM0PL (C6H) PWM0P.7 PWM0P.6 PWM0P.5 PWM0P.4 PWM0P.3 PWM0P.2 PWM0P.1 PWM0P.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

11-0 PWM0P.11~0 PWM0 peiod registers
PWM0 output period cycle = PWM0P[11:0] * PWM0 clock.
When PWM0P[11:0] = 000H, PWM0 outputs GND if the PWMS bit is set to “0” regardless of PWM duty cycle.
When PWM0P[11:0] = 000H, PWM0 outputs high level if the PWMS bit is set to “1” regardless of PWM duty cycle.

Table 8.58 PWM1 period register PWM1PH/L

97H, 96H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PWM1PH (97H) - - - - PWM1P.11 PWM1P.10 PWM1P.9 PWM1P.8
PWM1PL (96H) PWM1P.7 PWM1P.6 PWM1P.5 PWM1P.4 PWM1P.3 PWM1P.2 PWM1P.1 PWM1P.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

11-0 PWM1P.11~0 PWM1 data register
PWM1 output period cycle = PWM1P[11:0] * PWM1 clock.
When PWM1P[11:0] = 000H, PWM1 outputs GND if the PWMS bit is set to “0” regardless of PWM1 duty cycle.
When PWM1P[11:0] = 000H, PWM1 outputs high level if the PWMS bit is set to “1” regardless of PWM1 duty cycle.

Table 8.59 PWM0 Duty Control Register PWM0DH/L

C5H, C4H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PWM0DH (C5H) - - - - PWM0D.11 PWM0D.10 PWM0D.9 PWM0D.8
PWM0DL (C4H) PWM0D.7 PWM0D.6 PWM0D.5 PWM0D.4 PWM0D.3 PWM0D.2 PWM0D.1 PWM0D.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

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12-bit PWM duty registers
1. If PWM0P ≤ PWM0D,
PWM0 outputs high level when the PWM0S bit is cleared to 0.
11-0 PWM0D.11~0 PWM0 outputs GND level when the PWM0S bit is setted to 1.
2. If PWM0D = 00H,
PWM0 outputs GND level when the PWM0S bit is cleared to 0.
PWM0 outputs high level when the PWM0S bit is setted to 1.

Table 8.60 PWM1 Duty Control Register PWM1DH/L

95H, 94H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PWM1DH (95H) - - - - PWM1D.11 PWM1D.10 PWM1D.9 PWM1D.8
PWM1DL (94H) PWM1D.7 PWM1D.6 PWM1D.5 PWM1D.4 PWM1D.3 PWM1D.2 PWM1D.1 PWM1D.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

12-bit PWM duty registers
1. If PWM1P ≤ PWM1D,
PWM1 outputs high level when the PWM1S bit is cleared to 0.
PWM1 outputs GND level when the PWM1S bit is setted to 1.
11-0 PWM1D.11~0
2. If PWM1D = 00H,
PWM1 outputs GND level when the PWM1S bit is cleared to 0.
PWM1 outputs high level when the PWM1S bit is setted to 1.

Note: The change of PWMxPH will take affect at the next PWMx period. The user must change PWMxPL at first, and then
change PWMxPH for changing PWMx period.

8.6.3 PWM Clock

PWM Clock can be selected from 1, 1/2, 1/4, 1/8 system clock, and controlled by [PWMxCK1:PWMxCK0] in PWMxCON. As
shown in PTBB(Period Time Base Block) of Fig. 8.7.1, PWM clock (PWMx Clock) is generated by a 3-bit pre-Counter dividing
the system clock. And Period Counter and Duty Counter in PWM Module generate PWMx waveform by counting PWM clock.
When PWMxEN=1 in PWMxCON, PWMx clock outputs, and if PWMxSS=1 in PWMxCON, there would be PWM waveform in
PWMx Port. However, when PWMxEN=0, PWM clock stops and pre-Counter of PWMx clock resets to ‘0’.

8.6.4 PWM Waveform

As Shown in Fig. 8.7.2, 12-bit Period Counter and 12-bit Duty Counter decrement the counter of PWMx clock. In every end of a
PWM period, PWMxPH&PWMxPL will be automatically loaded to the period counter as a 12-bit data and PWMxDH&PWMxDL
will be automatically loaded to duty counter as a 12-bit data at the same time. Then the period counter and duty counter
decrement the counter of the latest loaded data. When the duty counter value count down to 1, duty counter stops and the time
this process costs is defined as Duty Zone. If PWMxSS=1, PWM pin would output an opposite level to PWMxS value. In
addition, the duty counter will keep value 1 until period counter count down to 1, and this part of time is defined as None Duty
Zone. If PWMxSS=1, PWM pin would output an same level to PWMxS value. When period counter value is 1, the current PWM
period ends and back to reload PWMxPH&PWMxPL& PWMxDH&PWMxDL automatically before starting the next PWM period.
PWM waveform is shown in Fig. 8.7.2.

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6 Tsys
PWMSS = 1
5 5 5 5

4 4 4

3 3 3
Period Counter
2 2
1 1

4 4 4

3 3 3

Duty Counter 2 2 2
1 1

System
Clock

PWM Clock

PWMEN

PWM pin output Duty Zone

when PWMS = 0 Duty Zone

Duty Zone
Duty Zone
PWM pin output
when PWMS = 1

PWMIF is set PWMIF is set

by hardware by hardware
Modify Modify
PWMP = 5 PWMP = 6 PWMP = 5
PWMD = 4 PWMD = 3 PWMD = 4

Fig. 8.7.2 PWMx Waveform

Notes: When PWMxEN=1, the adjustment of period or duty registers will be valid in the next PWM period.

8.6.5 PWM Output Control

As shown in Fig. 8.7.1, when PWMxSS=0 in PWMxCON, P1.4/P5.6 is used as normal I/O. Only when PWMxSS=0 in
PWMxCON, P1.4/P5.6 is used as PWM output port.
When PWMxSS=1&PWMxEN=0, P1.4/P5.6 output the value of PWMxS. Only when PWMxSS=1&PWMxEN=1, P1.4/P5.6
outputs PWMx waveform.

8.6.6 PWM Period Interrupt

As shown in Fig. 8.9.2, in every end of PWM period, PWMxIF in PWMxCON will be set automatically by hardware. When
PWMxIE=1&EPWM=1&EA=1, it will cause PWM period interrupt. Otherwise, PWM period interrupt cannot be generated.
PWMIF can only be cleared by software.

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8.6.6 PWM Programming Note
I. If PWMxEN=1&PWMxSS=0, PWMx output will shut down (used as normal I/O), and PWMx can be used as a 12-bit timer.
Meanwhile, if EPWM=1 in interrupt control register IEN1and PWMxIE=1 in PWMxCON and EA = 1, PWMx interrupt will occur
(unless PWMxP = 0).
II. When PWMxP=0& PWMxSS=1&PWMxEN=1, P1.4/P5.6 outputs the value of PWMxS no matter what value PWMxD is.
III. When 0 < PWMxP ≤ PWMxD, PWMSS = 1 and PWMxEN = 1:
If PWMxS=0, P1.4/P5.6 outputs high level;
If PWMxS=1, P1.4/P5.6 outputs low level.
IV. When PWMxD=0, PWMxP > 0, PWMxSS = 1 and PWMxEN = 1:
If PWMxS=0, P1.4/P5.6 outputs low level;
If PWMxS=1, P1.4/P5.6 outputs high level.
V. When PWMxEN = 0:
If PWMxS=0, P1.4/P5.6 outputs low level;
If PWMxS=1, P1.4/P5.6 outputs high level.

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8.7 Low-voltage detection (LPD1)
Low-voltage detection (LPD1) used to monitor the VDD voltage and the voltage of the VIN pin. VIN pin voltage detection
function code selection. If the VIN pin detection is effective VIN pin voltage is below 1.2V, the hardware setup to mark FVIN 0;
if the pin voltage is above 1.2V, the hardware set FVIN mark of 1. Low-voltage detection circuit detects the VDD voltage lower
than 2.7V, the hardware setup the mark FVDD 0; higher than 2.7V to VDD is detected, the hardware setup the mark FVDD 1.
The low voltage detection to provide the VIN pin and VDD voltage marker to the power management features, but only the VDD
voltage marker to the automatic switching of the power supply.
Table 8.61 Low-voltage detection control register
B3H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
LPDCON LPDEN FVIN LPDIF VOUTS FVDD LPDS - AUTOS
W/R W/R R W/R W/R R R - W/R
0 0
Reset value u u
1 0 0 0 0 -
（POR/WDT/LVR/PIN） 0 0
0 0

Bit Number Bit Mnemonic Description

LPD Enable bit
7 LPDEN 0: Disable lower power detection
1: Enable lower power detection
VIN pin voltage status flags
0: VIN pin voltage lower than 1.2V
6 FVIN
1: VIN pin voltage higher than 1.2V
If the code choose to disable the VIN voltage detection function, this flag is invalid
LPD interrupt flag
5 LPDIF 0: No LPD interrupt happen
1: LPD interrerupt happens
Power supply status
4 VOUTS 0: battery-powered to VOUT
1: External power supply to VOUT
VDD voltage state marker
3 FVDD 0: VDD voltage lower than 2.7V
1: VDD voltage higher than 2.7V
LPD interrupt source
2 LPDS 0: VDD voltage caused the interrupt
1: VIN pin voltage caused interrupt
Power supply automatically switch to allow
0 AUTOS 0: allow the power supply automatically switches
1: Disable the power supply automatically switches

Table 8.62 VOUT(LPD2) Low-voltage detection control register

BFH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
LPDCON1 LPDEN1 LPDF - - - LPDS2 LPDS1 LPDS0
W/R W/R R - - - W/R W/R W/R
Reset value
0 0 - - - 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

LPD Enable bit
7 LPDEN1 0: Disable lower power detection
1: Enable lower power detection
LPD State Flag bit
6 LPDF
0: Cleared by hardware when VOUT>LPD detect voltage.

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0: Set to ‘1’ by hardware when VOUT>LPD detect voltage.
Notes：When LPDEN=0, LPDF=0.
LPD Voltage Control bits
000: 2.55 V
001: 2.70 V
010: 2.85 V
3-0 LPDS [2:0] 011: 3.00 V
100: 3.15 V
101: 3.30 V
110: 3.45 V
111: 3.60 V

Table 8.63 Metering LDO Voltage Control Register

DFH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
LDOCON BGEN LDOEN1 LDOEN0 - - - - -
W/R W/R W/R W/R - - - -
0 0 0
Reset value u u u
- - - - -
（POR/WDT/LVR/PIN） 0 0 0
0 0 0

Bit Number Bit Mnemonic Description

Metering LDO Bandgap Switch Control bit
7 BGEN 0：Disable
1：Enable
LDO Output Control bits
00: 0 V (no output)
6-5 LDOEN[1:0]
01: 2.8 V
1x: VOUT

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8.8Low Voltage Reset (LVR)
8.8.1 Features
 TLVR is about 30-60us.
 An internal reset indicates low voltage reset generates, when VDD ≤ VLVR

The LVR function is used to monitor the supply voltage and generate an internal reset in the device when the supply
voltage is below the specified value VLVR. The LVR de-bounce Timer TLVR is about 30-60us.
The LVR circuit has the following functions when the LVR function is enabled: (t means the time of the supply voltage
below VLVR)
- Generates a system reset when VDD ≤ VLVR and t ≥ TLVR.
- Cancels the system reset when VDD > VLVR or VDD < VLVR, but t < TLVR.
The LVR function is enabled by the Code Option.
It is typically used in AC line or large battery supplier applications, where heavy loads may be switched on and cause the
MCU supply-voltage temporarily falls below the minimum specified operating voltage. This feature is can protect system from
working under bad power supply environment.

8.9 Watchdog Timer (WDT) and reset state

8.9.1 Features
 WDT runs even in the Power-Down mode
 Auto detect Program Counter(PC) over range, and generate OVL Reset
 Selectable different WDT overflow frequency
8.9.2 OVL Reset
To enhance the anti-noise ability, SH79F642B built in Program Counter (PC) over range detect circuit, if program counter value
is larger than flash rom size, or detect operation code equal to A5H which is not exist in 8051 instruction set, a OVL reset will be
generate to reset CPU, and set WDOF bit. So, to make use of this feature, user should fill unused flash rom with A5H.
8.9.3 Watchdog Timer
The watchdog timer is a down counter, and its clock source is an independent built-in RC oscillator, so it always runs even in the
Power-Down mode. The watchdog timer will generate a device reset when it overflows. It can be enabled or disabled
permanently by the code option.
The watchdog timer control bits (WDT.2-0) are used to select different overflow frequency. The watchdog timer overflow flag
(WDOF) will be automatically set to “1” by hardware when overflow happens. To prevent overflow happen, by reading or writing
the WDT register RSTSTAT, the watchdog timer should re-count before the overflow happens.
There are also some reset flags in this register as below:
8.9.2 Registers
Table 8.64 RSTSTAT Control Register
B1H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RSTSTAT WDOF - PORF LVRF CLRF WDT.2 WDT.1 WDT.0
W/R W/R - W/R W/R W/R W/R W/R W/R
Reset value （POR） 0 - 1 0 0 0 0 0
Reset value （WDT） 1 - u u u 0 0 0
Reset value （LVR） u - u 1 u 0 0 0
Reset value （PIN） u - u u 1 0 0 0

Bit Number Bit Mnemonic Description

Watch Dog Timer Overflow or OVL Reset Flag
Set by hardware when WDT overflow or OVL reset happened, cleared by
7 WDOF software or Power On Reset
0: Watch Dog not overflows and no OVL reset generated
1: Watch Dog overflow or OVL reset occurred

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Power On Reset Flag
Set only by Power On Reset, cleared only by software
5 PORF
0: No Power On Reset.
1: Power On Reset occurred.
Low Voltage Reset Flag
Set only by Low Voltage Reset, cleared by software or Power On Reset
4 LVRF
0: No Low Voltage Reset occurs
1: Low Voltage Reset occurred
External Pin Reset Flag
Set only by External Pin Reset, cleared by software or Power On Reset
3 CLRF
0: No External Pin Reset occurs
1: External Pin Reset occurred
WDT Overflow period control bit
000: Overflow period minimal value = 4096ms
001: Overflow period minimal value = 1024ms
010: Overflow period minimal value = 256ms
011: Overflow period minimal value = 128ms
2-0 WDT[2:0] 100: Overflow period minimal value = 64ms
101: Overflow period minimal value = 16ms
110: Overflow period minimal value = 4ms
111: Overflow period minimal value = 1ms
Notes: If WDT_opt is enable in application, user must clear WatchDog
periodically, and the interval must be less than the value list above.

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8.10 Power Management
SH79F642B provides two power supply, an external power input from the VDD pin switch to VOUT, a battery from the VBAT pin
switch to VOUT. The normal power supply external power supply, if the external power failure situation, the automatic cut by the
external power supply to the battery-powered; if the external power supply to restore power, then automatically switch to
battery-powered external power supply. The external power supply voltage detection by the built-in low voltage detector LPD
implementation.
The VOUT powered all the features of the circuit except for the analog front-end of Energy Metering. The analog front-end of
Energy Metering is supported by VDD or LDO. LDO is powered by VOUT.
In order to cooperate with different power source, SH79F642B provides low power cost mode to meet working requirement with
lower power needs.

8.10.1 Low-power mode

To reduce power consumption, SH79F642B supplies two power saving modes: Idle mode and Power-Down mode. These two
modes are controlled by PCON & SUSLO register.
8.10.1.1 Idle mode and super idle mode
Idle mode :In this mode, the clock to CPU is frozen, the program execution is halted, and the CPU will stop at a defined
state. But the peripherals continue to be clocked. When entering idle mode, all the CPU status before entering will be
preserved. Such as: PSW, PC, SFR & RAM are all be retained.
By two consecutive instructions: setting SUSLO register as 55H, and immediately followed by setting the IDL bit in PCON
register, will make SH79F642B enter idle mode. If the consecutive instruction sequence requirement is not met, the CPU will
clear either SUSLO register or IDL bit in the next machine cycle. And the CPU will not enter IDLE mode.
The setting of IDL bit will be the last instruction that CPU executed.
There are two ways to exit Idle mode:
(1) An interrupt generated. After warm-up time, the clock to the CPU will be restored, and the hardware will clear SUSLO
register and IDL bit in PCON register. Then the program will perform the interrupt service routine first, and then jumps to the
instruction immediately following the instruction that activated Idle mode.
(2) Reset signal (logic low on the RESET pin, WDT RESET if enabled, LVR REST if enabled), this will restore the clock to the
CPU, the SUSLO register and the IDL bit in PCON register will be cleared by hardware, finally the SH79F642B will be reset.
And the program will perform from address 0000H. The RAM will keep unchanged and the SFR value might be changed
according to different function module.
8.10.1.2 Power-Down mode
The Power-Down mode places the SH79F642B in a very low power state. Power-Down mode will stop all the clocks including
CPU and peripherals. If WDT is enabled, WDT block will keep on working. When entering Power-Down mode, all the CPU
status before entering will be preserved. Such as: PSW, PC, SFR & RAM are all retained.
By two consecutive instructions: setting SUSLO register as 0x55, and immediately followed by setting the PD bit in PCON
register, will make SH79F642B enter Power-Down mode. If the consecutive instruction sequence requirement is not met, the
CPU will clear either SUSLO register or PD bit in the next machine cycle. And the CPU will not enter Power-Down mode.
The setting of PD bit will be the last instruction that CPU performed.
Note: If IDL bit and PD bit are set simultaneously, the SH79F642B enters Power-Down mode. The CPU will not go in Idle mode
when exiting from Power-Down mode, and the hardware will clear both IDL & PD bit after exit form Power-Down mode.
There are two ways to exit the Power-Down mode:
(1) An active external Interrupt such as INT0, INT1, INT2 and INT3 and LPD Interrupt will make SH79F642B exit Power-Down
mode. The oscillator will start after interrupt happens, after warm-up time, the clocks to the CPU and peripheral will be
restored, the SUSLO register and PD bit in PCON register will be cleared by hardware. Program execution resumes with the
interrupt service routine. After completion of the interrupt service routine, program execution resumes with the instruction
immediately following the instruction that activated Power-Down mode.
(2) Reset signal (WDT RESET if enabled, LVR REST if enabled). This will restore the clock to the CPU after warm-up time, the
SUSLO register and the PD bit in PCON register will be cleared by hardware, finally the SH79F642B will be reset. And the
program will perform from address 0000H. The RAM will keep unchanged and the SFR value might be changed according
to different function module.
Note: In order to entering Idle/Power-Down, it is necessary to add 3 NOPs after setting IDL/PD bit in PCON.

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8.10.2 Power mode
Depending on the available power, corresponding to the two power modes: Normal Power Mode and Battery-powered Mode.
The power mode switchs automatically by the power management or under software control. Automatic switching function can
be disabled or enabled by adjusting registers. No matter the device is powered by the external power supply VDD or battery
supply, or both of them, SH79F642B can work properly anyway.

8.10.2.1 Normal power supply mode

Normal power supply mode of the power is provided by an external power source, while the battery does not work, which is the
main operation mode. Under normal power supply mode, all logic functions can run well and PLL clock is set to system clock.
Also, the Energy Metering works at the same time. The temperature register and battery voltage can start ADC sampling at a
fixed time. In normal power supply mode, it is effective to reduce power consumption when entering the idle mode and closing
ADC modules. Taking the needs of the brown-out detection into account, the LPD interrupt should be open.
Table 8.65 The Working Status of the Function Modules in Normal Power Mode
Mode
Normal Idle Power-Down
Function
CPU,EUART0 & 1 & 2,
Disabled Functions - CPU ADC, TIMER0 & 1 & 2,
PWM0 & 1
PLL, LCD, Energy Metering, PLL, LCD,
Functions controlled ADC, LPD, ADC, LPD, Energy Metering (Constant
by software EUART0 & 1 & 2 EUART0 & 1 & 2 Metering Mode), PLL, LCD, LPD
TIMER0 & 1 & 2, PWM0 & 1 TIMER0 & 1 & 2, PWM0 & 1
Functions controlled
WDT, LVR WDT, LVR WDT, LVR
by Code Option

Functions always work CPU, RTC, External Interrupt RTC, External Interrupt RTC, External Interrupt

8.10.2.2 Battery-powered
In battery-powered mode SH79F642B is supplied by battery, and external power supply is shut down. Other functions can be
controlled by software.
Table 8.66 The Working Status of the Function Modules In Battery Mode
Mode
Normal Idle Power-Down
Function
CPU,EUART0 & 1 & 2,
Disabled Functions - CPU ADC, TIMER0 & 1 & 2,
PWM0 & 1

PLL, LCD, Energy Metering, PLL, LCD,

ADC, LPD, ADC, LPD, Energy Metering (Constant
Functions controlled
EUART0 & 1&2 EUART0 & 1&2
by software Metering Mode)，PLL, LCD, LPD
TIMER0 & 1 & 2, TIMER0 & 1 & 2,
PWM0 & 1 PWM0 & 1

Functions controlled
WDT, LVR WDT, LVR WDT, LVR
by Code Option

Functions always work CPU, RTC, External Interrupt RTC, External Interrupt RTC, External Interrupt

8.10.2.3 Power Mode Switch

In the normal power supply mode, if the VIN pin voltage detection (allowed by LPD registers) is valid, and low-voltage detection
(LPD) has detected that the VIN pin voltage is below 1.2V, it would cause the LPD interrupt. If Low-voltage detection (LPD) has
detected that the VDD pin voltage is below 2.7V, and the device power supply switches to the battery power, it would enter the
battery-powered mode and cause LPD interrupt again.

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In normal power supply mode, if the VIN pin voltage detection function is invalid (disabled by LPD registers), and low-voltage
detection (LPD) has detected that the VDD pin voltage is below 2.7V, it would cause the LPD interrupt, and the device would
switch to the battery-powerred mode immediately.
In battery-powered mode, the VIN pin voltage detection function is invalid (disabled by LPD registers), and if low-voltage
detection (LPD) has detected that the VDD pin voltage is above 2.7V, the device would switch to normal power mode with
external power supply and generate the LPD interrupt request. If the VIN pin voltage detection (allowed by LPD registers) is
valid, and low-voltage detection (LPD) has detected that the VIN pin voltage is above 1.2V, it would cause the LPD interrupt
again.
Automatic switching function can be allowed or disabled by AUTOS (LPDCON.0). To ensure no misuse writings occur, like the
way entering power saving mode, it requires to write 55H to the power switching control register first, and then clear or set
AUTOS (LPDCON. 0). The instructions must be continuous, otherwise automatic switching function is invalid.
If the automatic switching function is disabled by AUTOS (LPDCON.0), the power mode switch can also be implemented by
software. To ensure no misuse writings occur, like the way entering power saving mode, it requires to write 55H to the power
switching control register first, and then to configure the power supply. Otherwise automatic switching function is invalid.

8.10.3 Register
Table 8.67 LPD control register
B3H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
LPDCON LPDEN FVIN LPDIF VOUTS FVDD LPDS - AUTOS
W/R W/R R W/R W/R R R - W/R
0 0
Reset value u u
1 0 0 0 0 -
（POR/WDT/LVR/PIN） 0 0
0 0

Bit Number Bit Mnemonic Description

LPD Enable bit
7 LPDEN 0: Disable lower power detection
1: Enable lower power detection
VIN pin voltage status flags
0: VIN pin voltage lower than 1.2V
6 FVIN
1: VIN pin voltage higher than 1.2V
If the code choose to disable the VIN voltage detection function, this flag is invalid
LPD interrupt flag
5 LPDIF 0: no LPD interrupt happen
1: LPD interrerupt happens
Power supply status
4 VOUTS 0: battery-powered to VOUT
1: External power supply to VOUT
VDD voltage state marker
3 FVDD 0: VDD voltage lower than 2.7V
1: VDD voltage higher than 2.7V
LPD interrupt source
2 LPDS 0: VDD voltage caused the interrupt
1: VIN pin voltage caused interrupt
Power supply automatically switch to allow
0 AUTOS 0: Allow the power supply automatically switches
1: Disable the power supply automatically switches

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Table 8.68 Power switching control register
E7H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PASLO PASLO.7 PASLO.6 PASLO.5 PASLO.4 PASLO.3 PASLO.2 PASLO.1 PASLO.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

This register is used to control power switching. Only consecutive instructions to modify the
LPD control register after writing 55H to PASLO enable the power supply status and
7-0 PASLO[7-0]
automatical power supply switching written control. Otherwise, in the next cycle PASLO will
be cleared by hardware, and AUTOS or VOUTS change back to the previous value.

Table 8.69 Power control register

87H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PCON SMOD SSTAT SSTAT1 SSTAT2 GF1 GF0 PD IDL
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

7 SMOD Baudrate Speed-up bit of EUART
6 SSTAT SCON[7:5] Function Selector
5 SSTAT1 SCON1[7:5] Function Selector
4 SSTAT2 SCON2[7:5] Function Selector
3-2 GF[1:0] General-purpose flag for software
Power-Down Mode control bit
1 PD 0: Cleared by hardware when an interrupt or reset occurs.
1: Set by software to activate the Power-Down mode.
Idle Mode control bit
0 IDL 0: Cleared by hardware when an interrupt or reset occurs.
1: Set by software to activate the Idle mode.

Table 8.70 Suspend Mode Control register

8EH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SUSLO SUSLO.7 SUSLO.6 SUSLO.5 SUSLO.4 SUSLO.3 SUSLO.2 SUSLO.1 SUSLO.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value
0 0 0 0 0 0 0 0
（POR/WDT/LVR/PIN）

Bit Number Bit Mnemonic Description

This register is used to control the CPU enter suspend mode (IDLE or Power-Down).
7-0 SUSLO[7-0] Only consecutive instructions like below will make CPU enter suspend mode. Other
wise either SUSLO, IDL or PD bit will be cleared by hardware in the next machine cycle.

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 SH79F642B
Program example:
IDLE_MODE:
MOV SUSLO, #55H
ORL PCON, #01H
NOP
NOP
NOP

POWERDOWN_MODE:
MOV SUSLO, #55H
ORL PCON, #02H
NOP
NOP
NOP

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 SH79F642B
8.11 Warm-up Timer
8.11.1 Features
 Built-in power on warm-up counter to eliminate unstable state of power on
 Built-in oscillator warm-up counter to eliminate unstable state when oscillation startup
SH79F642B has a built-in power warm-up counter; it is designed to eliminate unstable state after power on or to do some
internal initial operation such as read customer option etc.
SH79F642B has also a built-in oscillator warm-up counter, it is designed to eliminate unstable state when oscillator starts
oscillating in the following conditions: Power-on reset, Pin reset, LVR reset, Watchdog Reset and Wake up from Power-down
mode.
After power-on, SH79F642B will start power warm-up procedure first, and then oscillator warm-up procedure.
Table 8.71 Power Warm-up Time

Power On Reset/ Wakeup from

WDT Reset WDT Reset
Pin Reset/ Power-Down Mode
(Not in Power-Down Mode) (Wakeup from Power-Down Mode)
Low Voltage Reset (Only for interrupt)
OSC OSC OSC OSC
TPWRT TPWRT TPWRT TPWRT
Warm up Time Warm up Time Warm up Time Warm up Time

11ms YES 1000CKs None 1000CKs None 16CKs None

Table 8.75 Oscillator Warm-up Time Table

Oscillator type Warm-up time

32.768 kHz crystal 213 X Tosc

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8.12 Code Option

OP_WDT[7]:
0: disable watchdog (WDT) fuction（default）
1: enable watchdog (WDT) fuction

OP_WDTPD[6]:
0: disable watchdog fuction in Power-down mode
1: enable watchdog fuction in Power-down mode

OP_WDTSIDL[5]:
0: disable watchdog fuction in Super-IDLE mode
1: enable watchdog fuction in Super-IDLE mode

OP_LVREN[4]
0: disable Low Voltage Reset (LVR) fuction（default）
1: enable Low Voltage Reset (LVR) fuction

OP_RST[3]
0: P2.0 as RST pin（default）
1: P2.0 as I/O pin

OP_VIN[2]
0: P2.3 as VIN pin （default）, VIN pin voltage detection function is enabled
1: P2.3 as I/O pin or AN0, VIN pin voltage detection function is disabled

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9. Energy Metering
9.1 Features
SH79F642 provides all the features that single-phase energy metering needed, including active power and active energy,
reactive power and reactive power, apparent power and apparent energy, voltage/ current RMS and frequency calculation to
support flexible anti-tampering program and calibration program.
 Active energy error less than 0.1% in the dynamic range of 2000:1.
 Reactive energy error less than 0.5% in the dynamic range of 1000:1.
 Voltage/ Current RMS
 Voltage frequency measurement
 Pulse output PF/QF
 Zero-corss and voltage sag interrupt detection
 Supports software control pulse output
 Supports single phase, 3 wire service
SH79F642 energy metering unit (EMU) is composed of the analog front-end (AFE) and digital signal processor (DSP). The
analog front-end acquisition two current signal and one voltage signal, the digital signal processor to complete the metering
function of the active power and active energy, reactive power and reactive energy, voltage rms, current rms and frequency
calculation. By the SFR registers and interrupt mode, the digital signal processing part can config calibration parameters and
read metering parameters.The PF/QF pin output the result of metering (Calibration pulse output) can be connected directly to
the standard meter to contrast error. EMU clock isselectable.

9.2 Analog Front End (AFE)

SH79F642 analog front end includes three analog gain amplifier (PGA), three Σ-Δ analog-to-digital converter (ADC) and a
reference voltage (VREF). The analog front end collects and quantifies the voltage and current signal.

9.2.1 Analog Gain Amplifier(PGA)

The analog gain amplifier completes to amplify the amplitude of the input differential signal, then the signal be sent to ADC after
the multiplexer to ensure the linearity of the measurement when the minimal signal input. The magnification of 1,2,4,8,16 of the
three PGA can be configured independently through the register. The maximum of the input signal is ±0.4V when the
magfication is 1, ±0.2V when the magfication is 2, ±0.01V when the magfication is 4, and ±0.05V when the magfication is 8.
Three PGA input differential signals corresponding to the three-way, respectively, two current signals and one voltage signal.

9.2.2 Analog-to-Digital Converter (ADC)

SH79F642 have 23bits sigma-delta ADC, quantized voltage and current input.
The indirect register I1DTA, I2DTA and VDTA store two-channel current and one channel voltage ADC output value,and update
frequency is EMUCLK( = ½ PLL )/1024,For example,when EMCUCLK=4KHz,the sample data updata rate is 4000.

9.2.3 Reference Voltage (VREF)

ADC embedded high precision bandgap reference voltage, the ADC voltage reference. Voltage value of 1.4V, the temperature
coefficient of ± 25ppm / ℃

9.3 Digital Signal Processor (DSP)

Digital signal processor accept the voltage and current quantized value of FIR output, and implement the digital signal
processing, to get the energy data such as active energy, reactive power, voltage and current rms and output pulse of active
and reactive power.

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9.4 Register
EMU, including two types of registers, one is SFR registers, the direct register, accessed by SFR address directly; the other is
metering parameters and calibration parameter register, indirect register, indirectly accessed by direct register

9.4.1 SFR Register

Table 9.1 EMU SFR register list
Addresss Name Description
D1H EADR EMU Address Register
D2H EDTAH EMU High Byte Data Register
D3H EDTAM EMU Mid Byte Data Register
D4H EDTAL EMU Low Byte Data Register
D5H EMUSR EMU Status/ Control Register
D6H EMUIE EMU Interrupt Enable Register
D7H EMUIF EMU Interrupt Flag Register

Table 9.2 EMU Address Register

D1H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
EADR RW EADR.6 EADR.5 EADR.4 EADR.3 EADR.2 EADR.1 EADR.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value
0 0 0 0 0 0 0 0
(POR/WDT/LVR/PIN)

Bit Number Bit Mnemonic Description

EMU Indirect RegisterRead/ Write Flag
7 RW 0：Read EMU indirect register
1：Write EMU indirect register
6-0 EADR[6:0] EMU Address Register

Table 9.3 EMU High Byte Register

D2H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
EDTAH EDTAH.7 EDTAH.6 EDTAH.5 EDTAH.4 EDTAH.3 EDTAH.2 EDTAH.1 EDTAH.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value
0 0 0 0 0 0 0 0
(POR/WDT/LVR/PIN)

Bit Number Bit Mnemonic Description

7-0 EDTAH[7:0] EMU High Byte Data Register

Table 9.4 EMU Mid Byte Register

D3H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
EDTAM EDTAM.7 EDTAM.6 EDTAM.5 EDTAM.4 EDTAM.3 EDTAM.2 EDTAM.1 EDTAM.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R

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Reset value
0 0 0 0 0 0 0 0
(POR/WDT/LVR/PIN)

Bit Number Bit Mnemonic Description

7-0 EDTAM[7:0] EMU Mid Byte Data Register

Table 9.5 EMU Low Byte Register

D4H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
EDTAL EDTAL.7 EDTAL.6 EDTAL.5 EDTAL.4 EDTAL.3 EDTAL.2 EDTAL.1 EDTAL.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value
0 0 0 0 0 0 0 0
(POR/WDT/LVR/PIN)

Bit Number Bit Mnemonic Description

7-0 EDTAL[7:0] EMU Low Byte Data Register

Table 9.6 EMU Status/ Control Register

D5H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
EMUSR DSPEN EMUCLK1 EMUCLK0 SAGF NoQLd NoPLd REVQ REVP
W/R W/R W/R W/R W/R W/R W/R W/R W/R
0 1 1 0 0 0 0 0
Reset value u u u u u u u u
(POR/WDT/LVR/PIN) 0 1 1 0 0 0 0 0
0 1 1 0 0 0 0 0

Bit Number Bit Mnemonic Description

DSP Gate
7 DSPEN 0：Disable
1：enable
EMU Clock Select
00: PLL/2
6-5 EMUCLK[1:0] 01: PLL/4
10: PLL/8
11: PLL/16
Reactive Power no load Flag
3 NoQLd 0：Reactive power is greater than or equal to the startup power
1：Reactive power is less than the startup power
Active Power no load Flag
2 NoPLd 0：Active power is greater than or equal to the startup power
1：Active power is less than the startup power
Reverse Reactive Energy Flag
1 REVQ 0：Positive reactive energy
1：Negative reactive energy
Reverse Active Energy Flag
0 REVP 0：Positive active energy
1：Negative active energy
NOTE:
When DSPEN = 0, clear power and RMS’s calculate register, except the parameters configuration and energy
accumulation register.

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9.4.2 Indirect Register
The indirect registers include metering parameter registers and calibration parameter registers
All metering parameter registers are read-only but FREQ which can only be read by the EADR EDTAH / EDTAM / EDTAL
register indirect
1. EDTAH / EDTAM / EDTAL are stored 3 bytes of high, mid, low byte data if the metering parameter register is a 3-byte
register.
2. EDTAM / EDTAL are stored 2 bytes of mid, low byte data, and EDTAH is sign-extension bit of EDTM.7, if the metering
parameter register is a 2-byte register
Operating rules of metering parameters: first,write the accessed register address to EADR, read/ write flag is 0, then the
metering data of corresponding address update to the SFR registers EDTAH / EDTAM / EDTAL,finally, access EDTAH /
EDTAM / EDTAL register
As the same, calibration parameter configuration registers are read through the EADR EDTAM / EDTAL register indirectly,
but EDTAH register invalid
1. EDTAM and EDTAL are high and low bytes data of calibration parameter configuration register, if the parameter
configuration register is a 2-byte register.
2. EDTAL is the data of calibration parameter configuration register and EDTAM data is invalid, if the parameter
configuration register is a single-byte register.
Operating rules of calibration parameters
1. To access parameter configuration registers, first, write the accessed register address to EADR, read/ write flag is 0,
then the calibration parameter data of corresponding address update to the SFR registers EDTAM / EDTAL, finally, access
EDTAM / EDTAL register.
2. To write the calibration parameter configuration registers, first, write data to EDTAM / EDTAL, then, write the accessed
register address to EADR, read/ write flag is 1, then, the data of EDTAM / EDTAL registers update to calibration parameter
configuration registers of corresponding address.
Note: As the internal of EMU indirect register using a separate mechanism to read and writ, except this order, several NOP
need to be inserted after the EADR register read and write commands, then operate EDATH, EDATM, EDATL, more than 3
NOP need to be inserted when the system clock is 8.192MHz.
Metering Parameter Register
Table 9.7 EMU Metering Parameter Register list
Addresss Name Length Description
00H I1DTA 3 ADC output value of current channel 1
01H I2DTA 3 ADC output value of current channel 2
02H VDTA 3 ADC output value of voltage channel
03H APWR1 3 Active power value channel 1
04H RPWR1 3 Reactive power value channel 1
05H APWR2 3 Active power value channel 2
06H RPWR2 3 Reactive power value channel 2
07H AERY 3 Active energy value(CmodeFreq[2]=0)
08H RERY 3 Reactive energy value(CmodeFreq[2]=0)
09H FREQ 2 Voltage frequency value
0AH I1Rms 3 Current rms of channel 1
0BH I2Rms 3 Current rms of channel 2
0CH VRMS 3 Voltage rms

Active energy pulse accumulated value

0DH WPA 3
(CmodeFreq[2]=0)

Reactive energy pulse accumulated value

0EH VARPA 3
(CmodeFreq[2]=0)

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 SH79F642B
0FH APWRA1 3 Active power average value of channel 1
10H RPWRA1 3 Reactive power average value of channel 1
11H APWRA2 3 Active power average value of channel 2
12H RPWRA2 3 Reactive power average value of channel 2
13H AERYL 3 Active energy low value (CmodeFreq[2]=0)
14H RERYL 3 Reactive energy low value (CmodeFreq[2]=0)

15H VDTAMAX 3 MAX ADC sampling value of voltage channel

Active energy accumulated value (high) in CONST mode
16H AERY_CONSTH 3
(CmodeFreq[2]=1)
Reactive energy accumulated value (high) in CONST
17H RERY_CONSTH 3
mode (CmodeFreq[2]=1)
Active energy accumulated value (low) in CONST mode
18H AERY_CONSTL 3
(CmodeFreq[2]=1)
Reactive energy accumulated value (low) in CONST
19H RERY_CONSTL 3
mode (CmodeFreq[2]=1)
Active energy pulse accumulated value in CONST mode
1AH WPA_CONST 3
(CmodeFreq[2]=1)
Reactive energy pulse accumulated value in CONST
1BH 3
VARPA_CONST mode (CmodeFreq[2]=1)

Table 9.8 ADC Output of Current Channel 1

00H Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
I1DTA I1DTA.23 I1DTA.22 I1DTA.21 I1DTA.20…3 I1DTA.2 I1DTA.1 I1DTA.0
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

ADC output value of current channel 1, the binary complement means a signed
23-0 I1DTA[23:0]
value

Table 9.9 ADC Output of Current Channel 2

01H Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
I2DTA I2DTA.23 I2DTA.22 I2DTA.21 I2DTA.20…3 I2DTA.2 I2DTA.1 I2DTA.0
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

ADC output value of current channel 2, the binary complement means a signed
23-0 I2DTA[23:0]
value

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Table 9.10 ADC Output of Voltage Channel
02H Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
VDTA VDTA.23 VDTA.22 VDTA.21 VDTA.20…3 VDTA.2 VDTA.1 VDTA.0
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

ADC output value of voltage channel, the binary complement means a signed
23-0 VDTA[23:0]
value

Table 9.11 Active Power Value Channel 1 Register

03H Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
APWR1 APWR1.23 APWR1.22 APWR1.21 APWR1.20… APWR1.2 APWR1.1 APWR1.0
3
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

Active power value, the binary complement means a signed value ;
23-0 APWR[23:0] Note:The positive number is active power of positive;Negative represent active power
negative.

Table 9.12 Reactive Power Value Channel 1 Register

04H Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
RPWR1.
RPWR1 RPWR1.23 RPWR1.22 RPWR1.21 RPWR1.2 RPWR1.1 RPWR1.0
20…3
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

Reactive power value, the binary complement means a signed value ;
23-0 RPWR[23:0] Note: The negative number is reactive power of positive ; Positive represent reactive
power of negative.

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 SH79F642B
Table 9.13 Active Power Value Channel 2 Register
05H Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
APWR2 APWR2.23 APWR2.22 APWR2.21 APWR2.20… APWR2.2 APWR2.1 APWR2.0
3
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

Active power value, the binary complement means a signed value ;
23-0 APWR[23:0] Note:The positive number is active power of positive;Negative represent active power
negative.

Table 9.14 Reactive Power Value Channel 2 Register

06H Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
RPWR2.
RPWR2 RPWR2.23 RPWR2.22 RPWR2.21 RPWR2.2 RPWR2.1 RPWR2.0
20…3
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

Reactive power value, the binary complement means a signed value ;
23-0 RPWR[23:0] Note: The negative number is reactive power of positive ; Positive represent reactive
power of negative.

Table 9.15 Active Energy Register (CmodeFreq[2]=0)

07H Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
AERY AERY.23 AERY.22 AERY.21 AERY.20…3 AERY.2 AERY.1 AERY.0
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

Active energy value, the binary complement means a signed value
23-0 AERY[23:0] Note:The positive number is active power of positive;Negative represent active power
negative.

Table 9.16 Reactive Energy Register (CmodeFreq[2]=0)

08H Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
RERY RERY.23 RERY.22 RERY.21 RERY.20…3 RERY.2 RERY.1 RERY.0

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 SH79F642B
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

Reactive energy value, the binary complement means a signed value
23-0 RERY[23:0] Note: The negative number is reactive power of positive ; Positive represent reactive
power of negative.

Table 9.17 Voltage Frequence Register

09H Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
FREQ FREQ.15 FREQ.14 FREQ.13 FREQ.12…3 FREQ.2 FREQ.1 FREQ.0
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

15-0 FREQ[15:0] Voltage frequency, unsigned value, reset value 00H
The frequency value is a 16 bit unsigned number, got through the zero count way,.Update cycle less than 1 second,
precision 0.01Hz ( 40Hz ~ 70Hz ).Parameter format formula: f = 4000/FREQ.
Table 9.18 I1 RMS Register
0AH Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
I1Rms I1Rms.23 I1Rms.22 I1Rms.21 I1Rms.20…3 I1Rms.2 I1Rms.1 I1Rms.0
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

23-0 I1Rms[23:0] Current rms of channel 1, unsigned value

Table 9.19 I2 RMS Register

0BH Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
I2Rms I2Rms.23 I2Rms.22 I2Rms.21 I2Rms.20…3 I2Rms.2 I2Rms.1 I2Rms.0
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

23-0 I2Rms[23:0] Current rms of channel 2, unsigned value

Table 9.20 Voltage RMS Register

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0CH Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
VRMS VRMS.23 VRMS.22 VRMS.21 VRMS.20…3 VRMS.2 VRMS.1 VRMS.0
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

23-0 VRMS[23:0] Voltage rms, unsigned value
Voltage/ current rms update frequence is set by SUMSAMPS register.
Table 9.21 Active Energy Pulse Accumulated Register
0DH Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
WPA WPA.23 WPA.22 WPA.21 WPA.20…3 WPA.2 WPA.1 WPA.0
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

23-0 WPA[23:0] Active energy pulse accumulated value, unsigned value

Table 9.22 Reactive Energy Pulse Accumulated Register

0EH Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
VARPA VARPA.23 VARPA.22 VARPA.21 VARPA.20…3 VARPA.2 VARPA.1 VARPA.0
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

23-0 VARPA[23:0] Reactive energy pulse accumulated value, unsigned value

Table 9.23 Active power average value of channel 1

0FH Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
APWRA1 APWRA1.23 APWRA1.22 APWRA1.21 APWRA1.20 APWRA1.2 APWRA1.1 APWRA1.0
3
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

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 SH79F642B
Active power average value of channel 1，the binary complement means a signed
23-0 APWR1[23:0] value，the cycle of measurement is set by SUMSAMPS.
Note:The positive number is active power of positive;Negative represent active power
negative.

Table 9.24 Reactive power average value of channel 2

10H Bit23 Bit22 Bit21
Bit20~Bit3 Bit2 Bit1 Bit0
RPWRA1 RPWRA1.23 RPWRA1.22 RPWRA1.21 RPWRA1.20 RPWRA1.2 RPWRA1.1 RPWRA1.0
3
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

Reactive power average value of channel 1，the binary complement means a
23-0 RPWR1[23:0] signed value，the cycle of measurement is set by SUMSAMPS.
Note:The positive number is reactive power of negative;Negative represent reactive
power positive.

Table 9.25 Active power average value of channel 2

11H Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
APWRA2 APWR2.23 APWR2.22 APWR2.21 APWR2.20…3 APWR2.2 APWR2.1 APWR2.0
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

Active power average value of channel 2，the binary complement means a signed
23-0 APWR2[23:0] value，the cycle of measurement is set by SUMSAMPS.
Note:The positive number is active power of positive;Negative represent active power
negative.

Table 9.26 Reactive power average value of channel 2

12H Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
RPWRA2 RPWRA2.23 RPWRA2.22 RPWRA2.21 RPWRA2.20…3 RPWRA2.2 RPWRA2.1 RPWRA2.0
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

Reactive power average value of channel 2，the binary complement means a
23-0 RPWR2[23:0] signed value，the cycle of measurement is set by SUMSAMPS.
Note:The positive number is reactive power of negative;Negative represent reactive
power positive.

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 SH79F642B
Table 9.27 Active energy low value (CmodeFreq[2]=0)
13H Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
AERYL AERYL.23 AERYL.22 AERYL.21 AERYL.20…3 AERYL.2 AERYL.1 AERYL.0
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

23-0 AERYL[23:0] Active energy low value，low 24 bit.
Table 9.28 Reactive energy low value (CmodeFreq[2]=0)
14H Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
RERYL RERYL.23 RERYL.22 RERYL.21 RERYL.20…3 RERYL.2 RERYL.1 RERYL.0
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

23-0 RERYL[23:0] Reactive energy low value，low 24 bit.

Table 9.29 MAX ADC sampling value of voltage channel

15H Bit23 Bit22 Bit21Bit20~Bit3 Bit2 Bit1 Bit0
VDMAX VDMAX.23 VDMAX.22 VDMAX.21 VDMAX.20… VDMAX.2 VDMAX.1 VDMAX.0
3
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

MAX ADC sampling value of voltage channel，the cycle of measurement is set by
23-0 VDMAX [23:0]
SUMSAMPS, signed value.

Table 9.30 Active energy accumulated value (high) in CONST mode (CmodeFreq[2]=1)
16H Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
AERY_CONS AERY_CONS AERY_CONS AERY_CONS AERY_CONS AERY_CONS AERY_CONS
AERY_CONSTH
TH.23 TH.22 TH.21 TH.20…3 TH.2 TH.1 TH.0
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

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 SH79F642B
Bit Number Bit Mnemonic Description
Active energy accumulated value (high) in CONST mode，the binary
23-0 AERY_CONSTH[23:0]
complement means a signed value

Table 9.31 Reactive energy accumulated value (high) in CONST mode (CmodeFreq[2]=1)
17H Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
RERY_CON RERY_CON RERY_CON RERY_CON RERY_CON RERY_CON RERY_CON
RERY_CONSTH
STH.23 STH.22 STH.21 STH.20…3 STH.2 STH.1 STH.0
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

Reactive energy accumulated value (high) in CONST mode，the binary
23-0 RERY_CONSTH[23:0]
complement means a signed value

Table 9.32 Active energy accumulated value (low) in CONST mode (CmodeFreq[2]=1)
18H Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
AERY_CONS AERY_CONS AERY_CONS AERY_CONS AERY_CONS AERY_CONS AERY_CONS
AERY_CONSTL
TL.23 TL.22 TL.21 TL.20…3 TL.2 TL.1 TL.0
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

AERY_CONSTH[23:0] Active energy accumulated value (low) in CONST mode， the binary
23-0
complement means a signed value

Table 9.33 Reactive energy accumulated value (low) in CONST mode (CmodeFreq[2]=1)
19H Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
RERY_CON RERY_CON RERY_CON RERY_CON RERY_CON RERY_CON RERY_CON
RERY_CONSTL
STL.23 STL.22 STL.21 STL.20…3 STL.2 STL.1 STL.0
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

RERY_CONSTL[23:0] Reactive energy accumulated value (low) in CONST mode，the binary
23-0
complement means a signed value

124
 SH79F642B
Table 9.34 Active energy pulse accumulated value in CONST mode (CmodeFreq[2]=1)
1AH Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
WPA_CONS WPA_CONS WPA_CONS WPA_CONS WPA_CONS WPA_CONS WPA_CONS
WPA_CONST
T.23 T.22 T.21 T.20…3 T.2 T.1 T.0
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

23-0 WPA_CONST[23:0] Active energy pulse accumulated value in CONST mode，unsigned value

Table 9.35 Reactive energy pulse accumulated value in CONST mode (CmodeFreq[2]=1)
19H Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
VARPA_CON VARPA_CON VARPA_CON VARPA_CON VARPA_CON VARPA_CON VARPA_CON
VARPA_CONST
ST.23 ST.22 ST.21 ST.20…3 ST.2 ST.1 ST.0
W/R R R R R R R R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

VARPA_CONST[23:0] Reactive energy pulse accumulated value in CONST mode，unsigned
23-0
value

125
 SH79F642B

Calibration Parameter Register

Table 9.36 EMU calibration parameter register list
Addresss Name Length Description
30H EMUCFG0 2 EMU configuration parameter register 0
31H EMUCFG1 3 EMU configuration parameter register 1
32H EMUCFG2 3 EMU configuration parameter register 2
33H EMUCFG3 2 EMU configuration parameter register 3
34H W1GAIN 2 Active power gain of channel 1 (active & reactive)
35H P1CAL 2 Current phase compensation of channel 1
36H W2GAIN 2 Active power gain of channel 2 (active & reactive)
37H P2CAL 2 Current phase compensation of channel 2
38H I2GAIN 2 Current gain of channel 2
39H WATT1OS 2 Active power offset of Channel 1
3AH WATT2OS 2 Active power offset of Channel 2
3BH VAR1OS 2 Reactive power offset of Channel 1
3CH VAR2OS 2 Reactive power offset of Channel 2
3DH IRMS1OS 3 Current RMS offset of Channel 1
3EH IRMS2OS 3 Current RMS offset of Channel 2
3FH VRMSOS 3 Voltage RMS offset
40H ADCOSI1 2 ADC offset of current channel 1
41H ADCOSI2 2 ADC offset of current channel 2
42H ADCOSU 2 ADC offset of voltage channel
43H SPTS 2 Configuration for power startup
44H VCONST 3 Voltage constant
45H SAGTHR 2 Threshold configuration for voltage sag
46H SAGCNT 2 Sampling count for voltage sag
47H ICONT 2 Configuration for output pulse frequency
Fast active pulse counting, the binary complement means a
48H PCNT 2
signed value (CmodeFreq[2]=0).
Fast reactive pulse counting, the binary complement means a
49H QCNT 2
signed value (CmodeFreq[2]=0).
4AH SUMSAMPS 2 Calculate cycle
4BH APCONST 3 Active power const
4CH RPCONST 3 Reactive power const
Fast active pulse couner, the binary complement means a
4DH PCNT_CONST 2
signed value (CmodeFreq[2]=1).
Fast reactive pulse counter, the binary complement means a
4EH QCNT_CONST 2
signed value (CmodeFreq[2]=1).
51H RESERVE 3 Software clear this register necessory

Table 9.37 EMU configuration parameter register 0:

30H Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
EMUCFG0 - - - - - - APGAU1 APGAU0
W/R - - - - - - W/R W/R
Reset value 0 0
u u
（POR/WDT/LVR/ - - - - - -
0 0
PIN）
0 0
30H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ADCSHO
EMUCFG0 APGAI21 APGAI20 APGAI11 APGAI10 ADCUON ADCI2ON ADCI1ON
RT
W/R W/R W/R W/R W/R W/R W/R W/R W/R

126
 SH79F642B
Reset value 0 0 0 0 0 0 0 0
u u u u u u u u
（POR/WDT/LVR/
0 0 0 0 0 0 0 0
PIN）
0 0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

Gain of analog PGA of voltage channel 1
00: 1X gain
9-8 APGAU[1:0]
01: 2X gain
1X: 4X gain
Gain of analog PGA of current channel 2
00: 1X gain
7-6 APGAI2[1:0] 01: 4X gain
10: 8X gain
11: 16X gain
Gain of analog PGA of current channel 1
00: 1X gain
5-4 APGAI1[1:0] 01: 4X gain
10: 8X gain
11: 16X gain
Short control of ADC internal input
3 ADCSHORT 0: ADC input no short
1: ADC input short
ADC enable control of channel voltage
2 ADCUON 0: Stop ADC
1: Start ADC
ADC enable control of channel current 2
1 ADCI2ON 0: Stop ADC
1: Start ADC
ADC enable control of channel current 1
0 ADCI1ON 0: Stop ADC
1: Start ADC

Bit Number Bit Mnemonic Description

EMU configuration parameter register 0, Typical value is 0x000037. If there is more than
15-0 EMUCFG0[15-0]
1 ADC need to configurate, check the application manual.

Table 9.38 EMU configuration parameter register 1:

31H Bit23 Bit22 Bit21 Bit20 Bit19 Bit18 Bit17 Bit16
EMUCFG1 - - POL MNL - HPFONU HPFONI2 HPFONI1
W/R - - W/R W/R - W/R W/R W/R
Reset value 0 0 0 0 0
u u u u u
（POR/WDT/LVR/ - - -
0 0 0 0 0
PIN）
0 0 0 0 0
31H Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
EMUCFG1 PWidth1 PWidth0 PFAST1 PFAST0 QMOD1 QMOD0 PMOD1 PMOD0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value 0 0 0 0 0 0 0 0
u u u u u u u u
（POR/WDT/LVR/
0 0 0 0 0 0 0 0
PIN）
0 0 0 0 0 0 0 0
31H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

127
 SH79F642B
CmodeFre CmodeFre CmodeFre ConstMod
EMUCFG1 QRUN PRUN PWRSEL1 PWRSEL0
q2 q1 q0 e
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value 0 0 0 0 0 0 0 0
u u u u u u u u
（POR/WDT/LVR/
0 0 0 0 0 0 0 0
PIN）
0 0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

21 POL PF/QF output polarity control
0: High level is the active level( CONST mode can not choose this one )
1: Low level is the active level
Off Neutral Wire Mode enable mode
0: Disable Off Neutral Wire Mode (init)
20 MNL
1: Enable Off Neutral Wire Mode. Use the value in VCONST register ( instead of
Voltage RMS ) to calculate active/reactive power value.
High-pass filter select of channel voltage
18 HPFONU 0: Open High-pass filter (init)
1: Close High-pass filter
High-pass filter select of channel current 2
17 HPFONI2 0: Open High-pass filter
1: Close High-pass filter
High-pass filter select of channel current 1
16 HPFONI1 0: Open High-pass filter
1: Close High-pass filter
Output pulse width ( be care of the effect of clock switch )
00: 90ms(+/-5%)(init)
15-14 PWidth[1:0] 01: 45ms(+/-5%)
10: reserve
11: 11ms(+/-5%)
Small-signal pulse speed up
00: 1X
13-12 PFAST[1:0] 01: 4X
10: 8X
11: 16X
Reactive Power Accumulation Method
00: Driect accumulate
11-10 QMOD[1:0] 01: Accumulate the positive only
10: Accumulate the absolute value
11: Driect accumulate
Active power accumulation method
00: Driect accumulate
9-8 PMOD[1:0] 01: Accumulate the positive only
10: Accumulate the absolute value
11: Driect accumulate
Reactive Energy Accumulation Enable
7 QRUN 0: Disable
1: Enable
Active Energy Accumulation Enable
6 PRUN 0: Disable
1: Enable
Metering Source Channel Select
00: Channel1
5-4 PWRSEL[1:0] 01: Channel 2
10: Sum of channel 1 & 2
11: Sum of absolute value of channel 1 & 2

128
 SH79F642B
Accumulation Clock Frequency and Accumulation Data source select
000: Accumulation Clock Frequency: 2 X update frequency, accumulation data source:
instant power value ( selected by PWMSEL[1:0])
001: Accumulation Clock Frequency: 4 X update frequency, accumulation data source:
instant power value ( selected by PWMSEL[1:0])
010: Accumulation Clock Frequency: 8 X update frequency, accumulation data source:
instant power value ( selected by PWMSEL[1:0])
011: Accumulation Clock Frequency: 16 X update frequency, accumulation data
3-1 CmodeFreq[2:0] source: instant power value ( selected by PWMSEL[1:0])
100: Accumulation Clock Frequency: 32.768KHz, accumulation data source:
PCONST/RPCONST
101: Accumulation Clock Frequency: 8.192KHz, accumulation data source:
PCONST/RPCONST
110: Accumulation Clock Frequency: 4.096KHz, accumulation data source:
PCONST/RPCONST
111: Accumulation Clock Frequency: 1.024KHz, accumulation data source:
PCONST/RPCONST
Accumulation Module Enable
0 Cmodeen 0: Disable (init)
1: Enable

Bit Number Bit Mnemonic Description

23-0 EMUCFG1[23-0] EMU calibration parameter register 1，Typical value is 0x0000c1
NOTE：update frequency is set by EMUCLK[1:0] of EMUSR.
Table 9.39 EMU configuration parameter register 2:
32H Bit23 Bit22 Bit21 Bit20 Bit19 Bit18 Bit17 Bit16
PGACH PGACH PGACH
EMUCFG2 OPCKSE OPCKS OPCKS APGAUI.2 APGAUI.1 APGAUI.0 APGAI2I.2 APGAI2I.1
L.2 EL.1 EL.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value 0 0 1 1 1 1 1 1
u u u u u u u u
（POR/WDT/LVR
0 0 1 1 1 1 1 1
/PIN）
0 0 1 1 1 1 1 1
32H Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
APGAI2I. APGAI1I APGAI1I
EMUCFG2 APGAI1I.0 ADCUI.3 ADCUI.2 ADCUI.1 ADCUI.0
0 .2 .1
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value 1 1 1 1 0 0 1 1
u u u u u u u u
（POR/WDT/LVR
1 1 1 1 0 0 1 1
/PIN）
1 1 1 1 0 0 1 1
31H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
EMUCFG2 ADCI1.3 ADCI1.2 ADCI1.1 ADCI1.0 ADCI2.3 ADCI2.2 ADCI2.1 ADCI2.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value 0 0 1 1 0 0 1 1
u u u u u u u u
（POR/WDT/LVR
0 0 1 1 0 0 1 1
/PIN）
0 0 1 1 0 0 1 1

Bit Number Bit Mnemonic Description

129
 SH79F642B
PGA’S Chop Clock Select
000:2K
001:4K
010:8K
23-21 PGACHOPCKSEL[2:0] 011:16K
100:32K
101:64K
others:no clock
20-18 APGAUI[2:0] ADC bias current adjust of voltage channel
17-15 APGAI2I[2:0] ADC bias current adjust of current channel 1
14-12 APGAI1I[2:0] ADC bias current adjust of current channel 2
11-8 ADCUI[3:0] PGA bias current adjust of voltage channel
7-4 ADCI1[3:0] PGA bias current adjust of current channel 1
3-0 ADCI2[3:0] PGA bias current adjust of current channel 2

Bit Number Bit Mnemonic Description

EMU configuration parameter register 2 ， Typical value is 0x9FF333 ， low-power
23-0 EMUCFG2[23-0]
dissipation value is 0x400888

Table 9.40 EMU configuration parameter register 3:

33H Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
EMUCFG3 - - - - - - - PD_BG
W/R - - - - - - - W/R
Reset value 1
u
（POR/WDT/LVR/ - - - - - - -
1
PIN）
1
33H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
BG_CHO BG_CHO BG_DEM
EN_BG_ EN_BG_ BG_DEMC BG_CUR BG_CUR
EMUCFG3 PCK_SEL PCK_SEL CK_SEL.
CHOP DEM K_SEL.1 _SEL.1 _SEL.0
.1 .0 0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value 1 1 1 0 1 0 0 0
u u u u u u u u
（POR/WDT/LVR/
1 1 1 0 1 0 0 0
PIN） 1 1 1 0 1 0 0 0

Bit Number Bit Mnemonic Description

VREF- Status Enable Control
8 PD_BG =0 Enable;
=1,Disable
VREF CHOP Clock Enable Control
7 EN_BG_CHOP =0 Disable;
=1,Enable
VREF current mirror clock Enable Control
6 EN_BG_DEM =0 Disable;
=1,Enable
VREF CHOP clock select
5-4 BG_CHOPCK_SEL[1:0]
00:4K,01:8K,10:16K,11:32K
VREFcurrent mirror clock select
3-2 BG_DEMCK_SEL[1:0]
00:4K,01:8K,10:16K,11:32K
1-0 BG_CUR_SEL[1:0] Current mirror current select

Bit Number Bit Mnemonic Description

130
 SH79F642B
15-0 EMUCFG3[15-0] EMU configuration parameter register 3. Typical value is 0x00E8

Table 9.41 Channel 1 Active Power Gain Register

34H Bit15 Bit14 Bit13 Bit12~Bit3 Bit2 Bit1 Bit0
W1GAIN W1GAIN.15 W1GAIN.14 W1GAIN.13 W1GAIN.12…3 W1GAIN.2 W1GAIN.1 W1GAIN.0
W/R W/R W/R W/R W/R W/R W/R W/R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

15-0 W1GAIN[15:0] Active power gain of channel 1, the binary complement means a signed value
The 15 bit is sign bit.

Table 9.42 Channel 1 Current Phase Compensation Register

35H Bit15 Bit14 Bit13 Bit12~Bit3 Bit2 Bit1 Bit0
P1CAL P1CAL.15 P1CAL.14 P1CAL.13 P1CAL.12…3 P1CAL.2 P1CAL.1 P1CAL.0
W/R W/R W/R W/R W/R W/R W/R W/R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

Current phase compensation of channel 1, the binary complement means a
15-0 P1CAL[15:0]
signed value
Table 9.43 Channel 2 Active Power Gain Register
36H Bit15 Bit14 Bit13 Bit12~Bit3 Bit2 Bit1 Bit0
W2GAIN W2GAIN.15 W2GAIN.14 W2GAIN.13 W2GAIN.12…3 W2GAIN.2 W2GAIN.1 W2GAIN.0
W/R W/R W/R W/R W/R W/R W/R W/R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

15-0 W2GAIN[15:0] Active power gain of channel 2, the binary complement means a signed value
The 15 bit is sign bit.

Table 9.44 Channel 2 Current Phase Compensation Register

37H Bit15 Bit14 Bit13 Bit12~Bit3 Bit2 Bit1 Bit0
P2CAL P2CAL.15 P2CAL.14 P2CAL.13 P2CAL.12…3 P2CAL.2 P2CAL.1 P2CAL.0
W/R W/R W/R W/R W/R W/R W/R W/R

131
 SH79F642B
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

Current phase compensation of channel 2, the binary complement means a
15-0 P2CAL[15:0]
signed value

phase compensation value: ± 215 − 1 ，The formula：

1.1667 ⋅ Err
PXCAL = round ( − × 215 ) (50Hz signal , Err >0)
0.07846 + 0.5825 ⋅ Err
1.1411 ⋅ Err
PXCAL = round (− × 215 ) (50Hz signal , Err <0)
0.07846 − 0.5697 ⋅ Err
or
1.1659 ⋅ Err
PXCAL = round ( − × 215 ) (60Hz signal , Err >0)
0.09411 + 0.5817 ⋅ Err
1.1403 ⋅ Err
PXCAL = round (− × 215 ) (60Hz signal , Err <0)
0.09411 − 0.5689 ⋅ Err

Table 9.45 Current Gain Configuration of Channel 2

38H Bit15 Bit14 Bit13 Bit12~Bit3 Bit2 Bit1 Bit0
I2GAIN I2GAIN.15 I2GAIN.14 I2GAIN.13 I2GAIN.12…3 I2GAIN.2 I2GAIN.1 I2GAIN.0
W/R W/R W/R W/R W/R W/R W/R W/R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

15-0 I2GAIN[15:0] Current gain of channel 2, the binary complement means a signed value
Comparing the current rms value of the two channels is needed at anti-tampering, so, the two current channel register
should be equal when the same current input, and this can be completed by current gain of channel 2 configuration register
I2GAIN. The current rms of channel 2 is the result of the calculated current rms of channel 2 multiplied by a coefficient (1 +
I2GAIN/2^16).
Table 9.46 Active power offset of Channel 1
39H Bit15 Bit14 Bit13 Bit12~Bit3 Bit2 Bit1 Bit0
WATT1OS W1OS.15 W1OS.14 W1OS.13 W1OS.12…3 W1OS.2 W1OS.1 W1OS.0
W/R W/R W/R W/R W/R W/R W/R W/R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

11-0 W1OS[11:0] Active power offset of Channel 1, the binary complement means a signed value

132
 SH79F642B
This register participate in the active power and energy calculation of channel 1.
Table 9.47 Active power offset of Channel 2
3AH Bit15 Bit14 Bit13 Bit12~Bit3 Bit2 Bit1 Bit0
WATT2OS W2OS.15 W2OS.14 W2OS.13 W2OS.12…3 W2OS.2 W2OS.1 W2OS.0
W/R W/R W/R W/R W/R W/R W/R W/R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

11-0 W2OS[11:0] Active power offset of Channel 2, the binary complement means a signed value
This register participate in the active power and energy calculation of channel 2.

Table 9.48 Reactive power offset of Channel 1

3BH Bit15 Bit14 Bit13 Bit12~Bit3 Bit2 Bit1 Bit0
VAR1OS VAR1OS.15 VAR1OS.14 VAR1OS.13 VAR1OS.12…3 VAR1OS.2 VAR1OS.1 VAR1OS.0
W/R W/R W/R W/R W/R W/R W/R W/R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

11-0 VAR1OS[11:0] Reactive power offset of Channel 1, the binary complement means a signed value
This register participate in the reactive power and energy calculation of channel 1.

Table 9.49 Reactive power offset of Channel 2

3CH Bit15 Bit14 Bit13 Bit12~Bit3 Bit2 Bit1 Bit0
VAR2OS VAR2OS.15 VAR2OS.14 VAR2OS.13 VAR2OS.12…3 VAR2OS.2 VAR2OS.1 VAR2OS.0
W/R W/R W/R W/R W/R W/R W/R W/R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

11-0 VAR2OS[11:0] Reactive power offset of Channel 2, the binary complement means a signed value
This register participate in the reactive power and energy calculation of channel 2.
Table 9.50 I1 RMS offset
3DH Bit23 Bit22~11 Bit10 Bit9~Bit3 Bit2 Bit1 Bit0
IRMS1OS22
IRMS1OS IRMS1OS.23 IRMS1OS.10 IRMS1OS.9…3 IRMS1OS.2 IRMS1OS.1 IRMS1OS.0
….11

133
 SH79F642B
W/R W/R W/R W/R W/R W/R W/R W/R
0 0 0 0000000 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0000000 0 0 0
0 0 0 0000000 0 0 0

Bit Number Bit Mnemonic Description

23-0 IRMS1OS[23:0] Current RMS offset of Channel 1, the binary complement means a signed value
This register participate in the rms current channel 1 calculation. 1LSB corresponding to 32768 LSB (left shift 15 bits) of
current rms.
Table 9.51 I2 RMS offset
3EH Bit23 Bit22~11 Bit10 Bit9~Bit3 Bit2 Bit1 Bit0

IRMS2OS22
IRMS2OS IRMS2OS.23 IRMS2OS.10 IRMS2OS.9…3 IRMS2OS.2 IRMS2OS.1 IRMS2OS.0
….11

W/R W/R W/R W/R W/R W/R W/R W/R

0 0 0 0000000 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0000000 0 0 0
0 0 0 0000000 0 0 0

Bit Number Bit Mnemonic Description

23-0 IRMS2OS[23:0] Current RMS offset of Channel 2, the binary complement means a signed value
This register participate in the rms current channel 2 calculation. 1LSB corresponding to 32768 LSB (left shift 15 bits) of
current rms.

Table 9.52 Voltage RMS offset

3FH Bit23 Bit22~Bit11 Bit10 Bit9~Bit3 Bit2 Bit1 Bit0
VRMSOS22
VRMSOS VRMSOS.23 VRMSOS.10 VRMSOS.9…3 VRMSOS.2 VRMSOS.1 VRMSOS.0
….11
W/R W/R W/R W/R W/R W/R W/R W/R
0 0 0 0000000 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0000000 0 0 0
0 0 0 0000000 0 0 0

Bit Number Bit Mnemonic Description

23-0 VRMSOS[23:0] Voltage RMS offset, the binary complement means a signed value
This register participate in the rms voltage calculation. 1LSB corresponding to 64 LSB (left shift 6 bits) of voltage rms.

Table 9.53 ADC offset of current channel 1

40H Bit15 Bit14 Bit13 Bit12~Bit3 Bit2 Bit1 Bit0
ADCOSI1.1 ADCOSI1.1 ADCOSI1.1 ADCOSI1.1
ADCOSI1 ADCOSI1.2 ADCOSI1.1 ADCOSI1.0
5 4 3 2…3
W/R W/R W/R W/R W/R W/R W/R W/R

134
 SH79F642B
Reset value 0 0 0 0 0 0 0
u u u u u u u
（POR/WDT/LVR/
0 0 0 0 0 0 0
PIN）
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

15-0 ADCOSI1 [15-0] ADC offset of current channel 1, the binary complement means a signed value.
ADC offset metering position of current channel 2 is before high-pass filter in physics.

Table 9.54 ADC offset of current channel 2

41H Bit15 Bit14 Bit13 Bit12~Bit3 Bit2 Bit1 Bit0
ADCOSI2.1 ADCOSI2.1 ADCOSI2.1 ADCOSI2.1
ADCOSI2 ADCOSI2.2 ADCOSI2.1 ADCOSI2.0
5 4 3 2…3
W/R W/R W/R W/R W/R W/R W/R W/R
Reset value 0 0 0 0 0 0 0
u u u u u u u
（POR/WDT/LVR/
0 0 0 0 0 0 0
PIN）
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

15-0 ADCOSI2 [15-0] ADC offset of current channel 2, the binary complement means a signed value.
ADC offset metering position of current channel 2 is before high-pass filter in physics.

Table 9.55 ADC offset of voltage channel

42H Bit15 Bit14 Bit13 Bit12~Bit3 Bit2 Bit1 Bit0
ADCOSU.12
ADCOSU ADCOSU.15 ADCOSU.14 ADCOSU.13 ADCOSU.2 ADCOSU.1 ADCOSU.0
…3
W/R W/R W/R W/R W/R W/R W/R W/R
Reset value 0 0 0 0 0 0 0
u u u u u u u
（POR/WDT/LVR/
0 0 0 0 0 0 0
PIN） 0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

15-0 ADCOSU [15-0] ADC offset of voltage channel, the binary complement means a signed value.
ADC offset metering position of voltage channel is before high-pass filter in physics.

Table 9.56 Power Startup Threshold Register

43H Bit15 Bit14 Bit13 Bit12~Bit3 Bit2 Bit1 Bit0
SPTS SPTS.15 SPTS.14 SPTS.13 SPTS.12…3 SPTS.2 SPTS.1 SPTS.0
W/R W/R W/R W/R W/R W/R W/R W/R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

15-0 SPTS[15:0] Threshold configuration for power startup, unsigned value

Table 9.57 Voltage Constant

44H Bit15 Bit14 Bit13 Bit12~Bit3 Bit2 Bit1 Bit0

135
 SH79F642B
VCONST VCONST.15 VCONST.14 VCONST.13 VCONST.12…3 VCONST.2 VCONST.1 VCONST.0
W/R W/R W/R W/R W/R W/R W/R W/R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

15-0 VCONST[11:0] Voltage constant, unsigned value
If voltage sag, this register instead of the input voltage for active energy calculation. Corresponding the voltage channel,
Table 9.58 Voltage Sag Threshold
45H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SAGTHR SAGTHR.7 SAGTHR.6 SAGTHR.5 SAGTHR.4 SAGTHR.3 SAGTHR.2 SAGTHR.1 SAGTHR.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
0 0 0 0 0 0 0 0
Reset value u u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

7-0 SAGTHR[7:0] Threshold configuration for voltage sag, unsigned value
Compare the detected voltage value with SAGTHR, if the voltage is less than SAGTHR or there is no zero-crossing of
voltage in SAGCNT period of metering sampling, then the voltage sag occurs, set the voltage sag flag and into the state of
voltage sag. The detected voltage value comes from the high 8 bits of the voltage channel ADC. In the state of voltage sag, if
the voltage is less than SAGTHR or there is no zero-crossing of voltage, the voltage sag flag is no longer set, otherwise,clear
the voltage sag state.

Table 9.59 Voltage Sag Sampling Counting

46H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SAGCNT SAGCNT.7 SAGCNT.6 SAGCNT.5 SAGCNT.4 SAGCNT.3 SAGCNT.2 SAGCNT.1 SAGCNT.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R
1 1 1 1 1 1 1 1
Reset value u u u u u u u u
(POR/WDT/LVR/PIN) 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1

Bit Number Bit Mnemonic Description

7-0 SAGCNT[7:0] Sampling count for voltage sag, unsigned value
If the internal counter accumulated value is equal to SAGCNT, then set the voltage sag interrupt request flag SAGIF to 1.

Table 9.60 Output Pulse Frequency

47H Bit15 Bit14 Bit13 Bit12~Bit3 Bit2 Bit1 Bit0 第0位
ICONT ICONT.15 ICONT.14 ICONT.13 ICONT.12…8 ICONT.7 ICONT.6..2 ICONT.1 ICONT.0
W/R W/R W/R W/R W/R W/R W/R W/R W/R

136
 SH79F642B
0 0 0 0 1 0 0 0
Reset value u u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 1 0 0 0
0 0 0 0 1 0 0 0

Bit Number Bit Mnemonic Description

15-0 ICONT[15:0] Configuration for output pulse frequency, unsigned value
If the ICONT set to 0, equal with 1 when the pulse compare

Table 9.61 Fast Active Pulse Counting

48H Bit15 Bit14 Bit13 Bit12~Bit3 Bit2 Bit1 Bit0
PCNT PCNT.15 PCNT.14 PCNT.13 PCNT.12…3 PCNT.2 PCNT.1 PCNT.0
W/R W/R W/R W/R W/R W/R W/R W/R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

15-0 PCNT[15:0] Fast active pulse counting, the binary complement means a signed value

Table 9.62 Fast Reactive Pulse Counting

49H Bit15 Bit14 Bit13 Bit12~Bit3 Bit2 Bit1 Bit0
QCNT QCNT.15 QCNT.14 QCNT.13 QCNT.12…3 QCNT.2 QCNT.1 QCNT.0
W/R W/R W/R W/R W/R W/R W/R W/R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

15-0 QCNT[15:0] Fast reactive pulse counting, the binary complement means a signed value

Table 9.63 Calculate cycle register

Bit12~Bit
4AH Bit15 Bit14 Bit13 Bit2 Bit1 Bit0
3
SUMSAMPS - SAMP.14 SAMP.13…10 SAMP.9 SAMP.8 SAMP.7...4 SAMP.3...0
W/R W/R W/R W/R W/R W/R W/R W/R
1111
0 0 0 0 1 1111
uuuu
Reset value u u u u u uuuu
1111
（POR/LVR/PIN） 0 0 0 0 1 1111
1111
0 0 0 0 1 1111

Bit Number Bit Mnemonic Description

Calculate cycle register, the binary complement means a unsigned value. It is the max
15-0 SAMP [14-0]
detection cycle of power, RMS, max ADC value. Reset value is 0x1FF.
Seting up formula:
Calculate cycle value = T * update frequency. T(s): the cycle time. if update frequency is 4000Hz, T = 1s, the calculate
cycle value is 4000(0XFA0).

137
 SH79F642B
Table 9.64 Active power const register
4BH Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
APCONST APCST.23 APCST.22 APCST.21 APCST.20…3 APCST.2 APCST.1 APCST.0
W/R W/R W/R W/R W/R W/R W/R W/R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

23-0 APCST [23:0] Active power const register, the binary complement means a unsigned value
Table 9.65 Reactive power const register
4CH Bit23 Bit22 Bit21 Bit20~Bit3 Bit2 Bit1 Bit0
RPCONST RPCST.23 RPCST.22 RPCST.21 RPCST.20…3 RPCST.2 RPCST.1 RPCST.0
W/R W/R W/R W/R W/R W/R W/R W/R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

23-0 RPCST [23:0] Reactive power const, the binary complement means a unsigned value

Table 9.66 Fast active pulse counter

4DH Bit15 Bit14 Bit13 Bit12~Bit3 Bit2 Bit1 Bit0
PCNT_C PCNT_C PCNT_CO PCNT_CONST.12 PCNT_C PCNT_C PCNT_C
PCNT_CONST
ONST.15 ONST.14 NST.13 …3 ONST.2 ONST.1 ONST.0
W/R W/R W/R W/R W/R W/R W/R W/R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

15-0 PCNT_CONST [15-0] Fast active pulse counter, the binary complement means a signed value.

Table 9.67 Fast reactive pulse counter

4EH Bit15 Bit14 Bit13 Bit12~Bit3 Bit2 Bit1 Bit0
QCNT_ QCNT_
QCNT_C QCNT_C QCNT_C QCNT_CONST.12 QCNT_C
QCNT_CONST CONST. CONST.
ONST.15 ONST.14 ONST.13 …3 ONST.0
2 1
W/R W/R W/R W/R W/R W/R W/R W/R
0 0 0 0 0 0 0
Reset value u u u u u u u
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0
0 0 0 0 0 0 0

Bit Number Bit Mnemonic Description

15-0 QCNT_CONST [15-0] Fast reactive pulse counter, the binary complement means a signed value.

138
 SH79F642B
9.5 Metering Function Description
EMU metering of active power, active energy, reactive power, reactive energy, voltage rms, current rms, corresponding
correction function.
9.5.1 Active Power, Reactive Power
The voltage multiplied the current, and passed the low pass filter, then multiplied by the correction gain, the active power is
achieved and stored to the register APWR1/APWR2. The high bit of W1GAIN and W2GAIN is sign bit, and correction gain is
1+W1GAIN/216. The correction gain range of -0.5~1.5.
P1CAL LPFINDEX
W1GAIN

⊕
I1P +
ADC I1DTA Φ

⊗ ⊗ ⊕
I1N -
PGA APWR1 ∑ APWRA1
ADCOSI1
LPFINDEX
SUMSAMPS
WATT1OS

⊕
VP +
ADC VDTA
VN - Q1GAIN
PGA
ADCOSV

P2CAL LPFINDEX
π
⊗ ⊗ ⊕ RPWR1 ∑ RPWRA1

⊕
I2P + 2
ADC SUMSAMPS
I2N - I2DTA Φ
VAR1OS
PGA
ADCOSI2 Q2GAIN

⊗ ⊗ ⊕ RPWR2 ∑ RPWRA2

SUMSAMPS
VAR2OS

W2GAIN

⊗ ⊗ ⊕ APWR2 ∑ APWRA2

SUMSAMPS
WATT2OS

X2 ⊕ ∑ VRMS

VRMSOS SUMSAMPS

X 2
⊕ ∑ ⊗ IRMS2

IRM2OS SUMSAMPS I2GAIN

X2 ⊕ ∑ IRMS1

IRM1OS SUMSAMPS

The active ( reactive ) power average value is calculated by a cycle time which set by SUMSAMPS register. The same to
voltage RMS and current RMS value.
9.5.2 Energy and Pulse Output
The internal active energy register of 48bits, the highest bit is sign bit, to accumulate active power.The active energy value
register (AERY) is high 24 bits of the internal active energy register, and the value back to 0 after overflowed.
The internal reactive energy register of 48bits, the highest bit is sign bit, to accumulate reactive power.The reactive energy
value register (RERY) is high 24 bits of the internal reactive energy register, and the value back to 0 after overflowed.
By the conversion of the active and reactive energy, the corresponding proportion pulse output from PF and QF pin.
The energy can select 3 cumulative mode of forward, absolute value and algebraic sum metering through the QMOD and
PMOD of EMCON.
There are two source of energy accumulation, one is active power value of present metering channel, the other is the const
value which store in PCONST/RPCONST.

139
 SH79F642B
APWR

∑
AERY[23:0]
PCONT +
AERYL[23:0]
PF
PCONST -

ICONT

RPWR +
QF
∑
RERY[23:0]
QCONT -
RERYL[24:0]
RPCONST

The active energy accumulating, the fast active pulse register PCNT increase 1LSB when the 23 bit (least significant bit to
0) of the internal active energy register increase 1, and if the absolute value of the register is greater than or euqal to the the
value of ouput pulse frequence configuration register, outputing an active pulse of PF, setting PFIF(EMUIF.3) to 1, and the
corresponding energy pulse accumulated register plus 1, the absolute active energy pulse accumulated register plus 1, clear
REVP flag.
The active energy accumulating, the fast active pulse register PCNT decrease 1LSB when the 23 bit (least significant bit to
0) of the internal active energy register decrease 1, and if the absolute value of the register is greater than or euqal to the the
value of ouput pulse frequence configuration register, outputing an active pulse of PF, setting PFIF(EMUIF.3) to 1, and the
corresponding energy pulse accumulated register plus 1, the absolute active energy pulse accumulated register plus 1, set
REVP flag to 1.
The reactive energy accumulating, the fast reactive pulse register QCNT increase 1LSB when the 23 bit (least significant
bit to 0) of the internal reactive energy register increase 1, and if the absolute value of the register is greater than or euqal to the
the value of ouput pulse frequence configuration register, outputing an reactive pulse of QF, setting QFIF(EMUIF.4) to 1, and
the corresponding energy pulse accumulated register plus 1. the absolute reactive energy pulse accumulated register plus 1,
clear REVQ flag.
The reactive energy accumulating, the fast reactive pulse register QCNT decrease 1LSB when the 23 bit (least significant
bit to 0) of the internal reactive energy register decrease 1, and if the absolute value of the register is greater than or euqal to the
the value of ouput pulse frequence configuration register, outputing an reactive pulse of QF, setting QFIF(EMUIF.4) to 1, and
the corresponding energy pulse accumulated register plus 1. the absolute reactive energy pulse accumulated register plus 1,
set REVQ flag to 1.
The reverse of active and reactive energy can be indicated by the REVP and RECQ of the status/control register EMUSR.
When active pulse output, update REVP, and update REVQ when reactive pulse output.
The NoQld and NoPld of EMUSR could display the state of energy startup in real time, and the threshold selection will be
easier.

140
 SH79F642B
9.5.3 No Neutral Wire Mode
If the no neutral wire mode is enabled. Use the value in VCONST register ( instead of ADC sampling value of voltage
channel ) to calculate active/reactive power value.
9.5.4 MAX ADC Sampling Value Record of Voltage Channel
In a sampling period ( set by SAMSAMPS register), record the max ADC sampling absolute value of voltage channel and
update the value to VDTAMAX register.
Voltage
SUMSAMPS Vaveform VDTAMAX
monitor

⊕
V1P
ADC VDTA
V1N

ADCOSV

Sag Detect

9.5.5 single Phase 3 Wire Metering Mode

In this metering mode, APWR (RPWR) is sum of channel 1 and channel 2’s active (reactive) power value. And the add
mode can be absolute value added or not. The revise method can be found in the application manual.

9.5.6 Voltage Sag Detection

When ADC Sampling Value of Voltage Channel do not catch zero crossing point or the absolute max value less than
SAGTHR value, in the period which set by SAGCNT, voltage sag happened, set SAGF and SAGIF to 1. Or clear SAGF and set
SAGIF to 1.
9.5.7 Zero Crossing Detection
Zero crossing point detect by ADC Sampling Value of Voltage Channel, filtering the direct current component is necessary.

ADC
⊕ VDTA
Zero crossing
detect

ADCOSV

9.6 EMU Interrupt System

EMU supply 6 interrupts: QF, PF, SAG,SUM, ZX and DSP.
SAG: When the line voltage sag is detected, set SAGIF flag of EMUIF register to 1
ZX: When the line voltage zero-crossing is detected, set ZXIF flag of EMUIF register to 1
DSP: When the DSP performs over, set DSPIF flag of EMUIF register to 1
The 6 interrupt request flags of EMU are all generated aftet a metering cycle, and share a common EMU interrupt. If
EMUIE and the corresponding bit of EMUIF are 1, set the energy metering interrupt request flag EMUF(EXF0.6), if the energy
metering interrupt enable flag EEMU(IEN1.0) is 1, EMU interrupt. Write 0 to the corresponding bit of EMUIF when clearing the
interrupt request flag, if the result of EMUIF AND EMUIE is 0, then clear EMUF.
Table 9.68 EMU interrupt enable register

141
 SH79F642B
D6H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
EMUIE QFEN PFEN DSPIE QFIE PFIE SUMIE SAGIE ZXIE
W/R W/R W/R W/R W/R W/R W/R W/R W/R
Reset value
0 0 0 0 0 0 0 0
(POR/WDT/LVR/PIN)

Bit Number Bit Mnemonic Description

Reactive pulse QF-pin output
7 QFEN 0：Disable reactive pulse output
1：Enable reactive pulse output
Active pulse PF-pin output
6 PFEN 0：Disable active pulse output
1：Enable active pulse output
The interrupt enable of the end of DSP performing
5 DSPIE 0：Disable DSP end interrupt
1：Enable DSP end interrupt
The interrupt enable of reactive pulse output
4 QFIE 0：Disable reactive pulse output interrupt
1：Enable reactive pulse output interrupt
The interrupt enable of active pulse output
3 PFIE 0：Disable active pulse output interrupt
1：Enable active pulse output interrupt
The interrupt enable of accumulation
2 SUMIE 0：Disable accumulation interrupt
1：Enable accumulation interrupt
The interrupt enable of voltage sag
1 SAGIE 0：Disable voltage sag interrupt
1：Enable voltage sag interrupt
The interrupt enable of zero-crossing
0 ZXIE 0：Disable zero-crossing interrupt
1：Enable zero-crossing interrupt

142
 SH79F642B
Table 9.69 EMU interrupt request register
D7H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
EMUIF - - DSPIF QFIF PFIF SUMIF SAGIF ZXIF
W/R - - W/R W/R W/R W/R W/R W/R
Reset value
- - 0 0 0 0 0 0
(POR/WDT/LVR/PIN)

Bit Number Bit Mnemonic Description

The interrupt request flag of the end of DSP performing
5 DSPIF 0：No interrupt flag
1：Interrupt flag
The interrupt request flag of reactive pulse output
4 QFIF 0：No interrupt flag
1：Interrupt flag
The interrupt request flag of active pulse output
3 PFIF 0：No interrupt flag
1：Interrupt flag
The interrupt request flag of accumulation
2 SUMIF 0：No interrupt flag
1：Interrupt flag
The interrupt request flag of voltage sag
1 SAGIF 0：No interrupt flag
1：Interrupt flag
The interrupt request flag of zero-crossing
0 ZXIF 0：No interrupt flag
1：Interrupt flag

143
 SH79F642B
10. Instruction Set

ARITHMETIC OPERATIONS
Opcode Description Code Byte Cycle
ADD A, Rn Add register to accumulator 0x28-0x2F 1 1
ADD A, direct Add direct byte to accumulator 0x25 2 2
ADD A, @Ri Add indirect RAM to accumulator 0x26-0x27 1 2
ADD A, #data Add immediate data to accumulator 0x24 2 2
Add register to accumulator with carry
ADDC A, Rn 0x38-0x3F 1 1
flag
ADDC A, direct Add direct byte to A with carry flag 0x35 2 2
ADDC A, @Ri Add indirect RAM to A with carry flag 0x36-0x37 1 2
ADDC A, #data Add immediate data to A with carry flag 0x34 2 2
SUBB A, Rn Subtract register from A with borrow 0x98-0x9F 1 1
SUBB A, direct Subtract direct byte from A with borrow 0x95 2 2
SUBB A, @Ri Subtract indirect RAM from A with borrow 0x96-0x97 1 2
Subtract immediate data from A with
SUBB A, #data 0x94 2 2
borrow
INC A Increment accumulator 0x04 1 1
INC Rn Increment register 0x08-0x0F 1 2
INC direct Increment direct byte 0x05 2 3
INC @Ri Increment indirect RAM 0x06-0x07 1 3
DEC A Decrement accumulator 0x14 1 1
DEC Rn Decrement register 0x18-0x1F 1 2
DEC direct Decrement direct byte 0x15 2 3
DEC @Ri Decrement indirect RAM 0x16-0x17 1 3
INC DPTR Increment data pointer 0xA3 1 4
MUL AB 8X8 11
Multiply A and B 0xA4 1
16 X 8 20
DIV AB 8/8 11
Divide A by B 0x84 1
16 / 8 20
DA A Decimal adjust accumulator 0xD4 1 1

144
 SH79F642B

LOGIC OPERATIONS
Opcode Description Code Byte Cycle
ANL A, Rn AND register to accumulator 0x58-0x5F 1 1
ANL A, direct AND direct byte to accumulator 0x55 2 2
ANL A, @Ri AND indirect RAM to accumulator 0x56-0x57 1 2
ANL A, #data AND immediate data to accumulator 0x54 2 2
ANL direct, A AND accumulator to direct byte 0x52 2 3
ANL direct, #data AND immediate data to direct byte 0x53 3 3
ORL A, Rn OR register to accumulator 0x48-0x4F 1 1
ORL A, direct OR direct byte to accumulator 0x45 2 2
ORL A, @Ri OR indirect RAM to accumulator 0x46-0x47 1 2
ORL A, #data OR immediate data to accumulator 0x44 2 2
ORL direct, A OR accumulator to direct byte 0x42 2 3
ORL direct, #data OR immediate data to direct byte 0x43 3 3
XRL A, Rn Exclusive OR register to accumulator 0x68-0x6F 1 1
XRL A, direct Exclusive OR direct byte to accumulator 0x65 2 2
XRL A, @Ri Exclusive OR indirect RAM to accumulator 0x66-0x67 1 2
Exclusive OR immediate data to
XRL A, #data 0x64 2 2
accumulator
XRL direct, A Exclusive OR accumulator to direct byte 0x62 2 3
XRL direct, #data Exclusive OR immediate data to direct byte 0x63 3 3
CLR A Clear accumulator 0xE4 1 1
CPL A Complement accumulator 0xF4 1 1
RL A Rotate accumulator left 0x23 1 1
RLC A Rotate accumulator left through carry 0x33 1 1
RR A Rotate accumulator right 0x03 1 1
RRC A Rotate accumulator right through carry 0x13 1 1
SWAP A Swap nibbles within the accumulator 0xC4 1 4

145
 SH79F642B

DATA TRANSFERS
Opcode Description Code Byte Cycle
MOV A, Rn Move register to accumulator 0xE8-0xEF 1 1
MOV A, direct Move direct byte to accumulator 0xE5 2 2
MOV A, @Ri Move indirect RAM to accumulator 0xE6-0xE7 1 2
MOV A, #data Move immediate data to accumulator 0x74 2 2
MOV Rn, A Move accumulator to register 0xF8-0xFF 1 2
MOV Rn, direct Move direct byte to register 0xA8-0xAF 2 3
MOV Rn, #data Move immediate data to register 0x78-0x7F 2 2
MOV direct, A Move accumulator to direct byte 0xF5 2 2
MOV direct, Rn Move register to direct byte 0x88-0x8F 2 2
MOV direct1, direct2 Move direct byte to direct byte 0x85 3 3
MOV direct, @Ri Move indirect RAM to direct byte 0x86-0x87 2 3
MOV direct, #data Move immediate data to direct byte 0x75 3 3
MOV @Ri, A Move accumulator to indirect RAM 0xF6-0xF7 1 2
MOV @Ri, direct Move direct byte to indirect RAM 0xA6-0xA7 2 3
MOV @Ri, #data Move immediate data to indirect RAM 0x76-0x77 2 2
MOV DPTR, #data16 Load data pointer with a 16-bit constant 0x90 3 3
MOVC A, @A+DPTR Move code byte relative to DPTR to A 0x93 1 7
MOVC A, @A+PC Move code byte relative to PC to A 0x83 1 8
MOVX A, @Ri Move external RAM (8-bit address) to A 0xE2-0xE3 1 5
MOVX A, @DPTR Move external RAM (16-bit address) to A 0xE0 1 6
MOVX @Ri, A Move A to external RAM (8-bit address) 0xF2-F3 1 4
MOVX @DPTR, A Move A to external RAM (16-bit address) 0xF0 1 5
PUSH direct Push direct byte onto stack 0xC0 2 5
POP direct Pop direct byte from stack 0xD0 2 4
XCH A, Rn Exchange register with accumulator 0xC8-0xCF 1 3
XCH A, direct Exchange direct byte with accumulator 0xC5 2 4
XCH A, @Ri Exchange indirect RAM with accumulator 0xC6-0xC7 1 4
Exchange low-order nibble indirect RAM
XCHD A, @Ri 0xD6-0xD7 1 4
with A

146
 SH79F642B

PROGRAM BRANCHES
Opcode Description Code Byte Cycle
ACALL addr11 Absolute subroutine call 0x11-0xF1 2 7
LCALL addr16 Long subroutine call 0x12 3 7
RET Return from subroutine 0x22 1 8
RETI Return from interrupt 0x32 1 8
AJMP addr11 Absolute jump 0x01-0xE1 2 4
LJMP addr16 Long jump 0x02 3 5
SJMP rel Short jump (relative address) 0x80 2 4
JMP @A+DPTR Jump indirect relative to the DPTR 0x73 1 6
JZ rel (not taken) 3
Jump if accumulator is zero 0x60 2
(taken) 5
JNZ rel (not taken) 3
Jump if accumulator is not zero 0x70 2
(taken) 5
JC rel (not taken) 2
Jump if carry flag is set 0x40 2
(taken) 4
JNC rel (not taken) 2
Jump if carry flag is not set 0x50 2
(taken) 4
JB bit,rel (not taken) 4
Jump if direct bit is set 0x20 3
(taken) 6
JNB bit,rel (not taken) 4
Jump if direct bit is not set 0x30 3
(taken) 6
JBC bit, rel (not taken) 4
Jump if direct bit is set and clear bit 0x10 3
(taken) 6
CJNE A,direct,rel (not taken) Compare direct byte to A and jump if not 4
0xB5 3
(taken) equal 6
CJNE A,#data,rel (not taken) Compare immediate to A and jump if not 4
0xB4 3
(taken) equal 6
CJNE Rn,#data,rel (not taken) Compare immediate to reg. and jump if 4
0xB8-0xBF 3
(taken) not equal 6
CJNE @Ri,#data,rel (not taken) Compare immediate to Ri and jump if not 4
0xB6-0xB7 3
(taken) equal 6
DJNZ Rn,rel (not aken) 3
Decrement register and jump if not zero 0xD8-0xDF 2
(taken) 5
DJNZ direct,rel (not taken) Decrement direct byte and jump if not 4
0xD5 3
(taken) zero 6
NOP No operation 0 1 1

147
 SH79F642B

BOOLEAN MANIPULATION
Opcode Description Code Byte Cycle
CLR C Clear carry flag 0xC3 1 1
CLR bit Clear direct bit 0xC2 2 3
SETB C Set carry flag 0xD3 1 1
SETB bit Set direct bit 0xD2 2 3
CPL C Complement carry flag 0xB3 1 1
CPL bit Complement direct bit 0xB2 2 3
ANL C, bit AND direct bit to carry flag 0x82 2 2
ANL C, /bit AND complement of direct bit to carry 0xB0 2 2
ORL C, bit OR direct bit to carry flag 0x72 2 2
ORL C, /bit OR complement of direct bit to carry 0xA0 2 2
MOV C, bit Move direct bit to carry flag 0xA2 2 2
MOV bit, C Move carry flag to direct bit 0x92 2 3

148
 SH79F642B
11. Electrical Characteristics
Absolute Maximum Ratings
DC Supply Voltage. . . . . . . . . . . .. . . . . . . . . –0.3V to +3.8V * Comments

Input / Output Voltage. . . . . . . . DGND-0.3V to VOUT +0.3V Stresses exceed those listed under “Absolute Maximum
Ratings” may cause permanent damage to this device.
Analog input voltage.. . .. . . . . . . .AGND-0.3V to VDD +0.3V These are stress ratings only. Functional operation of this
device at these or any other conditions above those
Operating Ambient Temperature. . . . . . .. . .-40°C to +85°C indicated in the operational sections of this specification is
not implied or intended. Exposure to the absolute maximum
Store Temperature. . . . . . . . . . . . . . . . . . . .–55°C to +125°C rating conditions for extended periods may affect device
reliability.
FLASH Memory write / erase operations . . 0°C to +85°C

Electrical Characteristics (VDD = 3.0 – 3.6V, DGND = 0V, VBAT = 2.4 – 3.6V, TA = 25°C, unless otherwise specified)
Parameter Symbol Min. Typ. ∗ Max. Unit Condition
Operating Voltage VDD 2.2 3.3 3.6 V 32.768kHz ≤ fSYS ≤ 8.192MHz
Battery Voltage VBAT 2.2 3.3 3.8 V 32.768kHz ≤ fSYS ≤ 8.192MHz
fsys = Fsys/12, PLL on
All output pins unload(including all digital
Operating Current IOP2 - 1.4 mA input pins un-floating), CPU on (execute
NOP instruction), LCD on,WDT on , LVR
on, LPD on, EMU on, RTC on, disable other
fuctions, VDD =3.3V, VBAT=3.3V.
fsys = 32.768kHz, PLL off
All output pins unload(including all digital
Stand by Current (IDLE) ISB1 - 11 18 uA input pins un-floating)LCD off, WDT off,
LVR on, RTC on, LPD on, disable other
fuctions, VDD =3.3V, VBAT=3.3V.
fOSC = OFF, PLL off
All output pins unload(including all digital
Stand by Current
ISB2 - - 10 uA input pins un-floating), LCD off, RTC off,
(Power-Down)
WDT off, LVR on, disable other fuctions,
VDD =3.3V, VBAT=3.3V.
All output pins unload；watchdog on VDD
WDT Current IWDT - - 1 uA
=3.3V
LPD2 Current ILPD2 - - 4 uA -
PLL Current IPLL 350 380 µA -
Traditional LCD mode, VDD =3.3V
LCD Current 1 ILCD1 - 3 5 uA 900k LCD bias, contrast[2:0]=000
(Not include LCD panel)
LCD Fast charge mode, VDD =3.3V
900k LCD bias, 1/16 LCD com period,
LCD Current 2 ILCD2 - 7 9 uA
contrast[2:0]=111
(Not include LCD panel)
Input Low Voltage 1 VIL1 GND - 0.3 X VDD V I/O port
Input high Voltage 1 VIH1 0.7 X VDD - VDD V I/O port
————

Input Low Voltage 2 VIL2 GND - 0.2 X VDD V RST, T0, T1, T2, T2EX, INT0, INT1, INT2,
INT3 (Schmitt trigger)

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————

Input high Voltage 2 VIH2 0.8 X VDD - VDD V RST, T0, T1, T2, T2EX, INT0, INT1, INT2,
INT3 (Schmitt trigger)
Input Leakage Current IIL -1 1 uA No pull-high, VIN= VDD or DGND
Pull-high Resistor RPH1 - 50 - kΩ VDD =3.3V, VIN=DGND
I/O port, IOH = -3mA, VDD = 3.3V
Output High Voltage1 VOH1 VDD – 0.4 - - V
(not include P4,P5,P0.6,P0.7)
I/O port, IOL = 8mA, VDD = 3.3V
Output Low Voltage1 VOL1 - - GND + 0.5 V
(not include P4,P5,P0.6,P0.7)

I/O port, IOL = 2mA，VDD = 3.3 V

Output Low Voltage2 VOL2 GND + 1.0 - GND + 1.3 V
(P2,P3)
*: "Typical" data is measured at 3.3V, 25 ° C, unless otherwise indicated

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3.3V A/D Converter Electrical Characteristics

Parameter Symbol Min. Typ. ∗ Max. Unit Condition
Supply voltage VAD 2.4 3.3 3.6 V

Resolution NR 10 - bit GND ≤ VAIN ≤ VOUT

-
A/D Input Voltage VAIN GND - VOUT V

A/D Input Resistor* RAIN 2 - - MΩ VIN=3.3V

A/D conversion current IAD - 1 3 mA ADC模块工作, VOUT =3.3V
A/D Input current IADIN 10 uA VOUT = 3.3V
Analog voltage source is
ZAIN - - 10 KΩ
recommended impedance
Total Absolute error EAD - - ±4 LSB fsys =4.096MHz, VOUT =3.3V
Total Conversion time** TCON 28 - - us 10bit, fsys = 4.096MHz, VOUT = 3.3V
*: "Typical" data is measured at 3.3V, 25 ° C, unless otherwise indicated

Analog Front-End Electrical Characteristics of Energy Metering

(VDD = 3.0 - 3.6V, AGND = 0V, TA = -40°C~ 85°C, fSYS = 4.096MHz, unless otherwise specified)
Parameter Symbol Min. Typ. Max. Unit Condition
Supply voltage VAV 3.0 3.3 3.6 V
I1P/I1N
mV
Input signal level I2P/I2N ±400 ±440 PGA=1
VP/VN peak

Operating clock CLK - 4.096 - MHz

PGA gain error EPGA - - ±3 % GAIN = 1、2、4、8、16, VDD = 3.3V
-10 - 10 mV GAIN = 1
PGA Input offset VOFF
-0.5 - 0.5 mV GAIN = 16

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Accuracy of Energy Metering

(VDD = 3.0 - 3.6V, DGND = 0V, AGND = 0V, VBAT = 3.3V, TA = -40°C~ 85°C, fSYS = 4.096MHz, unless otherwise specified)
Parameter Symbol Min. Typ. Max. Unit Condition
Active energy metering
EACT - 0.1 - % Dynamic range of 2000:1 at 25°C
error
Reactive energy metering
EREA - 0.1 - % Dynamic range of 1000:1 at 25°C
error
Voltage RMS metering
EVRMS - 0.5 - % Dynamic range of 1000:1 at 25°C
error
Current RMS metering
EIRMS - 0.5 - % Dynamic range of 1000:1 at 25°C
error

Power supply switch electrical characteristics

(VDD = 3.0 - 3.6V, DGND = 0V, VBAT = 2.4V - 3.6V, TA = 25°C, unless otherwise specified)
Parameter Symbol Min. Typ. ∗ Max. Unit Condition
Switch operating voltage
VOUT 2.2 - 3.8 V -
range
VIN switching threshold V
VVIN 1.1 1.2 1.3 -
voltage
VDD switching threshold V
VVDD 2.6 2.7 2.8 -
voltage

Switch leakage current ISW - 10 - nA VBAT = 0，VOUT = 3.3V

VDD to VBAT switch
TVDDD - 20 - µs VDD < 2.7V
delay (VDD detection
VBAT to VDD switching
TBATD - 8 - µs VDD > 2.7V
delay
VDD to VOUT resistance RVDO - - 10 欧 VDD = 3.0V

VBAT to VOUT resistance RBATO - - 22 欧 VBAT = 2.4V

VBAT leakage current IVBAT - - 1 µA VDD = 3.3V，VOUT = VDD

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 SH79F642B
AC Electrical Characteristics (VOUT = 2.4V - 3.6V, DGND = 0V, TA = 25°C, fOSC = 32.768kHz, unless otherwise specified)
Parameter Symbol Min. Typ. ∗ Max. Unit Condition
Oscillator Start time TOSC - 1 2 s Oscillator = 32768Hz
PLL Start time TPLL - 2 - ms Does not include oscillator start-up
PLL jitter(Period) JPLL - 1 - ns -
RST pulse width tRESET 10 - - us Active-low
RESET pin Pull-high RRPH - 50 - kΩ VOUT = 3.3V, VIN = DGND
Resistor

Low Voltage Reset Electrical Characteristics (VOUT = 2.4V - 3.6V, DGND = 0V, TA = 25°C, unless otherwise specified)
Parameter Symbol Min. Typ. ∗ Max. Unit Condition

LVR voltage VLVRL 2.2 2.3 2.4 V LVR enabled，VOUT = 2.2V - 3.6V

LVR low voltage reset

TLVR - 30 - us -
width

32.768Hz Crystal Characteristics

Parameter Symbol Min. Typ. ∗ Max. Unit Condition
Frequency F32K - 32768 - Hz
Load capacitance CL - 12.5 - pF

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 SH79F642B
12. Ordering Information
Product ID Package

SH79F642BP/064PR LQFP64(10*10)
SH79F642BS/064SR LQFP64(7*7)
SH79F6421S/064SR LQFP64(7*7)

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 SH79F642B
13. Package Information
LQFP64 (BODY SIZE: 10*10) Unit: inch / mm

HD
D

64 49

1 48

HE
E
16 33

17 e b 32

c
A2

A
A1

See Detail F
L
Seating Plane
L1
DETAIL F

Symbol Uint: inch Uint: mm

A 0.063 (MAX) 1.60 (MAX)
A1 0.002 (MIN.), 0.006(MAX.) 0.05 (MIN), 0.15 (MAX)
A2 0.055 ± 0.002 1.40 ± 0.05
b 0.009 ± 0.002 0.22 ± 0.05
c 0.004 (MIN), 0.008 (MAX) 0.09 (MIN), 0.20 (MAX)
D 0.394 BASIC 10.00 BASIC
E 0.394 BASIC 10.00 BASIC
e 0.020 BASIC 0.50 BASIC
HD 0.472 BASIC 12.00 BASIC
HE 0.472 BASIC 12.00 BASIC
L 0.024 ± 0.006 0.60 ± 0.15
L1 0.039 REF 1.00 REF

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 SH79F642B
LQFP64 Outline Dimensions (BODY SIZE: 7×7) Unit: inch / mm
HD

64 49

1 48

HE
E
16 33

17 e b 32

c
A2

A
A1

See Detail F
L
L1
DETAIL F

Dimensions in inches Dimensions in mm

Symbol
MIN MAX MIN MAX
A --- 0.063 --- 1.600
A1 0.002 0.006 0.050 0.150
A2 0.053 0.057 1.350 1.450
D 0.272 0.280 6.900 7.100
E 0.272 0.280 6.900 7.100
HD 0.348 0.360 8.850 9.150
HE 0.348 0.360 8.850 9.150
b 0.007 0.009 0.170 0.240
e 0.016BSC 0.400BSC
c 0.004 0.008 0.090 0.200
L 0.018 0.030 0.450 0.750
L1 0.033 0.045 0.850 1.150
θ 0° 10° 0° 10°

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 SH79F642B
15. Datasheet Document History

Version Record Date

2.0 Original Version May. 2019

157