H - P, L - C T: IGH Erformance OW Urrent Ransceiver

S i 4 4 6 4 / 6 3 / 6 1/60
H I G H - P ERFORMANCE , L O W -C U R R E N T T RANSCEIVER
Features
 Frequency range = 119–1050 MHz  Fast wake and hop times
 Receive sensitivity = –126 dBm  Power supply = 1.8 to 3.6 V
 Modulation  Excellent selectivity performance
(G)FSK, 4(G)FSK, (G)MSK 60 dB adjacent channel
OOK and ASK 75 dB blocking at 1 MHz
 Max output power  Antenna diversity and T/R switch control

+20 dBm (Si4464/63)  Highly configurable packet handler
+16 dBm (Si4461)  TX and RX 64 byte FIFOs
+13 dBm (Si4460)  Auto frequency control (AFC)
 PA support for +27 or +30 dBm  Automatic gain control (AGC)
 Low active power consumption  Low BOM
10/13 mA RX  Low battery detector
18mA TX at +10 dBm (Si4460)  Temperature sensor
 Ultra low current powerdown modes 20-Pin QFN package Pin Assignments
30 nA shutdown, 50 nA standby  IEEE 802.15.4g compliant
GPIO3
GPIO2
XOUT
 Data rate = 0.123 kbps to 1 Mbps  FCC Part 90 Mask D
GND
XIN
 ETSI Class-I Operation with SAW
SDN 1 20 19 18 17 16
Applications RXp 2 15 nSEL
 Smart metering (802.15.4g & MBus)  Remote keyless entry RXn 3 GND 14 SDI
 Remote control  Home automation TX 4 PAD 13 SDO
 Home security and alarm  Industrial control
NC 5 12 SCLK
 Telemetry  Sensor networks
 Garage and gate openers  Health monitors 6 7 8 9 10 11 nIRQ
VDD
TXRamp
GPIO0
GPIO1
VDD
 Electronic shelf labels
Description
Silicon Laboratories' Si446x devices are high-performance, low-current Patents pending

transceivers covering the sub-GHz frequency bands from 119 to 1050 MHz.
The radios are part of the EZRadioPRO® family, which includes a complete
line of transmitters, receivers, and transceivers covering a wide range of
applications. All parts offer outstanding sensitivity of –126 dBm while
achieving extremely low active and standby current consumption. The Si4464
offers continuous frequency coverage across the entire sub-GHz band from
119–960 MHz with extremely fine frequency resolution. The Si4463 includes
optimal phase noise, blocking, and selectivity performance for narrow band
and licensed band applications, such as FCC Part90 and 169 MHz wireless
Mbus. The 60 dB adjacent channel selectivity with 12.5 kHz channel spacing
ensures robust receive operation in harsh RF conditions, which is particularly
important for narrowband operation. The Si4464/63 offers exceptional output
power of up to +20 dBm with outstanding TX efficiency. The high output
power and sensitivity results in an industry-leading link budget of 146 dB
allowing extended ranges and highly robust communication links. The Si4460
active mode TX current consumption of 18 mA at +11 dBm and RX current of
10 mA coupled with extremely low standby current and fast wake times
ensure extended battery life in the most demanding applications. The
Si4464/63 can achieve up to +27 dBm output power with built-in ramping
control of a low-cost external FET. The devices are compliant with all
worldwide regulatory standards: FCC, ETSI, and ARIB. All devices are
designed to be compliant with 802.15.4g and WMbus smart metering
standards.
Rev 1.0 2/12 Copyright © 2012 by Silicon Laboratories Si4464/63/62/61/60

Si4464/63/61/60
Functional Block Diagram
GPIO3 GPIO2 XIN XOUT
Loop
PFD / CP
Filter
VCO
FBDIV Frac-N Div 30 MHz XO
LO Bootup
TX DIV
Gen OSC
SDN IF
RF
PKDET PKDET
nSEL
SPI Interface
MODEM
Controller
RXP FIFO SDI
LNA PGA ADC SDO
RXN Packet
Handler SCLK
nIRQ
PowerRamp LDOs
TX PA
Cntl POR Digital
Logic
LBD
PA
32K LP
LDO
OSC
VDD TXRAMP VDD GPIO0 GPIO1
Product Freq. Range Max Output TX Current RX Current Narrow Image Cal +
Power Channel + IF Shift
Part90
Si4464 Continuous +20 dBm 169 MHz: 70 mA 10.6/13.6 mA  
119–960 MHz 915 MHz: 85 mA
Si4463 Major bands +20 dBm 169 MHz: 70 mA 10/13 mA  

142-1050 MHz 915 MHz: 85 mA
Si4461 Major bands +16 dBm +13 dBm: 29 mA 10/13 mA  

142-1050 MHz +14 dBm: 33 mA
Si4460 Major bands +13 dBm +10 dBm: 18 mA 10/13 mA  

142-1050 MHz +11 dBm: 20 mA
2 Rev 1.0
Si4464/63/61/60
TABLE O F C ONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1. Definition of Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2. Fast Response Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.3. Operating Modes and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4. Application Programming Interface (API) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5. START_TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.7. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4. Modulation and Hardware Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1. MODEM_MOD_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2. Modulation Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3. Hardware Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.4. Preamble Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5. Internal Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1. RX Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2. RX Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
5.4. Transmitter (TX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5.5. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
6. Data Handling and Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
6.1. RX and TX FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.2. Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7. RX Modem Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8. Auxiliary Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.1. Wake-up Timer and 32 kHz Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.2. Low Duty Cycle Mode (Auto RX Wake-Up) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
8.3. Temperature, Battery Voltage, and Auxiliary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.4. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
8.5. Antenna Diversity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9. Pin Descriptions: Si4464/63/62/61/60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11. Package Outline: Si4464/63/61/60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
12. PCB Land Pattern: Si4464/63/61/60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
13. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
13.1. Si4464/63/61/60 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Rev 1.0 3
Si4464/63/61/60
1. Electrical Specifications
Table 1. DC Characteristics1
Parameter Symbol Conditions Min Typ Max Units
Supply Voltage VDD 1.8 3.3 3.6 V
Range
Power Saving Modes IShutdown RC Oscillator, Main Digital Regulator, — 30 — nA
and Low Power Digital Regulator OFF
IStandby Register values maintained and RC — 50 — nA
oscillator/WUT OFF
ISleepRC RC Oscillator/WUT ON and all register values main- — 900 — nA
tained, and all other blocks OFF
ISleepXO Sleep current using an external 32 kHz crystal.2 — 1.7 — µA
ISensor Low battery detector ON, register values maintained, — 1 — µA
-LBD and all other blocks OFF
IReady Crystal Oscillator and Main Digital Regulator ON, — 1.8 — mA
all other blocks OFF
TUNE Mode Current ITune_RX RX Tune, High Performance Mode — 7.2 — mA
ITune_TX TX Tune, High Performance Mode — 8 — mA
RX Mode Current IRXH High Performance Mode — 13 — mA
IRXL Low Power Mode2 — 10 — mA
TX Mode Current ITX_+20 +20 dBm output power, class-E match, 915 MHz, — 85 — mA
(Si4464/63) 3.3 V
+20 dBm output power, class-E match, 460 MHz, — 75 — mA
3.3 V
+20 dBm output power, square-wave match, — 70 — mA
169 MHz, 3.3 V
TX Mode Current ITX_+16 +16 dBm output power, class-E match, 868 MHz, — 43 — mA
(Si4461) 3.3 V2
ITX_+14 +14 dBm output power, Switched-current match, — 37 — mA
868 MHz, 3.3 V2
ITX_+13 +13 dBm output power, switched-current match, — 29 — mA
868 MHz, 3.3 V2
TX Mode Current ITX_+10 +10 dBm output power, Class-E match, 868 MHz, — 18 — mA
(Si4460) 3.3 V2
Notes:
1. All specifications guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the "Production Test Conditions" section of "1.1. Definition of Test Conditions" on page 13.
2. Guaranteed by qualification. Qualification test conditions are listed in the “Qualification Test Conditions” section in "1.1.
Definition of Test Conditions" on page 13.
4 Rev 1.0
Si4464/63/61/60
Table 2. Synthesizer AC Electrical Characteristics1

Synthesizer Frequency FSYN 142 — 175 MHz
Range (Si4463/61/60)
284 — 350 MHz
425 — 525 MHz
850 — 1050 MHz
Synthesizer Frequency FSYN See Notes 1, 2, and 3 119 — 960 MHz

Range (Si4464)
Synthesizer Frequency FRES-960 850–1050 MHz — 28.6 — Hz
Resolution4
FRES-525 425–525 MHz — 14.3 — Hz
FRES-350 283–350 MHz — 9.5 — Hz
FRES-175 142–175 MHz — 4.7 — Hz
Synthesizer Settling Time2 tLOCK Measured from exiting Ready mode with — 50 — µs
XOSC running to any frequency.
Including VCO Calibration.
Phase Noise2 L(fM) F = 10 kHz, 460 MHz, High Perf Mode — –106 — dBc/Hz
F = 100 kHz, 460 MHz, High Perf Mode — –110 — dBc/Hz
F = 1 MHz, 460 MHz, High Perf Mode — –123 — dBc/Hz
F = 10 MHz, 460 MHz, High Perf Mode — –130 — dBc/Hz
Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the “Production Test Conditions” section in "1.1. Definition of Test Conditions" on page 13.
2. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.
3. For applications that use the major bands covered by Si4463/61/60, customers should use those parts instead of
Si4464.
4. Default API setting for modulation deviation resolution is double the typical value specified.
Rev 1.0 5
Si4464/63/61/60
Table 3. Receiver AC Electrical Characteristics1
RX Frequency FRX 142 — 175 MHz

Range (Si4463/61/60) 284 — 350 MHz
425 — 525 MHz
850 — 1050 MHz
RX Frequency FRX See Notes 1, 2, 3, 4, and 5 119 — 960 MHz
Range (Si4464)
RX Sensitivity PRX_0.5 (BER < 0.1%) — –126 — dBm
(500 bps, GFSK, BT = 0.5,
f = 250Hz)3
PRX_40 (BER < 0.1%) — –110 — dBm
(40 kbps, GFSK, BT = 0.5,
f = 20 kHz)3
PRX_100 (BER < 0.1%) — –106 — dBm
(100 kbps, GFSK, BT = 0.5,
f = 50 kHz)1
PRX_125 (BER < 0.1%) — –105 — dBm
(125 kbps, GFSK, BT = 0.5,
f = 62.5 kHz)3
PRX_500 (BER < 0.1%) — –97 — dBm
(500 kbps, GFSK, BT = 0.5,
f = 250 kHz)3
PRX_9.6 (PER 1%) — –110 — dBm
(9.6 kbps, 4GFSK, BT = 0.5,
f =  kHz)3,4
PRX_1M (PER 1%) — –88 — dBm
(1 Mbps, 4GFSK, BT = 0.5,
f = 1.25 kHz)3,4
PRX_OOK (BER < 0.1%, 4.8 kbps, 350 kHz BW, — –109 — dBm
OOK, PN15 data)3
(BER < 0.1%, 40 kbps, 350 kHz BW, — –104 — dBm
OOK, PN15 data)3
(BER < 0.1%, 120 kbps, 350 kHz BW, — –99 — dBm
OOK, PN15 data)3
RX Channel Bandwidth5 BW 1.1 — 850 kHz
Notes:
listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 13.
Si4464.
4. For PER tests, 48 preamble symbols, 4 byte sync word, 10 byte payload and CRC-32 was used. PER and BER tested
in the 450–470 MHz band.
5. Guaranteed by bench characterization.
6 Rev 1.0
Si4464/63/61/60
Table 3. Receiver AC Electrical Characteristics1 (Continued)
BER Variation vs Power PRX_RES Up to +5 dBm Input Level — 0 0.1 ppm

Level3
RSSI Resolution RESRSSI — ±0.5 — dB
1-Ch Offset Selectivity, C/I1-CH Desired Ref Signal 3 dB above sensitiv- — –60 — dB
169 MHz3 ity, BER < 0.1%. Interferer is CW, and
1-Ch Offset Selectivity, C/I1-CH desired is modulated with 2.4 kbps — –58 — dB
450 MHz3 F = 1.2 kHz GFSK with BT = 0.5, RX
channel BW=4.8 kHz,
1-Ch Offset Selectivity, C/I1-CH channel spacing = 12.5 kHz — –53 — dB
868 / 915 MHz3
Blocking 1 MHz Offset3 1MBLOCK Desired Ref Signal 3 dB above sensitiv- — –75 — dB
ity. Interferer is CW, and desired is
modulated with 2.4 kbps,
F = 1.2 kHz GFSK
Blocking 8 MHz Offset3 8MBLOCK — –84 — dB
Image Rejection3 ImREJ No image rejection calibration. Rejec- — 35 — dB

tion at the image frequency.
IF = 468 kHz
With image rejection calibration in — 55 — dB
Si446x. Rejection at the image fre-
quency. IF = 468 kHz
Spurious Emissions3 POB_RX1 Measured at RX pins — — –54 dBm
Notes:
Si4464.
4. For PER tests, 48 preamble symbols, 4 byte sync word, 10 byte payload and CRC-32 was used. PER and BER tested
in the 450–470 MHz band.
5. Guaranteed by bench characterization.
Rev 1.0 7
Si4464/63/61/60
Table 4. Transmitter AC Electrical Characteristics1

TX Frequency
142 — 175 MHz
Range (Si4463/61/60)
284 — 350 MHz

FTX
425 — 525 MHz
850 — 1050 MHz
TX Frequency
Range (Si4464)
FTX See Notes 1, 2,3, 4, 5, and 6 119 — 960 MHz
(G)FSK Data Rate2,3 DRFSK 0.123 — 500 kbps
4(G)FSK Data Rate2,3 DR4FSK 0.123 — 1 Mbps
OOK Data Rate2,3 DROOK 0.123 — 120 kbps

Modulation Deviation f960 850–1050 MHz — 1.5 — MHz
Range2
f525 425–525 MHz — 750 — kHz
f350 283–350 MHz — 500 — kHz
f175 142–175 MHz — 250 — kHz

Modulation Deviation FRES-960 850–1050 MHz — 28.6 — Hz
Resolution2,4
FRES-525 425–525 MHz — 14.3 — Hz
FRES-350 283–350 MHz — 9.5 — Hz
FRES-175 142–175 MHz — 4.7 — Hz

Output Power Range
PTX –20 — +20 dBm
(Si4464/63)5
Output Power Range
PTX61 –40 — +16 dBm
(Si4461)5
Output Power Range
PTX60 –40 — +13 dBm
(Si4460)5
TX RF Output Steps2 PRF_OUT
Using switched current match within
— 0.1 — dB
6 dB of max power
Notes:
3. The maximum data rate is dependant on the XTAL frequency and is calculated as per the formula:
Maximum Symbol Rate = Fxtal/60, where Fxtal is the XTAL frequency (typically 30 MHz).
5. Output power is dependent on matching components and board layout.
Si4464.
8 Rev 1.0
Si4464/63/61/60
Table 4. Transmitter AC Electrical Characteristics1 (Continued)
TX RF Output Level2
PRF_TEMP –40 to +85 C — 1 — dB
Variation vs. Temperature
TX RF Output Level
Variation vs. Frequency2 PRF_FREQ Measured across 902–928 MHz — 0.5 — dB
Transmit Modulation Gaussian Filtering Bandwith Time

Filtering2 B*T — 0.5 —
Product
Spurious Emissions2 POUT = +13 dBm,
POB-TX1 — — –54 dBm
Frequencies <1 GHz
POB-TX2 1–12.75 GHz, excluding harmonics — — –42 dBm
2
Harmonics P2HARM Using reference design TX matching — — –42 dBm
network and filter with max output
P3HARM power. Harmonics reduce linearly with — — –42 dBm
output power.
Notes:
3. The maximum data rate is dependant on the XTAL frequency and is calculated as per the formula:
Maximum Symbol Rate = Fxtal/60, where Fxtal is the XTAL frequency (typically 30 MHz).
5. Output power is dependent on matching components and board layout.
Si4464.
Rev 1.0 9
Si4464/63/61/60
Table 5. Auxiliary Block Specifications1
Temperature Sensor TSS — 1.78 — mV/°C

Sensitivity2
Low Battery Detector LBDRES — 50 — mV
Resolution
Microcontroller Clock FMC Configurable to Fxtal or Fxtal 32.768K — Fxtal Hz
Output Frequency Range3 divided by 2, 3, 7.5, 10, 15, or
30 where Fxtal is the reference
XTAL frequency. In addition,
32.768 kHz is also supported.
Temperature Sensor TEMPCT Programmable setting — 3 — ms
Conversion2
XTAL Range4 XTALRange 25 32 MHz
30 MHz XTAL Start-Up Time t30M Using XTAL and board layout in — 250 — µs
reference design. Start-up time
will vary with XTAL type and
board layout.
30 MHz XTAL Cap 30MRES
— 70 — fF
Resolution2
32 kHz XTAL Start-Up Time2 t32k — 2 — sec
32 kHz Accuracy using 32KRCRES — 2500 — ppm
Internal RC Oscillator2
POR Reset Time tPOR — — 5 ms
Notes:
3. Microcontroller clock frequency tested in production at 1 MHz, 30 MHz and 32.768 kHz. Other frequencies tested in
bench characterization.
4. XTAL Range tested in production using an external clock source (similar to using a TCXO).
10 Rev 1.0
Si4464/63/61/60
Table 6. Digital IO Specifications (GPIO_x, SCLK, SDO, SDI, nSEL, nIRQ)1

Symbol Conditions Min Typ Max Units
Parameter
Rise Time2,3 TRISE 0.1 x VDD to 0.9 x VDD, — 2.3 — ns
CL = 10 pF,
DRV<1:0> = HH
Fall Time3,4 TFALL 0.9 x VDD to 0.1 x VDD, — 2 — ns
CL = 10 pF,
DRV<1:0> = HH
Input Capacitance CIN — 2 — pF
Logic High Level Input Voltage VIH VDD x 0.7 — — V
Logic Low Level Input Voltage VIL — — VDD x 0.3 V
Input Current IIN 0<VIN< VDD –10 — 10 µA
Input Current If Pullup is Activated IINP VIL = 0 V 1 — 10 µA
3
Drive Strength for Output Low IOmaxLL DRV[1:0] = LL — 18.7 — mA
Level IOmaxLH DRV[1:0] = LH 3
— 13.7 — mA
IOmaxHL DRV[1:0] = HL3 — 8.5 — mA
3
IOmaxHH DRV[1:0] = HH — 3 — mA
3
Drive Strength for Output High IOmaxLL DRV[1:0] = LL — 15.3 — mA
Level IOmaxLH DRV[1:0] = LH3 — 11.6 — mA
3
IOmaxHH DRV[1:0] = HH — 2.7 — mA
Drive Strength for Output High IOmaxLL DRV[1:0] = LL3 — 6.3 — mA
Level for GPIO0 3
IOmaxLH DRV[1:0] = LH — 5.6 — mA
IOmaxHH DRV[1:0] = HH3 — 2.1 — mA
Logic High Level Output Voltage VOH DRV[1:0] = HL VDD x 0.8 — — V
Logic Low Level Output Voltage VOL DRV[1:0] = HL — — VDD x 0.2 V
Notes:
1. All specifications guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test
Conditions" section in "1.1. Definition of Test Conditions" on page 13.
2. 8 ns is typical for GPIO0 rise time.
3. For 3.3 V at room temperature.
4. 2.4 ns is typical for GPIO0 fall time.
Rev 1.0 11
Si4464/63/61/60
Table 7. Absolute Maximum Ratings

Parameter Value Unit
VDD to GND –0.3, +3.6 V
Instantaneous VRF-peak to GND on TX Output Pin –0.3, +8.0 V
Sustained VRF-peak to GND on TX Output Pin –0.3, +6.5 V
Voltage on Digital Control Inputs –0.3, VDD + 0.3 V
Voltage on Analog Inputs –0.3, VDD + 0.3 V
RX Input Power +10 dBm
Operating Ambient Temperature Range TA –40 to +85 C
Thermal Impedance JA 30 C/W
Junction Temperature TJ +125 C
Storage Temperature Range TSTG –55 to +125 C
Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at or beyond these ratings in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Power Amplifier may be damaged if switched on without proper load or termination connected. TX
matching network design will influence TX VRF-peak on TX output pin. Caution: ESD sensitive device.
12 Rev 1.0
Si4464/63/61/60
1.1. Definition of Test Conditions
Production Test Conditions:
TA = +25 °C
VDD = +3.3 VDC
Sensitivitymeasured at 920 MHz
TX output power measured at 915 MHz
External reference signal (XOUT) = 1.0 VPP at 30 MHz, centered around 0.8 VDC
Production test schematic (unless noted otherwise)
All RF input and output levels referred to the pins of the Si4464/63/61/60 (not the RF module)
Qualification Test Conditions:

TA = –40 to +85 °C (Typical TA = 25 °C)
VDD = +1.8 to +3.6 VDC (Typical VDD = 3.3 VDC)
Using TX/RX Split Antenna reference design or production test schematic
All RF input and output levels referred to the pins of the Si4464/63/61/60 (not the RF module)
Rev 1.0 13
Si4464/63/61/60
2. Functional Description
The Si446x devices are high-performance, low-current, wireless ISM transceivers that cover the sub-GHz bands.
The wide operating voltage range of 1.8–3.6 V and low current consumption make the Si446x an ideal solution for
battery powered applications. The Si446x operates as a time division duplexing (TDD) transceiver where the
device alternately transmits and receives data packets. The device uses a single-conversion mixer to downconvert
the 2/4-level FSK/GFSK or OOK/ASK modulated receive signal to a low IF frequency. Following a programmable
gain amplifier (PGA) the signal is converted to the digital domain by a high performance  ADC allowing filtering,
demodulation, slicing, and packet handling to be performed in the built-in DSP increasing the receiver’s
performance and flexibility versus analog based architectures. The demodulated signal is output to the system
MCU through a programmable GPIO or via the standard SPI bus by reading the 64-byte RX FIFO.
A single high precision local oscillator (LO) is used for both transmit and receive modes since the transmitter and
receiver do not operate at the same time. The LO is generated by an integrated VCO and  Fractional-N PLL
synthesizer. The synthesizer is designed to support configurable data rates from 0.123 kbps to 1 Mbps. The
Si4463/61/60 operate in the frequency bands of 142–175, 283–350, 425–525, and 850–1050 MHz with a
maximum frequency accuracy step size of 28.6 Hz. The Si4464 offers continuous freq coverage across the entire
119–960 MHz band. The transmit FSK data is modulated directly into the  data stream and can be shaped by a
Gaussian low-pass filter to reduce unwanted spectral content.
The Si4464/63 contains a power amplifier (PA) that supports output power up to +20 dBm with very high efficiency,
consuming only 70 mA at 169 MHz and 85 mA at 915 MHz. The integrated +20 dBm power amplifier can also be
used to compensate for the reduced performance of a lower cost, lower performance antenna or antenna with size
constraints due to a small form-factor. Competing solutions require large and expensive external PAs to achieve
comparable performance. The Si4461 supplies output power up to +16 dBm. The Si4460 is designed to support
single coin cell operation with current consumption below 18 mA for +10 dBm output power. Two match topologies
are available for the Si4461 and Si4460, class-E and switched-current. Class-E matching provides optimal current
consumption, while switched-current matching demonstrates the best performance over varying battery voltage
and temperature with slightly higher current consumption. The PA is single-ended to allow for easy antenna
matching and low BOM cost. The PA incorporates automatic ramp-up and ramp-down control to reduce unwanted
spectral spreading. The Si446x family supports frequency hopping, TX/RX switch control, and antenna diversity
switch control to extend the link range and improve performance. Built-in antenna diversity and support for
frequency hopping can be used to further extend range and enhance performance. Antenna diversity is completely
integrated into the Si446x and can improve the system link budget by 8–10 dB, resulting in substantial range
increases under adverse environmental conditions. A highly configurable packet handler allows for autonomous
encoding/decoding of nearly any packet structure. Additional system features, such as an automatic wake-up
timer, low battery detector, 64 byte TX/RX FIFOs, and preamble detection, reduce overall current consumption and
allows for the use of lower-cost system MCUs. An integrated temperature sensor, power-on-reset (POR), and
GPIOs further reduce overall system cost and size. The Si446x is designed to work with an MCU, crystal, and a
few passive components to create a very low-cost system.
The application shown in Figure 1 is designed for a system with a TX/RX direct-tie configuration without the use of
a TX/RX switch. Most applications with output power less than 17 dBm will use this configuration. Figure 2
demonstrates an application for +20 dBm using an external T/R-switch.
14 Rev 1.0
Si4464/63/61/60
30 MHz
GPIO2
GPIO3
XOUT
GND
XIN
C6
Microcontroller
20 19 18 17 16
SDN nSEL GP1
1 15
RXp SDI GP2
L5 2 14
C2
L4 L3 RXn SDO GP3
3 Si4461 13
L2 TX SCLK GP4
4 12
NC nIRQ GP5
C4 C1 5 11
C5 C3 6 7 8 9 10
L1
VDD
TXRAMP
GPIO0
GPIO1
VDD
VDD
C7 C8 C9
100 p 100 n 1u
Figure 1. Si4461 Direct-Tie Application Example
30 MHz
GPIO2
GPIO3
XOUT
GND
XIN
C7
Microcontroller
20 19 18 17 16
SDN nSEL GP1
1 15
RXp SDI GP2
L5 2 14
C6
L4 RXn SDO GP3
3 Si4463 13
L3 L2 TX SCLK GP4
4 12
NC nIRQ GP5
C4 C1 5 11
C5 6 7 8 9 10
C3 C2 L1
VDD
TXRAMP
GPIO0
GPIO1
VDD
VDD
Figure 2. Si4463 Single Antenna with RF Switch Example
Rev 1.0 15
Si4464/63/61/60
3. Controller Interface
3.1. Serial Peripheral Interface (SPI)
The Si446x communicates with the host MCU over a standard 4-wire serial peripheral interface (SPI): SCLK, SDI,
SDO, and nSEL. The SPI interface is designed to operate at a maximum of 10 MHz. The SPI timing parameters
are demonstrated in Table 8. The host MCU writes data over the SDI pin and can read data from the device on the
SDO output pin. Figure 3 demonstrates an SPI write command. The nSEL pin should go low to initiate the SPI
command. The first byte of SDI data will be one of the firmware commands followed by n bytes of parameter data
which will be variable depending on the specific command. The rising edges of SCLK should be aligned with the
center of the SDI data.
Table 8. Serial Interface Timing Parameters

Symbol Parameter Min (ns) Diagram
tCH Clock high time 40
tCL Clock low time 40

SCLK
tDS Data setup time 20
tSS tCL tCH tDS tDH tDD tSH tDE
tDH Data hold time 20
SDI
tDD Output data delay time 20
tEN Output enable time 20
tDE Output disable time 50 SDO
tSS Select setup time 20 tEN tSW
nSEL
tSH Select hold time 50
tSW Select high period 80
nSEL
SDO
SDI FW Command Param Byte 0 Param Byte n
SCLK
Figure 3. SPI Write Command

The Si446x contains an internal MCU which controls all the internal functions of the radio. For SPI read commands
a typical MCU flow of checking clear-to-send (CTS) is used to make sure the internal MCU has executed the
command and prepared the data to be output over the SDO pin. Figure 4 demonstrates the general flow of an SPI
read command. Once the CTS value reads FFh then the read data is ready to be clocked out to the host MCU. The
typical time for a valid FFh CTS reading is 20 µs. Figure 5 demonstrates the remaining read cycle after CTS is set
to FFh. The internal MCU will clock out the SDO data on the negative edge so the host MCU should process the
SDO data on the rising edge of SCLK.
16 Rev 1.0
Si4464/63/61/60
Firmware Flow
0xFF Retrieve
Send Command Read CTS CTS Value
Response
0x00
NSEL
SDO CTS
SDI ReadCmdBuff
SCK
Figure 4. SPI Read Command—Check CTS Value
NSEL
SDO Response Byte 0 Response Byte n
SDI
SCK
Figure 5. SPI Read Command—Clock Out Read Data
Rev 1.0 17
Si4464/63/61/60
3.2. Fast Response Registers
The fast response registers are registers that can be read immediately without the requirement to monitor and
check CTS. There are four fast response registers that can be programmed for a specific function. The fast
response registers can be read through API commands, 0x51 for Fast Response A, 0x53 for Fast Response B,
0x55 for Fast Response C, and 0x57 for Fast Response D. The fast response registers can be configured by the
“FRR_CTL_X_MODE” properties.
The fast response registers may be read in a burst fashion. After the initial 16 clock cycles, each additional eight
clock cycles will clock out the contents of the next fast response register in a circular fashion.
3.3. Operating Modes and Timing
The primary states of the Si446x are shown in Figure 6. The shutdown state completely shuts down the radio to
minimize current consumption. Standby/Sleep, SPI Active, Ready, TX Tune, and RX tune are available to optimize
the current consumption and response time to RX/TX for a given application. API commands START_RX,
START_TX, and CHANGE_STATE control the operating state with the exception of shutdown which is controlled
by SDN, pin 1. Table 9 shows each of the operating modes with the time required to reach either RX or TX mode as
well as the current consumption of each mode. The times in Table 9 are measured from the rising edge of nSEL
until the chip is in the desired state. An automatic sequencer will put the chip into RX or TX from any state. It is not
necessary to manually step through the states. To simplify the diagram it is not shown but any of the lower power
states can be returned to automatically after RX or TX.
Figure 6. State Machine Diagram
Table 9. Operating State Response Time and Current Consumption

Response Time to Current in State
State/Mode
TX RX /Mode
Shutdown State 15 ms 15 ms 30 nA
Standby State 460 µs 460 µs 50 nA
Sleep State 460 µs 460 µs 900 nA
SPI Active State 300 µs 310 µs 1.35 mA
Ready State 130 µs 140 µs 1.8 mA
TX Tune State 65 µs 8 mA
RX Tune State 90 µs 7.2 mA
TX State — 120 µs 18 mA @ +10 dBm
RX State 120 µs 75 µs 10 or 13 mA
18 Rev 1.0
Si4464/63/61/60
Figure 7 demonstrates the timing and current consumption in each mode associated with commanding the chip
from shutdown to TX state. Figure 8 demonstrates the timing and current consumption for each state associated
with commanding the chip from standby to TX state. The most advantageous state to use will depend on the duty
cycle of the application or how often the part is in either RX or TX state. In most applications the utilization of the
standby state will be most advantageous for battery life but for very low duty cycle applications shutdown will have
an advantage. For the fastest timing the next state can be selected in the START_RX or START_TX API
commands to minimize SPI transactions and internal MCU processing.
TX = 19 mA
Tune = 100 [email protected] mA
Ready = 300 [email protected]

mA
POR = 1 [email protected] mA
Reg Inrush = 5 usec@2 mA
POWER_UP 14 msec@2 mA
Standby = 10 usec@50 nA
Shutdown = 30 nA Shutdown = 30 nA
Figure 7. Start-Up Timing and Current Consumption using Shutdown State
Tune = 100 [email protected] mA
TX = 19 mA
Ready = 375 [email protected] mA
Reg Inrush = 5 usec@1 mA
Standby = 50 nA Standby = 50 nA
Figure 8. Start-Up Timing and Current Consumption using Standby State
Rev 1.0 19
Si4464/63/61/60
3.3.1. Shutdown State
The shutdown state is the lowest current consumption state of the device with nominally less than 30 nA of current
consumption. The shutdown state may be entered by driving the SDN pin (Pin 1) high. The SDN pin should be held
low in all states except the shutdown state. In the shutdown state, the contents of the registers are lost and there is
no SPI access. When coming out of the shutdown state a power on reset (POR) will be initiated along with the
internal calibrations. After the POR the POWER_UP command is required to initialize the radio. The SDN pin
needs to be held high for at least 10us before driving low again so that internal capacitors can discharge. Not
holding the SDN high for this period of time may cause the POR to be missed and the device to boot up incorrectly.
3.3.2. Standby State
Standby state has the lowest current consumption with the exception of shutdown but has much faster response
time to RX or TX mode. In most cases standby should be used as the low power state. In this state the register
values are maintained with all other blocks disabled. The SPI is accessible during this mode but any SPI event,
including FIFO R/W, will enable an internal boot oscillator and automatically move the part to SPI active state. After
an SPI event the host will need to re-command the device back to standby through the “Change State” API
command to achieve the 50 nA current consumption. If an interrupt has occurred (i.e., the nIRQ pin = 0) the
interrupt registers must be read to achieve the minimum current consumption of this mode.
3.3.3. Sleep State
Sleep state is the same as standby state but the wake-up-timer and a 32 kHz clock source are enabled. The
source of the 32 kHz clock can either be an internal 32 kHz RC oscillator which is periodically calibrated or a
32 kHz oscillator using an external XTAL.The SPI is accessible during this mode but an SPI event will enable an
internal boot oscillator and automatically move the part to SPI active mode. After an SPI event the host will need to
re-command the device back to sleep. If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers
must be read to achieve the minimum current consumption of this mode.
3.3.4. SPI Active State
In SPI active state the SPI and a boot up oscillator are enabled. After SPI transactions during either standby or
sleep the device will not automatically return to these states. A “Change State” API command will be required to
return to either the standby or sleep modes.
3.3.5. Ready State
Ready state is designed to give a fast transition time to TX or RX state with reasonable current consumption. In this
mode the Crystal oscillator remains enabled reducing the time required to switch to TX or RX mode by eliminating
the crystal start-up time.
3.3.6. TX State
The TX state may be entered from any of the state with the “Start TX” or “Change State” API commands. A built-in
sequencer takes care of all the actions required to transition between states from enabling the crystal oscillator to
ramping up the PA. The following sequence of events will occur automatically when going from standby to TX state.
1. Enable internal LDOs.
2. Start up crystal oscillator and wait until ready (controlled by an internal timer).
3. Enable PLL.
4. Calibrate VCO/PLL.
5. Wait until PLL settles to required transmit frequency (controlled by an internal timer).
6. Activate power amplifier and wait until power ramping is completed (controlled by an internal timer).
7. Transmit packet.
Steps in this sequence may be eliminated depending on which state the chip is configured to prior to commanding
to TX. By default, the VCO and PLL are calibrated every time the PLL is enabled. When the START_TX API
command is utilized the next state may be defined to ensure optimal timing and turnaround.
20 Rev 1.0
Si4464/63/61/60
Figure 9 shows an example of the commands and timing for the START_TX command. CTS will go high as soon
as the sequencer puts the part into TX state. As the sequencer is stepping through the events listed above, CTS
will be low and no new commands or property changes are allowed. If the Fast Response (FRR) or nIRQ is used to
monitor the current state there will be slight delay caused by the internal hardware from when the event actually
occurs to when the transition occurs on the FRR or nIRQ. The time from entering TX state to when the FRR will
update is 5 µs and the time to when the nIRQ will transition is 13 µs. If a GPIO is programmed for TX state or used
as control for a transmit/receive switch (TR switch) there is no delay.
CTS
NSEL
SDI START_TX
Current State YYY State Tx State TXCOMPLETE_STATE
FRR YYY State Tx State TXCOMPLETE_STATE
nIRQ
GPIOx – TX state
Figure 9. Start_TX Commands and Timing

3.3.7. RX State
The RX state may be entered from any of the other states by using the “Start RX” or “Change State” API command.
A built-in sequencer takes care of all the actions required to transition between states. The following sequence of
events will occur automatically to get the chip into RX mode when going from standby to RX state:
1. Enable the digital LDO and the analog LDOs.
2. Start up crystal oscillator and wait until ready (controlled by an internal timer).
3. Enable PLL.
4. Calibrate VCO
5. Wait until PLL settles to required receive frequency (controlled by an internal timer).
6. Enable receiver circuits: LNA, mixers, and ADC.
7. Enable receive mode in the digital modem.
Depending on the configuration of the radio, all or some of the following functions will be performed automatically
by the digital modem: AGC, AFC (optional), update status registers, bit synchronization, packet handling (optional)
including sync word, header check, and CRC. Similar to the TX state, the next state after RX may be defined in the
“Start RX” API command. The START_RX commands and timing will be equivalent to the timing shown in Figure 9.
Rev 1.0 21
Si4464/63/61/60
3.4. Application Programming Interface (API)
An application programming interface (API), which the host MCU will communicate with, is embedded inside the
device. The API is divided into two sections, commands and properties. The commands are used to control the
chip and retrieve its status. The properties are general configurations which will change infrequently. The available
commands are shown in Table 10.
Table 10. API Commands

Number Name Description
0x00 NOP No operation command
0x01 PART_INFO Reports basic information about the device
0x02 POWER_UP Boot options and XTAL freq offset
0x10 FUNC_INFO Returns the function revision information of the device
0x11 SET_PROPERTY Sets the value of a property
0x12 GET_PROPERTY Retrieves the value of a property
0x13 GPIO_PIN_CFG Configures the GPIO pins
0x14 GET_SENSOR_READING Retrieves temp sensor, low battery detector, or ADC reading
0x15 FIFO_RESET Resets the TX and RX FIFO
0x20 GET_INT_STATUS Returns the interrupt status
0x21 GET_PH_STATUS Returns the packet handler status and interrupts
0x22 GET_MODEM_STATUS Returns the modem status and interrupts
0x23 GET_CHIP_STATUS Returns the chip status and interrupts
0x31 START_TX Changes to TX state and configures common parameters
0x32 START_RX Changes to RX state and configures common parameters
REQUEST_DEVICE_ Returns current device state

0x33
STATE
0x34 CHANGE_STATE Commands the part to any of the defined states or modes
0x50 FAST RESPONSE A Fast response registers for faster read access
0x51 FAST RESPONSE B Fast response registers for faster read access
0x53 FAST RESPONSE C Fast response registers for faster read access
0x57 FAST RESPONSE D Fast response registers for faster read access
0x66 TX_FIFO_WRITE Write data to TX FIFO
0x77 RX_FIFO_READ Read data from RX FIFO
22 Rev 1.0
Si4464/63/61/60
The complete command and property descriptions are provided in “AN625: Si446x API Descriptions”. The
START_TX command is described in “3.5. START_TX” as an example. If a property has previously been set or a
default configuration is sufficient it is not necessary to write all arguments. For instance if the user wants to
command the part to TX state with the default or previous settings for CHANNEL[7:0], TXCOMPLETE_STATE[3:0],
etc then only the CMD 0x31 needs to be sent. It is not necessary to send the remaining arguments unless it is
desired to change these arguments.
3.5. START_TX
Summary: Switches to TX state and starts packet transmission.
Purpose:
Switches to TX state when condition is met. Command arguments are retained though sleep state, so they only
need to be written when they change. CTS will not return high until in TX state.
Command Stream
START_TX Command 7 6 5 4 3 2 1 0
CMD 0x31
CHANNEL CHANNEL[7:0]
CONDITION TXCOMPLETE_STATE[3:0] 0 RETRANSMIT START[1:0]
TX_LEN TX_LEN[15:8]
TX_LEN TX_LEN[7:0]
Reply Stream
START_TX Reply 7 6 5 4 3 2 1 0
CMD_COMPLETE CTS[7:0]
Parameters:
CHANNEL[7:0] - Channel number to transmit the packet on. Frequency is determined using integer, fractional, and
step size properties in the FREQ_CONTROL property group. This value will be overwritten with
START_RX:CHANNEL
TXCOMPLETE_STATE[7:4] - State to go to when current packet transmission completes.
0 = No change
1 = Sleep state.
2 = Spi Active state.
3 = Ready state.
4 = Another enumeration for Ready state.
5 = Tune state for TX.
6 = Tune state for RX.
7 = TX state.
8 = RX state.
RETRANSMIT
0 = Send data that has been written to fifo. If fifo is empty a fifo underflow interrupt will occur.
1 = Send last packet again. If this option is used, ensure that no new data is written to the fifo.
START[1:0]
0 = Start TX immediately.
1 = Start TX when wake up timer expires.
TX_LEN[15:0] - If this field is nonzero, the packet will be transmitted using only field 1 with no packet handler
features (eg. crc, whitening). If this field is zero, the configuration of the packet handler fields is used. If
RETRANSMIT is set, this field is ignored.
Response
None
Rev 1.0 23
Si4464/63/61/60
3.6. Interrupts
The Si446x is capable of generating an interrupt signal when certain events occur. The chip notifies the
microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal
will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) occur.
The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Registers. The nIRQ output signal
will then be reset until the next change in status is detected.
The interrupts sources are grouped into three groups: packet handler, chip status, and modem. The individual
interrupts in these groups can be enabled/disabled in the interrupt property registers, 0101, 0102, and 0103. An
interrupt must be enabled for it to trigger an event on the nIRQ pin. The interrupt group must be enabled as well as
the individual interrupts in API property 0100.
Number Command Summary

Returns the interrupt status—packet handler, modem,
0x20 GET_INT_STATUS
and chip
0x21 GET_PH_STATUS Returns the packet handler status.
0x22 GET_MODEM_STATUS Returns the modem status byte.
0x23 GET_CHIP_STATUS Returns the chip status.
Number Property Default Summary

Enables interrupt groups for PH, Modem, and
0x0100 INT_CTL_ENABLE 0x04
Chip.
0x0101 INT_CTL_PH_ENABLE 0x00 Packet handler interrupt enable property.
0x0102 INT_CTL_MODEM_ENABLE 0x00 Modem interrupt enable property.
0x0103 INT_CTL_CHIP_ENABLE 0x04 Chip interrupt enable property.
Once an interrupt event occurs and the nIRQ pin is low there are two ways to read and clear the interrupts. All of
the interrupts may be read and cleared in the “GET_INT_STATUS” API command. By default all interrupts will be
cleared once read. If only specific interrupts want to be read in the fastest possible method the individual interrupt
groups (Packet Handler, Chip Status, Modem) may be read and cleared by the “GET_MODEM_STATUS”,
“GET_PH_STATUS” (packet handler), and “GET_CHIP_STATUS” API commands.
The instantaneous status of a specific function maybe read if the specific interrupt is enabled or disabled. The
status results are provided after the interrupts and can be read with the same commands as the interrupts. The
status bits will give the current state of the function whether the interrupt is enabled or not.
The fast response registers can also give information about the interrupt groups but reading the fast response
registers will not clear the interrupt and reset the nIRQ pin.
24 Rev 1.0
Si4464/63/61/60
3.7. GPIO
Four general purpose IO pins are available to utilize in the application. The GPIO are configured by the
GPIO_PIN_CFG command in address 13h. For a complete list of the GPIO options please see the API guide.
GPIO pins 0 and 1 should be used for active signals such as data or clock. GPIO pins 2 and 3 have more
susceptibility to generating spurious in the synthesizer than pins 0 and 1. The drive strength of the GPIO’s can be
adjusted with the GEN_CONFIG parameter in the GPIO_PIN_CFG command. By default the drive strength is set
to minimum. The default configuration for the GPIOs and the state during SDN is shown below in Table 11.The
state of the IO during shutdown is also shown inTable 11.
Table 11. GPIOs

Pin SDN State POR Default
GPIO0 0 POR
GPIO1 0 CTS
GPIO2 0 POR
GPIO3 0 POR
nIRQ resistive VDD pull-up nIRQ
SDO resistive VDD pull-up SDO
SDI High Z SDI
Rev 1.0 25
Si4464/63/61/60
4. Modulation and Hardware Configuration Options
The Si446x supports different modulation options and can be used in various configurations to tailor the device to
any specific application or legacy system for drop in replacement. The modulation and configuration options are set
in API property, MODEM_MOD_TYPE.
4.1. MODEM_MOD_TYPE
Summary: Modulation Type
Purpose:
This property selects between OOK, FSK, 4FSK and GFSK modulation, modulation source, and tx direct mode
control.
The modulator must be configured for one mode through the entire packet. If portions of the packet alternate
between FSK and 4FSK modes, the modem should be programmed to 4FSK mode.
Property: 0x2000
Default: 0x02
Fields:
TX_DIRECT_MODE_TYPE - default:0
0 = Direct mode operates in synchronous mode, applies to TX only.
1 = Direct mode operates in asynchronous mode, applies to TX only. GFSK is not supported.
TX_DIRECT_MODE_GPIO[1:0] - default:0x0
0 = TX direct mode uses gpio0 as data source, applies to TX only.
MOD_SOURCE[1:0] - default:0x0
0 = Modulation source is packet handler fifo
1 = Modulation source is direct mode pin
2 = Modulation source is pseudo-random generator
MOD_TYPE[2:0] - default:0x2
0 = CW
1 = OOK
2 = 2FSK
3 = 2GFSK
4 = 4FSK
5 = 4GFSK
Register View
MODEM_MOD_TYPE
7 6 5 4 3 2 1 0
TX_DIRECT_MODE_TYPE TX_DIRECT_MODE_GPIO[1:0] MOD_SOURCE[1:0] MOD_TYPE[2:0]
0 0x0 0x0 0x2
26 Rev 1.0
Si4464/63/61/60
4.2. Modulation Types
The Si446x supports five different modulation options: Gaussian frequency shift keying (GFSK), frequency-shift
keying (FSK), four-level GFSK (4GFSK), four-level FSK (4FSK), on-off keying (OOK), and amplitude-shift keying
(ASK). Minimum shift keying (MSK) can also be created by using GFSK settings. GFSK is the recommended
modulation type as it provides the best performance and cleanest modulation spectrum. The modulation type is set
by the “MOD_TYPE[2:0]” registers in the “MODEM_MOD_TYPE” API property. A continuous-wave (CW) carrier
may also be selected for RF evaluation purposes. The modulation source may also be selected to be a
pseudo-random source for evaluation purposes.
4.3. Hardware Configuration Options
There are different receive demodulator options to optimize the performance and mutually-exclusive options for
how the RX/TX data is transferred from the host MCU to the RF device.
4.3.1. Receive Demodulator Options
There are multiple demodulators integrated into the device to optimize the performance for different applications,
modulation formats, and packet structures. The calculator built into WDS will choose the optimal demodulator
based on the input criteria.
4.3.1.1. Synchronous Demodulator
The synchronous demodulator's internal frequency error estimator acquires the frequency error based on a
101010 preamble structure. The bit clock recovery circuit locks to the incoming data stream within four transactions
of a “10” or “01” bit stream. The synchronous demodulator gives optimal performance for 2- or 4-level FSK or
GFSK modulation that has a modulation index less than 2.
4.3.1.2. Asynchronous Demodulator
The asynchronous demodulator should be used OOK modulation and for FSK/GFSK/4GFSK under one or more of
the following conditions:
Modulation index > 2
Non-standard preamble (not 1010101... pattern)
When the modulation index exceeds 2, the asynchronous demodulator has better sensitivity compared to the
synchronous demodulator. An internal deglitch circuit provides a glitch-free data output and a data clock signal to
simplify the interface to the host. There is no requirement to perform deglitching in the host MCU. The
asynchronous demodulator will typically be utilized for legacy systems and will have many performance benefits
over devices used in legacy designs. Unlike the Si4432/31 solution for non-standard packet structures, there is no
requirement to perform deglitching on the data in the host MCU. Glitch-free data is output from Si446x devices, and
a sample clock for the asynchronous data can also be supplied to the host MCU; so, oversampling or bit clock
recovery is not required by the host MCU. There are multiple detector options in the asynchronous demodulator
block, which will be selected based upon the options entered into the WDS calculator. The asynchronous
demodulator's internal frequency error estimator is able to acquire the frequency error based on any preamble
structure.
4.3.2. RX/TX Data Interface With MCU
There are two different options for transferring the data from the RF device to the host MCU. FIFO mode uses the
SPI interface to transfer the data, while direct mode transfers the data in real time over GPIO.
4.3.2.1. FIFO Mode
In FIFO mode, the transmit and receive data is stored in integrated FIFO register memory. The TX FIFO is
accessed by writing Command 66h followed directly by the data/clk that the host wants to write into the TX FIFO.
The RX FIFO is accessed by writing command 77h followed by the number of clock cycles of data the host would
like to read out of the RX FIFO. The RX data will be clocked out onto the SDO pin.
In TX mode, if the packet handler is enabled, the data bytes stored in FIFO memory are “packaged” together with
other fields and bytes of information to construct the final transmit packet structure. These other potential fields
include the Preamble, Sync word, Header, CRC checksum, etc. The configuration of the packet structure in TX
mode is determined by the Automatic Packet Handler (if enabled), in conjunction with a variety of Packet Handler
properties. If the Automatic Packet Handler is disabled, the entire desired packet structure should be loaded into
FIFO memory; no other fields (such as Preamble or Sync word) will be automatically added to the bytes stored in
Rev 1.0 27
Si4464/63/61/60
FIFO memory. For further information on the configuration of the FIFOs for a specific application or packet size,
see "6. Data Handling and Packet Handler" on page 39. In RX mode, only the bytes of the received packet
structure that are considered to be “data bytes” are stored in FIFO memory. Which bytes of the received packet are
considered “data bytes” is determined by the Automatic Packet Handler (if enabled) in conjunction with the Packet
Handler configuration. If the Automatic Packet Handler is disabled, all bytes following the Sync word are
considered data bytes and are stored in FIFO memory. Thus, even if Automatic Packet Handling operation is not
desired, the preamble detection threshold and Sync word still need to be programmed so that the RX Modem
knows when to start filling data into the FIFO. When the FIFO is being used in RX mode, all of the received data
may still be observed directly (in realtime) by properly programming a GPIO pin as the RXDATA output pin; this can
be quite useful during application development. When in FIFO mode, the chip will automatically exit the TX or RX
State when either the PACKET_SENT or PACKET_RX interrupt occurs. The chip will return to the IDLE state
programmed in the argument of the “START TX” or “START RX” API command, TXCOMPLETE_STATE[3:0] or
RXVALID_STATE[3:0]. For example, the chip may be placed into TX mode by sending the “START TX” command
and by writing the 30h to the TXCOMPLETE_STATE[3:0] argument. The chip will transmit all of the contents of the
FIFO, and the ipksent interrupt will occur. When this event occurs, the chip will return to the ready state as defined
by TXCOMPLETE_STATE[3:0] = 30h.
4.3.2.2. Direct Mode
For legacy systems that perform packet handling within the host MCU or other baseband chip, it may not be
desirable to use the FIFO. For this scenario, a Direct mode is provided, which bypasses the FIFOs entirely. In TX
Direct mode, the TX modulation data is applied to an input pin of the chip and processed in “real time” (i.e., not
stored in a register for transmission at a later time). Any of the GPIOs may be configured for use as the TX Data
input function. Furthermore, an additional pin may be required for a TX Clock output function if GFSK modulation is
desired (only the TX Data input pin is required for FSK). To achieve direct mode, the GPIO must be configured in
the “GPIO_PIN_CFG” API command as well as the “MODEM_MOD_TYPE” API property. For GFSK,
“TX_DIRECT_MODE_TYPE” must be set to Synchronous. For 2FSK or OOK, the type can be set to asynchronous
or synchronous. The MOD_SOURCE[1:0] should be set to 01h for are all direct mode configurations. In RX Direct
mode, the RX Data and RX Clock can be programmed for direct (real-time) output to GPIO pins. The
microcontroller may then process the RX data without using the FIFO or packet handler functions of the RFIC.
4.4. Preamble Length
The preamble length requirement is only relevant if using the synchronous demodulator. If the asynchronous
demodulator is being used, then there is no requirement for a conventional 101010 pattern.
The preamble detection threshold determines the number of valid preamble bits the radio must receive to qualify a
valid preamble. The preamble threshold should be adjusted depending on the nature of the application. The
required preamble length threshold depends on when receive mode is entered in relation to the start of the
transmitted packet and the length of the transmit preamble. With a shorter than recommended preamble detection
threshold, the probability of false detection is directly related to how long the receiver operates on noise before the
transmit preamble is received. False detection on noise may cause the actual packet to be missed. The preamble
detection threshold may be adjusted in the modem calculator by modifying the “PM detection threshold” in the “RX
parameters tab” in the radio control panel. For most applications with a preamble length longer than 32 bits, the
default value of 20 is recommended for the preamble detection threshold. A shorter Preamble Detection Threshold
may be chosen if occasional false detections may be tolerated. When antenna diversity is enabled, a 20- bit
preamble detection threshold is recommended. When the receiver is synchronously enabled just before the start of
the packet, a shorter preamble detection threshold may be used. Table 12 demonstrates the recommended
preamble detection threshold and preamble length for various modes.
28 Rev 1.0
Si4464/63/61/60
Table 12. Recommended Preamble Length
Mode AFC Antenna Preamble Type Recommended Recommended
Diversity Preamble Length Preamble Detection
Threshold
(G)FSK Disabled Disabled Standard 4 Bytes 20 bits
(G)FSK Enabled Disabled Standard 5 Bytes 20 bits
(G)FSK Disabled Disabled Non-standard 2 Bytes 0 bits
(G)FSK Enabled Non-standard Not Supported
(G)FSK Disabled Enabled Standard 7 Bytes 24 bits
(G)FSK Enabled Enabled Standard 8 Bytes 24 bits
4(G)FSK Disabled Disabled Standard 40 symbols 16 symbols
4(G)FSK Enabled Disabled Standard 48 symbols 16 symbols
4(G)FSK Non-standard Not Supported
OOK Disabled Disabled Standard 4 Bytes 20 bits
OOK Disabled Disabled Non-standard 2 Bytes 0 bits
OOK Enabled Not Supported
Notes:
1. The recommended preamble length and preamble detection thresholds listed above are to achieve 0% PER. They may
be shortened when occasional packet errors are tolerable.
2. All recommended preamble lengths and detection thresholds include AGC and BCR settling times.
3. “Standard” preamble type should be set for an alternating data squence at the max data rate (…10101010…)
4. “Non-standard” preamble type can be set for any preamble type including …10101010...
5. When preamble detection threshold = 0, sync word needs to be 3 Bytes to avoid false syncs. When only a 2 Byte sync
word is available the sync word detection can be extended by including the last preamble Byte into the RX sync word
setting.
Rev 1.0 29
Si4464/63/61/60
5. Internal Functional Blocks
The following sections provide an overview to the key internal blocks and features.
5.1. RX Chain
The internal low-noise amplifier (LNA) is designed to be a wide-band LNA that can be matched with three external
discrete components to cover any common range of frequencies in the sub-GHz band. The LNA has extremely low
noise to suppress the noise of the following stages and achieve optimal sensitivity; so, no external gain or front-end
modules are necessary. The LNA has gain control, which is controlled by the internal automatic gain control (AGC)
algorithm. The LNA is followed by an I-Q mixer, filter, programmable gain amplifier (PGA), and ADC. The I-Q
mixers downconvert the signal to an intermediate frequency. The PGA then boosts the gain to be within dynamic
range of the ADC. The ADC rejects out-of-band blockers and converts the signal to the digital domain where
filtering, demodulation, and processing is performed. Peak detectors are integrated at the output of the LNA and
PGA for use in the AGC algorithm.
The RX and TX pins maybe directly tied externally for output powers less than +17 dBm, see the direct-tie
reference designs on the Silicon Labs web site for more details.
5.1.1. RX Chain Architecture
It is possible to operate the RX chain in different architecture configurations: fixed-IF, zero-IF, scaled-IF, and
modulated IF. There are trade-offs between the architectures in terms of sensitivity, selectivity, and image rejection.
Fixed-IF is the default configuration and is recommended for most applications. With 35 dB native image rejection
and autonomous image calibration to achieve 55 dB, the fixed-IF solution gives the best performance for most
applications. Fixed-IF obtains the best sensitivity, but it has the effect of degraded selectivity at the image frequency.
An autonomous image rejection calibration is included in Si446x devices and described in more detail in "5.2.3.
Image Rejection and Calibration" on page 32. For fixed-IF and zero-IF, the sensitivity is degraded for data rates less
than 100 kbps or bandwidths less than 200 kHz. The reduction in sensitivity is caused by increased flicker noise as
dc is approached. The benefit of zero-IF is that there is no image frequency; so, there is no degradation in the
selectivity curve, but it has the worst sensitivity. Modulated IF is useful for OOK if image elimination is required
similar to Zero-IF. Scaled-IF is a trade-off between fixed-IF and zero-IF. In the scaled-IF architecture, the image
frequency is placed or hidden in the adjacent channel where it only slightly degrades the typical adjacent channel
selectivity. The scaled-IF approach has better sensitivity than zero-IF but still some degradation in selectivity due to
the image. In scaled-IF mode, the image frequency is directly proportional to the channel bandwidth selected.
Figure 10 demonstrates the trade-off in sensitivity between the different architecture options.
RX Architecture vs Datarate
1% Packet Error Rate (PER)
-90
-95
Sensitivity (dBm)
-100
-105 Fixed IF
Scaled IF
-110 Zero IF
-115
-120
1 10 100
Datarate (kbps)
Figure 10. RX Architecture vs. Data Rate
30 Rev 1.0
Si4464/63/61/60
5.2. RX Modem
Using high-performance ADCs allows channel filtering, image rejection, and demodulation to be performed in the
digital domain, which allows for flexibility in optimizing the device for particular applications. The digital modem
performs the following functions:
Channel selection filter
TX modulation
RX demodulation
Automatic Gain Control (AGC)
Preamble detection
Invalid preamble detection
Radio signal strength indicator (RSSI)
Automatic frequency compensation (AFC)
Image Rejection Calibration
Packet handling including EZMAC® features

Cyclic redundancy check (CRC)
The digital channel filter and demodulator are optimized for ultra-low-power consumption and are highly
configurable. Supported modulation types are GFSK, FSK, 4GFSK, 4FSK, GMSK, ASK, and OOK. The channel
filter can be configured to support bandwidths ranging from 850 down to 1.1 kHz. A large variety of data rates are
supported ranging from 0.123 up to 1 Mbps. The configurable preamble detector is used with the synchronous
demodulator to improve the reliability of the sync-word detection. Preamble detection can be skipped using only
sync detection, which is a valuable feature of the asynchronous demodulator when very short preambles are used
in protocols, such as MBus. The received signal strength indicator (RSSI) provides a measure of the signal
strength received on the tuned channel. The resolution of the RSSI is 0.5 dB. This high-resolution RSSI enables
accurate channel power measurements for clear channel assessment (CCA), carrier sense (CS), and listen before
talk (LBT) functionality. A comprehensive programmable packet handler including key features of Silicon Labs’
EZMAC is integrated to create a variety of communication topologies ranging from peer-to-peer networks to mesh
networks. The extensive programmability of the packet header allows for advanced packet filtering, which, in turn
enables a mix of broadcast, group, and point-to-point communication. A wireless communication channel can be
corrupted by noise and interference, so it is important to know if the received data is free of errors. A cyclic
redundancy check (CRC) is used to detect the presence of erroneous bits in each packet. A CRC is computed and
appended at the end of each transmitted packet and verified by the receiver to confirm that no errors have
occurred. The packet handler and CRC can significantly reduce the load on the system microcontroller allowing for
a simpler and cheaper microcontroller. The digital modem includes the TX modulator, which converts the TX data
bits into the corresponding stream of digital modulation values to be summed with the fractional input to the
sigma-delta modulator. This modulation approach results in highly accurate resolution of the frequency deviation. A
Gaussian filter is implemented to support GFSK and 4GFSK, considerably reducing the energy in adjacent
channels. The default bandwidth-time product (BT) is 0.5 for all programmed data rates, but it may be adjusted to
other values.
5.2.1. Automatic Gain Control (AGC)
The AGC algorithm is implemented digitally using an advanced control loop optimized for fast response time. The
AGC occurs within a single bit or in less than 2 µs. Peak detectors at the output of the LNA and PGA allow for
optimal adjustment of the LNA gain and PGA gain to optimize IM3, selectivity, and sensitivity performance.
5.2.2. Auto Frequency Correction (AFC)
Frequency mistuning caused by crystal inaccuracies can be compensated for by enabling the digital automatic
frequency control (AFC) in receive mode. There are two types of integrated frequency compensation: modem
frequency compensation, and AFC by adjusting the PLL frequency. With AFC disabled, the modem compensation
can correct for frequency offsets up to ±0.25 times the IF bandwidth. When the AFC is enabled, the received signal
will be centered in the pass-band of the IF filter, providing optimal sensitivity and selectivity over a wider range of
frequency offsets up to ±0.35 times the IF bandwidth. When AFC is enabled, the preamble length needs to be long
enough to settle the AFC. As shown in Table 12 on page 29, an additional byte of preamble is typically required to
settle the AFC.
Rev 1.0 31
Si4464/63/61/60
5.2.3. Image Rejection and Calibration
Since the receiver utilizes a low-IF architecture, the selectivity will be affected by the image frequency. The IF
frequency is 468.75 kHz (Fxtal/64), and the image frequency will be at 937.5 kHz below the RF frequency. The
native image rejection of the Si446x family is 35 dB. Image rejection calibration is available in the Si446x to
improve the image rejection to more than 55 dB. The calibration is initiated with the IRCAL API command. The
calibration uses an internal signal source, so no external signal generator is required. The initial calibration takes
250 ms, and periodic re-calibration takes 100 ms. Re-calibration should be initiated when the temperature has
changed more than 30 °C.
For high-band (868/915M), the following commands should be used for image calibration:
IRCAL 56 10 FA F0—course calibration (150 ms)
IRCAL 13 10 FA F0—fine calibration (100 ms)
For low-band (430–510 MHz) the following commands should be used for image calibration:
IRCAL 56 10 CA F0—course calibration (150 ms)
IRCAL 13 10 CA F0—fine calibration (100 ms)
5.2.4. Received Signal Strength Indicator
The received signal strength indicator (RSSI) is an estimate of the signal strength in the channel to which the
receiver is tuned. The RSSI measurement is done after the channel filter, so it is only a measurement of the
desired or undesired in-band signal power. There are two different locations for reading the RSSI value and
different options for configuring the RSSI value. The fastest method for reading the RSSI is to configure one of the
four fast response registers for a latched RSSI value. The fast response registers can be read in 16 SPI clock
cycles with no requirement to wait for CTS. The RSSI value may also be read out of the GET_MODEM_STATUS
command. In this command, both the current RSSI and the latched RSSI are available. Reading the RSSI in the
GET_MODEM_STATUS command takes longer than reading the RSSI out of the fast response register. After the
initial command, it will take 33 µs for CTS to be set and then the four or five bytes of SPI clock cycles to read out
the respective current or latched RSSI values.
The RSSI configuration options are set in the MODEM_RSSI_CONTROL API property. The RSSI values may be
latched and stored based on the following events: preamble detection, sync detection, or four bit times measured
after the start of RX mode. The requirement for four bit times is determined by the delay and settling through the
modem and digital channel filter. In MODEM_RSSI_CONTROL, the RSSI may be defined to update every bit or
averaged and updated every four bits. If RSSI averaging over four bits is enabled, the latched RSSI value after the
start of RX mode will be seven bits to allow for the averaging. The latched RSSI values are cleared when entering
RX mode so they may be read after the packet is received or after dropping back to standby mode. If the RSSI
value have been cleared by the start of RX but not latched yet, a 0 value will be read if it is attempted to be read.
During the reception of a packet, it may be useful to detect if a secondary interfering signal (desired or undesired)
arrives. To detect this event, a feature for RSSI jump detection is available. While receiving a packet, if the RSSI
changes by a programmed amount, an interrupt or GPIO can be configured to notify the host. The level of RSSI
increase (jump) is programmable through the MODEM_RSSI_JUMP_THRESH API property. If an RSSI jump is
detected, the modem may be programmed to automatically reset so that it may lock onto the new stronger signal.
The packet handler cannot be automatically reset by this feature. If this feature is being used in conjunction with
the packet handler, the host will need to manually reset the receiver to reset the packet handler. The configuration
and options for RSSI jump detection are programmed in the MODEM_RSSI_CONTROL2 API property. By default,
RSSI jump detection is not enabled.
The RSSI values and curves may be offset by the MODEM_RSSI_COMP API property. The default value of 7’h32
corresponds to no RSSI offset. Setting a value less than 7’h32 corresponds to a negative offset, and a value higher
than 7’h32 corresponds to a positive offset. The offset value is in 1 dB steps. For example, setting a value of 7’h3A
would correspond to a positive offset of 8 dB.
32 Rev 1.0
Si4464/63/61/60
Clear channel assessment (CCA) or RSSI threshold detection is also available. An RSSI threshold may be set in
the MODEM_RSSI_THRESH API property. If the RSSI value is above this threshold, an interrupt or GPIO may
notify the host. Both the latched version and asynchronous version of this threshold are available on any of the
GPIOs. Automatic fast hopping based on RSSI is available. See “5.3.1.2. Automatic RX Hopping and Hop Table”.
5.3. Synthesizer
An integrated Sigma Delta () Fractional-N PLL synthesizer capable of operating over the bands from 142–175,
283–350, 425–525, and 850–1050 MHz for the Si4460/61/63. The Si4464 offers continuous frequency coverage
over the entire 119–960 MHz band. Using a  synthesizer has many advantages; it provides flexibility in choosing
data rate, deviation, channel frequency, and channel spacing. The transmit modulation is applied directly to the
loop in the digital domain through the fractional divider, which results in very precise accuracy and control over the
transmit deviation. The frequency resolution in the 850–1050 MHz band is 28.6 Hz with more resolution in the
other bands. The nominal reference frequency to the PLL is 30 MHz, but any XTAL frequency from 25 to 32 MHz
may be used. The modem configuration calculator in WDS will automatically account for the XTAL frequency being
used. The PLL utilizes a differential LC VCO with integrated on-chip inductors. The output of the VCO is followed
by a configurable divider, which will divide the signal down to the desired output frequency band.
5.3.1. Synthesizer Frequency Control
The frequency is set by changing the integer and fractional settings to the synthesizer. The WDS calculator will
automatically provide these settings, but the synthesizer equation is shown below for convenience. The APIs for
setting the frequency are FREQ_CONTROL_INTE, FREQ_CONTROL_FRAC2, FREQ_CONTROL_FRAC1, and
FREQ_CONTROL_FRAC0.
 freq_xo
RF_channel =  fc_inte + -----------------
fc_frac- 2
19 
 -----------------------------  Hz 
2 outdiv
Note: The fc_frac/219 value in the above formula has to be a number between 1 and 2.
Table 13. Output Divider (Outdiv) Values for the Si4460/61/63

Outdiv Lower (MHz) Upper (MHz)
24 142 175
12 284 350
8 425 525
4 850 1050
Table 14. Output Divider (Outdiv) for the Si4464

Outdiv Lower (MHz) Upper (MHz)
24 119 168.99
16 169 224.99
12 225 337.99
8 338 449.99
6 450 675.99
4 675 960
Rev 1.0 33
Si4464/63/61/60
5.3.1.1. EZ Frequency Programming
In applications that utilize multiple frequencies or channels, it may not be desirable to write four API registers each
time a frequency change is required. EZ frequency programming is provided so that only a single register write
(channel number) is required to change frequency. A base frequency is first set by first programming the integer
and fractional components of the synthesizer. This base frequency will correspond to channel 0. Next, a channel
step size is programmed into the FREQ_CONTROL_CHANNEL_STEP_SIZE_1 and
FREQ_CONTROL_CHANNEL_STEP_SIZE_0 API registers. The resulting frequency will be:
RF Frequency = Base Frerquency + Channel  Stepsi ze
The second argument of the START_RX or START_TX is CHANNEL, which sets the channel number for EZ
frequency programming. For example, if the channel step size is set to 1 MHz, the base frequency is set to
900 MHz with the INTE and FRAC API registers, and a CHANNEL number of 5 is programmed during the
START_TX command, the resulting frequency will be 905 MHz. If no CHANNEL argument is written as part of the
START_RX/TX command, it will default to the previous value. The initial value of CHANNEL is 0; so, if no
CHANNEL value is written, it will result in the programmed base frequency.
5.3.1.2. Automatic RX Hopping and Hop Table
The transceiver supports an automatic hopping feature that can be fully configured through the API. This is
intended for RX hopping where the device has to hop from channel to channel and look for packets. Once the
device is put into the RX state, it automatically starts hopping through the hop table if the feature is enabled.
The hop table can hold up to 64 entries and is maintained in firmware. Each entry is a channel number; so, the hop
table can hold up to 64 channels. The number of entries in the table is set by RX HOP TABLE_SIZE API. The
specified channels correspond to the EZ frequency programming method for programming the frequency. The
receiver starts at the base channel and hops in sequence from the top of the hop table to the bottom. The table will
wrap around to the base channel once it reaches the end of the table. An entry of 0xFF in the table indicates that
the entry should be skipped. The device will hop to the next non 0xFF entry.
There are three conditions that can be used to determine whether to continue hopping or to stay on a particular
channel. These conditions are:
RSSI threshold
Preamble timeout (invalid preamble pattern)
Sync word timeout (invalid or no sync word detected after preamble)
These conditions can be used individually, or they can be enabled all together by configuring the
RX_HOP_CONTROL API. However, the firmware will make a decision on whether or not to hop based on the first
condition that is met.
The RSSI that is monitored is the current RSSI value. This is compared to the threshold, and, if it is above the
threshold value, it will stay on the channel. If the RSSI is below the threshold, it will continue hopping. There is no
averaging of RSSI done during the automatic hopping from channel to channel. Since the preamble timeout and
the sync word timeout are features that require packet handling, the RSSI threshold is the only condition that can
be used if the user is in “direct” or “RAW” mode where packet handling features are not used.
Note that the RSSI threshold is not an absolute RSSI value; instead, it is a relative value and should be verified on
the bench to find an optimal threshold for the application.
The turnaround time from RX to RX on a different channel using this method is 115 µs. The time spent in receive
mode will be determined by the configuration of the hop conditions. Manual RX hopping will have the fastest
turn-around time but will require more overhead and management by the host MCU.
The following are example steps for using Auto Hop:
1. Set the base frequency (inte + frac) and channel step size.
2. Define the number of entries in the hop table (RX_HOP_TABLE_SIZE).
3. Write the channels to the hop table (RX_HOP_TABLE_ENTRY_n)
4. Configure the hop condition and enable auto hopping- RSSI, preamble, or sync (RX_HOP_CONTROL).
5. Set preamble and sync parameters if enabled.
34 Rev 1.0
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6. Program the RSSI threshold property in the modem using “MODEM_RSSI_THRESH”.
7. Set the preamble threshold using “PREAMBLE_CONFIG_STD_1”.
8. Program the preamble timeout property using “PREAMBLE_CONFIG_STD_2”.
9. Set the sync detection parameters if enabled.
10. If needed, use “GPIO_PIN_CFG” to configure a GPIO to toggle on hop and hop table wrap.
11. Use the “START_RX” API with channel number set to the first valid entry in the hop table (i.e., the first non
0xFF entry).
12. Device should now be in auto hop mode.
5.3.1.3. Manual RX Hopping
The RX_HOP command provides the fastest method for hopping from RX to RX but it requires more overhead and
management by the host MCU. Using the RX_HOP command, the turn-around time is 75 µs. The timing is faster
with this method than Start_RX or RX hopping because one of the calculations required for the synthesizer
calibrations is offloaded to the host and must be calculated/stored by the host, VCO_CNT0. For information about
using fast manual hopping, contact customer support.
5.4. Transmitter (TX)
The Si4464/63 contains an integrated +20 dBm transmitter or power amplifier that is capable of transmitting from
–20 to +20 dBm. The output power steps are less than 0.25 dB within 6 dB of max power but become larger and
more non-linear close to minimum output power. The Si4464/63 PA is designed to provide the highest efficiency
and lowest current consumption possible. The Si4461 PA is capable of transmitting from –40 to +16 dBm. The
Si4461 PA can be optimized for either optimum current consumption (Class E) or for fine output power steps and
performance over voltage and temperature (switched-current). Switched-current matching will have fine output
power steps and more constant output power over VDD, but it will have higher current consumption than the
class-E matching. The class E will have the most efficient current consumption, but it will have more coarse output
power steps and variation across VDD. The Si4460 is designed to supply +10 dBm output power for less than
20 mA for applications that require operation from a single coin cell battery. The Si4460 can also operate with
either class-E or switched current matching and output up to +13 dBm Tx power. All PA options are single-ended to
allow for easy antenna matching and low BOM cost. Automatic ramp-up and ramp-down is automatically
performed to reduce unwanted spectral spreading.
Number Command Summary

0x2200 PA_MODE Sets PA type.
0x2201 PA_PWR_LVL Adjust TX power in fine steps.
Adjust TX power in coarse steps
0x2202 PA_BIAS_CLKDUTY and optimizes for different
match configurations.
Changes the ramp up/down time
0x2203 PA_TC
of the PA.
5.4.1. Si4464/63: +20 dBm PA

The +20 dBm configuration utilizes a class-E matching configuration. Typical performance for the 900 MHz band
for output power steps, voltage, and temperature are shown in Figures 11–13. The output power is changed in 128
steps through PA_PWR_LVL API. For detailed matching values, BOM, and performance at other frequencies, refer
to the PA Matching application note.
Rev 1.0 35
Si4464/63/61/60
TX Power vs. PA_PWR_LVL

25
20
15
TX Power(dBm)
10
5
0
-5
-10
-15
-20
-25
-30
-35
0 10 20 30 40 50 60 70 80 90 100 110 120
PA_PWR_LVL
Figure 11. +20 dBm TX Power vs. PA_PWR_LVL
TX Power vs. VDD

22
20
TX Power (dBm)
18
16
14
12
10
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Supply Voltage (VDD)
Figure 12. +20 dBm TX Power vs. VDD
TX Power vs Temp
20.5
20
TX Power (dBm)
19.5
19
18.5
18
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
Temperature (C)
Figure 13. +20 dBm TX Power vs. Temp
36 Rev 1.0
Si4464/63/61/60
5.4.2. Si4461 +16 dBm PA
The Si4461 PA can utilize different matches to optimize the performance for 16, 14, 13 dBm, or a lower power. A
class-E match is recommended for 16 dBm to maximize the efficiency and battery life. For 13 and 14 dBm, a
switched current match is recommended to provide optimal performance over VDD and temperature variation.
Typical performance for the 900 MHz band for output power steps, voltage, and temperature are shown in Figures
14 and 15. The output power is changed in 128 steps through the PA_PWR_LVL API. For detailed matching
values, BOM, and performance at other frequencies, refer to “AN627: Si4460/61 Low-Power PA Matching.
Figure 14. +13 dBm TX Power vs. PA_PWR_LVL
Figure 15. +13 dBm TX Power vs. Supply Voltage (VDD)
Rev 1.0 37
Si4464/63/61/60
5.5. Crystal Oscillator
The Si446x includes an integrated crystal oscillator with a fast start-up time of less than 250 µs. The design is
differential with the required crystal load capacitance integrated on-chip to minimize the number of external
components. By default, all that is required off-chip is the crystal. The default crystal is 30 MHz, but the circuit is
designed to handle any XTAL from 25 to 32 MHz. If a crystal different than 30 MHz is used, the POWER_UP API
boot command must be modified. The WDS calculator crystal frequency field must also be changed to reflect the
frequency being used. The crystal load capacitance can be digitally programmed to accommodate crystals with
various load capacitance requirements and to adjust the frequency of the crystal oscillator. The tuning of the crystal
load capacitance is programmed through the GLOBAL_XO_TUNE API property. The total internal capacitance is
11 pF and is adjustable in 127 steps (70 fF/step). The crystal frequency adjustment can be used to compensate for
crystal production tolerances. The frequency offset characteristics of the capacitor bank are demonstrated in
Figure 16.
Figure 16. Capacitor Bank Frequency Offset Characteristics

Utilizing the on-chip temperature sensor and suitable control software, the temperature dependency of the crystal
can be canceled.
A TCXO or external signal source can easily be used in lieu of a conventional XTAL and should be connected to
the XIN pin. The incoming clock signal is recommended to be ac-coupled to the XIN pin since the dc bias is
controlled by the internal crystal oscillator buffering circuitry. The input swing range should be between
600 mV–1.8 V peak-to-peak. If external drive is desired, the incoming signal amplitude should not go below 0 V or
exceed 1.8 V. The best dc bias should be approximately 0.7 V. However, if the signal swing exceeds 1.4 Vpp, the
dc bias can be set to 1/2 the peak-to-peak voltage swing. The XO capacitor bank should be set to 0 whenever an
external drive is used on the XIN pin. In addition, the POWER_UP command should be invoked with the TCXO
option whenever external drive is used.
38 Rev 1.0
Si4464/63/61/60
6. Data Handling and Packet Handler
6.1. RX and TX FIFOs
Two 64-byte FIFOs are integrated into the chip, one for RX and one for TX, as shown in Figure 17. Writing to
command Register 66h loads data into the TX FIFO, and reading from command Register 77h reads data from the
RX FIFO. The TX FIFO has a threshold for when the FIFO is almost empty, which is set by the “TX_FIFO_EMPTY”
property. An interrupt event occurs when the data in the TX FIFO reaches the almost empty threshold. If more data
is not loaded into the FIFO, the chip automatically exits the TX state after the PACKET_SENT interrupt occurs. The
RX FIFO has one programmable threshold, which is programmed by setting the “RX_FIFO_FULL” property. When
the incoming RX data crosses the Almost Full Threshold, an interrupt will be generated to the microcontroller via
the nIRQ pin. The microcontroller will then need to read the data from the RX FIFO. The RX Almost Full Threshold
indication implies that the host can read at least the threshold number of bytes from the RX FIFO at that time. Both
the TX and RX FIFOs may be cleared or reset with the “FIFO_RESET” command.
TX FIFO RX FIFO
RX FIFO Almost
Full Threshold
TX FIFO Almost
Empty Threshold
Figure 17. TX and RX FIFOs

6.2. Packet Handler
When using the FIFOs, automatic packet handling may be enabled for TX mode, RX mode, or both. The usual
fields for network communication, such as preamble, synchronization word, headers, packet length, and CRC, can
be configured to be automatically added to the data payload. The fields needed for packet generation normally
change infrequently and can therefore be stored in registers. Automatically adding these fields to the data payload
in TX mode and automatically checking them in RX mode greatly reduces the amount of communication between
the microcontroller and Si446x. It also greatly reduces the required computational power of the microcontroller. The
general packet structure is shown in Figure 18. Any or all of the fields can be enabled and checked by the internal
packet handler.
Pkt Len gth or Data
Header or Data
C RC Field 1 (op t)
C RC Field 2 (op t)
C RC Field 3 (op t)
C RC Field 4 (op t)
C RC Field 5 (op t)
Sync Word
Field 3 (opt)
Field 4 (opt)
Field 5 (opt)
F ield 2 (o pt)
Field 1
Data
Data
Data
Preamble
1-255 Bytes 1-4 Bytes Con fig Config Con fig Con fig Con fig
0, 2, o r 4 0, 2, o r 4 0, 2, o r 4 0, 2, or 4 0, 2, or 4
Bytes Bytes B ytes Bytes Bytes
Figure 18. Packet Handler Structure
Rev 1.0 39
Si4464/63/61/60
The fields are highly programmable and can be used to check any kind of pattern in a packet structure. The
general functions of the packet handler include the following:
Detection/validation of Preamble quality in RX mode (PREAMBLE_VALID signal)
Detection of Sync word in RX mode (SYNC_OK signal)
Detection of valid packets in RX mode (PKT_VALID signal)
Detection of CRC errors in RX mode (CRC_ERR signal)
Data de-whitening and/or Manchester decoding (if enabled) in RX mode
Match/Header checking in RX mode
Storage of Data Field bytes into FIFO memory in RX mode
Construction of Preamble field in TX mode
Construction of Sync field in TX mode
Construction of Data Field from FIFO memory in TX mode
Construction of CRC field (if enabled) in TX mode
Data whitening and/or Manchester encoding (if enabled) in TX mode
For details on how to configure the packet handler, see “AN626: Packet Handler Operation for Si446x RFICs”.
40 Rev 1.0
Si4464/63/61/60
7. RX Modem Configuration
The Si446x can easily be configured for different data rate, deviation, frequency, etc. by using the WDS settings
calculator, which generates an initialization file for use by the host MCU.
8. Auxiliary Blocks
8.1. Wake-up Timer and 32 kHz Clock Source
The chip contains an integrated wake-up timer that can be used to periodically wake the chip from sleep mode. The
wake-up timer runs from either the internal 32 kHz RC Oscillator, or from an external 32 kHz XTAL.
The wake-up timer can be configured to run when in sleep mode. If WUT_EN = 1 in the GLOBAL_WUT_CONFIG
property, prior to entering sleep mode, the wake-up timer will count for a time specified defined by the
GLOBAL_WUT_R and GLOBAL_WUT_M properties. At the expiration of this period, an interrupt will be generated
on the nIRQ pin if this interrupt is enabled in the INT_CTL_CHIP_ENABLE property. The microcontroller will then
need to verify the interrupt by reading the chip interrupt status either via GET_INT_STATUS or a fast response
register. The formula for calculating the Wake-Up Period is as follows:
WUT_R
42
WUT = WUT_M  -----------------------------  ms 
32 768
The RC oscillator frequency will change with temperature; so, a periodic recalibration is required. The RC oscillator
is automatically calibrated during the POWER_UP command and exits from the Shutdown state. To enable the
recalibration feature, CAL_EN must be set in the GLOBAL_WUT_CONFIG property, and the desired calibration
period should be selected via WUT_CAL_PERIOD[2:0] in the same API property. During the calibration, the
32 kHz RC oscillator frequency is compared to the 30 MHz XTAL and then adjusted accordingly. The calibration
needs to start the 30 MHz XTAL, which increases the average current consumption; so, a longer CAL_PERIOD
results in a lower average current consumption. The 32 kHz XTAL accuracy is comprised of both the XTAL
parameters and the internal circuit. The XTAL accuracy can be defined as the XTAL initial error + XTAL aging +
XTAL temperature drift + detuning from the internal oscillator circuit. The error caused by the internal circuit is
typically less than 10 ppm.
Rev 1.0 41
Si4464/63/61/60
Table 15. WUT Specific Commands and Properties

API Properties Description Requirements/Notes
GLOBAL_WUT_CONFIG GLOBAL WUT configuration WUT_EN—Enable/disable wake up timer.
WUT_LBD_EN—Enable/disable low battery detect
measurement on WUT interval.
WUT_LDC_EN:
0 = Disable low duty cycle operation.
1 = RX LDC operation
treated as wake up START_RX
WUT state is used
2 = TX LDC operation
treated as wakeup START_TX
WUT state is used
CAL_EN—Enable calibration of the 32 kHz RC
oscillator
WUT_CAL_PERIOD[2:0]—Sets calibration period.
GLOBAL_WUT_M_15_8 Sets HW WUT_M[15:8] WUT_M—Parameter to set the actual wakeup time.
See equation above.
GLOBAL_ WUT_M_7_0 Sets HW WUT_M[7:0] WUT_M—Parameter to set the actual wakeup time.
See equation above.
GLOBAL_WUT_R Sets WUT_R[4:0] WUT_R—Parameter to set the actual wakeup time.
Sets WUT_SLEEP to choose See equation above.
WUT state WUT_SLEEP:
0 = Go to ready state after WUT
1 = Go to sleep state after WUT
GLOBAL_WUT_LDC Sets FW internal WUT_LDC WUT_LDC—Parameter to set the actual wakeup
time. See equation in "8.2. Low Duty Cycle Mode
(Auto RX Wake-Up)" on page 43.
Table 16. WUT Related API Commands and Properties

Command/Property Description Requirements/Notes
WUT Interrupt Enable
CHIP_INT_STATUS_EN—Enables chip status
INT_CTL_ENABLE Interrupt enable property
interrupt.
INT_CTL_CHIP_ENABLE Chip interrupt enable property WUT_EN—Enables WUT interrupt.
32 kHz Clock Source Selection
CLK_32K_SEL[2:0]—Configuring the source of
GLOBAL_CLK_CFG Clock configuration options WUT.
WUT Interrupt Output
Host can enable interrupt on GPIOx_MODE[5:0] = 14 and
GPIO_PIN_CFG
WUT expire NIRQ_MODE[5:0] = 39.
RX/TX Operation
START RX/TX when wake up
START_RX/TX START = 1.
timer expire
42 Rev 1.0
Si4464/63/61/60
8.2. Low Duty Cycle Mode (Auto RX Wake-Up)
The low duty cycle (LDC) mode is implemented to automatically wake-up the receiver to check if a valid signal is
available or to enable the transmitter to send a packet. It allows low average current polling operation by the Si446x
for which the wake-up timer (WUT) is used. RX and TX LDC operation must be set via the
GLOBAL_WUT_CONFIG property when setting up the WUT. The LDC wake-up period is determined by the
following formula:
WUT_R
42
LDC = WUT_LDC  -----------------------------  ms 
32 768
where the WUT_LDC parameter can be set by the GLOBAL_WUT_LDC property. The WUT period must be set in
conjunction with the LDC mode duration; for the relevant API properties, see the wake-up timer (WUT) section.
Figure 19. RX and TX LDC Sequences

The basic operation of RX LDC mode is shown in Figure 20. The receiver periodically wakes itself up to work on
RX_STATE during LDC mode duration. If a valid preamble is not detected, a receive error is detected, or an entire
packet is not received, the receiver returns to the WUT state (i.e., ready or sleep) at the end of LDC mode duration
and remains in that mode until the beginning of the next wake-up period. If a valid preamble or sync word is
detected, the receiver delays the LDC mode duration to receive the entire packet. If a packet is not received during
two LDC mode durations, the receiver returns to the WUT state at the last LDC mode duration until the beginning
of the next wake-up period.
Figure 20. Low Duty Cycle Mode for RX

In TX LDC mode, the transmitter periodically wakes itself up to transmit a packet that is in the data buffer. If a
packet has been transmitted, nIRQ goes low if the option is set in the INT_CTL_ENABLE property. After
transmitting, the transmitter immediately returns to the WUT state and stays there until the next wake-up time
expires.
Rev 1.0 43
Si4464/63/61/60
8.3. Temperature, Battery Voltage, and Auxiliary ADC
The Si446x family contains an integrated auxiliary ADC for measuring internal battery voltage, an internal
temperature sensor, or an external component over a GPIO. The ADC utilizes a SAR architecture and achieves
11-bit resolution. The Effective Number of Bits (ENOB) is 9 bits. When measuring external components, the input
voltage range is 1 V, and the conversion rate is between 300 Hz to 2.44 kHz. The ADC value is read by first
sending the GET_ADC_READING command and enabling the inputs that are desired to be read: GPIO, battery, or
temp.
GET_ADC_READING 7 6 5 4 3 2 1 0
Command
CMD 0x14
ADC_EN 0 TEMPERATURE_EN BATTERY_VOLTAGE_EN ADC_GPIO_EN ADC_GPIO_PIN[1:0]
When the conversion is finished and all the data is ready, CTS will go high, and the data can be read out in the
following order.
GET_ADC_READING Reply 7 6 5 4 3 2 1 0
CMD_COMPLETE CTS[7:0]
GPIO_ADC GPIO_ADC[15:8]
GPIO_ADC GPIO_ADC[7:0]
BATTERY_ADC BATTERY_ADC[15:8]
BATTERY_ADC BATTERY_ADC[7:0]
TEMP_ADC TEMP_ADC[15:8]
TEMP_ADC TEMP_ADC[7:0]
TEMP_SLOPE TEMP_SLOPE[7:0]
TEMP_INTERCEPT TEMP_INTERCEPT[7:0]
To convert the ADC value to a voltage for either a battery or GPIO reading, the following formula should be used:
4.8  ADC DATA

-----------------------------------------
2048
To convert the ADC reading to an absolute temperature, the following formula should be used:
S  ADC DATA
= ------------------------------------- + 1
2048
8.4. Low Battery Detector

The low battery detector (LBD) is enabled and utilized as part of the wake-up-timer (WUT). The LBD function is not
available unless the WUT is enabled, but the host MCU can manually check the battery voltage anytime with the
auxiliary ADC. The LBD function is enabled in the GLOBAL_WUT_CONFIG API property. The battery voltage will
be compared against the threshold each time the WUT expires. The threshold for the LBD function is set in
GLOBAL_LOW_BATT_THRESH. The threshold steps are in increments of 50 mV, ranging from a minimum of
1.5 V up to 3.05 V. The accuracy of the LBD is ±3%. The LBD notification can be configured as an interrupt on the
nIRQ pin or enabled as a direct function on one of the GPIOs.
44 Rev 1.0
Si4464/63/61/60
8.5. Antenna Diversity
To mitigate the problem of frequency-selective fading due to multipath propagation, some transceiver systems use
a scheme known as antenna diversity. In this scheme, two antennas are used. Each time the transceiver enters RX
mode the receive signal strength from each antenna is evaluated. This evaluation process takes place during the
preamble portion of the packet. The antenna with the strongest received signal is then used for the remainder of
that RX packet. The same antenna will also be used for the next corresponding TX packet. This chip fully supports
antenna diversity with an integrated antenna diversity control algorithm. The required signals needed to control an
external SPDT RF switch (such as a PIN diode or GaAs switch) are available on the GPIOx pins. The operation of
these GPIO signals is programmable to allow for different antenna diversity architectures and configurations. The
antdiv[2:0] bits are found in the MODEM_ANT_DIV_CONTROL API property descriptions and enable the antenna
diversity mode. The GPIO pins are capable of sourcing up to 5 mA of current; so, it may be used directly to
forward-bias a PIN diode if desired. The antenna diversity algorithm will automatically toggle back and forth
between the antennas until the packet starts to arrive. The recommended preamble length for optimal antenna
selection is 8 bytes.
Rev 1.0 45
Si4464/63/61/60
9. Pin Descriptions: Si4464/63/62/61/60
GPIO3
GPIO2
XOUT
GND
XIN
SDN 1 20 19 18 17 16
RXp 2 15 nSEL
RXn 3 GND 14 SDI
TX 4 PAD 13 SDO
NC 5 12 SCLK
6 7 8 9 10 11 nIRQ
VDD
GPIO0
GPIO1
TXRamp
VDD
Pin Pin Name I/0 Description
Shutdown Input Pin.
0–VDD V digital input. SDN should be = 0 in all modes except Shutdown mode.
1 SDN I When SDN = 1, the chip will be completely shut down, and the contents of the
registers will be lost.
2 RXp I Differential RF Input Pins of the LNA.
3 RXn I See application schematic for example matching network.
Transmit Output Pin.

4 TX O The PA output is an open-drain connection, so the L-C match must supply
VDD (+3.3 VDC nominal) to this pin.
5 NC No Connect. Not connected internally to any circuitry.
+1.8 to +3.6 V Supply Voltage Input to Internal Regulators.

6 VDD VDD
The recommended VDD supply voltage is +3.0 V.
Programmable Bias Output with Ramp Capability for External FET PA.
7 TXRAMP O
See reference design.
+1.8 to +3.6 V Supply Voltage Input to Internal Regulators.
8 VDD VDD
The recommended VDD supply voltage is +3.0 V.
9 GPIO0 I/O General Purpose Digital I/O.
May be configured through the registers to perform various functions including:
10 GPIO1 I/O Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery
Detect, TRSW, AntDiversity control, etc.
General Microcontroller Interrupt Status Output.
When the Si4463/61 exhibits any one of the interrupt events, the nIRQ pin will
11 nIRQ O be set low = 0. The Microcontroller can then determine the state of the inter-
rupt by reading the interrupt status. No external resistor pull-up is required, but
it may be desirable if multiple interrupt lines are connected.
46 Rev 1.0
Si4464/63/61/60
Pin Pin Name I/0 Description
Serial Clock Input.
12 SCLK I 0–VDD V digital input. This pin provides the serial data clock function for the
4-line serial data bus. Data is clocked into the Si4463/61 on positive edge tran-
sitions.
0–VDD V Digital Output.
13 SDO O
Provides a serial readback function of the internal control registers.
Serial Data Input.
14 SDI I 0–VDD V digital input. This pin provides the serial data stream for the 4-line
serial data bus.
Serial Interface Select Input.
15 nSEL I 0–VDD V digital input. This pin provides the Select/Enable function for the
4-line serial data bus.
Crystal Oscillator Output.
16 XOUT O Connect to an external 25.6 to 32 MHz crystal, or leave floating when driving
with an external source on XIN.
Crystal Oscillator Input.
Connect to an external 25.6 to 32 MHz crystal, or connect to an external
17 XIN I source. If using an external source or TCXO with no crystal, then 500–900 mV
amplitude is required. No dc bias is required, but, if used, it should be set to
500 mV.
18 GND GND Connect to PCB ground.
19 GPIO2 I/O General Purpose Digital I/O.

May be configured through the registers to perform various functions, including
20 GPIO3 I/O Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery
Detect, TRSW, AntDiversity control, etc.
The exposed metal paddle on the bottom of the Si446x supplies the RF and cir-
cuit ground(s) for the entire chip. It is very important that a good solder connec-
PKG PADDLE_GND GND tion is made between this exposed metal paddle and the ground plane of the
PCB underlying the Si446x.
Rev 1.0 47
Si4464/63/61/60
10. Ordering Information
Part Number1,2 Description Package Type Operating

Temperature
QFN-20
Si4464-Bxx-FM ISM EZRadioPRO Transceiver –40 to 85 °C
Pb-free
QFN-20
Pb-free
QFN-20
Pb-free
QFN-20
Pb-free
Notes:
1. Add an “(R)” at the end of the device part number to denote tape and reel option.
2. For Bxx, the first “x” indicates the ROM version, and the second “x” indicates the FW version in OTP.
48 Rev 1.0
Si4464/63/61/60
11. Package Outline: Si4464/63/61/60
Figure 21 illustrates the package details for the Si446x. Table 17 lists the values for the dimensions shown in the
illustration.
Figure 21. 20-Pin Quad Flat No-Lead (QFN)
Rev 1.0 49
Si4464/63/61/60
Table 17. Package Dimensions

Symbol Millimeters
Min Nom Max
A 0.80 0.85 0.90
A1 0.00 0.02 0.05
b 0.18 0.25 0.30
D 4.00 BSC
D2 2.45 2.60 2.75
e 0.50 BSC
E 4.00 BSC
E2 2.45 2.60 2.75
L 0.30 0.40 0.50
aaa — — 0.15
bbb — — 0.08
ccc — — 0.10
ddd — — 0.10
eee — — 0.10
ggg — — 0.05
Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220,
Variation VGGD-8.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
50 Rev 1.0
Si4464/63/61/60
12. PCB Land Pattern: Si4464/63/61/60
Figure 22 illustrates the PCB land pattern details for the Si446x. Table 18 lists the values for the dimensions shown
in the illustration.
Figure 22. PCB Land Pattern
Rev 1.0 51
Si4464/63/61/60
Table 18. PCB Land Pattern Dimensions

Symbol Millimeters
Min Max
C1 3.90 4.00
C2 3.90 4.00
E 0.50 REF
X1 0.20 0.30
X2 2.55 2.65
Y1 0.65 0.75
Y2 2.55 2.65
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum, all
the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for the
perimeter pads.
7. A 2x2 array of 1.10 x 1.10 mm openings on 1.30 mm pitch should be
used for the center ground pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for small body components.
52 Rev 1.0
Si4464/63/61/60
13. Top Marking
13.1. Si4464/63/61/60 Top Marking
13.2. Top Marking Explanation
Mark Method YAG Laser

44600A = Si4460 Rev 0A1
44610A = Si4461 Rev 0A1
Line 1 Marking Part Number
44630A = Si4463 Rev 0A1
44640A = Si4464 Rev 0A1
Line 2 Marking TTTTT = Internal Code Internal tracking code.2
YY = Year Assigned by the Assembly House. Corresponds to the last
Line 3 Marking WW = Workweek significant digit of the year and workweek of the mold date.
Notes:
1. The first letter after the part number is part of the ROM revision. The last letter indicates the firmware
revision.
2. The first letter of this line is part of the ROM revision.
Rev 1.0 53
Si4464/63/61/60
DOCUMENT CHANGE LIST
Revision 0.4 to Revision 1.0
 Updated Table 3 on page 6.
 Updated Table 6 on page 11.
 Updated Figure 14 on page 37.
 Replaced Table 12 on page 29.
 Updated "11. Package Outline: Si4464/63/61/60" on
page 49.
54 Rev 1.0
Si4464/63/61/60
NOTES:
Rev 1.0 55
Si4464/63/61/60
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and EZRadioPRO are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
56 Rev 1.0

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S i 4 4 6 4 / 6 3 / 6 1/60

OOK and ASK 75 dB blocking at 1 MHz

 Max output power  Antenna diversity and T/R switch control

Silicon Laboratories' Si446x devices are high-performance, low-current Patents pending

Rev 1.0 2/12 Copyright © 2012 by Silicon Laboratories Si4464/63/62/61/60

GPIO3 GPIO2 XIN XOUT

VDD TXRAMP VDD GPIO0 GPIO1

Si4463 Major bands +20 dBm 169 MHz: 70 mA 10/13 mA  

Si4461 Major bands +16 dBm +13 dBm: 29 mA 10/13 mA  

Si4460 Major bands +13 dBm +10 dBm: 18 mA 10/13 mA  

Table 2. Synthesizer AC Electrical Characteristics1

425 — 525 MHz

850 — 1050 MHz

Synthesizer Frequency FSYN See Notes 1, 2, and 3 119 — 960 MHz

FRES-350 283–350 MHz — 9.5 — Hz

FRES-175 142–175 MHz — 4.7 — Hz

Parameter Symbol Conditions Min Typ Max Units

RX Frequency FRX 142 — 175 MHz

Parameter Symbol Conditions Min Typ Max Units

BER Variation vs Power PRX_RES Up to +5 dBm Input Level — 0 0.1 ppm

Image Rejection3 ImREJ No image rejection calibration. Rejec- — 35 — dB

Table 4. Transmitter AC Electrical Characteristics1

Parameter Symbol Conditions Min Typ Max Units

284 — 350 MHz

850 — 1050 MHz

(G)FSK Data Rate2,3 DRFSK 0.123 — 500 kbps

4(G)FSK Data Rate2,3 DR4FSK 0.123 — 1 Mbps

OOK Data Rate2,3 DROOK 0.123 — 120 kbps

f350 283–350 MHz — 500 — kHz

f175 142–175 MHz — 250 — kHz

FRES-350 283–350 MHz — 9.5 — Hz

FRES-175 142–175 MHz — 4.7 — Hz

Parameter Symbol Conditions Min Typ Max Units

Transmit Modulation Gaussian Filtering Bandwith Time

Parameter Symbol Conditions Min Typ Max Units

Temperature Sensor TSS — 1.78 — mV/°C

Table 6. Digital IO Specifications (GPIO_x, SCLK, SDO, SDI, nSEL, nIRQ)1

Table 7. Absolute Maximum Ratings

Qualification Test Conditions:

Figure 1. Si4461 Direct-Tie Application Example

Figure 2. Si4463 Single Antenna with RF Switch Example

Table 8. Serial Interface Timing Parameters

tCH Clock high time 40

tCL Clock low time 40

tEN Output enable time 20

tDE Output disable time 50 SDO

tSS Select setup time 20 tEN tSW

tSW Select high period 80

SDI FW Command Param Byte 0 Param Byte n

Figure 3. SPI Write Command

Figure 4. SPI Read Command—Check CTS Value

SDO Response Byte 0 Response Byte n

Figure 5. SPI Read Command—Clock Out Read Data

Figure 6. State Machine Diagram

Table 9. Operating State Response Time and Current Consumption

Tune = 100 [email protected] mA

Ready = 300 [email protected]

Reg Inrush = 5 usec@2 mA

Figure 7. Start-Up Timing and Current Consumption using Shutdown State