PLL Frequency Synthesizer

ADF4106
FEATURES GENERAL DESCRIPTION
6.0 GHz Bandwidth The ADF4106 frequency synthesizer can be used to implement
2.7 V to 3.3 V Power Supply local oscillators in the upconversion and downconversion sections
Separate Charge Pump Supply (VP) Allows Extended of wireless receivers and transmitters. It consists of a low noise
Tuning Voltage in 3 V Systems digital PFD (phase frequency detector), a precision charge pump,
Programmable Dual-Modulus Prescaler a programmable reference divider, programmable A and B
8/9, 16/17, 32/33, 64/65 counters, and a dual-modulus prescaler (P/P + 1). The A (6-bit)
Programmable Charge Pump Currents and B (13-bit) counters, in conjunction with the dual-modulus
Programmable Antibacklash Pulsewidth prescaler (P/P + 1), implement an N divider (N = BP + A). In
3-Wire Serial Interface addition, the 14-bit reference counter (R counter) allows selectable
Analog and Digital Lock Detect REFIN frequencies at the PFD input. A complete PLL (phase-
Hardware and Software Power-Down Modes locked loop) can be implemented if the synthesizer is used with
an external loop filter and VCO (voltage controlled oscillator).
APPLICATIONS
Its very high bandwidth means that frequency doublers can be
Broadband Wireless Access
eliminated in many high frequency systems, simplifying system
Instrumentation
architecture and lowering cost.
Wireless LANs
Base Stations for Wireless Radio

FUNCTIONAL BLOCK DIAGRAM

AVDD DVDD VP CPGND RSET

REFERENCE

REFIN 14-BIT PHASE

R COUNTER CHARGE CP
FREQUENCY PUMP
DETECTOR

14

R COUNTER LOCK CURRENT CURRENT

LATCH DETECT SETTING 1 SETTING 2

CLK
24-BIT INPUT FUNCTION CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
DATA REGISTER LATCH
22
LE

AB COUNTER HIGH Z
FROM LATCH
FUNCTION 19 AVDD
LATCH MUX MUXOUT
13
N = BP + A SDOUT
13-BIT
B COUNTER

LOAD
RFINA M3 M2 M1
PRESCALER
RFINB P/P + 1
LOAD

6-BIT
A COUNTER
ADF4106
6

CE AGND DGND
REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 www.analog.com
registered trademarks are the property of their respective companies. Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
ADF4106–SPECIFICATIONS1 (AVR ==5.1DVk;= 3dBmV
referred
10%; AV ≤ V ≤ 5.5 V; AGND = DGND = CPGND = 0 V;
DD DD DD P
to 50 ; T = T to T , unless otherwise noted.)
SET A MIN MAX

BChips2
1
Parameter B Version (Typ) Unit Test Conditions/Comments
RF CHARACTERISTICS See Figure 3 for Input Circuit
RF Input Frequency (RFIN)3 0.5/6.0 0.5/6.0 GHz min/max
RF Input Sensitivity –10/0 –10/0 dBm min/max
Maximum Allowable
Prescaler Output Frequency4 300 300 MHz max
REFIN CHARACTERISTICS
REFIN Input Frequency 20/250 20/250 MHz min/max For f < 20 MHz, Use DC-Coupled
Square Wave (0 to VDD)
REFIN Input Sensitivity5 0.8/AVDD 0.8/AVDD V p-p min/max AC-Coupled; When DC-Coupled,
0 to VDD max (CMOS Compatible)
REFIN Input Capacitance 10 10 pF max
REFIN Input Current ± 100 ± 100 µA max
PHASE DETECTOR
Phase Detector Frequency6 56 56 MHz max
CHARGE PUMP
ICP Sink/Source Programmable, See Table V
High Value 5 5 mA typ With RSET = 5.1 kΩ
Low Value 625 625 µA typ
Absolute Accuracy 2.5 2.5 % typ With RSET = 5.1 kΩ
RSET Range 2.7/10 2.7/10 kΩ typ See Table V
ICP Three-State Leakage Current 1 1 nA typ
Sink and Source Current Matching 2 2 % typ 0.5 V ⱕ VCP ⱕ VP – 0.5 V
ICP vs. VCP 1.5 1.5 % typ 0.5 V ⱕ VCP ⱕ VP – 0.5 V
ICP vs. Temperature 2 2 % typ VCP = VP/2
LOGIC INPUTS
VINH, Input High Voltage 1.4 1.4 V min
VINL, Input Low Voltage 0.6 0.6 V max
IINH/IINL, Input Current ±1 ±1 µA max
CIN, Input Capacitance 10 10 pF max
LOGIC OUTPUTS
VOH, Output High Voltage 1.4 1.4 V min Open-Drain Output Chosen 1 kΩ
Pull-up to 1.8 V
VOH, Output High Voltage VDD – 0.4 VDD – 0.4 V min CMOS Output Chosen
IOH 100 100 µA max
VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 µA
POWER SUPPLIES
AVDD 2.7/3.3 2.7/3.3 V min/V max
DVDD AVDD AVDD
VP AVDD/5.5 AVDD/5.5 V min/V max AVDD ⱕ VP ⱕ 5.5 V
IDD7 (AIDD + DIDD) 15 13 mA max 13 mA typ
IP 0.4 0.4 mA max TA = 25°C
Power-Down Mode8 (AIDD + DIDD) 10 10 µA typ

–2– REV. A
 ADF4106
BChips2
1
Parameter B Version (Typ) Unit Test Conditions/Comments
NOISE CHARACTERISTICS
ADF4106 Phase Noise Floor9 –174 –174 dBc/Hz typ @ 25 kHz PFD Frequency
–166 –166 dBc/Hz typ @ 200 kHz PFD Frequency
–159 –159 dBc/Hz typ @ 1 MHz PFD Frequency
Phase Noise Performance10 @ VCO Output
900 MHz Output11 –93 –93 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
5800 MHz Output12 –74 –74 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
5800 MHz Output13 –84 –84 dBc/Hz typ @ 1 kHz Offset and 1 MHz PFD Frequency
Spurious Signals
900 MHz Output11 –90/–92 –90/–92 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
5800 MHz Output12 –65/–70 –65/–70 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
5800 MHz Output13 –70/–75 –70/–75 dBc typ @ 1 MHz/2 MHz and 1 MHz PFD Frequency
NOTES
1
Operating temperature range (B Version) is –40°C to +85°C.
2
The BChip specifications are given as typical values.
3
Use a square wave for lower frequencies, below the mimimum stated.
4
The maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency
that is less than this value.
5
AVDD = DVDD = 3 V.
6
Guaranteed by design. Sample tested to ensure compliance.
7
TA = 25°C; AVDD = DVDD = 3 V; P = 16; RF IN = 6.0 GHz.
8
TA = 25°C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RF IN = 6.0 GHz.
9
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).
10
The phase noise is measured with the EVAL-ADF4106EB1 evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REF IN for
the synthesizer (f REFOUT = 10 MHz @ 0 dBm).
11
fREFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; f RF = 900 MHz; N = 4500; Loop B/W = 20 kHz.
12
fREFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; f RF = 5800 MHz; N = 29000; Loop B/W = 20 kHz.
13
fREFIN = 10 MHz; fPFD = 1 MHz; Offset Frequency = 1 kHz; f RF = 5800 MHz; N = 5800; Loop B/W = 100 kHz.
Specifications subject to change without notice.

(AVDD = DVDD = 3 V  10%; AVDD ≤ VP ≤ 5.5 V; AGND = DGND = CPGND = 0 V; RSET = 5.1 k;
TIMING CHARACTERISTICS TA = TMIN to TMAX, unless otherwise noted.)
Limit at
TMIN to TMAX
Parameter (B Version) Unit Test Conditions/Comments
t1 10 ns min DATA to CLOCK Setup Time
t2 10 ns min DATA to CLOCK Hold Time
t3 25 ns min CLOCK High Duration
t4 25 ns min CLOCK Low Duration
t5 10 ns min CLOCK to LE Setup Time
t6 20 ns min LE Pulsewidth
NOTES
Guaranteed by design but not production tested.
Specifications subject to change without notice.

t3 t4

CLOCK
t1 t2

DB1 (CONTROL DB0 (LSB)

DATA DB23 (MSB) DB22 DB2
BIT C2) (CONTROL BIT C1)
t6

LE

t5
LE

Figure 1. Timing Diagram

REV. A –3–
ADF4106
ABSOLUTE MAXIMUM RATINGS 1, 2 LFCSP ␪JA Thermal Impedance . . . . . . . . . . . . . . . . 122°C/W
(TA = 25°C, unless otherwise noted.) Lead Temperature, Soldering
AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.6 V Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
VP to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.8 V
VP to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.8 V NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
Digital I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V nent damage to the device. This is a stress rating only; functional operation of the
Analog I/O Voltage to GND . . . . . . . . . . –0.3 V to VP + 0.3 V device at these or any other conditions above those listed in the operational
REFIN, RFINA, RFINB to GND . . . . . . –0.3 V to VDD + 0.3 V sections of this specification is not implied. Exposure to absolute maximum rating
Operating Temperature Range conditions for extended periods may affect device reliability.
2
This device is a high performance RF integrated circuit with an ESD rating of
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C and assembly.
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C 3
GND = AGND = DGND = 0 V.
TSSOP ␪JA Thermal Impedance . . . . . . . . . . . . . . 150.4°C/W

ORDERING GUIDE

Model Temperature Range Package Option*

ADF4106BRU –40°C to +85°C RU-16
ADF4106BRU-REEL –40°C to +85°C RU-16
ADF4106BRU-REEL7 –40°C to +85°C RU-16
ADF4106BCP –40°C to +85°C CP-20
ADF4106BCP-REEL –40°C to +85°C CP-20
ADF4106BCP-REEL7 –40°C to +85°C CP-20
EVAL-ADF4106EB1
*RU = Thin Shrink Small Outline Package (TSSOP).
CP = Lead Frame Chip Scale Package (LFCSP).
Contact the factory for chip availability.
Note that aluminum bond wire should not be used with the ADF4106 die.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADF4106 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

–4– REV. A
 ADF4106
PIN CONFIGURATIONS

TSSOP LFCSP

17 DVDD
16 DVDD
19 RSET
20 CP

18 VP
RSET 1 16 VP
CP 2 15 DVDD

CPGND 3 14 MUXOUT
CPGND 1 PIN 1 15 MUXOUT
AGND 4 ADF4106 13 LE AGND 2
INDICATOR
14 LE
TOP VIEW AGND 3 ADF4106 13 DATA
RFINB 5 (Not to Scale) 12 DATA 12 CLK
RFINB 4 TOP VIEW
RFINA 6 11 CLK RFINA 5 11 CE

AVDD 7 10 CE

AVDD 6
AVDD 7
REFIN 8
DGND 9
DGND 10
REFIN 8 9 DGND

NOTE: TRANSISTOR COUNT 6425 (CMOS), 303 (BIPOLAR)

PIN FUNCTION DESCRIPTIONS

Mnemonic Function
RSET Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal
voltage potential at the RSET pin is 0.6 V. The relationship between ICP and RSET is
25.5
ICP MAX =
RSET
So, with RSET = 5.1 kΩ, ICP MAX = 5 mA.
CP Charge Pump Output. When enabled, this provides ± ICP to the external loop filter, which in turn drives the
external VCO.
CPGND Charge Pump Ground. This is the ground return path for the charge pump.
AGND Analog Ground. This is the ground return path of the prescaler.
RFINB Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF. See Figure 3.
RFINA Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
AVDD Analog Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of
100 kΩ. See Figure 2. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
DGND Digital Ground.
CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state
mode. Taking the pin high powers up the device, depending on the status of the power-down bit F2.
CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
DATA Serial Data Input. The serial data is loaded MSB first with the 2 LSB being the control bits. This input is a
high impedance CMOS input.
LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four
latches, the latch being selected using the control bits.
MUXOUT This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be
accessed externally.
DVDD Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
VP Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can be
set to 5 V and used to drive a VCO with a tuning range of up to 5 V.

REV. A –5–
ADF4106–Typical Performance Characteristics
–40
FREQ UNIT – GHz KEYWORD – R
PARAM TYPE – S IMPEDANCE  – 50 10dB/DIV
DATA FORMAT – MA
–50 RL = –40dBc/Hz
FREQ MAGS11 ANGS11 FREQ MAGS11 ANGS11 RMS NOISE = 0.36
0.500 0.89148 – 17.2820 3.300 0.42777 – 102.748
0.600 0.88133 – 20.6919 3.400 0.42859 – 107.167 –60
0.700 0.87152 – 24.5386 3.500 0.43365 – 111.883
0.800 0.85855 – 27.3228 3.600 0.43849 – 117.548
–70

PHASE NOISE – dBc/Hz

0.900 0.84911 – 31.0698 3.700 0.44475 – 123.856
1.000 0.83512 – 34.8623 3.800 0.44800 – 130.399
1.100 0.82374 – 38.5574 3.900 0.45223 – 136.744
1.200 0.80871 – 41.9093 4.000 0.45555 – 142.766 –80
1.300 0.79176 – 45.6990 4.100 0.45313 – 149.269
1.400 0.77205 – 49.4185 4.200 0.45622 – 154.884
1.500 0.75696 – 52.8898 4.300 0.45555 – 159.680 –90
1.600 0.74234 – 56.2923 4.400 0.46108 – 164.916
1.700 0.72239 – 60.2584 4.500 0.45325 – 168.452
1.800 0.69419 – 63.1446 4.600 0.45054 – 173.462
1.900 0.67288 – 65.6464 4.700 0.45200 – 176.697
–100
2.000 0.66227 – 68.0742 4.800 0.45043 178.824
2.100 0.64758 – 71.3530 4.900 0.45282 174.947
2.200 0.62454 – 75.5658 5.000 0.44287 170.237 –110
2.300 0.59466 – 79.6404 5.100 0.44909 166.617
2.400 0.55932 – 82.8246 5.200 0.44294 162.786
2.500 0.52256 – 85.2795 5.300 0.44558 158.766 –120
2.600 0.48754 – 85.6298 5.400 0.45417 153.195
2.700 0.46411 – 86.1854 5.500 0.46038 147.721
2.800 0.45776 – 86.4997 5.600 0.47128 139.760 –130
2.900 0.44859 – 88.8080 5.700 0.47439 132.657
3.000 0.44588 – 91.9737 5.800 0.48604 125.782
3.100 0.43810 – 95.4087 5.900 0.50637 121.110 –140
3.200 0.43269 – 99.1282 6.000 0.52172 115.400 100Hz 1MHz
FREQUENCY OFFSET FROM 900MHz CARRIER

TPC 1. S-Parameter Data for the RF Input TPC 4. Integrated Phase Noise (900 MHz, 200 kHz,
and 20 kHz)

0 0
VDD = 3V REF LEVEL = –14.0dBm
VP = 3V –10 VDD = 3V, VP = 5V
–5 ICP = 5mA
–20 PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES BANDWIDTH = 1kHz
OUTPUT POWER – dB

OUTPUT POWER – dB
–30
–10 VIDEO BANDWIDTH = 1kHz
–40 SWEEP = 2.5 SECONDS
AVERAGES = 30
–15 –50

–60
–20
TA = +85C –70

–80 –91.0dBc/Hz
–25
TA = +25C
TA = –40C –90

–30 –100
0 1 2 3 4 5 6 –400kHz –200kHz 900MHz 200kHz 400kHz
RF INPUT FREQUENCY – GHz FREQUENCY

TPC 2. Input Sensitivity TPC 5. Reference Spurs (900 MHz, 200 kHz, and 20 kHz)

0 0
REF LEVEL = –14.3dBm REF LEVEL = –10dBm
–10 VDD = 3V, VP = 5V –10 VDD = 3V, VP = 5V
ICP = 5mA ICP = 5mA
–20 PFD FREQUENCY = 200kHz –20 PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 20kHz LOOP BANDWIDTH = 100kHz
RES BANDWIDTH = 10Hz RES BANDWIDTH = 10Hz
OUTPUT POWER – dB

OUTPUT POWER – dB

–30 –30
VIDEO BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz
–40 SWEEP = 1.9 SECONDS –40 SWEEP = 1.9 SECONDS
AVERAGES = 10 AVERAGES = 10
–50 –50

–60 –60

–70 –93.0dBc/Hz –70

–80 –80 –84.0dBc/Hz

–90 –90

–100 –100
–2kHz –1kHz 900MHz 1kHz 2kHz –2kHz –1kHz 5800MHz 1kHz 2kHz
FREQUENCY FREQUENCY

TPC 3. Phase Noise (900 MHz, 200 kHz, and 20 kHz) TPC 6. Phase Noise (5.8 GHz, 1 MHz, and 100 kHz)

–6– REV. A
 ADF4106
–40 –5
10dB/DIV VDD = 3V
–50 RL = –40dBc/Hz –15 VP = 5V
RMS NOISE = 1.8

FIRST REFERENCE SPUR – dBc

–60 –25
PHASE NOISE – dBc/Hz

–70 –35

–80 –45

–90 –55

–100 –65

–110 –75

–120 –85

–130 –95

–140 –105
100Hz 1MHz 0 1 2 3 4 5
FREQUENCY OFFSET FROM 5800MHz CARRIER TUNING VOLTAGE – V

TPC 7. Integrated Phase Noise (5.8 GHz, 1 MHz, TPC 10. Reference Spurs vs. VTUNE (5.8 GHz,
and 100 kHz) 1 MHz, and 100 kHz)

0 –120
REF LEVEL = –10.0dBm VDD = 3V, VP = 5V VDD = 3V
–10 ICP = 5mA VP = 5V
PDF FREQUENCY = 1MHz –130
–20 LOOP BANDWIDTH = 100kHz
RES BANDWIDTH = 1kHz

OUTPUT POWER – dBc/Hz

OUTPUT POWER – dB

–30 VIDEO BANDWIDTH = 1kHz

SWEEP = 13 SECONDS –140
–40 AVERAGES = 1

–50 –150
–66.0dBc –65.0dBc
–60
–160
–70

–80
–170
–90

–100 –180
–2 –1 5800 1 2 10k 100k 1M 10M 100M
FREQUENCY – MHz PHASE DETECTOR FREQUENCY – Hz

TPC 8. Reference Spurs (5.8 GHz, 1 MHz, and 100 kHz) TPC 11. Phase Noise (Referred to CP Output) vs.
PFD Frequency

–60 10
VDD = 3V
9
VP = 5V
8
–70
PHASE NOISE – dBc/Hz

6
AIDD – mA

–80 5

3
–90
2

–100 0
–40 –20 0 20 40 60 80 100 8/9 16/17 32/33 64/65
TEMPERATURE – C PRESCALER VALUE

TPC 9. Phase Noise (5.8 GHz, 1 MHz, and 100 kHz) TPC 12. AIDD vs. Prescaler Value
vs. Temperature

REV. A –7–
ADF4106
3.5 6
VDD = 3V
VP = 3V
3.0
4
VP = 5V
2.5 ICP = 5mA
2
DIDD – mA

2.0

ICP – mA
0
1.5

–2
1.0

0.5 –4

0 –6
50 100 150 200 250 300 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
PRESCALER OUTPUT FREQUENCY VCP – V

TPC 13. DIDD vs. Prescaler Output Frequency TPC 14. Charge Pump Output Characteristics

CIRCUIT DESCRIPTION PRESCALER (P/P + 1)

REFERENCE INPUT SECTION The dual-modulus prescaler (P/P + 1), along with the A and B
The reference input stage is shown in Figure 2. SW1 and SW2 counters, enables the large division ratio, N, to be realized (N =
are normally closed switches. SW3 is normally open. When BP + A). The dual-modulus prescaler, operating at CML levels,
power-down is initiated, SW3 is closed and SW1 and SW2 are takes the clock from the RF input stage and divides it down to a
opened. This ensures that there is no loading of the REFIN pin manageable frequency for the CMOS A and B counters. The
on power-down. prescaler is programmable. It can be set in software to 8/9, 16/17,
32/33, or 64/65. It is based on a synchronous 4/5 core. There is
POWER-DOWN a minimum divide ratio possible for fully contiguous output
CONTROL
frequencies. This minimum is determined by P, the prescaler
value, and is given by (P2 – P).
100k
NC
A AND B COUNTERS
SW2
REFIN TO R COUNTER
The A and B CMOS counters combine with the dual-modulus
NC
BUFFER prescaler to allow a wide ranging division ratio in the PLL feed-
SW1
back counter. The counters are specified to work when the
prescaler output is 300 MHz or less. Thus, with an RF input
NO
SW3 frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a
NC = NO CONNECT value of 8/9 is not.
Figure 2. Reference Input Stage Pulse Swallow Function
The A and B counters, in conjunction with the dual-modulus
RF INPUT STAGE prescaler, make it possible to generate output frequencies that
The RF input stage is shown in Figure 3. It is followed by a are spaced only by the reference frequency divided by R. The
two-stage limiting amplifier to generate the CML clock levels equation for the VCO frequency is as follows:
needed for the prescaler.
[ fREFIN
fVCO = (P × B) + A ×
R
]
BIAS 1.6V
GENERATOR AVDD
fVCO Output frequency of external voltage controlled
oscillator (VCO).
500 500 P Preset modulus of dual-modulus prescaler
(8/9, 16/17, and so on).
B Preset divide ratio of binary 13-bit counter
RF A
IN (3 to 8191).
A Preset divide ratio of binary 6-bit swallow
RF B
IN
counter (0 to 63).
fREFIN External reference frequency oscillator.

AGND

Figure 3. RF Input Stage

–8– REV. A
 ADF4106
MUXOUT AND LOCK DETECT
N = BP + A
The output multiplexer on the ADF4106 allows the user to access
TO PFD
various internal points on the chip. The state of MUXOUT is
13-BIT B
COUNTER controlled by M3, M2, and M1 in the function latch. Table V
FROM RF PRESCALER LOAD shows the full truth table. Figure 6 shows the MUXOUT section
INPUT STAGE P/P + 1 LOAD in block diagram form.
6-BIT A
MODULUS COUNTER Lock Detect
CONTROL
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
N DIVIDER
Digital lock detect is active high. When LDP in the R counter
Figure 4. A and B Counters latch is set to 0, digital lock detect is set high when the phase
error on three consecutive phase detector cycles is less than 15 ns.
R COUNTER With LDP set to 1, five consecutive cycles of less than 15 ns are
The 14-bit R counter allows the input reference frequency to be required to set the lock detect. It will stay set high until a phase
divided down to produce the reference clock to the phase fre- error of greater than 25 ns is detected on any subsequent PD cycle.
quency detector (PFD). Division ratios from 1 to 16,383 are The N-channel open-drain analog lock detect should be operated
allowed. with an external pull-up resistor of 10 kΩ nominal. When lock
has been detected, this output will be high with narrow low-
PHASE FREQUENCY DETECTOR AND CHARGE PUMP going pulses.
The PFD takes inputs from the R counter and N counter (N =
BP + A) and produces an output proportional to the phase and DVDD

frequency difference between them. Figure 5 is a simplified

schematic. The PFD includes a programmable delay element
that controls the width of the antibacklash pulse. This pulse ANALOG LOCK DETECT
ensures that there is no dead zone in the PFD transfer function DIGITAL LOCK DETECT
and minimizes phase noise and reference spurs. Two bits in the
reference counter latch, ABP2 and ABP1, control the width of R COUNTER OUTPUT MUX CONTROL
MUXOUT
the pulse. See Table III. N COUNTER OUTPUT

VP SDOUT
CHARGE
PUMP
UP
HI D1 Q1

U1 DGND
R DIVIDER
CLR1
Figure 6. MUXOUT Circuit
PROGRAMMABLE
U3 INPUT SHIFT REGISTER
DELAY
CP
The ADF4106 digital section includes a 24-bit input shift register,
ABP2 ABP1 a 14-bit R counter, and a 19-bit N counter, comprising a 6-bit A
counter and a 13-bit B counter. Data is clocked into the 24-bit
shift register on each rising edge of CLK. The data is clocked
HI
DOWN in MSB first. Data is transferred from the shift register to one
D2 Q2
of four latches on the rising edge of LE. The destination latch
U2 is determined by the state of the two control bits (C2, C1) in
N DIVIDER
CLR2
CPGND the shift register. These are the two LSBs, DB1 and DB0, as
shown in the timing diagram of Figure 1. The truth table for these
bits is shown in Table VI. Table I shows a summary of how
the latches are programmed.
R DIVIDER

Table I. C2, C1 Truth Table

N DIVIDER
Control Bits
CP OUTPUT C2 C1 Data Latch
0 0 R Counter
Figure 5. PFD Simplified Schematic and Timing (In Lock) 0 1 N Counter (A and B)
1 0 Function Latch (Including Prescaler)
1 1 Initialization Latch

REV. A –9–
ADF4106
Table II. Latch Summary

REFERENCE COUNTER LATCH

PRECISION
DETECT

ANTI-
LOCK

TEST BACKLASH 14-BIT REFERENCE COUNTER CONTROL

RESERVED MODE BITS WIDTH BITS

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

X 0 0 LDP T2 T1 ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0)

N COUNTER LATCH
CP GAIN

RESERVED 13-BIT B COUNTER 6-BIT A COUNTER CONTROL

BITS

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 C2 (0) C1 (1)

FUNCTION LATCH
CP THREE-
FASTLOCK
FASTLOCK

COUNTER
POLARITY
ENABLE

POWER-
DOWN 1
POWER-
DOWN 2

RESET
STATE
MODE

PRESCALER CURRENT CURRENT TIMER COUNTER MUXOUT CONTROL

PD

VALUE SETTING SETTING CONTROL CONTROL BITS

2 1

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (0)

INITIALIZATION LATCH
FASTLOCK

FASTLOCK

CP THREE-

POLARITY

COUNTER
POWER-

ENABLE
DOWN 2

POWER-
DOWN 1

RESET
MODE

STATE

PRESCALER CURRENT CURRENT MUXOUT CONTROL

PD

SETTING SETTING TIMER COUNTER BITS

VALUE CONTROL CONTROL
2 1

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (1)

–10– REV. A
 ADF4106
Table III. Reference Counter Latch Map

PRECISION
DETECT
ANTI-

LOCK
TEST 14-BIT REFERENCE COUNTER CONTROL
RESERVED MODE BITS BACKLASH BITS
WIDTH

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

X 0 0 LDP T2 T1 ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0)

X = DON’T CARE
R14 R13 R12 .......... R3 R2 R1 DIVIDE RATIO
0 0 0 .......... 0 0 1 1
0 0 0 .......... 0 1 0 2
0 0 0 .......... 0 1 1 3
0 0 0 .......... 1 0 0 4
. . . .......... . . . .
. . . .......... . . . .
. . . .......... . . . .
1 1 1 .......... 1 0 0 16380

1 1 1 .......... 1 0 1 16381

1 1 1 .......... 1 1 0 16382

1 1 1 .......... 1 1 1 16383

ABP2 ABP1 ANTIBACKLASH PULSEWIDTH

0 0 2.9 ns
0 1 1.3 ns
1 0 6.0 ns
1 1 2.9 ns

TEST MODE BITS

SHOULD BE SET
TO 00 FOR NORMAL
OPERATION .

LDP OPERATION
0 THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15 ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1 FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15 ns MUST OCCUR BEFORE LOCK DETECT IS SET.

BOTH OF THESE BITS

MUST BE SET TO 0 FOR
NORMAL OPERATION .

REV. A –11–
 ADF4106
CP GAIN Table IV. AB Counter Latch Map

RESERVED 13-BIT B COUNTER 6-BIT A COUNTER CONTROL

BITS

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

X X G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 C2 (0) C1 (1)

X = DON’T CARE

A COUNTER
A6 A5 .......... A2 A1 DIVIDE RATIO
0 0 .......... 0 0 0
0 0 .......... 0 1 1
0 0 .......... 1 0 2
0 0 .......... 1 1 3
. . .......... . . .
. . .......... . . .
. . .......... . . .
1 1 .......... 0 0 60
1 1 .......... 0 1 61
1 1 .......... 1 0 62
1 1 .......... 1 1 63

B13 B12 B11 B3 B2 B1 B COUNTER DIVIDE RATIO

0 0 0 .......... 0 0 0 NOT ALLOWED
0 0 0 .......... 0 0 1 NOT ALLOWED
0 0 0 .......... 0 1 0 NOT ALLOWED
0 0 0 .......... 1 1 1 3
. . . .......... . . . .
. . . .......... . . . .
. . . .......... . . . .
1 1 1 .......... 1 0 0 8188
1 1 1 .......... 1 0 1 8189
1 1 1 .......... 1 1 0 8190
1 1 1 .......... 1 1 1 8191

F4 (FUNCTION LATCH)
FASTLOCK ENABLE CP GAIN OPERATION

0 0 CHARGE PUMP CURRENT SETTING

1 IS PERMANENTLY USED.
0 1 CHARGE PUMP CURRENT SETTING
2 IS PERMANENTLY USED.
1 0 CHARGE PUMP CURRENT SETTING
1 IIS PERMANENTLY USED.
1 1 CHARGE PUMP CURRENT IS
SWITCHED TO SETTING 2. THE
TIME SPENT IN SETTING 2 IS
DEPENDENT ON WHICH FASTLOCK
MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION
N = BP + A; P IS PRESCALER VALUE SET IN THE FUNCTION LATCH.
B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY
ADJACENT VALUES OF (N  FREF), AT THE OUTPUT, NMIN, IS (P2 – P).

THESE BITS ARE NOT USED

BY THE DEVICE AND ARE
DON'T CARE BITS.

–12– REV. A
 ADF4106
Table V. Function Latch Map

FASTLOCK

POLARITY
FASTLOCK

COUNTER
ENABLE
POWER-

POWER-
DOWN 2

DOWN 1
THREE-

RESET
STATE
MODE
PRESCALER CURRENT CURRENT MUXOUT CONTROL
TIMER COUNTER

PD
CP
VALUE SETTING SETTING CONTROL BITS
2 1 CONTROL

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (0)

PHASE DETECTOR COUNTER

F2 POLARITY F1 OPERATION
0 NEGATIVE 0 NORMAL
1 POSITIVE 1 R, A, B COUNTERS
HELD IN RESET

CHARGE PUMP
F3 OUTPUT
0 NORMAL
1 THREE-STATE

F4 F5 FASTLOCK MODE
0 X FASTLOCK DISABLED
1 0 FASTLOCK MODE 1
1 1 FASTLOCK MODE 2

TIMEOUT M3 M2 M1 OUTPUT
TC4 TC3 TC2 TC1 (PFD CYCLES) 0 0 0 THREE-STATE OUTPUT
0 0 0 0 3 0 0 1 DIGITAL LOCK DETECT
0 0 0 1 7 (ACTIVE HIGH)
0 0 1 0 11 0 1 0 N DIVIDER OUTPUT
0 0 1 1 15 0 1 1 DVDD
DVDD
0 1 0 0 19 1 0 0 R DIVIDER OUTPUT
0 1 0 1 23 1 0 1 N-CHANNEL OPEN-DRAIN
0 1 1 0 27 LOCK DETECT
0 1 1 1 31 1 1 0 SERIAL DATA OUTPUT
1 0 0 0 35 1 1 1 DGND
1 0 0 1 39
1 0 1 0 43
1 0 1 1 47
1 1 0 0 51
1 1 0 1 55
1 1 1 0 59
1 1 1 1 63

CPI6 CPI5 CPI4 ICP (mA)

CPI3 CPI2 CPI1 3 k 5.1 k 11 k
0 0 0 1.06 0.625 0.289
0 0 1 2.12 1.25 0.580
0 1 0 3.18 1.875 0.870
0 1 1 4.24 2.5 1.160
1 0 0 5.30 3.125 1.450
1 0 1 6.36 3.75 1.730
1 1 0 7.42 4.375 2.020
1 1 1 8.50 5.0 2.320

CE PIN PD2 PD1 MODE

0 X X ASYNCHRONOUS POWER-DOWN
1 X 0 NORMAL OPERATION
1 0 1 ASYNCHRONOUS POWER-DOWN
1 1 1 SYNCHRONOUS POWER-DOWN

P2 P1 PRESCALER VALUE
0 0 8/9
0 1 16/17
1 0 32/33
1 1 64/65

REV. A –13–
ADF4106
Table VI. Initialization Latch Map

FASTLOCK

POLARITY
FASTLOCK

COUNTER
ENABLE
POWER-

POWER-
DOWN 2

DOWN 1
THREE-

RESET
STATE
MODE
PRESCALER CURRENT CURRENT MUXOUT CONTROL
TIMER COUNTER

PD
CP
VALUE SETTING SETTING CONTROL BITS
2 1 CONTROL

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (1)

PHASE DETECTOR COUNTER

F2 POLARITY F1 OPERATION
0 NEGATIVE 0 NORMAL
1 POSITIVE 1 R, A, B COUNTERS
HELD IN RESET

CHARGE PUMP
F3 OUTPUT
0 NORMAL
1 THREE-STATE

F4 F5 FASTLOCK MODE
0 X FASTLOCK DISABLED
1 0 FASTLOCK MODE 1
1 1 FASTLOCK MODE 2

TIMEOUT M3 M2 M1 OUTPUT
TC4 TC3 TC2 TC1 (PFD CYCLES) 0 0 0 THREE-STATE OUTPUT
0 0 0 0 3 0 0 1 DIGITAL LOCK DETECT
0 0 0 1 7 (ACTIVE HIGH)
0 0 1 0 11 0 1 0 N DIVIDER OUTPUT
0 0 1 1 15 0 1 1 DVDD
DVDD
0 1 0 0 19 1 0 0 R DIVIDER OUTPUT
0 1 0 1 23 1 0 1 N-CHANNEL OPEN-DRAIN
0 1 1 0 27 LOCK DETECT
0 1 1 1 31 1 1 0 SERIAL DATA OUTPUT
1 0 0 0 35 1 1 1 DGND
1 0 0 1 39
1 0 1 0 43
1 0 1 1 47
1 1 0 0 51
1 1 0 1 55
1 1 1 0 59
1 1 1 1 63

CPI6 CPI5 CPI4 ICP (mA)

CPI3 CPI2 CPI1 3 k 5.1 k 11 k
0 0 0 1.06 0.625 0.289
0 0 1 2.12 1.25 0.580
0 1 0 3.18 1.875 0.870
0 1 1 4.24 2.5 1.160
1 0 0 5.30 3.125 1.450
1 0 1 6.36 3.75 1.730
1 1 0 7.42 4.375 2.020
1 1 1 8.50 5.0 2.320

CE PIN PD2 PD1 MODE

0 X X ASYNCHRONOUS POWER-DOWN
1 X 0 NORMAL OPERATION
1 0 1 ASYNCHRONOUS POWER-DOWN
1 1 1 SYNCHRONOUS POWER-DOWN

P2 P1 PRESCALER VALUE
0 0 8/9
0 1 16/17
1 0 32/33
1 1 64/65

–14– REV. A
 ADF4106
FUNCTION LATCH Fastlock Mode 2
With C2, C1 set to 1, 0, the on-chip function latch will be The charge pump current is switched to the contents of Current
programmed. Table V shows the input data format for program- Setting 2. The device enters fastlock by having a 1 written to the
ming the function latch. CP gain bit in the AB counter latch. The device exits fastlock
under the control of the timer counter. After the timeout period
Counter Reset determined by the value in TC4 through TC1, the CP gain bit in
DB2 (F1) is the counter reset bit. When this is 1, the R counter the AB counter latch is automatically reset to 0 and the device
and the A, B counters are reset. For normal operation, this bit reverts to normal mode instead of fastlock. See Table V for the
should be 0. Upon power-up, the F1 bit needs to be disabled (set to 0). timeout periods.
The N counter then resumes counting in close alignment with the R
counter. (The maximum error is one prescaler cycle.) Timer Counter Control
The user has the option of programming two charge pump
Power-Down currents. The intent is that the Current Setting 1 is used when the
DB3 (PD1) and DB21 (PD2) on the ADF4106 provide program- RF output is stable and the system is in a static state. Current
mable power-down modes. They are enabled by the CE pin. When Setting 2 is meant to be used when the system is dynamic and in a
the CE pin is low, the device is immediately disabled regardless of state of change (e.g., when a new output frequency is pro-
the states of PD2, PD1. In the programmed asynchronous power- grammed). The normal sequence of events is as follows.
down, the device powers down immediately after latching a 1 into
bit PD1, with the condition that PD2 has been loaded with a 0. In Users initially decide what the preferred charge pump currents
the programmed synchronous power-down, the device power- will be. For example, they may choose 2.5 mA as Current
down is gated by the charge pump to prevent unwanted frequency Setting 1 and 5 mA as Current Setting 2. At the same time, they
jumps. Once the power-down is enabled by writing a 1 into bit must also decide how long they want the secondary current to stay
PD1 (on condition that a 1 has also been loaded to PD2), the active before reverting to the primary current. This is controlled
device will go into power-down on the occurrence of the next by the timer counter control bits DB14 to DB11 (TC4 through
charge pump event. When a power-down is activated (either TC1) in the function latch. The truth table is provided in Table V.
synchronous or asynchronous mode including CE pin-activated When users want to program a new output frequency, they can
power-down), the following events occur: simply program the AB counter latch with new values for A and B.
• All active dc current paths are removed. At the same time, they can set the CP gain bit to a 1, which sets
• The R, N, and timeout counters are forced to their load the charge pump with the value in CPI6 through CPI4 for a period
state conditions. of time determined by TC4 through TC1. When this time is up,
• The charge pump is forced into three-state mode. the charge pump current reverts to the value set by CPI3 through
• The digital lock detect circuitry is reset. CPI1. At the same time, the CP Gain bit in the AB counter latch
• The RFIN input is debiased. is reset to 0 and is ready for the next time the user wants to change
• The reference input buffer circuitry is disabled. the frequency.
• The input register remains active and capable of loading Note that there is an enable feature on the timer counter. It is
and latching data. enabled when Fastlock Mode 2 is chosen when the fastlock mode
MUXOUT Control bit (DB10) in the function latch is set to 1.
The on-chip multiplexer is controlled by M3, M2, and M1 on Charge Pump Currents
the ADF4106. Table V shows the truth table. CPI3, CPI2, and CPI1 program Current Setting 1 for the charge
Fastlock Enable Bit pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the
DB9 of the function latch is the fastlock enable bit. Only when charge pump. The truth table is in Table V.
this is 1 is fastlock enabled. Prescaler Value
Fastlock Mode Bit P2 and P1 in the function latch set the prescaler values. The
DB10 of the function latch is the fastlock mode bit. When fastlock prescaler value should be chosen so that the prescaler output
is enabled, this bit determines which fastlock mode is used. If frequency is always less than or equal to 300 MHz. Thus, with
the fastlock mode bit is 0, Fastlock Mode 1 is selected, and if an RF frequency of 4 GHz, a prescaler value of 16/17 is valid,
the fastlock mode bit is 1, Fastlock Mode 2 is selected. but a value of 8/9 is not.
Fastlock Mode 1 PD Polarity
The charge pump current is switched to the contents of Current This bit sets the phase detector polarity bit. See Table V.
Setting 2. The device enters fastlock by having a 1 written to the CP Three-State
CP gain bit in the AB counter latch. The device exits fastlock by This bit controls the CP output pin. With the bit set high, the
having a 0 written to the CP gain bit in the AB counter latch. CP output is put into three-state. With the bit set low, the CP
output is enabled.

REV. A –15–
ADF4106
INITIALIZATION LATCH Counter Reset Method
When C2, C1 = 1, 1, the initialization latch is programmed. This is • Apply VDD.
essentially the same as the function latch (programmed when C2, • Do a function latch load (10 in 2 LSB). As part of
C1 = 1, 0). this, load 1 to the F1 bit. This enables the counter reset.
However, when the initialization latch is programmed, there is • Do an R counter load (00 in 2 LSB).
an additional internal reset pulse applied to the R and AB • Do an AB counter load (01 in 2 LSB).
counters. This pulse ensures that the AB counter is at the load • Do a function latch load (10 in 2 LSB). As part of
point when the AB counter data is latched, and the device will this, load 0 to the F1 bit. This disables the counter reset.
begin counting in close phase alignment. This sequence provides the same close alignment as the initial-
If the latch is programmed for synchronous power-down (CE ization method. It offers direct control over the internal reset.
pin is high; PD1 bit is high; PD2 bit is low), the internal pulse Note that counter reset holds the counters at load point and
also triggers this power-down. The prescaler reference and the three-states the charge pump but does not trigger synchronous
oscillator input buffer are unaffected by the internal reset pulse, power-down.
so close phase alignment is maintained when counting resumes.
APPLICATION
When the first AB counter data is latched after initialization, the Local Oscillator for LMDS Base Station Transmitter
internal reset pulse is again activated. However, subsequent AB Figure 7 shows the ADF4106 being used with a VCO to pro-
counter loads will not trigger the internal reset pulse. duce the LO for an LMDS base station operation in the
5.4 GHz to 5.8 GHz band.
DEVICE PROGRAMMING AFTER INITIAL POWER-UP
After the device is initially powered up, there are three ways to The reference input signal is applied to the circuit at FREFIN
program it. and, in this case, is terminated in 50 Ω. A typical base station
system would have either a TCXO or an OCXO driving the
Initialization Latch Method reference input without any 50 Ω termination.
• Apply VDD.
• Program the initialization latch (11 in 2 LSB of input To have a channel spacing of 1 MHz at the output, the 10 MHz
word). Make sure that F1 bit is programmed to 0. reference input must be divided by 10, using the on-chip refer-
• Do a function latch load (10 in 2 LSB of the control ence divider of the ADF4106.
word), making sure that the F1 bit is programmed to a 0. The charge pump output of the ADF4106 (Pin 2) drives the
• Do an R load (00 in 2 LSB). loop filter. In calculating the loop filter component values, a
• Do an AB load (01 in 2 LSB). number of items need to be considered. In this example, the
When the initialization latch is loaded, the following occurs: loop filter was designed so that the overall phase margin for the
1. The function latch contents are loaded. system would be 45 degrees. Other PLL system specifications
2. An internal pulse resets the R, A, B, and timeout counters are given below:
to load state conditions and three-states the charge pump. KD = 2.5 mA
Note that the prescaler band gap reference and the oscilla- KV = 80 MHz/V
tor input buffer are unaffected by the internal reset pulse, Loop Bandwidth = 50 kHz
allowing close phase alignment when counting resumes. FREF = 1 MHz
3. Latching the first AB counter data after the initialization N = 5800
word will activate the same internal reset pulse. Successive Extra Reference Spur Attenuation = 10 dB
AB loads will not trigger the internal reset pulse unless All of these specifications are needed and used to come up with
there is another initialization. the loop filter component values shown in Figure 7.
CE Pin Method Figure 7 gives a typical phase noise performance of –83 dBc/Hz
• Apply VDD. at 1 kHz offset from the carrier. Spurs are better than –62 dBc.
• Bring CE low to put the device into power-down. This is an
asynchronous power-down (it happens immediately). The loop filter output drives the VCO, which, in turn, is fed
• Program the function latch (10). back to the RF input of the PLL synthesizer. It also drives the
• Program the R counter latch (00). RF output terminal. A T-circuit configuration provides 50 Ω
• Program the AB counter latch (01). matching between the VCO output, the RF output, and the
• Bring CE high to take the device out of power-down. RFIN terminal of the synthesizer. Note that the ADF4106 RF
input looks like 50 Ω at 5.8 GHz, so no terminating resistor is
The R and AB counters will then resume counting in close needed. When operating at lower frequencies, however, this is
alignment. Note that after CE goes high, a duration of 1 µs may not the case.
be required for the prescaler band gap voltage and oscillator
input buffer bias to reach steady state. In a PLL system, it is important to know when the system is
locked. In Figure 7, this is accomplished by using the MUXOUT
CE can be used to power the device up and down to check for signal from the synthesizer. The MUXOUT pin can be pro-
channel activity. The input register does not need to be repro- grammed to monitor various internal signals in the synthesizer.
grammed each time the device is disabled and enabled as long as it One of these is the LD or (lock detect) signal.
has been programmed at least once after VDD was initially applied.

–16– REV. A
 ADF4106
VDD VP

RFOUT

100pF

18
100pF 18
AVDD DVDD VP 6.2k
1000pF 1000pF CP VCC
FREFIN REFIN
100pF 20pF 18
4.3k V940ME03
51

ADF4106
1, 3, 4, 5, 7, 8,
1.5nF 9, 11, 12, 13

CE
LOCK
CLK MUXOUT DETECT
DATA
LE
SPI COMPATIBLE SERIAL BUS

100pF
RFINA
RSET
RFINB
CPGND

AGND

DGND

5.1k
100pF

NOTE
DECOUPLING CAPACITORS (0.1F/10pF) ON AVDD, DVDD,
VP OF THE ADF4106 AND ON VCC OF THE V940ME03 HAVE
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.

Figure 7. Local Oscillator for LMDS Station

INTERFACING On first application of power to the ADF4106, three writes are

The ADF4106 has a simple SPI compatible serial interface for® needed (one to the R counter latch, one to the N counter latch,
writing to the device. CLK, DATA, and LE control the data and one to the function latch) for the output to become active.
transfer. When LE (latch enable) goes high, the 24 bits that I/O port lines on the ADuC812 are also used to control
have been clocked into the input register on each rising edge of power-down (CE input) and to detect lock (MUXOUT config-
SCLK get transferred to the appropriate latch. See Figure 1 for ured as lock detect and polled by the port input).
the timing diagram and Table I for the latch truth table.
When operating in the mode described, the maximum SCLOCK
The maximum allowable serial clock rate is 20 MHz. This rate of the ADuC812 is 4 MHz. This means that the maximum
means that the maximum update rate possible for the device is rate at which the output frequency can be changed is 166 kHz.
833 kHz or one update every 1.2 µs. This is certainly more than
adequate for systems that have typical lock times in hundreds of
SCLOCK CLK
microseconds.
ADuC812 Interface MOSI DATA

Figure 8 shows the interface between the ADF4106 and the LE

ADuC812 ADF4106
ADuC812 MicroConverter®. Since the ADuC812 is based on
I/O PORTS CE
an 8051 core, this interface can be used with any 8051 based
microcontroller. The MicroConverter is set up for SPI master MUXOUT
(LOCK DETECT)
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4106 needs a
24-bit word. This is accomplished by writing three 8-bit bytes
from the MicroConverter to the device. When the third byte has
been written, the LE input should be brought high to complete Figure 8. ADuC812 to ADF4106 Interface
the transfer.

REV. A –17–
ADF4106
ADSP-2181 Interface
SCLOCK CLK
Figure 9 shows the interface between the ADF4106 and the
ADSP-21xx digital signal processor. The ADF4106 needs a 24-bit MOSI DATA
serial word for each latch write. The easiest way to accomplish
ADSP-21xx TFS LE ADF4106
this using the ADSP-21xx family is to use the autobuffered
transmit mode of operation with alternate framing. This provides CE
a means for transmitting an entire block of serial data before an I/O FLAGS
MUXOUT
interrupt is generated. Set up the word length for eight bits and use (LOCK DETECT)
three memory locations for each 24-bit word. To program each
24-bit latch, store the three 8-bit bytes, enable the autobuffered
mode, and then write to the transmit register of the DSP. This
last operation initiates the autobuffer transfer. Figure 9. ADSP-21xx to ADF4106 Interface

–18– REV. A
 ADF4106
OUTLINE DIMENSIONS

16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)
Dimensions shown in millimeters

5.10
5.00
4.90

16 9

4.50
6.40
4.40 BSC
4.30

1 8

PIN 1
1.20
MAX
0.15 0.20
0.05 0.09 0.75
0.30 8 0.60
0.65 0 0.45
0.19 SEATING
BSC
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MS-153AB

20-Lead Lead Frame Chip Scale Package [LFCSP]

(CP-20)
Dimensions shown in millimeters

0.60
4.0 MAX
BSC SQ
0.60
MAX 16 20
15 1
PIN 1
INDICATOR 2.25
TOP 3.75 BOTTOM
VIEW 2.10 SQ
BSC SQ VIEW
1.95
0.75 11 5
10 6
0.55
0.35
0.80 MAX
12 MAX 0.30
0.65 NOM
1.00 0.23
0.90 0.05 0.18
0.80 0.02
SEATING 0.00 COPLANARITY
0.50 0.20
PLANE 0.08
BSC REF

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1

REV. A –19–
ADF4106
Revision History
Location Page
5/03—Data Sheet changed from REV. 0 to REV. A.
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to TPC 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

C02720–0–5/03(A)
Update OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

–20– REV. A