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VHDL File

VHDL Programs

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Harshit Chaudhary
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34 views

VHDL File

VHDL Programs

Uploaded by

Harshit Chaudhary
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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FULL ADDER

AIM: To synthesize and simulate a full adder using V.H.D.L Behaioural


model .
TOOLS: XILINX ISE 10.1 and V.H.D.L language .
Truth table of FULL ADDER:
A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

CIN
0
1
0
1
0
1
0
1

SUM
0
1
1
0
1
0
0
1

RTL Schematic :

COUT
0
0
0
1
0
1
1
1

Program :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fulladder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end fulladder;
architecture Behavioral of fulladder is
begin
sum <= a xor b xor c;
carry <= (a and b)or(b and c)or(c and a);
end Behavioral;

RESULT :

SUBTRACTOR
AIM: To synthesize and simulate a subtractor using V.H.D.L Behaioural
model.

TOOLS: XILINX ISE 10.1 and V.H.D.L language .


Truth table :
a

differen
ce
0

0
1

1
0

1
0

0
1

1
0

RTL Schematic:

borrow
0

Programs :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity subtractor1 is
Port ( a,b,c : in STD_LOGIC;
borrow : out STD_LOGIC;
difference : out STD_LOGIC);
end subtractor1;
architecture Behavioral of subtractor1 is
begin
difference <= a xor b xor c;
borrow <= (( not a) and b) or (b and c) or (( not a) and c);
end Behavioral;
Result :

DECODER
AIM: To synthesize and simulate a decoder using V.H.D.L Behaioural
model.
TOOLS: XILINX ISE 10.1 and V.H.D.L language .
Truth table :
a
0

b
0

c
0

Y0
1

Y1
0

Y2
0

Y3
0

Y4
0

Y5
0

Y6
0

Y7
0

0
0
0
1
1
1
1

0
1
1
0
0
1
1

1
0
1
0
1
0
1

0
0
0
0
0
0
0

1
0
0
0
0
0
0

0
1
0
0
0
0
0

RTL Schematic:

Program :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Decoder is
Port ( a,b,c : in STD_LOGIC;

0
0
1
0
0
0
0

0
0
0
1
0
0
0

0
0
0
0
1
0
0

0
0
0
0
0
1
0

0
0
0
0
0
0
1

Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7 : out STD_LOGIC);


end Decoder;
architecture Behavioral of Decoder is
begin
Y0 <= (NOT a )

AND (NOT b )

Y1 <= (NOT a )

AND (NOT b )

Y2 <= (NOT a )

AND b

Y3 <= (NOT a )

AND ( b )

AND ( c);

AND (NOT b )

Y5 <= a

AND (NOT b )

Y6 <= ( a )

AND ( b )
AND ( b )

AND c;

AND (NOT c);

Y4 <= a

Y7 <= ( a )

AND (NOT c);

AND (NOT c);


AND (c);
AND (NOT c);

AND ( c);

end Behavioral;

RESULT:

INDEX
S.N
O

PROGRAM

DATE

SIGNATURE

Experiment NO. 6
AIM: To synthesis and simulate a 3 bit EVEN PARITY GENERATOR.
TOOL USED: XILINX ISE 10.1 and VHDL language.
THEORY: In an even parity generator, the parity bit is set to 1 if
the counts of ones in a given set of bits(excluding the parity bit )
is odd making the count of ones in the entire set of bits (including
the parity bit ) even. When the count of ones in the set of bits is
even, then the parity bit is set to 0.

TRUTH TABLE:
X
0
0
0
0
1
1
1
1
CIRCUIT DAIGRAM:

Y
0
0
1
1
0
0
1
1

Z
0
1
0
1
0
1
0
1

PE
0
1
1
0
1
0
0
1

PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity parity1 is
Port ( x,y,z : in STD_LOGIC;
pe : out STD_LOGIC);
end parity1;
architecture Behavioral of parity1 is
begin
pe <= (x xor y xor z);
end Behavioral;

RESULT:

Experiment NO. 5
AIM: To synthesis and simulate a 3 bit ODD PARITY GENERATOR.
TOOL USED: XILINX ISE 10.1 and VHDL language.
THEORY: In an odd parity generator, the parity bit is set to 1 if
the counts of ones in a given set of bits(excluding the parity bit )
is even making the count of ones in the entire set of bits
(including the parity bit ) odd. When the count of ones in the set
of bits is odd, then the parity bit is set to 0.

TRUTH TABLE:
X
0
0
0
0
1

Y
0
0
1
1
0

Z
0
1
0
1
0

PO
1
0
0
1
0

1
1
1

0
1
1

CIRCUIT DAIGRAM:

PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity parity1 is
Port ( x,y,z : in STD_LOGIC;
po : out STD_LOGIC);
end parity1;
architecture Behavioral of parity1 is
begin
po <= not (x xor y xor z);

1
0
1

1
1
0

end Behavioral;

RESULT:

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