CIRCUIT DIAGRAM : 2-BIT ADDER (HALF ADDER)

TRUTH TABLE
Input Output
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
3-BIT ADDER (FULL ADDER)

TRUTH TABLE
Input Output
A B Cin Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
1
EX NO:

DATE:

DESIGN AND SIMULATION OF ADDER USING VHDL

AIM:

To design adders using VHDL & simulate using modelsim.

TOOLS REQUIRED:

Simulation tool: modelsim.

PROCEDURE:

1. To start the programs click the modelsim software.

2. The main page is opened,click the file option to create a new source in VHDL.

3. After the program is typed, it is saved in a name with extension’ .vhd’

4. Then the program is compiled and errors are checked.

5. After that it is simulated.

6. Then the program is viewed and the signal option is clicked from the view menu and
input signals are given.

7. Then in the edit option, force is selected and the values are given.

8. Finally Add – wave is clicked view the result waveform.

PROGRAM :

Data flow model for half adder

library ieee;
use ieee.std_logic_1164.all;
entity half is
port ( A,B : in std_logic ;
S , C : out std_logic);
end half ;

architecture ha of half is
begin
S<= A xor B ;
C <= (A and B);
end ha ;

2
SIMULATION RESULTS:

3
PROGRAM:

Behavioral Model for fulladder

Library ieee;
Use ieee.std_logic_1164.all;

Entity fulladder is
port( A,B,Cin : in std_logic;
sum,Cout: out std_logic);
end;

architecture functional of fulladder is

begin
process(a,b,cin)
begin
if (Cin = '0' and A = '0' and B = '0' ) then
sum<= '0'; Cout <= '0';
elsif(Cin = '0' and A = '0' and B = '1') then
sum <= '1' ; Cout <= '0';
elsif(Cin = '0' and A = '1' and B = '0' ) then
sum <= '1' ; Cout <= '0';
elsif(Cin = '0' and A = '1' and B = '1' ) then
sum<= '0'; Cout <= '1';
elsif(Cin = '1' and A = '0' and B = '0' ) then
sum <= '1' ; Cout <= '0';
elsif(Cin = '1' and A = '0' and B = '1' ) then
sum<= '0'; Cout <= '1';
elsif(Cin = '1' and A = '1' and B = '0' ) then
sum<= '0'; Cout <= '1';
elsif(Cin = '1' and A = '1' and B = '1' ) then
sum <= '1' ; Cout <= '1';
else
sum <= '0' ; Cout <= '0';
end if;
end process;
end functional;

RESULT:

Thus the adders was designed using VHDL & simulated using modelsim.

4
BLOCK DIAGRAM:

TRUTH TABLE(8:1)

Selection Output
Input
lines

S Y
a b c d e f g h S1 S2
0

D 0 0 0 0 0 0 0 0 0 0 a

0 D 0 0 0 0 0 0 0 0 1 b

0 0 D 0 0 0 0 0 0 1 0 C

0 0 0 D 0 0 0 0 0 1 1 d

0 0 0 0 D 0 0 0 1 0 0 e

0 0 0 0 0 D 0 0 1 0 1 f

0 0 0 0 0 0 D 0 1 1 0 g

0 0 0 0 0 0 0 D 1 1 1 h

5
6
EX NO:

DATE:

DESIGN AND SIMULATION OF MULTIPLEXER AND DEMULTIPLEXER USING VHDL

AIM:

To design 8:1 mux and 1:8 demux using VHDL & simulate using modelsim.

TOOLS REQUIRED:

Simulation:modelsim

PROCEDURE FOR SIMULATION:

1.To start the program click the modelsim software.

2.The main page is opened;click the file option to create a new source in VHDL.

3.After the program is typed, it is saved in a name with exrension ‘.vhd’.

4.Then the program is complied and errors are checked.

5.After that it is simulated.

6.Then the program is viewed and the signal option is clicked from the view menu and
input signals are given.

7.Then in the edit option,force is selected and the values are given.

8.Finally Add-wave is clicked view the result waveform.

MULTIPLEXER

PROGRAM:

Behavioral Model
library ieee;
use ieee.std_logic_1164.all;
entity mux8 is
port(a,b,c,d,e,f,g,h:in std_logic;
s:in std_logic_vector(2 downto 0);
y:out std_logic);

7
CIRCUIT DIAGRAM:

EQUATION:

8
end mux8;
architecture arch of mux8 is
begin
process(a,b,c,d,e,f,g,h,s)
begin
case s is
when"000"=>
y<=a;
when"001"=>
y<=b;
when"010"=>
y<=c;
when"011"=>
y<=d;
when"100"=>
y<=e;
when"101"=>
y<=f;
when"110"=>
y<=g;
when"111"=>
y<=h;
when others=>
null;
end case;
end process;
end arch;

9
EQUATION:

TRUTH TABLE (1:8)

Input Selection lines Output

D S0 S1 S2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

1 0 0 0 D 0 0 0 0 0 0 0

1 0 0 1 0 D 0 0 0 0 0 0

1 0 1 0 0 0 D 0 0 0 0 0

1 0 1 1 0 0 0 D 0 0 0 0

1 1 0 0 0 0 0 0 D 0 0 0

1 1 0 1 0 0 0 0 0 D 0 0

1 1 1 0 0 0 0 0 0 0 D 0

1 1 1 1 0 0 0 0 0 0 0 D

10
DEMULTIPLEXER

PROGRAM:
Dataflow Model
library ieee;
use ieee.std_logic_1164.all;
entity demuxx is
port(s:in std_logic_vector(2 downto 0);
d:in std_logic;
y:out std_logic_vector(0 to 7));
end demuxx;
architecture data of demuxx is
begin
y(0)<=((not s(0)) and (not s(1)) and (not s(2)) and d);
y(1)<=(s(0) and (not s(1)) and (not s(2)) and d);
y(2)<=((not s(0)) and s(1) and (not s(2)) and d);
y(3)<=(s(0) and s(1) and (not s(2)) and d);
y(4)<=((not s(0)) and (not s(1)) and s(2) and d);
y(5)<=(s(0) and (not s(1)) and s(2) and d);
y(6)<=((not s(0)) and s(1) and s(2) and d);
y(7)<=(s(0) and s(1) and s(2) and d);
end data;

11
SIMULATION RESULTS:

12
RESULT:

Thus the design of 8:1 mux and 1:8 demux using VHDL & simulated using
modelsim.

13
CIRCUIT DIAGRAM:

TRUTH TABLE
  
I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

14
EXP.NO:
DATE:

DESIGN AND SIMULATION OF ENCODER AND DECODER USING VHDL

AIM:

To design encoder and decoder using VHDL & simulate using modelsim.

TOOLS REQUIRED:

Simulation: Modelsim

PROCEDURE FOR SIMULATION:

1. To start the program click the modelsim software.

2. The main page is opened; click the file option to create a new source in VHDL.

3. After the program is typed, it is saved in a name with exrension ‘.vhd’.

4. Then the program is complied and errors are checked.

5. After that it is simulated.

6. Then the program is viewed and the signal option is clicked from the view menu and
input signals are given.

7. Then in the edit option, force is selected and the values are given.

8. Finally Add-wave is clicked view the result waveform.

ENCODER

PROGRAM:

Behavioral Model for encoder

library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (i: in std_logic_vector(7 downto 0);
y:out std_logic_vector(2 downto 0));

15
BLOCK DIAGRAM:

TRUTH TABLE

a(0) a(1) a(2) d0 d1 d2 d3 d4 d5 d6 d7

0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

16
end encoder;

architecture encd of encoder is

begin
y<= “000” when i=”00000001” else
“001” when i=”00000010” else
“010” when i=”00000100” else
“011” when i=”00001000” else
“100” when i=”00010000” else
“101” when i=”00100000” else
“110” when i=”01000000” else
“111” when i=”10000000” else
“000” ;
End encd;

DECODER
PROGRAM:
library ieee;

use ieee.std_logic_1164.all;

entity decoder1 is

port(a0:in bit;

a1:in bit;

a2:in bit;

d0:out bit;

d1:out bit;

d2:out bit;

d3:out bit;

d4:out bit;

d5:out bit;

d6:out bit;

d7:out bit);
17
CIRCUIT DIAGRAM:

SIMULATION RESULTS:

18
end decoder1;

architecture decd of decoder1 is

begin

d0<=(not a0 and not a1 and not a2);

d1<=(not a0 and not a1 and a2);

d2<=(not a0 and a1 and not a2);

d3<=(not a0 and a1 and a2);

d4<=(a0 and not a1 and not a2);

d5<=(a0 and not a1 and a2);

d6<=(a0 and a1 and not a2);

d7<=(a0 and a1 and a2);

end decd;

RESULT:

Thus the encoder and decoder was designed using VHDL and simulated using
modelsim.
19
CIRCUIT DIAGRAM

20
EX NO:
DATE:
DESIGN AND SIMULATION OF MULTIPLIER USING VHDL

AIM:

To design Multiplier using VHDL & simulate using modelsim.

TOOLS REQUIRED:

Simulation:modelsim

PROCEDURE FOR SIMULATION:

1.To start the program click the modelsim software.

2.The main page is opened;click the file option to create a new source in VHDL.

3.After the program is typed, it is saved in a name with exrension ‘.vhd’.

4.Then the program is complied and errors are checked.

5.After that it is simulated.

6.Then the program is viewed and the signal option is clicked from the view menu and
input signals are given.

7.Then in the edit option,force is selected and the values are given.

8.Finally Add-wave is clicked view the result waveform.

PROGRAM:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity multiplier1 is

port (

A0 : in bit;

A1 : in bit;

B0 : in bit;

B1 : in bit;

21
MULTIPLIER FUNCTION TABLE

    a1      a0      b1      b0      c3      c2      c1      c0  

                              

    0        0        0        0        0        0        0        0   

               

    0        0        0        1        0        0        0        0   

               

    0        0        1        0        0        0        0        0   

               

    0        0        1        1        0        0        0        0   

               

    0        1        0        0        0        0        0        0   

               

    0        1        0        1        0        0        0        1   

               

    0        1        1        0        0        0        1        0   

               

    0        1        1        1        0        0        1        1   

               

    1        0        0        0        0        0        0        0   

               

    1        0        0        1        0        0        1        0   

               

    1        0        1        0        0        1        0        0   

               

    1        0        1        1        0        1        1        0   

               

    1        1        0        0        0        0        0        0   

               

    1        1        0        1        0        0        1        1   

               

22
     1        1        1        0        0        1        1        0   
               

    1        1        1        1        1        0        0        1   

               

C0 : out bit;

C1 : out bit;

C2 : out bit;

C3 : out bit);

end multiplier1;

architecture ece of multiplier1 is

begin

C3<=(A1 and A0 and B1 and B0);

C2<=(A1 and not A0 and B1)or(A1 and B1 and not B0);

C1<=((not A1 and A0 and B1)or(A0 and B1 and not B0)or(A1 and not B1 and B0)or(A1
and not A0 and B0));

C0<=A0 and B0;

end ece;

SIMULATION RESULT:

23
RESULT:

Thus the multiplier was designed using vhdl and simulated using modelsim.

24
BLOCK DIAGRAM OF DFF:

BLOCK DIAGRAM OF JK FF:

25
EX NO:
DATE:
DESIGN AND SIMULATION OF FLIP FLOPS USING VHDL

AIM:

To design flip flops using VHDL & simulate using modelsim.

TOOLS REQUIRED:

Simulation tool: modelsim.

PROCEDURE:

1. To start the programs click the modelsim software.

2. The main page is opened,click the file option to create a new source in VHDL.

3. After the program is typed, it is saved in a name with extension’ .vhd’

4. Then the program is compiled and errors are checked.

5. After that it is simulated.

6. Then the program is viewed and the signal option is clicked from the view menu and
input signals are given.

7. Then in the edit option, force is selected and the values are given.

8. Finally Add – wave is clicked view the result waveform.

PROGRAM:
DFF(VHDL) using Behavioral:
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port ( d,res,clk : in std_logic;
q : out std_logic);
end dff;
architecture behavioral of dff is
begin
process(clk)
begin
if(res='0') then q<='0';
elsif clk'event and clk='1'

26
SIMULATION RESULTS:

27
 then q<=d;
end if;
end process;
end behavioral;
JKFF(VHDL) using Behavioral:
library ieee;
use ieee.std_logic_1164.all;
entity jkff is
port(j,k,clk,reset : in std_logic;
q,qn : out std_logic);
end jkff;
architecture behavioral of jkff is
signal ff:std_logic;
begin
process(j,k,clk,reset)
variable jk:std_logic_vector(1 downto 0);
begin
jk:=j&k;
if(reset='0')then ff<='0';
elsif(clk'event and clk='1')then
case jk is
when"01"=>ff<='0';
when"10"=>ff<='1';
when"11"=>ff<=not(ff);
when others=>ff<=ff;
end case;
end if ;
end process;
q<=ff;
qn<=not(ff);
end behavioral;
RESULT :

Thus the design of flip flops using VHDL in done and simulated using modelsim.
28
STATE DIAGRAM:

FIGURE 1: UP COUNTER

29
EX NO:
DATE:
DESIGN AND SIMULATION OF COUNTER USING VHDL

AIM :

To design counters using VHDL & simulate using modelsim.

TOOLS REQUIRED:

Simulation tool: modelsim.

PROCEDURE:

1. To start the programs click the modelsim software.

2. The main page is opened,click the file option to create a new source in VHDL.

3. After the program is typed, it is saved in a name with extension’ .vhd’

4. Then the program is compiled and errors are checked.

5. After that it is simulated.

6. Then the program is viewed and the signal option is clicked from the view menu and
input signals are given.

7. Then in the edit option, force is selected and the values are given.

8. Finally Add – wave is clicked view the result waveform.

PROGRAM:

UP COUNTER(VHDL) using Behavioral:

library ieee;

use ieee.std_logic_1164.all;

entity upcounter is

port ( clk,clr : in std_logic;

q : inout std_logic_vector (2 downto 0));

end upcounter;

architecture behavioral of upcounter is

begin

process(clk)

variable temp: std_logic_vector (2 downto 0):="000";

30
STATE DIAGRAM:

FIGURE 2: DOWN COUNTER

31
begin

if (rising_edge (clk)) then

if clr='0' then

case temp is

when "000"=>temp:="001";

when "001"=>temp:="010";

when "010"=>temp:="011";

when "011"=>temp:="100";

when "100"=>temp:="101";

when "101"=>temp:="110";

when "110"=>temp:="111";

when "111"=>temp:="000";

when others=>temp:="000";

end case;

else

temp:="000";

end if;

end if;

q<=temp;

end process;

end behavioral;

DOWN COUNTER(VHDL) using Behavioral:

library ieee;
use ieee.std_logic_1164.all;
entity downcounter is
port ( clk,clr : in std_logic;
q : inout std_logic_vector (2 downto 0));
end downcounter;

32
SIMULATION RESULTS:

33
 architecture behavioral of downcounter is
begin
process(clk)
variable temp: std_logic_vector (2 downto 0):="000";
begin
if (rising_edge (clk)) then
if clr='0' then
case temp is
when "000"=>temp:="111";
when "111"=>temp:="110";
when "110"=>temp:="101";
when "101"=>temp:="100";
when "100"=>temp:="011";
when "011"=>temp:="010";
when "010"=>temp:="001";
when "001"=>temp:="000";
when others=>temp:="000";
end case;
else
temp:="000";
end if;
end if;
q<=temp;
end process;
end behavioral;

RESULT:

Thus the design of counters using VHDL is done and simulated using modelsim.

34
BLOCK DIAGRAM: SISO

BLOCK DIAGRAM: SIPO

35
EX NO:

DATE:

DESIGN AND SIMULATION OF SHIFT REGISTERS USING VHDL

AIM :

To design shift registers using VHDL & simulate using modelsim.

TOOLS REQUIRED:

Simulation tool: modelsim.

PROCEDURE:

1. To start the programs click the modelsim software.

2. The main page is opened,click the file option to create a new source in VHDL.

3. After the program is typed, it is saved in a name with extension’ .vhd’

4. Then the program is compiled and errors are checked.

5. After that it is simulated.

6. Then the program is viewed and the signal option is clicked from the view menu and
input signals are given.

7. Then in the edit option, force is selected and the values are given.

8. Finally Add – wave is clicked view the result waveform.

PROGRAM:

8-bit Shift Register with Positive edge Clock - Serial In and Serial Out:
library ieee;
use ieee.std_logic_1164.all;
entity siso is
port(C, SI : in std_logic;
SO : out std_logic);
end siso;
architecture archi of siso is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C)
36
 begin

SIMULATION RESULTS:

37
 if (C'event and C='1') then
for i in 0 to 6 loop
tmp(i+1) <= tmp(i);
end loop;
tmp(0) <= SI;
end if;
end process;
SO <= tmp(7);
end archi;
8-bit Shift Register with Positive edge Clock -Serial In and Parallel Out:

library ieee;
use ieee.std_logic_1164.all;
entity sipo is
port(C, SI : in std_logic;
PO : out std_logic_vector(7 downto 0));
end sipo;
architecture archi of sipo is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C)

begin

if (C'event and C='1') then

tmp <= tmp(6 downto 0) & SI;

end if;

end process;

PO <= tmp;

end archi;

RESULT:

Thus the design of shift registers is done using VHDL and simulated using
modelsim
38
BLOCK DIAGRAM:

39
EX.NO :

DATE :

DESIGN AND SIMULATION OF FREQUENCY DIVIDER USING VHDL

AIM:

To design frequency divider using VHDL and Simulate using modelsim.

APPARATUS REQUIRED:

Simulation : ModelSim

PROCEDURE:

1. To start the programs click the modelsim software.

2. 2. The main page is opened,click the file option to create a new source in VHDL.
3. 3. After the program is typed, it is saved in a name with extension’ .vhd’
4. 4. Then the program is compiled and errors are checked.
5. 5. After that it is simulated.
6. 6. Then the program is viewed and the signal option is clicked from the view menu
and input signals are given.
7. 7. Then in the edit option, force is selected and the values are given.
8. 8. Finally Add – wave is clicked view the result waveform.
PROGRAM :

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity freq is

generic(n:positive:=5);

port(clk,rst:in std_logic;

qa: inout std_logic);

end freq;

architecture behavioral of freq is

begin

process(clk,rst)
40
SIMULATION RESULT:

41
 variable count: natural;

begin

if(rst='1')then

count:=0;

qa<='0';

elsif(clk='1' and clk'event) then

count:=count+1;

if (count = n) then

qa<=not qa;

count:=0;

end if;

end if;

end process;

end behavioral;

RESULT:

Thus the frequency divider was designed using VHDL and Simulated using
modelsim successfully.

42
Inverter Circuit:

43
EX.NO :

DATE :

CMOS INVERTER DESIGN USING MULTISIM

(Dc and Transient Analysis)

AIM:

To Design CMOS Inverter Using Multisim Software and verify the output.

APPARATUS REQUIRED:

1. Multisim Software
2. PC:XP/WINDOWS

PROCEDURE FOR SIMULATION

1.To design the Cmos inverter, click the Multisim software.

2.The main page is opened; click the file to create a new source.

3.Design the circuit by selecting the appropriate components from the place menu.

4.After that, simulate the circuit.

5.Stop simulating.Go to analyses.

6.Select DC operating point.Add all the variables and click simulate.

7.Note down the operating point values.

8.Similarly select the transient analysis and simulate.

9. The output waveform is obtained

44
TRANSIENT ANALYSIS :

45
RESULT:

Thus the CMOS Inverter is Designed using Multisim and output was verified.

46
NAND Gate Circuit:

NOR Gate Circuit:

47
EX.NO :

DATE :

CMOS NAND AND NOR GATES DESIGN USING MULTISIM

(DC AND TRANSIENT ANALYSIS)

AIM:

To Design CMOS NAND and NOR Gates Using Multisim Software and verify the
output.

APPARATUS REQUIRED:

1. Multisim Software
2. PC:XP/WINDOWS

PROCEDURE FOR SIMULATION:

1.To design the Cmos, click the Multisim software.

2.The main page is opened; click the file to create a new source.

3.Design the circuit by selecting the appropriate components from the place menu.

4.After that, simulate the circuit.

5.Stop simulating.Go to analyses.

6.Select DC operating point.Add all the variables and click simulate.

7.Note down the operating point values.

8.Similarly select the transient analysis and simulate.

9. The output waveform is obtained

48
TRANSIENT ANALYSIS:

49
RESULT:

Thus the CMOS NAND and NOR Gates is Designed using Multisim and output was
verified.
50
D latch Circuit:

EX.NO :
51
DATE :

CMOS D LATCH

(Dc and Transient Analysis)

AIM

To Design CMOS D LATCH Using Multisim Software and verify the output.

APPARATUS REQUIRED

1. Multisim Software
2. PC:XP/WINDOWS
PROCEDURE FOR SIMULATION

1.To design the D latch, click the Multisim software.

2.The main page is opened; click the file to create a new source.

3.Design the circuit by selecting the appropriate components from the place menu.

4.After that, simulate the circuit.

5.Stop simulating.Go to analyses.

6.Select DC operating point.Add all the variables and click simulate.

7.Note down the operating point values.

8.Similarly select the transient analysis and simulate

.
9. The output waveform is obtained.

52
TRANSIENT ANALYSIS :

53
RESULT:

Thus the CMOS D LATCH is Designed using Multisim and output was verified.

54
TRUTH TABLE:

INPUT OUTPUT
a3 a2 a1 a0 b3 b2 b1 b0 cout s3 s2 s1 s0
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1 0 0 0 1 0
0 0 1 0 0 0 1 0 0 0 1 0 0
0 0 1 1 0 0 1 1 0 0 1 1 0
0 1 0 0 0 1 0 0 0 1 0 0 0
0 1 0 1 0 1 0 1 0 1 0 1 0
0 1 1 0 0 1 1 0 0 1 1 0 0
0 1 1 1 0 1 1 1 0 1 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0
1 0 0 1 1 0 0 1 1 0 0 1 0
1 0 1 0 1 0 1 0 1 0 1 0 0
1 0 1 1 1 0 1 1 1 0 1 1 0
1 1 0 0 1 1 0 0 1 1 0 0 0
1 1 0 1 1 1 0 1 1 1 0 1 0
1 1 1 0 1 1 1 0 1 1 1 0 0
1 1 1 1 1 1 1 1 1 1 1 1 0

55
EX.NO:
DATE:
FPGA IMPLEMENTATION OF 4 BIT ADDER
AIM:
To design “4 BIT ADDER” in Spartan-3 Trainer and to demonstrate its working is on
FPGA board.
PROCEDURE:
1.In the Xilinx,open a new project and give the file name.
2.Select Verilog module from XC3S400-4pq208.
3.Type the program and create new source.
4.Select implementation constraint file and give the file name.
5.Then click assign package pin(run) from user constraints.
6.Give the pin location and save the file.
7.Run the synthesis XST,implement design and generate program file sequentially.
8.select program and wait until it gets succeed.
9.Give the input and observe the output in the Xilinx kit.
PROGRAM:
library ieee;
use ieee.std_logic_1164.all;
entity fa is
port(a3,a2,a1,a0,b3,b2,b1,b0:in bit;
cout,s3,s2,s1,s0:out bit);
end fa;
architecture ece of fa is
begin
process(a3,a2,a1,a0,b3,b2,b1,b0)
begin
if(a3='0' and a2='0' and a1='0' and a0='0' and b3='0' and b2='0' and b1='0' and
b0='0')then
cout<='0';
s3<='0';
s2<='0';

56
BLOCK DIAGRAM

s1<='0';
57
 s0<='0';
elsif(a3='0' and a2='0' and a1='0' and a0='1' and b3='0' and b2='0' and b1='0' and
b0='1')then
cout<='0';
s3<='0';
s2<='0';
s1<='1';
s0<='0';
elsif(a3='0' and a2='0' and a1='1' and a0='0' and b3='0' and b2='0' and b1='1' and
b0='0')then
cout<='0';
s3<='0';
s2<='1';
s1<='0';
s0<='0';
elsif(a3='0' and a2='0' and a1='1' and a0='1' and b3='0' and b2='0' and b1='1' and
b0='1')then
cout<='0';
s3<='0';
s2<='1';
s1<='1';
s0<='0';
elsif(a3='0' and a2='1' and a1='0' and a0='0' and b3='0' and b2='1' and b1='0' and
b0='0')then
cout<='0';
s3<='1';
s2<='0';
s1<='0';
s0<='0';
elsif(a3='0' and a2='1' and a1='0' and a0='1' and b3='0' and b2='1' and b1='0' and
b0='1')then
cout<='0';
s3<='1';
s2<='0';

s1<='1';
58
s0<='0';
elsif(a3='0' and a2='1' and a1='1' and a0='0' and b3='0' and b2='1' and b1='1' and
b0='0')then
cout<='0';
s3<='1';
s2<='1';
s1<='0';
s0<='0';
elsif(a3='0' and a2='1' and a1='1' and a0='1' and b3='0' and b2='1' and b1='1' and
b0='1')then
cout<='0';
s3<='1';
s2<='1';
s1<='1';
s0<='0';
elsif(a3='1' and a2='0' and a1='0' and a0='0' and b3='1' and b2='0' and b1='0' and
b0='0')then
cout<='1';
s3<='0';
s2<='0';
s1<='0';
s0<='0';
elsif(a3='1' and a2='0' and a1='0' and a0='1' and b3='1' and b2='0' and b1='0' and
b0='1')then
cout<='1';
s3<='0';
s2<='0';
s1<='1';
s0<='0';
elsif(a3='1' and a2='0' and a1='1' and a0='0' and b3='1' and b2='0' and b1='1' and
b0='0')then
cout<='1';
s3<='0';
s2<='1';
s1<='0';
s0<='0';
59
 elsif(a3='1' and a2='0' and a1='1' and a0='1' and b3='1' and b2='0' and b1='1' and
b0='1')then
cout<='1';
s3<='0';
s2<='1';
s1<='1';
s0<='0';
elsif(a3='1' and a2='1' and a1='0' and a0='0' and b3='1' and b2='1' and b1='0' and
b0='0')then
cout<='1';
s3<='1';
s2<='0';

s1<='0';
s0<='0';
elsif(a3='1' and a2='1' and a1='0' and a0='1' and b3='1' and b2='1' and b1='0' and
b0='1')then
cout<='1';
s3<='1';
s2<='0';
s1<='1';
s0<='0';
elsif(a3='1' and a2='1' and a1='1' and a0='0' and b3='1' and b2='1' and b1='1' and
b0='0')then
cout<='1';
s3<='1';
s2<='1';
s1<='0';
s0<='0';
elsif(a3='1' and a2='1' and a1='1' and a0='1' and b3='1' and b2='1' and b1='1' and
b0='1')then
cout<='1';
s3<='1';
s2<='1';
s1<='1';
s0<='0';
60
 else
cout<='0';
s3<='0';
s2<='0';
s1<='0';
s0<='0';
end if;
end process;
end ece;

Block diagram:
61
RESULT:

Thus the “4-BIT ADDER” was implemented in Spartan-3 Trainer and its working
is demonstrated on interfacing board.

62
EX.NO:

DATE:
FPGA IMPLEMENTATION OF REAL TIME CLOCK
AIM:
63
 To design “REALTIME CLOCK” in Spartan-3 Trainer and to demonstrate its working
is on FPGA board.

PROCEDURE;

1.In the Xilinx,open a new project and give the file name.
2.Select Verilog module from XC3S400-4pq208.
3.Type the program and create new source.
4.Select implementation constraint file and give the file name.
5.Then click assign package pin(run) from user constraints.
6.Give the pin location and save the file.
7.Run the synthesis XST,implement design and generate program file sequentially.
8.select program and wait until it gets succeed.
9.Give the input and observe the output in the Xilinx kit.
VHD Code for Real Clock Timer:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-----------------------------------------------------------------------------------
--This is real time clock in this we use
-- to generate 1 sec clock we use enable signal high for last 1 count
-- sec1 counter for reading sec
-- sec2 counter for reading sec
-- min1 counter for reading min
-- min2 counter for reading min
-- hr1 counter for reading hr

64
Table: Real Clock Timer Interface to SPARTAN-3 FPGA
ne
CLK_4M loc = p181;
t
ne
RESET loc = p182;
t
ne
Load loc = p102;
t
ne
control loc = p101;
t
ne
RTC_SEG<0> loc = P24;
t
ne
RTC_SEG<1> loc = P20;
t
ne
RTC_SEG<2> loc = P27;
t
ne
RTC_SEG<3> loc = P26;
t
ne
RTC_SEG<4> loc = P29;
t
ne
RTC_SEG<5> loc = P28;
t
ne
RTC_SEG<6> loc = P33;
t
ne
RTC_SEG<7> loc = P31;
t
ne
RTC_Dis<0> loc = P22;
t
ne
RTC_Dis<1> loc = P21;
t
ne
RTC_Dis<2> loc = P18;
t
ne
RTC_Dis<3> loc = P19;
t

65
 ne
RTC_Dis<4> loc = P15;
t
ne
RTC_Dis<5> loc = P16;
t

--4mhz clock
-- hr2 counter for reading hr
entity RTC_IM is
port(RESET,CLK_4M,load,control:in std_logic;
RTC_SEG:out std_logic_vector(7 downto 0);
RTC_DIS:out std_logic_vector(5 downto 0));
end RTC_IM;
architecture Behavioral of RTC_IM is
signal tc,tc1,tc2,tc3,tc4,tc5,tc6,enable:std_logic;
signal sec1,sec2,min1,min2,hr1,hr2: std_logic_vector(3 downto 0);
signal sec1_rg:std_logic_vector(3 downto 0);
signal sec2_rg:std_logic_vector(3 downto 0);
signal min1_rg:std_logic_vector(3 downto 0);
signal min2_rg:std_logic_vector(3 downto 0);
signal hr1_rg:std_logic_vector(3 downto 0);
signal hr2_rg:std_logic_vector(3 downto 0);
signal pulsegen:std_logic_vector(21 downto 0);
signal sel:std_logic_vector(2 downto 0);
signal mout:std_logic_vector(3 downto 0);
signal sgout:std_logic_vector(7 downto 0);
signal dis_sig:std_logic_vector(5 downto 0);
signal cnk2:std_logic_vector(2 downto 0);
begin
--*************************** Pulse Generator ******************
p0:process(RESET,CLK_4M,pulsegen)
begin
66
if (RESET = '1') then
pulsegen <= "0000000000000000000000";
elsif rising_edge (CLK_4M) then
if (pulsegen = "1111010000100100000000") then
enable <= '1' when pulsegen = "1111010000100100000000" else --enable signal for
sec1 counter
'0';

--************************ Second_cntr1 *************************

p1:process (RESET,CLK_4M,sec1_rg,enable,load) --decade counter
begin
if (RESET = '1') then

pulsegen <= "0000000000000000000000";

else
pulsegen <= pulsegen + 1;
end if;
end if;
end process;
---------- Enable signal to generate 1-sec pulse for sec1 counter

sec1_rg <= "0000";

elsif load = '1' then

sec1_rg <= "0100";

elsif rising_edge(CLK_4M) then

if (enable = '1') then
if (sec1_rg = "1001")then
sec1_rg <= "0000";
else
sec1_rg <= sec1_rg + 1;
end if;
end if;
end if;

67
sec1 <= sec1_rg;
end process ;
-----------------------tc signal to start sec2 counter----------------------------------
tc <= '1' when (sec1_rg = "1001") and (enable = '1') else --signal for sec2 counter
'0';
--************************* Second_cntr2 ***********************
p2:process (RESET,CLK_4M,sec2_rg,tc,load) --sec2 counter for reading upto 59 sec
begin
if (RESET = '1') then
if (sec2_rg = "0101")then
sec2_rg <= "0000";
else
sec2_rg <= sec2_rg + 1;
end if;
end if;
end if;
sec2_rg <= "0000";
elsif (load = '1') then
sec2_rg <= "0100";
elsif rising_edge(CLK_4M) then
if (tc = '1') then

sec2 <= sec2_rg;

end process;
-----------------------------tc1 signal to start min1 counter------------------------
tc1 <= '1' when (sec2_rg = "0101") and (tc = '1') else
'0' ;
--************************ Minute_cntr1 *************************
p3:process(RESET,CLK_4M,min1_rg,tc1,load) -- min1 counter
begin
if (RESET = '1') then
min1_rg <= "0000";
elsif load = '1' then
min1_rg <= "0100";
68
 elsif rising_edge(CLK_4M) then
if (tc1 = '1') then
if (min1_rg = "1001")then
min1_rg <= "0000";
else
min1_rg <= min1_rg + 1;
end if;

end if;
end if;
min1 <= min1_rg;
end process;
--------------------------tc2 signal to start min2 counter----------------------------
if (RESET = '1') then
min2_rg <= "0000";
elsif load = '1' then
min2_rg <= "0100";
elsif rising_edge(CLK_4M) then
tc2 <= '1' when (min1_rg ="1001") and (tc1 = '1') else --pulse for min2 counter
'0';
--************************ Minute_cntr2 *************************
p4:process(RESET,CLK_4M,min2_rg,tc2,load) --min2 counter
begin
if (tc2 = '1') then
if (min2_rg = "0101")then
min2_rg <= "0000";
else
min2_rg <= min2_rg + 1;
end if;
end if;
end if;
min2 <= min2_rg;
end process;
--------------------------tc3 signal to start hr1 counter----------------------------------

tc3 <= '1' when (min2_rg ="0101") and (tc2 = '1') else
69
 '0';
--************************ Hour_cntr1 *************************
p5:process(RESET,CLK_4M,hr1_rg,tc3,load,control,tc6,tc5) --hr1 counter
begin
if (RESET = '1') then
hr1_rg <= "0000";
elsif (load = '1') then
hr1_rg <= "0001";
elsif rising_edge(CLK_4M) then
if control = '1' then
if (tc5 = '1') then
hr1_rg <= "0000";
else
if (tc3 = '1') then
end if;
end if;
else
if (tc6 = '1') then
hr1_rg <= "0001";

if (hr1_rg = "1001")then
hr1_rg <= "0000";
else
hr1_rg <= hr1_rg + 1;
end if;

else

if (tc3 = '1') then

if (hr1_rg = "1001")then
hr1_rg <= "0000";
else
hr1_rg <= hr1_rg + 1;
end if;
end if;
70
end if;
end if;
end if;
hr1 <= hr1_rg;
end process;
---------------------tc4 signal to start hr2 counter--------------------------
tc4 <= '1' when (hr1_rg ="1001") and (tc3 = '1') else
'0';
------------------------tc5 signal to RESET at 23:59:59--------------------------
tc5 <= '1' when (hr2_rg ="0010")and (hr1_rg ="0011") and (tc3 = '1') else
'0';
-----------------------------tc6 signal to RESET at 11:59:59---------------
tc6 <= '1' when (hr2_rg = "0001") and (hr1_rg = "0010") and (tc3 = '1') else
'0';
--************************ Hour_cntr2 *************************
p6:process(RESET,CLK_4M,hr2_rg,tc4,load,control) --hr2 counter
begin
if (RESET = '1') then

hr2_rg <= "0000";

elsif load = '1' then
hr2_rg <= "0000";
elsif rising_edge(CLK_4M) then
if (control = '1') then
if (tc5 = '1') then
hr2_rg <="0000";
else
if (tc4 = '1') then
if (hr2_rg = "0010")then
hr2_rg <= "0000";
else
hr2_rg <= hr2_rg + 1;
end if;
end if;
71
 end if;
else
if (tc6 = '1') then
hr2_rg <="0000";
else
if (tc4 = '1') then
if (hr2_rg = "0001")then
hr2_rg <= "0000";
else
hr2_rg <= hr2_rg + 1;
end if;
end if;
end if;
end if;
end if;
hr2 <= hr2_rg;
end process;
p14:process(RESET, pulsegen(9))
begin
if (RESET = '1') then
cnk2 <= "000";
elsif rising_edge(pulsegen(9)) then
if (cnk2 = "101") then
cnk2 <= "000";
else
cnk2 <= cnk2 + 1;
end if;
end if;
end process;
mout <= sec1 when cnk2 = "000" else
sec2 when cnk2 = "001" else
min1 when cnk2 = "010" else
min2 when cnk2 = "011" else
hr1 when cnk2 = "100" else
72
 hr2 when cnk2 = "101";
--********hgfedcba****************************
sgout <= "11000000" when mout = "0000" else
"11111001" when mout = "0001" else
"10100100" when mout = "0010" else
"10110000" when mout = "0011" else
"10011001" when mout = "0100" else
"10010010" when mout = "0101" else
"10000010" when mout = "0110" else
"11111000" when mout = "0111" else
"10000000" when mout = "1000" else
"10011000" when mout = "1001" else
"11111111" ;
dis_sig <= "111110" when cnk2 = "000" else
"111101" when cnk2 = "001" else
"111011" when cnk2 = "010" else
"110111" when cnk2 = "011" else
"101111" when cnk2 = "100" else
"011111" ;--when cnk2 = "101" ;
RTC_SEG <= not sgout;
RTC_DIS <= not dis_sig;
end Behavioral;

73
RESULT:

Thus the “REAL TIME CLOCK” was implemented in Spartan-3 Trainer and its
working is demonstrated on interfacing board.

74