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Rahul Purohit

Assignment 1 Object: Design following Circuit using DataFlow approach of VHDL. A) AND B) OR C) NOT D) NAND E) NOR F) EX-OR G) Ex-NOR

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A) AND Truth Table: INPUT(X) 0 0 1 1 Function: Z = X.Y VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ands is Port ( X : in std_logic; Y : in std_logic; Z : out std_logic); end ands; architecture Dataflow of ands is begin Z <= X and Y; end Dataflow;
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INPUT(Y) 0 1 0 1

OUTPUT(Z) 0 0 0 1

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RTL Design:

Waveform:

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B) OR Truth Table: INPUT(X) 0 0 1 1 Function: Z = X+Y VHDL Code: library IEEE;

INPUT(Y) 0 1 0 1

OUTPUT(Z) 0 1 1 1

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ors is Port ( X : in std_logic; Y : in std_logic; Z : out std_logic); end ors; architecture Dataflow of ors is begin Z <= X or Y; end Dataflow;
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RTL Design:

Waveform:

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C) NOT Truth Table: INPUT(X) 0 1 Function: Z = ~(Y) VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nores is Port ( X : in std_logic; Y : out std_logic); end nores; architecture Dataflow of nores is begin Y <= not(X); end Dataflow; OUTPUT(Y) 1 0

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RTL Design:

Waveform:

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D) NAND Truth Table: INPUT(X) 0 0 1 1 Function: Z = ~(X.Y) VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Nandss is Port ( X : in std_logic; Y : in std_logic; Z : out std_logic); end Nandss; architecture Dataflow of Nandss is begin Z <= not(X and Y); end Dataflow;
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INPUT(Y) 0 1 0 1

OUTPUT(Z) 1 1 1 0

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RTL Design:

Waveform:

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E) NOR Truth Table: INPUT(X) 0 0 1 1 Function: Z = ~(X+Y) VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nord is Port ( X : in std_logic; Y : in std_logic; Z : out std_logic); End nord; architecture Dataflow of nord is begin Z <= not(X or Y); end Dataflow;
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INPUT(Y) 0 1 0 1

OUTPUT(Z) 1 0 0 0

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RTL Design:

Waveform:

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F) EX-OR Truth Table: INPUT(X) 0 0 1 1 Function: Z = (X.~(Y))+(Y.~(X)) VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ExORD is Port ( X : in std_logic; Y : in std_logic; Z : out std_logic); End ExORD; architecture Dataflow of ExORD is begin Z <= (X and not(Y))or(Y and not(X)); end Dataflow;
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INPUT(Y) 0 1 0 1

OUTPUT(Z) 0 1 1 0

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RTL Design:

Waveform:

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G) EX-NOR Truth Table: INPUT(X) 0 0 1 1 Function: Z = (X.Y)+(~(X).~(Y)) VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ExnorD is Port ( X : in std_logic; Y : in std_logic; Z : out std_logic); End ExnorD; architecture Dataflow of ExnorD is begin Z <= (X and Y)or(not(X) and not(Y)); end Dataflow;
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INPUT(Y) 0 1 0 1

OUTPUT(Z) 1 0 0 1

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RTL Design:

Waveform:

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Rahul Purohit

Assignment 2 Object: Design following Circuit using Behaviour approach of VHDL. A) AND B) OR A) AND Truth Table: INPUT(X) 0 0 1 1 Function: Z = X.Y VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity AB is Port ( X : in std_logic; Y : in std_logic;
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INPUT(Y) 0 1 0 1

OUTPUT(Z) 0 0 0 1

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Z : out std_logic); end AB; architecture Behavioral of AB is begin process(X,Y) begin if((X='1')and(Y='1')) then Z <= '1'; else Z <= '0'; end if; end process; end Behavioral; RTL Design:

Waveform:

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Rahul Purohit

B) OR Truth Table: INPUT(X) 0 0 1 1 Function: Z = X+Y VHDL Code: library IEEE;

INPUT(Y) 0 1 0 1

OUTPUT(Z) 0 1 1 1

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity OB is Port ( X : in std_logic; Y : in std_logic; Z : out std_logic); end OB; architecture Behavioral of OB is begin process(X,Y) begin
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if((X='0')and(Y='0')) then Z <= '0'; else Z <= '1'; end if; end process; end Behavioral; RTL Design:

Waveform:

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Rahul Purohit

Assignment 3 Object: Design following Circuit using DataFlow approach of VHDL. A) Half-Adder B) Half-Subtractor A) Half-Adder Truth Table: A 0 0 1 1 Function: SUM = A xor B CARRY A and B VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity HA is Port ( A : in std_logic; B : in std_logic;
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B 0 1 0 1

SUM 0 1 1 0

CARRY 0 0 0 1

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SUM : out std_logic; CARRY : out std_logic); end HA; architecture Dataflow of HA is begin SUM <= A xor B; CARRY <= A and B; end Dataflow; RTL Design:

Waveform:

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B) Half Subtractor Truth Table: A 0 0 1 1

B 0 1 0 1

SUM 0 1 1 0

BORROW 0 1 0 0

Function: SUM = A xor B BORROW = ~(A) and B VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity HS is Port ( A : in std_logic; B : in std_logic; SUM : out std_logic; BORROW : out std_logic); end HS; architecture Dataflow of HS is begin SUM <= A xor B; BORROW <= not(A) and B;
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end Dataflow; RTL Design:

Waveform:

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Assignment 4 Object: Design following Circuit using DataFlow approach of VHDL. A) Full-Adder B) Full-Subtractor A) Full-Adder Truth Table: A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

SUM 0 1 1 0 1 0 0 1

CARRY 0 0 0 1 0 1 1 1

Function: SUM = A xor B xor C CARRY = A and B and C VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
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VLSI PRACTICAL FILE

Rahul Purohit

entity FA is Port ( A : in std_logic; B : in std_logic; C : in std_logic; SUM : out std_logic; CARRY : out std_logic); end FA; architecture Dataflow of FA is begin SUM <= A xor B xor C; CARRY <= A and B and C; end Dataflow; RTL Design:

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Waveform:

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B) Full-Subtractor Truth Table: A B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

C 0 1 0 1 0 1 0 1

SUM 0 1 1 0 1 0 0 1

BORROW 0 1 1 1 0 0 0 1

Function: SUM = A xor B xor C BORROW = (B and C) or (~(A) and C) or (~(A) and B) VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FS is Port ( A : in std_logic; B : in std_logic; C : in std_logic; SUM : out std_logic; BORROW : out std_logic); end FS;
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architecture Dataflow of FA is begin SUM <= A xor B xor C; BORROW <= (B and C) or (not(A) and C) or (not(A) and B); end Dataflow; RTL Design:

Waveform:

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Rahul Purohit

Assignment 5 Object: Design following Circuit using DataFlow approach of VHDL. A) 4X1 MUX B) 1X4 DEMUX A) 4X1 MUX Truth Table: INPUT S0 0 0 1 1 S1 0 1 0 1 OUTPUT Y D0 D1 D2 D3

Function: Y = ((d0 and (not s0) and (not s1)) or (d1 and (not s1) and s0) or (d2 and s1 and (not s0)) or (d3 and s0 and s1))

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VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux4 is Port ( S0 : in std_logic; S1 : in std_logic; D0 : in std_logic; D1 : in std_logic; D2 : in std_logic; D3 : in std_logic; Y : out std_logic); end mux4; architecture dataflow of mux4 is begin Y <=((D0 and (not S0) and (not S1)) or (D1 and (not S0) and S1) or (D2 and S0 and (not S1)) or (D3 and S0 and S1)); end dataflow;

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RTL Design:

Waveform:

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B) 1X4 DEMUX Truth Table: INPUT S0 S1 Y0 0 0 D 0 1 0 1 0 0 1 1 0 Function: Y0 = D.~(S0).~(s1) Y1 = D.~(S0).S1 Y2 = D.S0.~(S1) Y3 = D.S0.S1

OUTPUT Y1 Y2 0 0 D 0 0 D 0 0

Y3 0 0 0 D

VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity demux4 is Port ( Y0 : out std_logic; Y1 : out std_logic; Y2 : out std_logic; Y3 : out std_logic; S0 : in std_logic; S1 : in std_logic; D : in std_logic);
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end demux4; architecture Dataflow of demux4 is begin Y0 <= (D and (not S0) and (not S1)); Y1 <= (D and (not S0) and S1); Y2 <= (D and S0 and (not S1)); Y3 <= (D and S0 and S1); end Dataflow; RTL Design:

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Waveform:

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Assignment 6 Object: Design following Circuit using Behaviour approach of VHDL. A) 4X1 MUX B) 8X1 MUX A) 4X1 MUX Truth Table: INPUT S0 0 0 1 1 S1 0 1 0 1 OUTPUT Y D0 D1 D2 D3

Function: Y = ((d0 and (not s0) and (not s1)) or (d1 and (not s1) and s0) or (d2 and s1 and (not s0)) or (d3 and s0 and s1)) VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux4 is
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Rahul Purohit

Port ( S0 : in std_logic; S1 : in std_logic; D0 : in std_logic; D1 : in std_logic; D2 : in std_logic; D3 : in std_logic; Y : out std_logic); end mux4; architecture Behavioral of mux4 is begin process(D0,D1,D2,D3,S0,S1) begin if(S0 = '0' and S1 = '0') then Y <= D0; elsif(S0 = '0' and S1 = '1') then Y <= D1; elsif(S0 = '1' and S1 = '0') then Y <= D2; elsif(S0 = '1' and S0 = '1') then Y <= D3; end if; end process; end Behavioral;

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RTL Design:

Waveform:

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B) 8X1 MUX Truth Table: A 0 0 0 0 1 1 1 1 INPUT B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 OUTPUT Y D0 D1 D2 D3 D4 D5 D6 D7

Function: Y = ~(A).~(B).~(C).D0 or ~(A).~(B).C.D1 or ~(A).B.~(C).D2 or ~(A).B.C.D3 or A.~(B).~(C).D4 or A.~(B).C.D5 or A.B.~(C).D6 or A.B.C.D7 VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux8 is Port ( A : in std_logic; B : in std_logic; C : in std_logic; D0 : in std_logic;
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D1 : in std_logic; D2 : in std_logic; D3 : in std_logic; D4 : in std_logic; D5 : in std_logic; D6 : in std_logic; D7 : in std_logic; Y : out std_logic); end mux8; architecture Behavioral of mux8 is begin process(D0,D1,D2,D3,D4,D5,D6,D7,A,B,C) begin if(A = '0' and B = '0' and C = '0') then Y <= D0; elsif(A = '0' and B = '0' and C = '1') then Y <= D1; elsif(A = '0' and B = '1' and C = '0') then Y <= D2; elsif(A = '0' and B = '1' and C = '1') then Y <= D3; elsif(A = '1' and B = '0' and C = '0') then Y <= D4; elsif(A = '1' and B = '0' and C = '1') then Y <= D5; elsif(A = '1' and B = '1' and C = '0') then Y <= D6;
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elsif(A = '1' and B = '1' and C = '1') then Y <= D7; end if; end process; end Behavioral; RTL Design:

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Waveform:

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