VLSI

MANUAL

VLSI LAB
MANUAL

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34057 Very Large Scale Integration Practical

List of experiments
1. SIMULATION OF VHDL CODE FOR COMBINATIONAL CIRCUIT
2. SIMULATION OF VHDL CODE FOR ARITHMETIC CIRCUITS
3. SIMULATION OF VHDL CODE FOR MULTIPLEXER
4. SIMULATION OF VHDL CODE FOR DEMULTIPLEXER
5. VHDL IMPLEMENTATION OF MULTIPLEXER
6. VHDL IMPLEMENTATION OF DEMULTIPLEXER
7. VHDL IMPLEMENTATION OF 7 SEGMENT DECODER
8. VHDL IMPLEMENTATION OF 7 SEGMENT DECODER BY LUT
9. VHDL IMPLEMENTATION OF ENCODER
10. SIMULATION OF VHDL CODE FOR DELAY
11. VHDL IMPLEMENTATION FOR BLINKING A LED
12. SIMULATE A VHDL TEST BENCH CODE FOR TESTING A GATE
13. VHDL IMPLEMENTATION FOR BLINKING A ARRAY OF LEDS
14. VHDL IMPLEMENTATION OF A SPELLER WITH AN ARRAY OF LEDS
15. VHDL IMPLEMENTATION OF 7 SEGMENT DISPLAY

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INDEX
(Topics Covered)

S.No Date Name of Experiment Pag Marks Sign

e
No

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COMBINATIONAL CIRCUIT
Flow chart:

Source code: Entity diagram:

Library IEEE;
Use a, b,c,df
IEEE.STD_LOGIC_1164.ALL;
Use
IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity sop is
Port (a, b, c, d: in std_logic;
f: out std_logic);
End sop;

Architecture behavioral of
sop is Begin
y <= ((not b and not c and not d) or (not a and b and not c and d) or (a and
not b and not c and d) or (a and b and not c and not d));
End behavioral;

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1. SIMULATION OF VHDL CODE FOR COMBINATIONAL CIRCUIT

Aim
: To study the simulation using tools of ISE (Integrated Software Environment)
using VHDL
techniques. Optimize a 4 variable combinational function (SOP or POS), describe it in
VHDL code and simulate it.

Example: F= (0, 5, 8, 9, 12) in sop or pos

Apparatus Required:
PC, Xilinx Software

Procedure:
The simulation for various digital circuits using VHDL techniques is explained
here. The
Xilinx ISE software consists of four windows.
i. Source Window iii. Message window
ii.Process Window iv. Editor
Window Start Xilinx project navigator by using desktop
shortcut or by using Start All programs  Xilinx ISE 
Project Navigator Steps:
1) New Project Enter Project nameTop level source
type( HDL)(Next)(Next)(Finish).
2) New Project Device Properties:
Product Category = All
Family =Spartan 2
Device =XC2S50
Package = -5
Simulator =ISE Simulator(VHDL/Verilog)
Preferred Language =VHDL (Next)
3) Process Window:
Create New Source VHDL moduleEnter vhd file name
(Next). Assign input and output ports that are necessary for
given design.
4) Editor Window:
VHDL file is opened. Now enter the program and save it. Ensure that the
program(.VHDL file) must be under XC2S50 in source window.
5) Process Window:
Under synthesis XST, double click check syntax. This is done to correct
the errors made in program. Now double click Synthesis XST. After green or
yellow check appeared, you can view RTL and technology schematic.
6) .tbw File:
Select Behavioral simulation in source window.Create new source
test bench waveform Enter tbw file name (Next)(Finish).
In initialize Timing Window, select combinatorial in clock information
(Finish)
7) Editor Window:
Give the clock input and save it. Ensure that .tbw file must be under
XC2S50 in source window.
8) Process Window:
Under Xilinx ISE simulator, double click simulate behavioral model.
Simulation window opens. Verify the output by using truth table.

Result:

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Thus the simulation using Xilinx ISE tools using VHDL technique was studied.

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ADDITION
Source code: Entity diagram:

Library IEEE;
Use
IEEE.STD_LOGIC_1164.ALL; X, Y Sum
Use
IEEE.STD_LOGIC_ARITH.ALL; Cin Cout
Use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity FullAdder is
port(X, Y, Cin :in std_logic;
Cout, Sum: out
std_logic);
End FullAdder;

Architecture dataflow of

FullAdder is Begin
Sum <= X xor Y xor Cin;
Cout <= (X and Y) or (Cin and Y) or (Cin and X);

End architecture;

4 BIT ADDITIONS
Source code: Entity diagram:

Library IEEE;
Use
IEEE.STD_LOGIC_1164.ALL; A, B(3:0)S(3:0)
Use
IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Ci Co

Entity Adder4 is
Port (A, B: in std_logic _vector (3
downto 0); Ci: in std_logic;
S: out std_logic _vector (3
downto 0); Co: out std_logic);
End Adder4;

Architecture Structure of

Adder4 is Component

FullAdder
Port (X, Y, Cin: in std_logic;
Cout, Sum: out std_logic);
End component;

Signal C: std_logic _vector (3 downto1);

Begin

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FA0: FullAdder port map (A(0), B(0), Ci, C(1), S(0));

End FA1: FullAdder port map (A(1), B(1), C(1), C(2), S(1));
Structure; FA2: FullAdder port map (A(2), B(2), C(2), C(3), S(2));
FA3: FullAdder port map (A(3), B(3), C(3), Co, S(3));

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2) SIMULATION OF VHDL CODE FOR ARITHMETIC CIRCUITS

Aim:
To write a VHDL code for Design and Develop the circuit for the following
arithmetic
functions in VHDL Codes and simulate it. Addition, Subtraction Multiplication (4 x 4 bits)

Apparatus Required:

1) PC with Xilinx software

2) FPGA Kit.
3) JTAG Cable.

SUBTRACTION
Source code: Entity diagram:

Library IEEE;
Use
IEEE.STD_LOGIC_1164.ALL; a, b diff
Use
IEEE.STD_LOGIC_ARITH.ALL; bin bout
Use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity fullsub is
Port (a, b, bin: in std_logic;
Diff, bout: out std_logic);
End fullsub;

Architecture dataflow of

fullsub is Begin
Diff <= a xor b xor bin;
Bout <= (not a and b) or (not a and bin ) or (b and bin) ;
End dataflow;

4 BIT SUBTRACTIONS

Source code: Entity diagram: ..

Library IEEE;
Use
IEEE.STD_LOGIC_1164.ALL; a, b(3:0) diff(3:0)
Use
IEEE.STD_LOGIC_ARITH.ALL; bin bout
Use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity sub is
Port (a: in STD_LOGIC_VECTOR (3
downto 0); b: in
STD_LOGIC_VECTOR (3 downto 0);
Bin: in STD_LOGIC;
Diff: out STD_LOGIC_VECTOR (3
downto0); Bout: out STD_LOGIC);

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End sub;
Architecture structure of
sub is Component
fullsub
Port (a, b, bin: in
std_logic; Diff, bout:
out std_logic);

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End component;
Signal D: std_logic_vector(2 downto0);
Begin
X1: fullsub port map (a (0), b (0), bin, Diff (0), D (0));
X2: fullsub port map (a (1), b (1), D (0), Diff (1), D (1));
X3: fullsub port map (a (2), b (2), D (1), Diff (2), D (2));
X4: fullsub port map (a (3), b (3), D (2), Diff (3), Bout);
End structure;

ARITHMETIC CIRCUITS
Flow chart:

MULTIPLICATION
Source code: Entity diagram:
Library IEEE;
Use a (3:0) y(7:0)
IEEE.STD_LOGIC_1164.ALL;
Use
IEEE.STD_LOGIC_ARITH.ALL; b (3:0)
Use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity multiplication is
Port (a: in STD_LOGIC_VECTOR (3
downto 0); b: in STD_LOGIC_VECTOR
(3 downto 0);
y: out STD_LOGIC_VECTOR (7 downto 0));
End multiplication;
Architecture dataflow of
multiplication is Begin
y <= a * b;

End dataflow;

Result:

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Thus the VHDL code is written for addition, subtraction and multiplication
implemented on FPGA Kit.

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2 BIT MULTIPLEXER
Flow chart:

Source code: Entity diagram:

Library IEEE;
Use
IEEE.STD_LOGIC_1164.ALL; x z
Use
IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
y
Entity mux is
Port (x : in
STD_LOGIC; y: in
STD_LOGIC;
sel: in STD_LOGIC;
z: out STD_LOGIC); sel
End mux;
Architecture Behavioral of
mux is Begin
Process (x, y, sel)
Begin
If (sel='0') then
z<=x;
elsif (sel='1') then
z<=y;
End if;

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End
process;
End Behavioral;

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3) SIMULATION OF VHDL CODE FOR MULTIPLEXER

Aim:
To Design and develop a 2 bit multiplexer and port map the same for developing
upto 8 bit
multiplexer.

Apparatus Required:
PC, Xilinx Software

8:1 MULTIPLEXER
Source code: Entity diagram:
Library IEEE;
Use
IEEE.STD_LOGIC_1164.ALL; (a, b, c, d, e, f, g, h)z
Use c0, c1, c2
IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity multiplexer is
Port (a, b, c, d, e, f, g, h: in STD_LOGIC;
c0, c1, c2: in STD_LOGIC;
z: out STD_LOGIC );
End multiplexer;
Architecture structure of
multiplexer is Component
mux
Port (x: in
std_logic; y: in
std_logic; sel:
in std_logic; Z:
out std_logic);
End component;
Signal z1, z2, z3, z4, z5, z6 : std_logic:='0';
Begin
mux1: mux port map (x => a, y=> b, sel=> c0, z =>
z1); mux2: mux port map (x => c, y=> d, sel=> c0, z
=> z2); mux3: mux port map (x=> e, y=> f, sel=> c0,
z => z3); mux4: mux port map ( x => g, y => h, sel=>
c0, z => z4); mux5: mux port map (x => z1, y=> z2,
sel=>c1, z => z5); mux6: mux port map (x => z3, y
=> z4, sel=>c1, z => z6); mux7: mux port map (x =>
z5, y => z6, sel=>c2, z => z);
End structure;

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c0 c1 c2

c0
a x z1 c1
z
b y x z5
c0 z
c x y
z2 c2
z
d y x z7 z
z
c0
e y
x c1
z3
z
f y x z6
z
c0 y
g x z4
z
h y

Result:
Thus the simulation for 2 bit multiplexer and port maps the same for developing
up to 8 bit multiplexer. Using Xilinx ISE tools using VHDL technique was studied.

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DEMULTIPLEXER

Source code: Entity diagram:

Library IEEE;
Use
IEEE.STD_LOGIC_1164.ALL; I O (7:0)
Use
IEEE.STD_LOGIC_ARITH.ALL; S (2:0)
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity demultiplexer is
Port (I : in
std_logic;
s: in std_logic_vector(2 downto
0); O: out std_logic_vector(7
downto 0) );
End demultiplexer;
Architecture dataflow of
demultiplexer is Begin
End dataflow;

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O O (1) <= (I and s (0) and not s (1) and not s
(2));
( O (2) <= (I and not s (0) and s (1) and not s
0 (2)); O (3) <= (I and s (0) and s (1) and not
) s (2));
O (4) <= (I and not s (0) and not s (1) and s
< (2)); O (5) <= (I and s (0) and not s (1) and
= s (2));
O (6) <= (I and not s (0) and s (1) and s (2));
( O (7) <= (I and s (0) and s (1) and s (2));
I

a
n
d

n
o
t

(
0
)

a
n
d

n
o
t

(
1
)

a
n
d

n
o
t

(
2
)
)
;

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4) SIMULATION OF VHDL CODE FOR DEMULTIPLEXER

Aim:
To Design and develop a 8 bit demultiplexer. Simulate the same code in the
software.

Apparatus Required:
PC, Xilinx Software

Result:
Thus the simulation Design and develop an 8 output demultiplexer. Simulate the
same code in the software. Using Xilinx ISE tools using VHDL technique was studied.

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IMPLEMENTATION OF MULTIPLEXER
Flow chart:

Source code: Entity diagram:

Library IEEE;
Use
IEEE.STD_LOGIC_1164.ALL;
Use Data (3:0) m_out
IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL; sel(1:0)
Entity mux is
Port (data: in STD_LOGIC_VECTOR (3
downto 0); sel : in STD_LOGIC_VECTOR
(1 downto 0); m_out: out STD_LOGIC);
End mux;
Architecture Behavioral of
mux is Begin
Process (data, sel)
begin
Case sel is
When "00" => m_out <= data
(0); When "01" => m_out <=
data (1); When "10" => m_out
<= data (2); When "11" =>
m_out <= data (3); When
others => m_out <= 'X';

End case;
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End
process; End
Behavioral;

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5) VHDL IMPLEMENTATION OF MULTIPLEXER

Aim:
To write a VHDL code for Describe the code for a multiplexer and implement it in
FPGA kit in
which switches are connected for select input and for data inputs a LED is connected to
the output.

Apparatus Required:

1) PC with Xilinx software

2) FPGA Kit.
3) JTAG Cable.

Procedure:

1. Switch on the PC.

2. Run the Xilinx software ( Start All Programs  Xilinx ISE  Project Navigator)

3. Open the new project and enter the VHDL code for the given program in editor
window.

4. Save the program and check syntax.

5. Create UCF file and assign input & output pins properly. Then save it.

6. Now synthesis the program by double click on synthesis XST. View RTL and

Technology schematic. After the green or yellow check appeared, double click on

Implement design.Wait until green or yellow check to appear.

7. Right click on generate programming file and In properties, select JTAG

clock in startup options.

8. Generate .bit file by double clicking Generate Programming File.

9. Switch on the kit and load the .bit file into kit.

10.Check for the successful downloading and verify the output in FPGA kit with

assigned port pins

Result:

Thus the VHDL code is written for 4 to 1 multiplexer and implemented on FPGA
Kit.

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IMPLEMENTATION OF DEMULTIPLEXER

Flow Chart:

Source code: Entity diagram:

Library IEEE;
Use
IEEE.STD_LOGIC_1164.ALL; I O (7:0)
Use
IEEE.STD_LOGIC_ARITH.ALL; S(2:0)
Use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity demultiplexer is
Port (I : in std_logic;
s: in std_logic_vector(2 downto
0); O: out std_logic_vector(7
downto 0) );
End demultiplexer;

Architecture dataflow of
demultiplexer is Begin
O (0) <= (I and not s (0) and not s (1) and not s
(2)); O (1) <= (I and s (0) and not s (1) and not
s (2));
O (2) <= (I and not s (0) and s (1) and not s
(2)); O (3) <= (I and s (0) and s (1) and not
s (2));
O (4) <= (I and not s (0) and not s (1) and s
(2)); O (5) <= (I and s (0) and not s (1) and
s (2));
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O (6) <= (I and not s (0) and s (1) and s (2));
O (7) <= (I and s (0) and s (1) and s (2));
End dataflow;

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6) VHDL IMPLEMENTATION OF DEMULTIPLEXER

Aim:

To write a VHDL code for Switches are connected for select inputs and a data input, Eight
LEDs are connected to the output of the circuit.

Apparatus Required:

1) PC with Xilinx software

2) FPGA Kit.
3) JTAG Cable.

Result:

Thus the VHDL code is written for 1 to 4 demultiplexer and implemented on FPGA
Kit.

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IMPLEMENTATION OF 7 SEGMENT DECODER

Flow Chart:

Source code: Entity Diagram:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
I3,I2,I1,I0 sel (7:0)
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; A,B,C,D,E,F,G
Entity seven_seg is
Port ( I3,I2,I1,I0 : in STD_LOGIC;
sel : out std_logic_vector (7
downto 0); A,B,C,D,E,F,G : out STD_LOGIC);
End seven_seg;
Architecture Behavioral of seven_seg is
SIGNAL X0, X1, X2, X3, X4, X5, X6, X7, X8, X9 : STD_LOGIC;
Begin
sel <= "01111111";
X0<= (NOT I3 AND NOT I2 AND NOT I1 AND NOT
I0); X1<= (NOT I3 AND NOT I2 AND NOT I1 AND
I0); X2<= (NOT I3 AND NOT I2 AND I1 AND NOT
I0); X3<= (NOT I3 AND NOT I2 AND I1 AND I0);
X4<= (NOT I3 AND I2 AND NOT I1 AND NOT
I0); X5<= (NOT I3 AND I2 AND NOT I1 AND
I0); X6<= (NOT I3 AND I2 AND I1 AND NOT
I0); X7<= (NOT I3 AND I2 AND I1 AND I0);
X8<= (I3 AND NOT I2 AND NOT I1 AND NOT
I0); X9<= (I3 AND NOT I2 AND NOT I1 AND
I0);
A <= X1 OR
X4; B <= X5
OR X6; C <=
X2;
D <= X1 OR X4 OR X7 OR X9;
E <= X1 OR X3 OR X4 OR X5 OR X7
OR X9; F <= X1 OR X2 OR X3 OR X7;

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G <= X0 OR X1 OR X7;

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End Behavioral;

7. VHDL IMPLEMENTATION OF 7 SEGMENT DECODER

Aim:
To write a VHDL code for interfacing Develop Boolean expression for 4 input
variables and 7
output variables. Design and develop a seven segment decoder in VHDL for 7 equations.
A seven segment display is connected to the output of the circuit. Four switches are
connected to the input. The 4 bit input is decoded to 7 segment equivalent.

Apparatus Required:

1) PC with Xilinx software

2) FPGA Kit.
3) JTAG Cable.
4) 7 segment LED Display Interface
5) 26 pin FRC(Flat Ribbon Cable)

Result:

Thus the VHDL code is written for 7 segment LED display and implemented on
FPGA Kit.

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IMPLEMENTATION OF 7 SEGMENT DECODER BY LUT

Flow Chart:

Source code: Entity diagram:

Library IEEE;
Use Bcd_in(3:0) dsel (7:0)
IEEE.STD_LOGIC_1164.ALL;
Use LED(7:0)
IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity sevenseg is
Port (bcd_in : in STD_LOGIC_VECTOR (3 downto
0); dsel: out STD_LOGIC_VECTOR (7
downto 0);
LED: out STD_LOGIC_VECTOR (7 downto 0));
End sevenseg;

Architecture Behavioral of
sevenseg is Begin
Process (bcd_in)
Begin
dsel <= "01111111";
Case bcd_in is
When "0000" => LED <= "01000000";
When "0001" => LED <= "01111001";
When "0010" => LED <= "00100100";
When "0011" => LED <= "00110000";
When "0100" => LED <= "00011001";
When "0101" => LED <= "00010010";
When "0110" => LED <= "00000010";
When "0111" => LED <=
"01011000";
When "1000" => LED <= "00000000";
When "1001" => LED <= "00010000";
When others => LED <= "01111111";
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End case;
End process;
End Behavioral;

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8. VHDL IMPLEMENTATION OF 7 SEGMENT DECODER BY LUT

Aim
: To write a VHDL code for 7 segment decoder using Look up table. Describe the
seven segment decoder in VHDL using developed Look up table. A seven segment
display is connected to the output of the circuit. Four switches are connected to
the input. The 4 bit input is decoded into 7 segment equivalent.

Apparatus Required:

1) PC with Xilinx software

2) FPGA Kit.
3) JTAG Cable.
4) 7 segment LED Display Interface
5) 26 pin FRC(Flat Ribbon Cable)

Result:

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Thus the VHDL code is written for 7 segment decoder by LUT and implemented on
FPGA Kit.

IMPLEMENTATION OF ENCODER
Flow chart:

Source Code: Entity diagram:

Library IEEE;
Use data(7:0)s_out(3:0)
IEEE.STD_LOGIC_1164.ALL;
Use
IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity enc is
Port (data: in STD_LOGIC_VECTOR (7 downto 0);
s_out : out STD_LOGIC_VECTOR (3 downto
0));
End enc;
Architecture Behavioral of enc is
Begin
Process (data)
Begin
Case data is
When "11111110" => s_out <= "0000";
When "11111101" => s_out <= "0001";
When "11111011" => s_out <= "0010";
When "11110111" => s_out <= "0011";
When "11101111" => s_out <= "0100";
When "11011111" => s_out <= "0101";
When "10111111" => s_out <= "0110";
When "01111111" => s_out <= "0111";

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When others => s_out <= "XXX";
End case;
End process;

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End Behavioral;
9) VHDL IMPLEMENTATION OF ENCODER

Aim:
To write a VHDL code Design and develop HDL code for decimal (Octal) to BCD
encoder.
There will be10 input switches (or 8 switches) and 4 LEDs in the FPGA kit. The input
given from switches and it is noted that any one of the switch is active. The binary
equivalent for the corresponding input switch will be glowing in the
LED as output.

Apparatus Required:

1) PC with Xilinx software

2) FPGA Kit.
3) JTAG Cable.

Result:

Thus the VHDL code is written for 8 to 3 encoder and implemented on FPGA Kit.

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SIMULATION OF VHDL CODE FOR DELAY

Flow Chart:

Source code: Entity diagram:

Library IEEE;
Use
IEEE.STD_LOGIC_1164.ALL; Clocka
Use
IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity delay1 is
Port (clock: in std_logic;
a: out std_logic);
End delay1;
Architecture Behavioral of delay1 is
Begin
Process (clock)
Variable i: integer: = 0;
Begin
If (clock'event and clock = '1') then
If (i<= 50000000)
then i:= i+ 1;
a <= '1';
elsif (i> 50000000 and i <
100000000) then i:= i+ 1;
a <= '0';
elsif (i= 100000000)
then i:= 0;
End if;
End if;
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End process;

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End Behavioral;

10) SIMULATION OF VHDL CODE FOR DELAY

Aim:
Develop a VHDL code for making a delayed output for 1second or 2 seconds by
assuming
clock frequency provided in the FPGA Kit.

Apparatus Required:
PC, Xilinx Software

Result:

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Thus the simulation and Develop a VHDL code for making a delayed output for
1second or 2 seconds by assuming clock frequency provided in the FPGA Kit.

IMPLEMENTATION FOR BLINKING A LED:

Flow Chart:

Source Code: Entity Diagram:

Library IEEE;
Use
clockled(3:0)
IEEE.STD_LOGIC_1164.ALL;
Use
IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity blinkLED is
Port (clock: in std_logic;
LED: out std_logic_VECTOR (7 DOWNTO 0));
End blinkLED;
Architecture Behavioral of
blinkLED is Begin
Process (clock)
Variable i: integer := 0;
Begin
If clock'event and clock = '1'
then If i<= 50000000
then
i:= i+ 1;
LED <= "11111111";
elsif i > 50000000 and i < 100000000 then
i:= i+ 1;
LED <= "00000000";
elsif i = 100000000 then

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i:= 0;
End if;
End if;

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End
process;
End Behavioral; 11) VHDL IMPLEMENTATION FOR BLINKING A LED

Aim:
To Develop a VHDL Code for delay and verify by simulating it. This delay output is
connected to LED. Delay is adjusted such away LED blinks for every 1 or 2 seconds.

Apparatus Required:

1) PC with Xilinx software

2) FPGA Kit.
3) JTAG Cable.

Result:

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Thus the VHDL code is written for Develop a VHDL Code for delay and verify by
simulating it. This delay output is connected to LED. Delay is adjusted such away LED
blinks for every 1 or 2 seconds and implemented on FPGA Kit.

SIMULATE TEST BENCH CODE FOR TESTING A GATE

Flow Chart:

Source code:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE
IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY and_bench_vhd
IS END and_bench_vhd;
ARCHITECTURE behavior OF
and_bench_vhd IS COMPONENT
and_gate
PORT (a: IN
std_logic; b: IN
std_logic;
c: OUT std_logic);
END COMPONENT;
SIGNAL a : std_logic :=
'0'; SIGNAL b :
std_logic := '0'; SIGNAL
c : std_logic; BEGIN
uut: and_gate PORT MAP ( a => a, b => b,c
=> c); tb : PROCESS
BEGIN
a <= '0';
b <= '0';
Wait for 100
ns; a <=
'1';
b <= '0';
Wait for 100 ns;

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a <= '0';
b <= '1';
Wait for 100 ns;

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a <= '1';
b <= '1';
Wait for 100 ns;
END PROCESS;
END
; 12) SIMULATE A VHDL TEST BENCH CODE FOR TESTING A GATE

Aim:

To Develop a VHDL test bench code for testing any one of the simple gate. Simulate the test
bench code in the HDL software.

Apparatus Required:
PC, Xilinx Software

Result:

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Thus the simulation and Develop a VHDL code for VHDL test bench code for
tested any one of the simple gate. Simulate the test bench code in the HDL software.

IMPLEMENTATION FOR BLINKING AN ARRAY OF LEDS

Flow Chart:

Source code: Entity diagram:

Library IEEE;
Use
IEEE.STD_LOGIC_1164.ALL; Clock
Use
IEEE.STD_LOGIC_ARITH.ALL; rst Q(3:0)
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity array is
Port (clock, rst: in std_logic;
Q: out std_logic_vector(3 downto 0) );
End array;
Architecture Behavioral of array is
Signal tmp: std_logic_vector(3 downto 0):="0000";
Begin
Process (clock, rst)
Variable i: integer: =
0;
Begin
If (rst='0') then
tmp<= "0000";
elsif (clock'event and clock = '1')
then If (i<= 50000000) then
i:= i+ 1;
elsif (i= 50000001)
then i:= 0;
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tmp<= tmp+’1’;
End if;

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End
if; End
process;
Q<= tmp;
End Behavioral;
13) VHDL IMPLEMENTATION FOR BLINKING AN ARRAY OF LEDS

Aim:

To Design and develop a VHDL Code for 4 bit binary up counter. Four LEDs are
connected at
the output of the counter. The counter should up for every one seconds.

Apparatus Required:

1) PC with Xilinx software

2) FPGA Kit
3) JTAG Cable
4) Relay and Buzzer Interface
5) 26 pin FRC (Flat Ribbon Cable)

Result:

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Thus the VHDL code is written for VHDL Code for 4 bit binary up counter.
Four LEDs are connected at the output of the counter. The counter should up for
every one seconds. and implemented on FPGA Kit.

IMPLEMENTATION OF A SPELLER WITH AN ARRAY OF LEDS

Flow Chart:

Source code: Entity diagram:

Library IEEE;
Use
IEEE.STD_LOGIC_1164.ALL;
Use Clk Output(3:0)
IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL; select
Entity speller is
Port ( clk : in std_logic;
select1: in std_logic;
Output: out std_logic_vector(3 downto 0));
End speller;

Architecture Behavioral of
speller is Begin
Process (clk, select1)
Variable i, k :
integer := 0; Begin
If clk'event and clk = '1'
then If select1 = '1'
then
if i < 100000000
then i := i +
1;
elsif i = 100000000 then
If k < 7 then
k := k + 1;
elsif k = 7
then k := 0 ;
End
if; i :=
0;
End if;
If k = 0 then
Output <=
"0000"; elsif k =
1 then Output <=
"1000"; elsif k =
2 then Output <=
"1100"; elsif k =
3 then Output <=
"1110"; elsif k =
4 then Output <=
"1111"; elsif k =
5 then Output <=
"0111"; elsif k =

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6 then Output <=
"0011"; elsif k =
7 then Output <=
"0001";

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End if;
End
if;
End if;
End
process;
End Behavioral;

14) VHDL IMPLEMENTATION OF A SPELLER WITH AN ARRAY OF

LEDS
Aim
:

To Design and develop a Design and develop VHDL Code for a 5 bit Johnson ring
counter 4
bit The LEDs are connected at the output of the counter. The speller should work
for every one seconds.

Apparatus Required:

1) PC with Xilinx software

2) FPGA Kit
3) JTAG Cable
4) Relay and Buzzer Interface
5) 26 pin FRC(Flat Ribbon Cable)

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Result:

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Thus the VHDL code is written for VHDL Code Design and develop VHDL Code for
a 5 bit Johnson ring counter 4 bit The LEDs are connected at the output of the counter.
The speller should work for every one seconds.. and implemented on FPGA Kit.

IMPLEMENTATION OF 7 SEGMENT DISPLAY

Flow Chart:
Source code: Entity Diagram :
Library IEEE;
Use
IEEE.STD_LOGIC_1164.ALL;
Use Clock dsel(7:0)
IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL; Led(7:0)
entity display is
Port ( clk : in STD_LOGIC;
dsel : out STD_LOGIC_VECTOR (7 downto
0); led : out STD_LOGIC_VECTOR (7
downto 0));
end display;
architecture Behavioral of display is
signal count : STD_LOGIC_VECTOR(3 downto 0) :="0000";
Begin
process
(clk)
Variable i: integer :=
0; begin

if (clk ' event and clk ='1')

then if i<=10000000
then
i:=i+1;S
elsif i>10000000 then
if count = "1001"
then count <=
"0000"; else
count<=count+
1; end
if;
i:=0;

end if;
end if;
end process;

Process (clk)
Begin
dsel<=”0111111
1”;
case count is
when "0000" => led <= "01000000";
when "0001" => led <= "01111001";
when "0010" => led <= "00100100";
when "0011" => led <= "00110000";
when "0100" => led <= "00011101";
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when "0101" => led <= "00010010";
when "0110" => led <= "00000010";
when "0111" => led <= "01011000";
when "1000" => led <= "00000000";
when "1001" => led <= "00010000";

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When others => led <=

"01111111" ; end case;
end
process;
end behavioral;

15. VHDL IMPLEMENTATION OF 7 SEGMENT DISPLAY

Aim:
To write a VHDL code for Design and develop a seven segment decoder in VHDL.
Design
and develop a 4 bit BCD counter, the output of the counter is given to seven segment
decoder. A seven segment display is connected to the output of the decoder. The
display shows 0,1, 2.. 9 for every one second.

Apparatus Required:

1) PC with Xilinx software

2) FPGA Kit.
3) JTAG Cable.
4) Stepper motor Interface
5) 26 pin FRC(Flat Ribbon Cable)

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Result:

Thus the VHDL code is written for seven segment decoder and implemented on
FPGA Kit.