VHDL LABS

Simulation and RTL Verification Lab

Solution

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LAB 1 - Familiarization with Combinational Logic design

a) Full Adder RTL Code

----------------------------------------------------------------------------------- Module Name: FULL_ADDER - Behavioral
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULL_ADDER is
Port ( A,B,CIN : in STD_LOGIC;
S,COUT : out STD_LOGIC);
end FULL_ADDER;
architecture Behavioral of FULL_ADDER is
begin
S <= A xor B xor CIN;
COUT <= ((A and B) or (B and CIN) or (A and CIN));
end Behavioral;

Full Adder Test Bench

--------------------------------------------------------------------------------- Module Name: t_FULL_ADDER.vhd
-- VHDL Test Bench for module: FULL_ADDER
-------------------------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY t_FULL_ADDER_vhd IS
END t_FULL_ADDER_vhd;
ARCHITECTURE behavior OF t_FULL_ADDER_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT FULL_ADDER
PORT( A , B , CIN : IN std_logic;
S , COUT : OUT std_logic );
END COMPONENT;
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--Inputs
SIGNAL A ,B ,CIN : std_logic := '0';
--Outputs
SIGNAL S ,COUT : std_logic;
--Intermediate signal
SIGNAL ABC : std_logic_vector(2 DOWNTO 0):="000";
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: FULL_ADDER PORT MAP
(A => A, B => B, CIN => CIN, S => S, COUT => COUT );
tb : PROCESS
BEGIN
A <= ABC(0); B <= ABC(1); CIN <=ABC(2);
wait for 5 ns;
ABC <= ABC + 1;
END PROCESS;
END;

b) Ripple Carry Adder RTL Code

----------------------------------------------------------------------------------- Module Name: RIPPLE_ADDER - Behavioral
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RIPPLE_ADDER is
port (A, B : in std_logic_vector(3 downto 0);
CIN : in std_logic;
SUM : out std_logic_vector(3 downto 0);
COUT : out std_logic);
end;
architecture STRUCTURE of RIPPLE_ADDER is
alias IN1 : std_logic_vector( A'LENGTH-1 downto 0) is A;
alias IN2 : std_logic_vector( A'LENGTH-1 downto 0) is B;
signal C : std_logic_vector(IN1'RANGE);
--component declaration
component FULL_ADDER
port (A,B,CIN: in std_logic; S, COUT: out std_logic);
end component;

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begin
L1: for I in SUM'RANGE generate
L2: if I=0 generate
FA1: FULL_ADDER port map (IN1(0),IN2(0),CIN,SUM(0),C(0)); --component instantiation
end generate;
--for unit adder
L3: if I>0 generate
FA2: FULL_ADDER port map (IN1(I),IN2(I),C(I-1),SUM(I),C(I)); --component instantiation
end generate;
end generate;
COUT <= C(C'HIGH);
end STRUCTURE;

Ripple Carry Adder Test Bench

--------------------------------------------------------------------------------- Module Name: t_RIPPLE_ADDER.vhd
-- VHDL Test Bench for module: RIPPLE_ADDER
-------------------------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY t_RIPPLE_ADDER_vhd IS
END t_RIPPLE_ADDER_vhd;
ARCHITECTURE behavior OF t_RIPPLE_ADDER_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RIPPLE_ADDER
PORT( A ,B : IN std_logic_vector(3 downto 0);
CIN : IN std_logic;
SUM : OUT std_logic_vector(3 downto 0);
COUT : OUT std_logic);
END COMPONENT;
--Inputs
SIGNAL CIN : std_logic := '0';
SIGNAL A,B : std_logic_vector(3 downto 0) := (others=>'0');
--Outputs
SIGNAL SUM : std_logic_vector(3 downto 0);
SIGNAL COUT : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RIPPLE_ADDER
PORT MAP( A => A,B => B,CIN => CIN,SUM => SUM,COUT => COUT

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);

tb : PROCESS
BEGIN
A<= "0010";
wait for 5 ns;
A<= "1111";
wait for 5 ns;
A<= "1111";
wait for 5 ns;
A<= "1111";
wait for 5 ns;
A<= "1111";
wait ;
END PROCESS;

B<= "0100";

CIN<='1';

B<= "0001";

CIN<='0';

B<= "0000";

CIN<='1';

B<= "0001";

CIN<='1';

B<= "0100";

CIN<='0';

END;

c) 4:1 Mux RTL Code

------------------------------------------------------ Engineer: Praveena G
-- Module Name: mux_4_1 - Behavioral
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_4_1 is
Port ( Din : in STD_LOGIC_VECTOR (3 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
Dout : out STD_LOGIC);
end mux_4_1 ;
architecture Behavioral of mux_4_1 is
begin
process(Din,sel)
begin
case sel is
when "00" => Dout <= Din(0);
when "01" => Dout <= Din(1);
when "10" => Dout <= Din(2);
when "11" => Dout <= Din(3);
when others => null;
end case;
end process;
end Behavioral;
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4:1 Mux Test Bench

--------------------------------------------------------------------------------- Engineer: Praveena G
-- Module Name: t_mux_4_1.vhd
-- VHDL Test Bench for module: mux_4_1
-------------------------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY t_mux_4_1_vhd IS
END t_mux_4_1_vhd;
ARCHITECTURE behavior OF t_mux_4_1_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mux_4_1
PORT(Din : IN std_logic_vector(3 downto 0);
sel : IN std_logic_vector(1 downto 0);
Dout : OUT std_logic);
END COMPONENT;
--Inputs
SIGNAL Din : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL sel : std_logic_vector(1 downto 0) := (others=>'0');
--Outputs
SIGNAL Dout : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mux_4_1 PORT MAP(Din => Din,
sel => sel,
Dout => Dout);
PROCESS
BEGIN
Din <= "1010";
sel <= sel + 1;
wait for 5 ns;
END PROCESS;
END;

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d) Decoder - RTL Code

------------------------------------------------------------------------------------ Engineer: Praveena G
-- Module Name: decoder3_8 - Behavioral
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder3_8 is
Port ( D
: in std_logic_vector(2 downto 0);
Reset : in std_logic;
Y : out std_logic_vector(7 downto 0));
end decoder3_8;
architecture Behavioral of decoder3_8 is
begin
process(D,Reset)
begin
if(Reset='1') then
Y<="00000000";
else
case D is
when "000" => y <= "00000001";
when "001" => y <= "00000010";
when "010" => y <= "00000100";
when "011" => y <= "00001000";
when "100" => y <= "00010000";
when "101" => y <= "00100000";
when "110" => y <= "01000000";
when 111 => y <= "10000000";
when others => null;
end case;
end if;
end process;
end Behavioral;

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Decoder Test Bench

--------------------------------------------------------------------------------- Engineer: Praveena G
-- Module Name: t_decoder3_8.vhd
-- VHDL Test Bench for module: decoder3_8
-------------------------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY t_decoder3_8_vhd IS
END t_decoder3_8_vhd;
ARCHITECTURE behavior OF t_decoder3_8_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT decoder3_8
PORT( D : IN std_logic_vector(2 downto 0);
Reset : IN std_logic;
Y : OUT std_logic_vector(7 downto 0));
END COMPONENT;
--Inputs
SIGNAL Reset : std_logic := '0';
SIGNAL D : std_logic_vector(2 downto 0) := (others=>'0');
--Outputs
SIGNAL Y : std_logic_vector(7 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: decoder3_8 PORT MAP( D => D,
Reset => Reset,
Y => Y);
tb1 : PROCESS
BEGIN
wait for 5 ns;
reset <= '1';
wait for 10 ns;
reset <= '0';
wait; -- will wait forever
END PROCESS;
tb2 : PROCESS
BEGIN
wait for 5 ns;
D <= D + 1;
END PROCESS;
END;

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e) Priority Encoder RTL Code

----------------------------------------------------------------------------------- Engineer: Praveena G
-- Module Name: priority_encoder8_3 - Behavioral
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity priority_encoder8_3 is
Port ( D : in std_logic_vector(7 downto 0);
Reset : in std_logic;
Y
: out std_logic_vector(2 downto 0));
end priority_encoder8_3;
architecture Behavioral of priority_encoder8_3 is
begin
process(D,Reset)
begin
if(Reset='1') then
Y<="000";
else
if(D(7)='1') then
y <= "111";
elsif(D(6)='1') then
y <= "110";
elsif(D(5)='1') then
y <= "101";
elsif(D(4)='1') then
y <= "100";
elsif(D(3)='1') then
y <= "011";
elsif(D(2)='1') then
y <= "010";
elsif(D(1)='1') then
y <= "001";
elsif(D(0)='1') then
y <= "000";
else
y <= "000";
end if;
end if;
end process;
end Behavioral;

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Priority Encoder Test Bench

--------------------------------------------------------------------------------- Module Name: t_priority_encoder8_3.vhd
-- VHDL Test Bench for module: priority_encoder8_3
-------------------------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY t_priority_encoder8_3_vhd IS
END t_priority_encoder8_3_vhd;
ARCHITECTURE behavior OF t_priority_encoder8_3_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT priority_encoder8_3
PORT( D : IN std_logic_vector(7 downto 0);
Reset : IN std_logic;
Y : OUT std_logic_vector(2 downto 0));
END COMPONENT;
--Inputs
SIGNAL Reset : std_logic := '0';
SIGNAL D : std_logic_vector(7 downto 0) := (others=>'0');
--Outputs
SIGNAL Y : std_logic_vector(2 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: priority_encoder8_3 PORT MAP( D => D, Reset => Reset, Y => Y);
tb1: PROCESS
BEGIN
wait for 5 ns;
reset <= '1';
wait for 10 ns;
reset <= '0';
wait; -- will wait forever
END PROCESS;
tb2 : PROCESS
BEGIN
for i in 0 to 7 loop
D <= (others => '0');
D(i) <= '1';
wait for 5 ns;
end loop;
END PROCESS;
END;

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f) Comparator RTL Code

----------------------------------------------------------------------------------- Engineer: Praveena G
-- Module Name: comparator - Behavioral
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comparator is
Port ( reset : in STD_LOGIC;
A,B : in STD_LOGIC_VECTOR (3 downto 0);
E,G,L : out STD_LOGIC);
end comparator;
architecture Behavioral of comparator is
begin
process(reset,A,B)
begin
if(reset = '1') then
E <='0';G <='0';L <='0';
elsif(A = B) then
E <='1';G <='0';L <='0';
elsif(A < B) then
E <='0';G <='0';L <='1';
elsif(A > B) then
E <='0';G <='1';L <='0';
end if;
end process;
end Behavioral;

Comparator Test Bench

--------------------------------------------------------------------------------- Engineer: Praveena G
-- Module Name: t_comparator.vhd
-- VHDL Test Bench for module: comparator
-------------------------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

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ENTITY t_comparator_vhd IS
END t_comparator_vhd;
ARCHITECTURE behavior OF t_comparator_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT comparator
PORT(reset : IN std_logic;
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
E , G ,L : OUT std_logic);
END COMPONENT;
--Inputs
SIGNAL reset : std_logic := '0';
SIGNAL A : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL B : std_logic_vector(3 downto 0) := (others=>'0');
--Outputs
SIGNAL E ,G, L : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: comparator PORT MAP(reset => reset,
A => A,
B => B,
E => E,
G => G,
L => L );

tb : PROCESS
BEGIN
wait for 5 ns;
A <= A + 2;
B <= B + 3;
wait for 5 ns;
A <= A + 6;
B <= B + 1;
wait for 5 ns;
A <= A + 1;
B <= B + 2;
wait for 5 ns;
END PROCESS;
END;

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LAB 2 - Familiarization with Sequential Logic design

a) SR latch RTL Code
----------------------------------------------------------------------------------- Module Name: SRlatch - Behavioral
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRlatch is
Port ( S,R,Preset,Clear,Enable : in std_logic;
Q : inout std_logic;
Qn : out std_logic);
end SRlatch;
architecture Behavioral of SRlatch is
begin
process(Preset,Clear,Enable,S,R)
begin
if(Preset ='1' ) then
Q <= '1';
elsif(Clear ='1') then
Q <= '0';
elsif(Enable='1') then
Q <= (S or( (not R) and Q));
end if;
end process;
Qn <= not Q;
end Behavioral;

SR latch Test Bench

--------------------------------------------------------------------------------- Module Name: t_SRlatch.vhd
-- VHDL Test Bench for module: SRlatch
-------------------------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

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ENTITY t_SRlatch_vhd IS
END t_SRlatch_vhd;
ARCHITECTURE behavior OF t_SRlatch_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SRlatch
Port ( S,R,Preset,Clear,Enable : in std_logic;
Q : inout std_logic;
Qn : out std_logic);
END COMPONENT;
--Inputs
SIGNAL S , R , Preset ,Clear , Enable : std_logic := '0';
--BiDirs
SIGNAL Q : std_logic;
--Outputs
SIGNAL Qn : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SRlatch PORT MAP( S => S,R => R, Preset => Preset, Clear => Clear, Enable => Enable,
Q => Q, Qn => Qn);
tb : PROCESS
BEGIN
wait for 5 ns;
S <='0'; R <='0';
Preset <='0';
Clear <='1'; Enable <='1';
wait for 10 ns;
S <='0'; R <='0';
Preset <='1'; Clear <='0'; Enable <='1';
wait for 10 ns;
S <='0'; R <='1';
Preset <='0'; Clear <='0'; Enable <='1';
wait for 10 ns;
S <='1'; R <='0';
Preset <='0'; Clear <='0'; Enable <='0';
wait for 10 ns;
S <='1'; R <='0';
Preset <='0'; Clear <='0'; Enable <='1';
wait for 10 ns;
S <='0'; R <='1';
Preset <='0'; Clear <='0'; Enable <='1';
wait for 10 ns;
S <='0'; R <='1';
Preset <='0'; Clear <='0'; Enable <='0';
wait; -- will wait forever
END PROCESS;
END;

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b) SR Flipflop RTL Code

----------------------------------------------------------------------------------- Module Name: SRflipflop - Behavioral
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRflipflop is
Port ( S,R,Preset,Clear,clk : in std_logic;
Q : inout std_logic;
Qn : out std_logic);
end SRflipflop;
architecture Behavioral of SRflipflop is
begin
process( Preset,Clear,clk )
begin
if(Preset ='1' ) then
Q <= '1';
elsif(Clear ='1') then
Q <= '0';
elsif(clk='1' and clk'event) then
Q <= (S or( (not R) and Q));
end if;
end process;
Qn <= not Q;
end Behavioral;

SR Flipflop Test Bench

--------------------------------------------------------------------------------- Module Name: t_SRflipflop.vhd
-- VHDL Test Bench for module: SRflipflop
-------------------------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY t_SRflipflop_vhd IS
END t_SRflipflop_vhd;

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ARCHITECTURE behavior OF t_SRflipflop_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SRflipflop
PORT( S ,R ,Preset , Clear , clk : IN std_logic;
Q : INOUT std_logic;
Qn : OUT std_logic );
END COMPONENT;
--Inputs
SIGNAL S, R ,Preset , Clear , clk : std_logic := '0';
--BiDirs
SIGNAL Q : std_logic;
--Outputs
SIGNAL Qn : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SRflipflop PORT MAP ( S => S,R => R,Preset => Preset,Clear => Clear,clk => clk,
Q => Q,Qn => Qn);
tb1 : PROCESS
BEGIN
wait for 5 ns;
clk <= not(clk);
END PROCESS;
tb2 : PROCESS
BEGIN
wait for 5 ns;
S <='0';
R <='0';
Preset <='0'; Clear <='1';
wait for 10 ns;
S <='0';
R <='0';
Preset <='1'; Clear <='0';
wait for 10 ns;
S <='0';
R <='1';
Preset <='0'; Clear <='0';
wait for 10 ns;
S <='1';
R <='0';
Preset <='0'; Clear <='0';
wait for 10 ns;
S <='0';
R <='1';
Preset <='0'; Clear <='0';
wait; -- will wait forever
END PROCESS; END;

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c) D Flipflop RTL Code

----------------------------------------------------------------------------------- Module Name: Dff - Behavioral
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Dff is
Port ( D,Preset,Clear,clk : in std_logic;
Q : inout std_logic;
Qn : out std_logic);
end Dff;
architecture Behavioral of Dff is
begin
process(
Preset,Clear,clk )
begin
if(Preset ='1' ) then
Q <= '1';
elsif(Clear ='1') then
Q <= '0';
elsif(clk='1' and clk'event) then
Q <= D;
end if;
end process;
Qn <= not Q;
end Behavioral;

D Flipflop Test Bench

--------------------------------------------------------------------------------- Module Name: t_Dff.vhd
-- VHDL Test Bench for module: Dff
-------------------------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY t_Dff_vhd IS
END t_Dff_vhd;

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ARCHITECTURE behavior OF t_Dff_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Dff
PORT( D ,Preset ,Clear ,clk : IN std_logic;
Q : INOUT std_logic;
Qn : OUT std_logic );
END COMPONENT;
--Inputs
SIGNAL D,Preset ,Clear ,clk : std_logic := '0';
--BiDirs
SIGNAL Q : std_logic;
--Outputs
SIGNAL Qn : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Dff PORT MAP(D => D,Preset => Preset,Clear => Clear,clk => clk, Q => Q,Qn => Qn );
clk_input:PROCESS
BEGIN
wait for 5 ns;
clk <= not(clk);
END PROCESS;
D_input:PROCESS
BEGIN
wait for 15 ns;
D <= not(D);
END PROCESS;
control_inputs:PROCESS
BEGIN
Preset <='0'; Clear <='1';
wait for 10 ns;
Preset <='1'; Clear <='0';
wait for 10 ns;
Preset <='0'; Clear <='0';
wait;
END PROCESS;
END;

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d) 4 Bit counter RTL Code

----------------------------------------------------------------------------------- Module Name: counter - Behavioral
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port ( reset,clk : in std_logic;
q : inout std_logic_vector(3 downto 0));
end counter;
architecture Behavioral of counter is
begin
process(reset,clk)
begin
if (reset ='1') then
q <="0000";
elsif (clk ='1'and clk'event) then
q <= q + 1;
end if;
end process;
end behavioral;

4 Bit counter Test Bench

--------------------------------------------------------------------------------- Module Name: t_counter.vhd
-- VHDL Test Bench for module: counter
-------------------------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY t_counter_vhd IS
END t_counter_vhd;

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ARCHITECTURE behavior OF t_counter_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT counter
PORT( reset : IN std_logic;
clk : IN std_logic;
q : INOUT std_logic_vector(3 downto 0));
END COMPONENT;
--Inputs
SIGNAL reset : std_logic := '0';
SIGNAL clk : std_logic := '0';
--BiDirs
SIGNAL q : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: counter PORT MAP(reset => reset,
clk => clk,
q => q );
tb1 : PROCESS
BEGIN
wait for 5 ns;
clk <= not clk;
END PROCESS;
tb2 : PROCESS
BEGIN
wait for 5 ns;
reset <= '1';
wait for 10 ns;
reset <= '0';
wait;
END PROCESS;
END;

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e) Sequence counter RTL Code

----------------------------------------------------------------------------------- Module Name: seq_counter - Structural
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity seq_counter is
Port ( clk,preset,clear : in STD_LOGIC;
A,B,C : inout STD_LOGIC);
end seq_counter;
architecture structural of seq_counter is
--Intermediate signals
signal TA,TB,TC : std_logic;
--component declaration
component Tff is
Port ( T,Preset,Clear,clk : in std_logic;
Q : inout std_logic;
Qn : out std_logic);
end component;
begin
TC<= (A xor C);
TB<= (A or (not B) or C);
TA <= ((NOT A) AND B AND (NOT C))OR((NOT B) AND C);
Cff: Tff PORT MAP (T => TA,Preset => Preset,Clear => Clear,clk => clk,Q => A);
Bff: Tff PORT MAP (T => TB,Preset => Preset,Clear => Clear,clk => clk,Q => B);
Aff: Tff PORT MAP (T => TC,Preset => Preset,Clear => Clear,clk => clk,Q => C);
end structural;

Sequence counter Test Bench

---------------------------------------------------------------------------------- Module Name: t_seq_counter.vhd
-- VHDL Test Bench for module: seq_counter
-------------------------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

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ENTITY t_seq_counter_vhd IS
END t_seq_counter_vhd;
ARCHITECTURE behavior OF t_seq_counter_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT seq_counter
PORT( clk ,preset ,clear : IN std_logic;
A ,B ,C : INOUT std_logic );
END COMPONENT;
--Inputs
SIGNAL clk,preset ,clear : std_logic := '0';
--BiDirs
SIGNAL A,B,C : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: seq_counter PORT MAP( clk => clk,
A => A,

preset => preset,

clear => clear,
B => B,
C => C );

tb1 : PROCESS
BEGIN
wait for 5 ns;
clk <= not(clk);
END PROCESS;
tb2 : PROCESS
BEGIN
Preset <='0'; Clear <='1';
wait for 10 ns;
Preset <='1'; Clear <='0';
wait for 10 ns;
Preset <='0'; Clear <='0';
wait;
END PROCESS;
END;

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LAB 3 - Familiarization with FSM design

a) Sequence detector RTL Code
1/0

0/0

1/0

0/0
B

1/0
C

0/0
0/0

1/0

1/0

----------------------------------------------------------------------------------- Module Name: seq_detector - Behavioral

---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity seq_detector is
port (clk,x: in std_logic;
z: out std_logic);
end seq_detector;
-- detect a 0110 sequence
architecture mealy of seq_detector is
type states is (a,b,c,d,e);
signal state: states := a; -- initial value is a
signal next_state: states := a; -- initial value
begin
clock:process(clk)
begin
if (clk'event and clk = '1') then

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0/1

state <= next_state;

end if;
end process ;
nlogic:process(state,x) --next_state and output logic process
begin
next_state <= state; --update next state
case state is
when a => if x = '0' then
z <= '0';
next_state <=b;
else
z <= '0';
next_state <= a;
end if;
when b => if x = '1' then
--"0"
z <= '0';
next_state <= c;
else
z <= '0';
next_state <= b;
end if;
when c => if x = '1' then
--"01"
z <= '0';
next_state <= d;
else
z <= '0';
next_state <= b;
end if;
when d => if x = '0' then
--"011"
next_state <= e;
z <= '1';
else
next_state <= a;
z <= '0';
end if;
when e => if x = '0' then
--"0110"
next_state <= b;
z <= '0';
else
next_state <= a;
z <= '0';
end if;
end case;
end process ;
end mealy;

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Sequence detector Test Bench

--------------------------------------------------------------------------------- Module Name: t_seq_detector.vhd
-- VHDL Test Bench for module: seq_detector
-------------------------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY t_seq_detector_vhd IS
END t_seq_detector_vhd;
ARCHITECTURE behavior OF t_seq_detector_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT seq_detector
PORT(clk,x : IN std_logic; z : OUT std_logic);
END COMPONENT;
--Inputs
SIGNAL clk,x : std_logic := '0';
--Outputs
SIGNAL z : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: seq_detector PORT MAP(clk => clk, x => x,z => z);
tb1 : PROCESS
BEGIN
wait for 5 ns;
clk <= not clk;
END PROCESS;
tb2 : PROCESS
BEGIN
wait for 15 ns;
x <= '1';
wait for 10 ns;
x <= '1';
wait for 10 ns;
x <= '0';
wait for 10 ns;
x <= '1';
wait for 10 ns;
x <= '1';
wait for 10 ns;
x <= '0';
wait for 10 ns;
x <= '1';
wait for 10 ns;
x <= '0';
wait for 10 ns;
x <= '0';
wait for 15 ns;
x <= '1';
END PROCESS;
END;

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b) ODD PARITY CHECKER

----------------------------------------------------------------------------------- Module Name: mealy_odd_parity_1p - Behavioral
-- An odd parity checker as an FSM

One process Mealy.

-- Coding style:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mealy_odd_parity_1p IS
PORT( clk, reset: IN std_logic;
x: IN std_logic;
y: OUT std_logic);
END mealy_odd_parity_1p;
ARCHITECTURE mealy_1p OF mealy_odd_parity_1p IS
TYPE state_type IS (even, odd);
SIGNAL current_state: state_type;
BEGIN
PROCESS (clk, reset, current_state, x)
BEGIN
IF reset = '1' THEN
current_state <= even;
ELSIF (clk='1' and clk'event) THEN
CASE current_state IS
WHEN even =>
IF x = '1' THEN
current_state <= odd;
y <= '1';
ELSE
current_state <= even;
y <= '0';
END IF;
WHEN odd =>
IF x = '1' THEN
current_state <= even;
y <= '0';
ELSE
current_state <= odd;
y <= '1';
END IF;
END CASE;
END IF;
END PROCESS ;
END ARCHITECTURE mealy_1p;

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----------------------------------------------------------------------------------- Module Name: mealy_odd_parity_2p - Behavioral

Two process Mealy.

-- An odd parity checker as an FSM .Coding style:

---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mealy_odd_parity_2p IS
PORT( clk, reset: IN std_logic;
x: IN std_logic;
y: OUT std_logic);
END ENTITY mealy_odd_parity_2p;
ARCHITECTURE mealy_2p OF mealy_odd_parity_2p IS
TYPE state_type IS (even, odd);
SIGNAL current_state: state_type;
SIGNAL next_state: state_type;
BEGIN
CP:PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
current_state <= even;
ELSIF rising_edge (clk) THEN
current_state <= next_state;
END IF;
END PROCESS;
NSP:PROCESS (current_state, x)
BEGIN
CASE current_state IS
WHEN even =>
IF x = '1' THEN
y <= '1';
next_state <= odd;
ELSE
y <= '0';
next_state <= even;
END IF;
WHEN odd =>
IF x = '1' THEN
y <= '0';
next_state <= even;
ELSE
y <= '1';
next_state <= odd;
END IF;
END CASE;
END PROCESS; END ARCHITECTURE mealy_2p;

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----------------------------------------------------------------------------------- Module Name: mealy_odd_parity_3p - Behavioral

-- An odd parity checker as an FSM .

Three processes Mealy.

-- Coding style:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mealy_odd_parity_3p IS
PORT( clk, reset: IN std_logic;
x: IN std_logic;
y: OUT std_logic);
END ENTITY mealy_odd_parity_3p;
ARCHITECTURE mealy_3p OF mealy_odd_parity_3p IS
TYPE state_type IS (even, odd);
SIGNAL current_state: state_type;
SIGNAL next_state: state_type;
BEGIN
CP: PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
current_state <= even;
ELSIF rising_edge (clk) THEN
current_state <= next_state;
END IF;
END PROCESS ;
NSL: PROCESS (current_state, x)
BEGIN
CASE current_state IS
WHEN even =>
IF x = '1' THEN
next_state <= odd;
ELSE
next_state <= even;
END IF;
WHEN odd =>
IF x = '1' THEN
next_state <= even;
ELSE
next_state <= odd;
END IF;
END CASE;
END PROCESS ;

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OPL: PROCESS (current_state, x)

BEGIN
CASE current_state IS
WHEN even =>
IF x = '1' THEN
y <= '1';
ELSE
y <= '0';
END IF;
WHEN odd =>
IF x = '1' THEN
y <= '0';
ELSE
y <= '1';
END IF;
END CASE;
END PROCESS ;
END ARCHITECTURE mealy_3p;

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----------------------------------------------------------------------------------- Module Name: odd_parity_1p - Behavioral

-- An odd parity checker as an FSM .

One processes Moore

-- Coding style:
.
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY odd_parity_1p IS
PORT( clk, reset: IN std_logic;
x: IN std_logic;
y: OUT std_logic);
END ENTITY odd_parity_1p;
ARCHITECTURE moore_1p OF odd_parity_1p IS
TYPE state_type IS (even, odd);
SIGNAL current_state: state_type;
BEGIN
PROCESS (clk, reset, current_state)
BEGIN
IF reset = '1' THEN
current_state <= even;
ELSIF rising_edge (clk) THEN
CASE current_state IS
WHEN even =>
y <= '0';
IF x = '1' THEN
current_state <= odd;
ELSE
current_state <= even;
END IF;
WHEN odd =>
y <= '1';
IF x = '1' THEN
current_state <= even;
ELSE
current_state <= odd;
END IF;
END CASE;
END IF;
END PROCESS ;
END ARCHITECTURE moore_1p;

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----------------------------------------------------------------------------------- Module Name: odd_parity_2p - Behavioral

-- An odd parity checker as an FSM using VHDL.

Two processes Moore

-- Coding style:
.
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY odd_parity_2p IS
PORT( clk, reset: IN std_logic;
x: IN std_logic;
y: OUT std_logic);
END ENTITY odd_parity_2p;
ARCHITECTURE moore_2p OF odd_parity_2p IS
TYPE state_type IS (even, odd);
SIGNAL current_state: state_type;
SIGNAL next_state: state_type;
BEGIN
CP: PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
current_state <= even;
ELSIF rising_edge (clk) THEN
current_state <= next_state;
END IF;
END PROCESS ;
NSP: PROCESS (current_state, x)
BEGIN
CASE current_state IS
WHEN even =>
y <= '0';
IF x = '1' THEN
next_state <= odd;
ELSE
next_state <= even;
END IF;
WHEN odd =>
y <= '1';
IF x = '1' THEN
next_state <= even;
ELSE
next_state <= odd;
END IF;
END CASE;
END PROCESS ;

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END ARCHITECTURE moore_2p;

----------------------------------------------------------------------------------- Module Name: odd_parity_3p - Behavioral
-- An odd parity checker as an FSM using VHDL.

Three processes Moore

-- Coding style:
.
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY odd_parity_3p IS
PORT( clk, reset: IN std_logic;
x: IN std_logic;
y: OUT std_logic);
END ENTITY odd_parity_3p;
ARCHITECTURE moore_3p OF odd_parity_3p IS
TYPE state_type IS (even, odd);
SIGNAL current_state: state_type;
SIGNAL next_state: state_type;
BEGIN
CP: PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
current_state <= even;
ELSIF rising_edge (clk) THEN
current_state <= next_state;
END IF;
END PROCESS ;
NSP: PROCESS (current_state, x)
BEGIN
CASE current_state IS
WHEN even =>
IF x = '1' THEN
next_state <= odd;
ELSE
next_state <= even;
END IF;
WHEN odd =>
IF x = '1' THEN
next_state <= even;
ELSE
next_state <= odd;
END IF;
END CASE;
END PROCESS ;

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OPL: PROCESS (current_state)

BEGIN
CASE current_state IS
WHEN even =>
y <= '0';
WHEN odd =>
y <= '1';
END CASE;
END PROCESS ;
END ARCHITECTURE moore_3p;

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