ICC2：Design Planning（03）Power Network Synthesis

blog.csdn.net/m0_61544122/article/details/127880446

After the shape block, pg planning can be done next. Power network creation can be
divided into the following parts:

1.Add Power Pad

Before planning the power mesh , you need to insert the power pad first, so you need to
load upf in the create abstract stage. If there is no power pad when planning the power
mesh, you also need to set up a virtual power pad. The place of the power pad is the same
as the signal IO using the place_io command.

1.1 Setting Power I/O Constraints

To insert power io, you can use the method of inserting signal io, or you can use the
independent command set_power_io_constraints+place_io to insert power io

1) set_power_io_constraints+place_io

set_power_io_constraints \

  -io_guide_object <io guide>

  -reference_cell <io library cell name>

1/21
  -ratio <the maximum number of signal io between continuous power io> ;#Only look at
signal io, not power io

  -offset <the maximum distance between the starting point of io guide and the nearest
power io>

  -spacing <maximum distance between power io>

  -share <a bump can connect to the maximum number of power io>

Examples are as follows:

set_power_io_constraints -io_guide_object [get_io_guides "*bottom *top"] { {reference:

VDD_NS} {ratio: 7} }

set_power_io_constraints -io_guide_object [get_io_guides "*bottom *top"] { {reference:

VSS_NS} {ratio: 8} }

As shown in the figure above, VDD_NS radio is 7, and seven signal ios are placed between
two power ios, while VSS_NS ratio is 8, corresponding to 8 signal ios between two ground
ios.

2) set_signal_io_constraints+place_io

Users can manually set the relative position and quantity of power io and signal io.
Examples are as follows:

create_cell pg_vddh_left1 [get_lib_cells */VDD_EW]

create_cell pg_vddh_left2 [get_lib_cells */VDD_EW] ... set_signal_io_constraints –file

all_pads.io

## all_pads.io

...

pad_iopad_13

} {{40}

pg_vss_left_1

2/21
pg_vddh_left_1

{{order_only}

pad_iopad_14

...

1.2 Insert Physical Only I/O Cells

After power io and signal io are placed, physical only I/O cells can be placed, including the
following three types:

1) create_io_corner_cell

Insert the corner cell between the two io guides, generally at the four corners of the chip,
and the direction of the corner cell follows the first io guide.

There are two ways to add, one is to specify the inst name and the other is to specify the
ref cell name. The former requires corner cells in the netlist.

create_io_corner_cell \

-cell <inst> \

{ <io_guide1 io_guide2> }

create_io_corner_cell \

-reference_cell <lib_cell> \

{ <io_guide1 io_guide2> }

Examples are as follows:

3/21
2) create_io_break_cells

Cut off the io ring with different voltage.

create_io_break_cells

              [-reference_cells lib_cell_name_list]

              [-cells cell_name_list]

              [-location start | end | both | offset | cell]

              io_guide_list

4/21
3) Add I/O Filler Cell

Fill the gaps between IOs.

5/21
1.3 Route Flip Chip Nets

RDL winding is used to connect IO and bump.

1) Set routing rule for the RDL nets 

create_routing_rule RDL -widths {MRDL 12}

set_routing_rule -rule RDL \

[get_nets -of_objects [get_pins -of_objects \

[get_cells -filter "ref_name == BUMP"]]]

2) Route the RDL nets

route_rdl_flip_chip -layers {MRDL} \ [-nets <nets> | -nets_in_file <nets_file>]

6/21
3) optional，remove or reduce the amount of U and Z routing shape。

optimize_rdl_routes -layer RDL -reserve_power_resources true

4) optional，route a collection of nets and match their length

route_rdl_differential -layer RDL -nets [get_nets "A B C"]

2.Design the Power Network

The Pattern Based Power Network Synthesis (PPNS) process is as follows:

7/21
2.1 PG Regions

pg region can be created based on core area, block, voltage area, macro/groups of macros,
groups of regions, polygon.

Example:

create_pg_region r1 -core -exclude_macros {u_one u_two } -macro_offset 5.0 ; #Create

a pg region based on the core area, but exclude two macros and leave a distance of 5.0um
between them.

8/21
2.2 PG Ring
To define a pg ring, you need to specify the horizontal and vertical layers, as well as
conditions such as spacing, width, and via rule. You can also set the width and spacing for
each edge individually.

Following the above example:

create_pg_region r1 -core -exclude_macros {u_one u_two } -macro_offset 5.0

create_pg_ring_pattern ring1 -horizontal_layer M5 -vertical_layer M4 -horizontal_width

2.0 -vertical_width 2.0

set_pg_strategy s1 -pg_regions {r1} -pattern { {name: ring1} {nets:{vdd vss}} }

compile_pg -strategies s1

9/21
pattern also has the extended usage of blockage, parameters, and extension, which
represent shielding, parameters, and extension respectively. The usage can be seen in the
following example:

create_pg_ring_pattern ring1 -parameters {hw vw} -horizontal_layer M5 -vertical_layer

M4 -horizontal_width {@hw} -vertical_width {@vw} : #@hw and @vw are parameters,
which need to be declared with parameters in pg strategy.

set_pg_strategy s2 -pg_regions {r1} -blockage {voltage_areas: r2} -pattern { {name:

ring1} {nets: {vdd vss}} {parameters:{3 2}} {offset: {4 2}} {skip_sides: 1 } } -extension {
{side: 2 6} {direction: L} {stop: outermost_ring} } ;#blockage means to shield voltage
area r2, extension means to extend, and side specifies that the leftmost side is side 1.

10/21
2.3 PG Mesh
The pg mesh pattern usage process is as follows:

11/21
create_pg_mesh_pattern mesh1 \

-layers { { {horizontal_layer: M5} {width: 6} {spacing: 1} {pitch: 12} {offset: 5} } {

{vertical_layer: M6} {width: 6} {spacing: 2} {pitch: 20} {offset: 6} } } \

-via_rule { { {layers: M5} {layers: M6} {via_master: VIA56_2x3} } }

2.4 Define Custom PG Vias

12/21
set_pg_via_master_rule VIA36_2x3 -contact_code {VIA34SQ VIA45SQ VIA56QS} -
via_array_dimension {2 3} -offset {0.4 0.2} -offset_start center (default) -cut_spacing
{0.2 0.1}

2.5 Define Via Rule between Objects

Set the via rule to connect different strategy straps or strategies with existing shapes.

#let _ Holes are punched between M2 and M7 of the two strategies. If you
don’t want them to punch via master, you can write "NIL".

If set_pg_strategy_via_rule is not used or compile_pg does not use the -via_rule option,
via will be inserted on all intersecting shapes of different layers of the same pg net.

If you only want to use one via rule strategy, you can use the compile_pg -via_rule
rule_name option.

13/21
2.6 Standard Cell Connection Pattern

create_pg_std_cell_conn_pattern std_pat1 -layers {M1}

set_pg_strategy S_std_cells -core   -pattern { {{name: std_pat1} {nets: {VDD VSS}} }   -

extension {{stop: innermost_ring}}

compile_pg –strategies S_std_cells 

2.7 Macro Connections

The pg mesh solution for connecting macro pins.

create_pg_macro_conn_pattern

14/21
Three modes controlled by -pin_conn_type

1) scattered_pin

Extend the irregular pg pin to the external pg mesh.

create_pg_macro_conn_pattern P_HM_pins \

-pin_conn_type scattered_pin -layers {M4 M5}

set_pg_strategy S_HM_pins -macros $hardmacros \

-pattern { {pattern: P_HM_pin} {nets: {VSS VDD}}}

compile_pg -strategies {S_HM_ring S_HM_pins}

 2) long_pin

The pg pin is long, and the pg mesh intersects with the pg pin.

create_pg_macro_conn_pattern macro_long_pins \

-pin_conn_type long_pin \

-direction vertical \

15/21
-spacing interleaving \

-pitch $M5_pitch \

-width $M5_width \

-layers M5

set macros [get_cells -hier -filter "is_hard_macro"]

set_pg_strategy S_macros -macros $macros \

-pattern { {name: macro_long_pins} {nets: VDD VSS} }

3) ring_pin

16/21
The ring pin inside the macro, the finger is connected to the strap or macro ring.

3.Apply the PG Strategies

1) Ignore drc in the test phase

compile_pg -strategies s1 -ignore_drc

2) Check mesh, remove mesh

compile_pg -undo

3) Finally adjust the strategies

compile_pg -strategies s1 

compile_pg -strategies {s1 s2} -via_rule v1

3.1 Report of Missing Vias Due to DRC

If the via is not inserted because of the drc problem, you can use compile_pg to report

compile_pg -show_phantom

3.2 Specify Block-Level Power Nets

The pg net department created by PNS is directly applied to the top level. For example, to
specify pg strategies for a block, you need to give its complete hierarchy name.

set_pg_strategy s_top \

–blocks I_TOP/I_SWITCHED \

-pattern {{name: sw_strap} {nets: {I_TOP/I_SWITCHED/VDD_SW}} } 

17/21
If -block is not specified, then I_TOP/I_SWITCHED/VDD_SW will be a dummy net at
the top. To avoid this problem you need pg characterize.

3.3 Characterize Block PG Flow

1) Design input

Define the pg constraints of the full chip.

2) Characterize Block PG

characterize_block_pg: Extract top level and pg constraints of each block.

3) Create PG for each block and top level

Apply pg constraints compile pg.

4.Insert Special Cells

4.1 Boundary Cell

Add boundary cells to the inner or outer corners of the boundary/macro/blockage/voltage
area.

18/21
 For example, add boundary Cell to the block. By default, only the top level is added.

4.2 Tap Cell

Add tap cells to block level and top level.

19/21
Among them, the stagger is in a staggered form as shown in the figure above, which is
generally applied in this form, which can reduce the number of tap cells.

5.Insert Power Switch

Turning off the power domain/block can save leakage. The power switch is added between
the main supply and the switched supply that can be turned off, and the swtitched supply
is connected to the power rail of the standard cell.

According to the power/ground cutoff, it can be divided into the Header type that cuts off
the power and the Footer type that cuts off the ground. The former uses pmos transistors
of the same size and has lower leakage, and the latter uses nmos transistors, which tend to
have smaller ir drop and area. .

An example of use is as follows:

In terms of placement, the switch cell is mostly placed under the strap of the main supply
to facilitate punching and connection.

20/21
The sleep signal connection method mostly adopts the daisy chain method, besides, there
are two forms of hfn and fishbone.

Examples are as follows:

connect_power_switch -mode fishbone \

 -direction horizontal -start_point lower_left

6.PG Verification and Analysis

1) check_pg_drc

Check for DRC issues that violate the technology design rule.

2) check_pg_missing_vias

Check the pg network missing via problem.

3) check_pg_connectivity

Check the connection of pg pin/shape/via (floating)

21/21