REG2REG DESIGN FLOW

SYNTHESIS:

• It is the process of converting RTL code (high level description language) into gate level
netlist (circuit in terms of logic gates) with all constrains (sdc) as specified by the
designer.

• Converts abstract of design to proper implemented chip in terms of logic gates.

• This process takes in multiple steps:

I. Converting RTL into simple logic gates.
II. Mapping those gates to actual technology dependent logic gates available in the
technology library files.
III. Optimizing mapping netlist keeping the constrains set by designer intact.
Types of synthesis:
• Logical synthesis.
• Physical synthesis.
EDA TOOLS:

• Synopsys:

dc compiler used for Synthesis

ICC used for PNR

prime time used for STA

• Cadence:

geneus used for synthesis.

Innovus used for PNR.

Tempus used for STA.

Logical synthesis:
In this type of synthesis, we have logical level conversion to circuit level without any physical
inputs. we don’t have much info about the physical parameters and appearance of the design.

Inputs to Logical synthesis:

• RTL: HDL files

• .tf (Technology File)

• .lib/.db (Library of Standard Cell and Macros)

• SDC

• UPF (unified power format)

• ScanDEF

Outputs from Logical synthesis:

• SDC

• Optimized Gate Level Netlist

• UPF

• ScanDEF

Register Transfer Level V/S Gate Level Netlist:

REGISTER TRANSFER LEVEL GATE LEVEL NETLIST

Functionality of device written in Netlist refers to the actual implementation

language like Verilog, VHDL of a particular logic design and its
interconnections

Data is transferred between registers/flip Netlist is gate level description of device.

flops.
 RTL is independent of Technology. Gate level netlist can be dependant on
technology.

PROJECT:

We are doing a project called REG2REG.

We are doing our project on dc compiler.
To start the dc compiler we need to give the command dc_compiler in terminal.
To save the work information and to keep the data we save our work in a log file. For this we
give the command dc_compiler -output <filename.log>
After this command we enter into dc_compiler
First we need to set search path,
set search_path {path1 path2.....pathN}

• By giving paths of input files needed for synthesis the tool can take direct file name in
 the Target library, Link library and while loading RTL design

• While searching for references, after searching in the link_library, Tool searches in the
path provided here.

• If we don not give search path, we give have to mention filename along with path in
target library and link library and we lose the edge on solving references through search
path.
command :

set target_library {Technology_dependent_Libraries}

• target_library is a predefined variable, where it's purpose is to store Standard Cell

libraries.

• In this command we provide the technology dependant libraries of standard cells. We

should only provide Standard cell based Libraries only.

• Tool during mapping selects the cells and it's timing data from the library provided in this
command.

• If we do not give target_library we can not map design with technology dependant
library.
command :

set link_library {* Technology libraries, Macro libraries etc}

• link_library is a predefined variable, where it's purpose is to store Standard Cell libraries,
Macro Libraries etc.

• For unresolved references in the design we use link library. All the references in the
design must be linked.

• While resolving Tool resolves from left to right. The aesterisk in the Link library
searches for references in the memory of tool and then searches by the libraries provided
in the command.

• Even after this if there are still unresolved libraries, the tool searches for references from
the search_path.

• If we do not give Link Library the unresolved references in the design cannot be
 resolved.
command :

analyze <switch> <RTL file>

• analyze command has multiple switches. Of those we use -format verilog.

• so the command goes like analyze -format verilog reg2reg.v

• This command loads the RTL design and checks for any syntax errors in it.

• If errors are present it throws 0 else loads the design successfully.

• It also creates Intermediate files required while elaborate.

• Throws a warning if we did not give target or link libraries.

command :

elaborate <top_module name>

• First we need to know the top module name. For that we need to check the design file.
The command then goes as elaborate reg2reg

• This command translates the design with Gtech Libraries, SymbolWare libraries and
HDL operators with Design Ware components.

• Throws a warning if we did not give target or link libraries.

command :
 • We can check this translation of design by giving command start_gui. This command
generates design based on Graphic User Interface.

compile

• This is first stage compilation. We compile our design based on Target and Link
Libraries.

• During this stage the design gets mapped with Technolnogy dependant libraries.

• While compile the design is optimized in three ways 1.Architectural Optimization

2.Logic Level Optimization 3.Gate Level Optimization.
command :
 • After optimization the structures of cells changes. We can check by command start_gui

current_design
 • By this command we can check the Name of the design.
FIND CLOCK PORTS

foreach is a loop. 'i' is the variable we are taking.

all_register -clock_pins provides all the registers's clock pins in the design.
get_object_name is used so that while foreach loop is running the selection of register's clock
pins will be taken as SEL_001. To avoid that we give this command so that it gives the object
name of SEL_001.
all_fanin -to $i -flat -startpoints_only gives fanin for the clock pins of all registers flat switch
enables tool to give fanin for all hierarchial levels and startpoints_only gives the starting of the
all the fanins
all these are set into a.
Then the a is if conditioned with llength == 1. If that conditioned is satisfied, the item is again
if conditioned with ports of inputs if that is satisfied the item is appended into variable c.
We give lsort -u $c so that multiple same elements to be avoided.
This script gives clocks in the design
To run this script we give command source ./<filename> ,the below shown figure .
command :

create_clock <switches> <port_name>

• This command enables us to create a clock to the clock port.
• we have swtiches -name -period -waveform.
• -name: we give name for our clock if we don't use this switch the clock name will be
same as port name
• -period: we give time period for our clock
 • -waveform: in this witch we can give rise and fall times.
command :

report_clocks
• Gives detailed information of created clocks.
command :

check_timing
• This command updates design information, checks generated clocks, checks loops,checks
whether input delays and output delays given or not etc inforamtion is given.
command :
set_input_delay <delay> <based on clock> <To required ports>

• This command sets input delay for the required ports.

• We need to give input delay so as to calculate timing at capture flop. We are giving some
delay at input ports so as to mention that it is taking that much time to enter capture flop.

• We give 60% of Time period of the clock as the we are taking 60% as worst case.

• -clock : We give the clock that the delay is derived from.

• all_inputs : This command gives all input ports in the design.

• we need to remove clock ports from the inputs as we don't want delay for our clocks. For
this wee use the command remove_from_collection [all_inputs] [get_ports clk].
get_ports : gives ports in the design. get_ports clk : This command specifically gives
clk port.
command :
set_output_delay <delay> <based on clock> <To required ports>

• This command sets output delay for the required ports.

• We need to give output delay so as to calculate timing at capture flop. We are giving
some delay at output ports so as to mention that it is taking that much time to enter
capture flop.

• We give 60% of Time period of the clock as the we are taking 60% as worst case.

• -clock : We give the clock that the delay is derived from.

• all_outputs : This command gives all output ports in the design.

• Unlike set_input_delay we need not remove clock ports as there will be no clock ports in
output ports. If at all there is clock ports we need to remove clock ports.
command :

check_timing
command :

• once it shows no warnings we can move to next stage.

filter_collection <collection> <"filter expression">
• This command fiters out the collection based upon filter expression.
command :

• By the above command we wanted to see any ports that are directly connected to inputs
or outputs. Apparently we don't have such type in our design. So wee need not give input
delay based on virtual clock.
group_path <name> <from> <to> <weight>
• This command groups the path from a point to another point
• We can give weight to the path so that the tool optimizes the path better. The
optimization depends on the weight that is given.
• -name : Gives the name of the path.
• -from : Specifies from where the path should start
• -to : Specifies to where the path should end
• -weight : valued from 1 to 100. The value determines the optimization. Greater the value
better the optimization.
command :

set_clock_uncertainity <uncertainity value> <setup/hold> <To required clock>

• This command helps us to set uncertainity factor to clocks.
• We set uncertainty to clock so as to maintain practicality as there could be
jitter,skew,noice these factors could increase delay.
• We generally take 20% of timeperiod for setup and 15% of timeperiod to hold. 5% lesser
for hold as jitter is not present for hold.
command :
set_driving_cell <lib_cell name> <required_ports>
• This command is used to apply attributes of a particular driving cell on the input or inout
ports.
• Driving cell propogates quality of signal.
• With change in transition time of driving cell there would be change in the transition time
to be applied.
• While selecting driving cell we need to have idea about drive strength of cell.
• In the command i took buffer with strength of 8. Which means that the buffer can pass 8
times of load current.
• This strength of driving cell determines the delay. If buffer has more driving strength the
delay would be less. But with increase in drive strength power and area gets effected.
• -lib_cell : We provide the standard cell name of driving cell.
command :

• -no_design_rule : This switch can be used to apply only timing attributes rather than all
the attributes of cell.

set_load <value> <required_ports>

• This command enables us to apply load at the output side of the design.
• Load is nothing but capacitance. We are taking capacitance of the same driving cell
applied at the inputs.
• We can take any values but to be more practical we took that driving cell's input
capacitance value. As the outputs are connected to next cell input we take it's input
capacitance.
command :

• The value above is the max capacitance of the driving cell we have taken.
2nd compilation

• We again compile so as to tool to optimize as per our constarints.

report_timing <switches>

• Report timing command gives the report based on start and endpoints.

• Report timing gives the worst path report. It gives the complete timing information of the
path.

• There are multiple switches in this command some frequently used are

• -capacitance : Gives the capacitance value applied

• -transition_time : Reports the Tansition time taken.

• -input_pins : Gives the input pins in the path.

• -nets : Gives nets in the path.

• -significant_digits : We specify the number so that the report gives numbers in order of
provided digits.

• -nworst : We specify no.of worst paths needed to be displayed.

command :
• Here we can see that at the end of Timing report, The slack is MET.

• Setup_Slack = Required_Time - Arrival_Time.

• In the report, startpoint and endpoint is mentioned and Path group is also mentioned. If
we did not give Group path, The path group is taken by capture clock name.

• Arrival Time in the report should be read from start of the report to till data arrival time.

• Required Time in the report should be read from after data arrival time to data required
time.
• As Required time is greater than Arrival time the setup slack is met.

• The Setup Slack for this path is also met.

 • The SetupSlack for this path is Met with more positive slack.

• As the slack is more we can decrease the Required time for this path as a result the path
operates at higher frequency.

report_qor

• Gives Quality of results information and statistics of Current Design.

command :
• We can see from QOR there are no violating paths from Setup
• But there is a violating path from hold perspective.
• So to see that report we give report_timing -delay_type min. This command gives
report in Hold perspective.
command :

• Here we can see that at the end of Timing report, The slack is VIOLATED.

• Hold_Slack = Arrival_Time - Required_Time.

• In the report, startpoint and endpoint is mentioned and Path group is also mentioned. If
we did not give Group path, The path group is taken by capture clock name.

• Arrival Time in the report should be read from start of the report to till data arrival time.

• Required Time in the report should be read from after data arrival time to data required
time.
 • As Required time is greater than Arrival time the setup slack is violated.

write_sdc <filename.extension>
• Writes out a file containing sdc constraints that were given in the design.
command :
write_file <switches> <filename.extension>
• This command is used to write the gated level netlist into a file.
• -format : Specifies in which format we need to write the file.
• -output : Specifying the output file.
command: