CODING :

VHDL code for Buffer :

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bf is Port ( a : in STD_LOGIC_VECTOR(31 downto 0); b : out STD_LOGIC_VECTOR(31 downto 0)); end bf; architecture Behavioral of bf is begin b<= a; end Behavioral;

VHDL code for Not gate :

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nt is Port ( a : in STD_LOGIC_VECTOR(31 downto 0); b : out STD_LOGIC_VECTOR(31 downto 0)); end nt; architecture Behavioral of nt is begin b<= not a;

end Behavioral;

VHDL code for And gate :

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity lnd is Port ( a : in STD_LOGIC_VECTOR(31 downto 0); b : in STD_LOGIC_VECTOR(31 downto 0); c : out STD_LOGIC_VECTOR(31 downto 0)); end lnd; architecture Behavioral of lnd is begin c<= a and b; end Behavioral;

VHDL code for Nand gate :

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nd is Port ( a : in STD_LOGIC_VECTOR(31 downto 0); b : in STD_LOGIC_VECTOR(31 downto 0);

c : out STD_LOGIC_VECTOR(31 downto 0)); end nd; architecture Behavioral of nd is begin c<= a nand b; end Behavioral;

VHDL code for Or gate :

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity orl is Port ( a : in STD_LOGIC_VECTOR(31 downto 0); b : in STD_LOGIC_VECTOR(31 downto 0); c : out STD_LOGIC_VECTOR(31 downto 0)); end orl; architecture Behavioral of orl is begin c<= a or b; end Behavioral;

VHDL code for Nor gate :

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nr is Port ( a : in STD_LOGIC_VECTOR(31 downto 0); b : in STD_LOGIC_VECTOR(31 downto 0); c : out STD_LOGIC_VECTOR(31 downto 0)); end nr; architecture Behavioral of nr is begin c<= a nor b; end Behavioral;

VHDL code for Xor gate :

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xr is Port ( a : in STD_LOGIC_VECTOR(31 downto 0); b : in STD_LOGIC_VECTOR(31 downto 0); c : out STD_LOGIC_VECTOR(31 downto 0)); end xr; architecture Behavioral of xr is begin c<= a xor b;

end Behavioral;

VHDL code for Xnor gate :

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xnr is Port ( a : in STD_LOGIC_VECTOR(31 downto 0); b : in STD_LOGIC_VECTOR(31 downto 0); c : out STD_LOGIC_VECTOR(31 downto 0)); end xnr; architecture Behavioral of xnr is begin c<= a xnor b; end Behavioral;

VHDL code for Right Shift :

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity shift is Port ( a : in STD_LOGIC_VECTOR(31 downto 0); b : out STD_LOGIC_VECTOR(31 downto 0)); end shift;

architecture Behavioral of shift is begin b<=('0'& a(31 downto 1)); end Behavioral;

VHDL code for Left Shift :

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity l_shift is Port ( a : in STD_LOGIC_VECTOR(31 downto 0); b : out STD_LOGIC_VECTOR(31 downto 0)); end l_shift; architecture Behavioral of l_shift is begin b<=(a(30 downto 0) & '0'); end Behavioral;

VHDL code for Right Rotate :

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity cir is Port ( a : in STD_LOGIC_VECTOR(31 downto 0); b : out STD_LOGIC_VECTOR(31 downto 0));

end cir; architecture Behavioral of cir is begin b<=(a(0)&a(31 downto 1)); end Behavioral;

VHDL code for Left Rotate :

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity lft is Port ( a : in STD_LOGIC_VECTOR(31 downto 0); b : out STD_LOGIC_VECTOR(31 downto 0)); end lft; architecture Behavioral of lft is begin b<=(a(30 downto 0)&a(31)); end Behavioral;

VHDL code for Adder : 1-Bit Adder :

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity a11 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; cin : in STD_LOGIC; cout : out STD_LOGIC; sum : out STD_LOGIC); end a11; architecture Behavioral of a11 is begin process(a,b,cin) begin sum <= a xor b xor cin; cout <= (a and b) or (b and cin) or (a and cin); end process; end Behavioral;

4-Bit Adder :
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity aw12 is Port ( a : in STD_LOGIC_vector(3 downto 0); b : in STD_LOGIC_vector(3 downto 0); cin : in STD_LOGIC; cout : out STD_LOGIC; sum : out STD_LOGIC_vector(3 downto 0)); end aw12; architecture Behavioral of aw12 is

component a11 port ( a : in STD_LOGIC; b : in STD_LOGIC; cin : in STD_LOGIC; cout : out STD_LOGIC; sum : out STD_LOGIC); end component ; for u1,u2,u3,u4 : a11 use entity a11(Behavioral); signal t: STD_LOGIC_vector(2 downto 0); begin u1 : a11 port map (a=>a(0),b=>b(0),cin=>cin,cout=>t(0),sum=>sum(0)); u2 : a11 port map (a=>a(1),b=>b(1),cin=>t(0),cout=>t(1),sum=>sum(1)); u3 : a11 port map (a=>a(2),b=>b(2),cin=>t(1),cout=>t(2),sum=>sum(2)); u4 : a11 port map (a=>a(3),b=>b(3),cin=>t(2),cout=>cout,sum=>sum(3)); end Behavioral;

32- Bit Adder :

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity a13 is Port ( a : in STD_LOGIC_VECTOR(31 downto 0); b : in STD_LOGIC_VECTOR(31 downto 0); cin : in STD_LOGIC; sum : out STD_LOGIC_VECTOR(31 downto 0); cout : out STD_LOGIC); end a13; architecture Behavioral of a13 is

component aw12 port ( a : in STD_LOGIC_vector(3 downto 0); b : in STD_LOGIC_vector(3 downto 0); cin : in STD_LOGIC; cout : out STD_LOGIC; sum : out STD_LOGIC_vector(3 downto 0)); end component; for u1,u2,u3,u4,u5,u6,u7,u8 : aw12 use entity aw12(Behavioral); signal t: STD_LOGIC_vector(6 downto 0); begin u1 : aw12 port map (a=>a(3 downto 0),b=>b(3 downto 0), cin=>cin,cout=>t(0),sum=>sum(3 downto 0)); u2 : aw12 port map (a=>a(7 downto 4),b=>b(7 downto 4), cin=>t(0),cout=>t(1),sum=>sum(7 downto 4)); u3 : aw12 port map (a=>a(11 downto 8),b=>b(11 downto 8), cin=>t(1),cout=>t(2),sum=>sum(11 downto 8)); u4 : aw12 port map (a=>a(15 downto 12),b=>b(15 downto 12), cin=>t(2),cout=>t(3),sum=>sum(15 downto 12)); u5 : aw12 port map (a=>a(19 downto 16),b=>b(19 downto 16), cin=>t(3),cout=>t(4),sum=>sum(19 downto 16)); u6 : aw12 port map (a=>a(23 downto 20),b=>b(23 downto 20), cin=>t(4),cout=>t(5),sum=>sum(23 downto 20)); u7 : aw12 port map (a=>a(27 downto 24),b=>b(27 downto 24), cin=>t(5),cout=>t(6),sum=>sum(27 downto 24)); u8 : aw12 port map (a=>a(31 downto 28),b=>b(31 downto 28), cin=>t(6),cout=>cout,sum=>sum(31 downto 28)); end Behavioral;

VHDL code for Subtractor : 1-Bit Subtractor :

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity s1 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; cin : in STD_LOGIC; diff : out STD_LOGIC; bor : out STD_LOGIC); end s1; architecture Behavioral of s1 is begin process(a,b,cin) begin diff <= a xor b xor cin; bor <= ((not a) and b) or (b and cin) or ((not a) and cin); end process; end Behavioral;

4-Bit Subtractor :
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity s2 is Port ( a : in STD_LOGIC_vector(3 downto 0); b : in STD_LOGIC_vector(3 downto 0);

cin : in STD_LOGIC; diff : out STD_LOGIC_vector(3 downto 0); bor : out STD_LOGIC); end s2; architecture Behavioral of s2 is component s1 Port ( a : in STD_LOGIC; b : in STD_LOGIC; cin : in STD_LOGIC; diff : out STD_LOGIC; bor : out STD_LOGIC); end component ; for u1,u2,u3,u4 : s1 use entity s1(Behavioral); signal t: STD_LOGIC_vector(2 downto 0); begin u1 : s1 port map (a=>a(0),b=>b(0),cin=>cin,bor=>t(0),diff=>diff(0)); u2 : s1 port map (a=>a(1),b=>b(1),cin=>t(0),bor=>t(1),diff=>diff(1)); u3 : s1 port map (a=>a(2),b=>b(2),cin=>t(1),bor=>t(2),diff=>diff(2)); u4 : s1 port map (a=>a(3),b=>b(3),cin=>t(2),bor=>bor,diff=>diff(3)); end Behavioral;

32-Bit Subtractor :
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity s33 is Port ( a : in STD_LOGIC_VECTOR(31 downto 0); b : in STD_LOGIC_VECTOR(31 downto 0);

cin : in STD_LOGIC; diff : out STD_LOGIC_VECTOR(31 downto 0); bor : out STD_LOGIC); end s33; architecture Behavioral of s33 is component s2 Port ( a : in STD_LOGIC_vector(3 downto 0); b : in STD_LOGIC_vector(3 downto 0); cin : in STD_LOGIC; diff : out STD_LOGIC_vector(3 downto 0); bor : out STD_LOGIC); end component; for u1,u2,u3,u4,u5,u6,u7,u8 : s2 use entity s2(Behavioral); signal t: STD_LOGIC_vector(6 downto 0); begin u1 :s2 port map (a=>a(3 downto 0),b=>b(3 downto 0), cin=>cin,bor=>t(0),diff=>diff(3 downto 0)); u2 :s2 port map (a=>a(7 downto 4),b=>b(7 downto 4), cin=>t(0),bor=>t(1),diff=>diff(7 downto 4)); u3 :s2 port map (a=>a(11 downto 8),b=>b(11 downto 8), cin=>t(1),bor=>t(2),diff=>diff(11 downto 8)); u4 :s2 port map (a=>a(15 downto 12),b=>b(15 downto 12), cin=>t(2),bor=>t(3),diff=>diff(15 downto 12)); u5 :s2 port map (a=>a(19 downto 16),b=>b(19 downto 16), cin=>t(3),bor=>t(4),diff=>diff(19 downto 16)); u6 :s2 port map (a=>a(23 downto 20),b=>b(23 downto 20), cin=>t(4),bor=>t(5),diff=>diff(23 downto 20)); u7 :s2 port map (a=>a(27 downto 24),b=>b(27 downto 24),

cin=>t(5),bor=>t(6),diff=>diff(27 downto 24)); u8 :s2 port map (a=>a(31 downto 28),b=>b(31 downto 28), cin=>t(6),bor=>bor,diff=>diff(31 downto 28)); end Behavioral;

VHDL code for Comparator :

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity cmn is Port ( a : in STD_LOGIC_VECTOR(31 downto 0); b : in STD_LOGIC_VECTOR(31 downto 0); c : out STD_LOGIC_VECTOR(3 downto 0)); end cmn; architecture Behavioral of cmn is component s33 port(a,b : in STD_LOGIC_VECTOR(31 downto 0); cin :in STD_LOGIC; diff : out STD_LOGIC_VECTOR(31 downto 0); bor :out STD_LOGIC ); end component; signal s : STD_LOGIC_VECTOR(31 downto 0); signal bout : STD_LOGIC; begin u1 : s33 port map (a,b,'0',s,bout); process(s,bout) begin if s="00000000000000000000000000000000" then

if bout= '0' then c<="000"&'1'; end if; else if bout= '0' then c<="00"&'1'&'0'; end if; if bout= '1' then c<='0'&'1'&"00"; end if; end if; end process; end Behavioral;

VHDL code for Multiplier : 1-Bit And gate :

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity lnd1 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end lnd1; architecture Behavioral of lnd1 is begin

c<= a and b; end Behavioral;

32-Bit Multiplier :
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mul1 is port (a,b:in std_logic_vector(31 downto 0); mul:out std_logic_vector(63 downto 0)); end mul1; architecture behavioral of mul1 is component a13 is port (a,b:in std_logic_vector(31 downto 0); cin:in std_logic; sum:out std_logic_vector(31 downto 0); cout:out std_logic); end component; component lnd1 is port (a,b:in std_logic; c:out std_logic); end component; signal s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,s20,s21,s22,s23, s24,s25,s26,s27,s28,s29,s30,s31,s32:std_logic_vector(31 downto 0); signalc1,d1,c2,d2,c3,d3,c4,d4,c5,d5,c6,d6,c7,d7,c8,d8,c9,d9,c10,d10,c11,d11,c12,d12,c13 ,d13,c14,d14,c15,d15,c16,d16,c17,d17,c18,d18,c19,d19,c20,d20,c21,d21,c22,d22,c23,d23 ,c24,d24,c25,d25,c26,d26,c27,d27,c28,d28,c29,d29,c30,d30,c31,d31:std_logic_vector(31

downto 0); signal co:std_logic_vector(30 downto 0); begin u0:for i in 0 to 31 generate u1:lnd1 port map(a(0),b(i),s1(i)) ; u2:lnd1 port map(a(1),b(i),s2(i)) ; u3:lnd1 port map(a(2),b(i),s3(i)) ; u4:lnd1 port map(a(3),b(i),s4(i)) ; u5:lnd1 port map(a(4),b(i),s5(i)) ; u6:lnd1 port map(a(5),b(i),s6(i)) ; u7:lnd1 port map(a(6),b(i),s7(i)) ; u8:lnd1 port map(a(7),b(i),s8(i)) ; u9:lnd1 port map(a(8),b(i),s9(i)) ; u10:lnd1 port map(a(9),b(i),s10(i)) ; u11:lnd1 port map(a(10),b(i),s11(i)) ; u12:lnd1 port map(a(11),b(i),s12(i)) ; u13:lnd1 port map(a(12),b(i),s13(i)) ; u14:lnd1 port map(a(13),b(i),s14(i)) ; u15:lnd1 port map(a(14),b(i),s15(i)) ; u16:lnd1 port map(a(15),b(i),s16(i)) ; u17:lnd1 port map(a(16),b(i),s17(i)) ; u18:lnd1 port map(a(17),b(i),s18(i)) ; u19:lnd1 port map(a(18),b(i),s19(i)) ; u20:lnd1 port map(a(19),b(i),s20(i)) ; u21:lnd1 port map(a(20),b(i),s21(i)) ; u22:lnd1 port map(a(21),b(i),s22(i)) ; u23:lnd1 port map(a(22),b(i),s23(i)) ;

u24:lnd1 port map(a(23),b(i),s24(i)) ; u25:lnd1 port map(a(24),b(i),s25(i)) ; u26:lnd1 port map(a(25),b(i),s26(i)) ; u27:lnd1 port map(a(26),b(i),s27(i)) ; u28:lnd1 port map(a(27),b(i),s28(i)) ; u29:lnd1 port map(a(28),b(i),s29(i)) ; u30:lnd1 port map(a(29),b(i),s30(i)) ; u31:lnd1 port map(a(30),b(i),s31(i)) ; end generate; c1<= '0' & s1(31 downto 1); v1:a13 port map(c1,s2,'0',d1,co(0)); c2<= co(0) & d1(31 downto 1); v2:a13 port map(c2,s3,'0',d2,co(1)); c3<= co(1) & d2(31 downto 1); v3:a13 port map(c3,s4,'0',d3,co(2)); c4<= co(2) & d3(31 downto 1); v4:a13 port map(c4,s5,'0',d4,co(3)); c5<= co(3) & d4(31 downto 1); v5:a13 port map(c5,s6,'0',d5,co(4)); c6<= co(4) & d5(31 downto 1); v6:a13 port map(c6,s7,'0',d6,co(5)); c7<= co(5) & d6(31 downto 1); v7:a13 port map(c7,s8,'0',d7,co(6)); c8<= co(6) & d7(31 downto 1); v8:a13 port map(c8,s9,'0',d8,co(7)); c9<= co(7) & d8(31 downto 1); v9:a13 port map(c9,s10,'0',d9,co(8));

c10<= co(8) & d9(31 downto 1); v10:a13 port map(c10,s11,'0',d10,co(9)); c11<= co(9) & d10(31 downto 1); v11:a13 port map(c11,s12,'0',d11,co(10)); c12<= co(10) & d11(31 downto 1); v12:a13 port map(c12,s13,'0',d12,co(11)); c13<= co(11) & d12(31 downto 1); v13:a13 port map(c13,s14,'0',d13,co(12)); c14<= co(12) & d13(31 downto 1); v14:a13 port map(c14,s15,'0',d14,co(13)); c15<= co(13) & d14(31 downto 1); v15:a13 port map(c15,s16,'0',d15,co(14)); c16<= co(14) & d15(31 downto 1); v16:a13 port map(c16,s17,'0',d16,co(15)); c17<= co(15) & d16(31 downto 1); v17:a13 port map(c17,s18,'0',d17,co(16)); c18<= co(16) & d17(31 downto 1); v18:a13 port map(c18,s19,'0',d18,co(17)); c19<= co(17) & d18(31 downto 1); v19:a13 port map(c19,s20,'0',d19,co(18)); c20<= co(18) & d19(31 downto 1); v20:a13 port map(c20,s21,'0',d20,co(19)); c21<= co(19) & d20(31 downto 1); v21:a13 port map(c21,s22,'0',d21,co(20)); c22<= co(20) & d21(31 downto 1); v22:a13 port map(c22,s23,'0',d22,co(21)); c23<= co(21) & d22(31 downto 1);

v23:a13 port map(c23,s24,'0',d23,co(22)); c24<= co(22) & d23(31 downto 1); v24:a13 port map(c24,s25,'0',d24,co(23)); c25<= co(23) & d24(31 downto 1); v25:a13 port map(c25,s26,'0',d25,co(24)); c26<= co(24) & d25(31 downto 1); v26:a13 port map(c26,s27,'0',d26,co(25)); c27<= co(25) & d26(31 downto 1); v27:a13 port map(c27,s28,'0',d27,co(26)); c28<= co(26) & d27(31 downto 1); v28:a13 port map(c28,s29,'0',d28,co(27)); c29<= co(27) & d28(31 downto 1); v29:a13 port map(c29,s30,'0',d29,co(28)); c30<= co(28) & d29(31 downto 1); v30:a13 port map(c30,s31,'0',d30,co(29)); c31<= co(29) & d30(31 downto 1); v31:a13 port map(c31,s32,'0',d31,co(30)); mul<=co(30)&d31&d30(0)&d29(0)&d28(0)&d27(0)&d26(0)&d25(0)&d24(0)&d23(0)& d22(0)&d21(0)&d20(0)&d19(0)&d18(0)&d17(0)&d16(0)&d15(0)&d14(0)&d13(0)&d12( 0)&d11(0)&d10(0)&d9(0)&d8(0)&d7(0)&d6(0)&d5(0)&d4(0)&d3(0)&d2(0)&d1(0)&s1( 0); end behavioral;

VHDL coding for ALU :

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL; entity alu is Port ( a : in STD_LOGIC_VECTOR(31 downto 0); b : in STD_LOGIC_VECTOR(31 downto 0); sel : in std_logic_vector(3 downto 0); cin : in STD_LOGIC; result : out STD_LOGIC_VECTOR(31 downto 0); r : out std_logic_vector(3 downto 0); cout : out STD_LOGIC); end alu; architecture Behavioral of alu is component a13 Port ( a : in STD_LOGIC_VECTOR(31 downto 0); b : in STD_LOGIC_VECTOR(31 downto 0); cin : in STD_LOGIC; sum : out STD_LOGIC_VECTOR(31 downto 0); cout : out STD_LOGIC); end component; for u1 : a13 use entity a13(Behavioral); component s33 Port ( a : in STD_LOGIC_VECTOR(31 downto 0); b : in STD_LOGIC_VECTOR(31 downto 0); cin : in STD_LOGIC; diff : out STD_LOGIC_VECTOR(31 downto 0); bor : out STD_LOGIC); end component;

for u2 : s33 use entity s33(Behavioral); component l_shift Port ( a b : in : out std_logic_vector ( 31 DOWNTO 0); std_logic_vector ( 31 DOWNTO 0));

end component; for u3 : l_shift use entity l_shift(Behavioral); component shift Port ( a b : in : out std_logic_vector ( 31 DOWNTO 0); std_logic_vector ( 31 DOWNTO 0));

end component; for u4 :shift use entity shift (Behavioral); component orl Port ( a b c : in : in : out std_logic_vector ( 31 DOWNTO 0); std_logic_vector ( 31 DOWNTO 0); std_logic_vector ( 31 DOWNTO 0));

end component; for u5 : orl use entity orl(Behavioral); component nr Port ( a b c : in : in : out std_logic_vector ( 31 DOWNTO 0); std_logic_vector ( 31 DOWNTO 0); std_logic_vector ( 31 DOWNTO 0));

end component; for u6 : nr

use entity nr(Behavioral); component nd Port ( a : in STD_LOGIC_vector(31 downto 0); b : in STD_LOGIC_vector(31 downto 0); c : out STD_LOGIC_vector(31 downto 0)); end component; for u7 : nd use entity nd(Behavioral); component lnd Port ( a : in STD_LOGIC_vector(31 downto 0); b : in STD_LOGIC_vector(31 downto 0); c : out STD_LOGIC_vector(31 downto 0)); end component; for u8 : lnd use entity lnd(Behavioral); component nt Port ( a b : in : out std_logic_vector ( 31 DOWNTO 0); std_logic_vector ( 31 DOWNTO 0));

end component; for u9 : nt use entity nt(Behavioral); component xr Port ( a : in STD_LOGIC_vector(31 downto 0); b : in STD_LOGIC_vector(31 downto 0); c : out STD_LOGIC_vector(31 downto 0)); end component; for u10 : xr

use entity xr(Behavioral); component xnr Port ( a : in STD_LOGIC_vector(31 downto 0); b : in STD_LOGIC_vector(31 downto 0); c : out STD_LOGIC_vector(31 downto 0)); end component; for u11 : xnr use entity xnr(Behavioral); component cir Port ( a b : in : out std_logic_vector ( 31 DOWNTO 0); std_logic_vector ( 31 DOWNTO 0));

end component; for u12 : cir use entity cir(Behavioral); component lft Port ( a b : in : out std_logic_vector ( 31 DOWNTO 0); std_logic_vector ( 31 DOWNTO 0));

end component; for u13 : lft use entity lft(Behavioral); component cmn Port ( a : in STD_LOGIC_vector(31 downto 0); b : in STD_LOGIC_vector(31 downto 0); c : out STD_LOGIC_vector(3 downto 0)); end component; for u14 : cmn use entity cmn(Behavioral);

component mul1 Port( a : in STD_LOGIC_vector(31 downto 0); b : in STD_LOGIC_vector(31 downto 0); mul : out STD_LOGIC_vector(31 downto 0)); end component; for u15 : mul1 use entity mul1(Behavioral); component bf Port ( a b : in : out std_logic_vector ( 31 DOWNTO 0); std_logic_vector ( 31 DOWNTO 0));

end component; for u16 : bf use entity bf(Behavioral); signal ta,tb : std_logic ; signal t1,t2,t3,t4,t5,t6,t7,t8,t9,t10,t11,t12,t13,t16: STD_LOGIC_vector(31 downto 0); signal t14: std_logic_vector(3 downto 0); signal t15: std_logic_vector(63 downto 0); begin u1 : a13 port map (a=>a,b=>b,cin=>cin,cout=>ta,sum=>t1); u2 : s33 port map (a=>a,b=>b,cin=>cin,bor=>tb,diff=>t2); u3 : l_shift port map (a=>a,b=>t3); u4 : shift port map (a=>a,b=>t4); u5 : orl port map (a=>a,b=>b,c=>t5); u6 : nr port map (a=>a,b=>b,c=>t6); u7 : nd port map (a=>a,b=>b,c=>t7); u8 : lnd port map (a=>a,b=>b,c=>t8); u9 : nt port map (a=>a,b=>t9);

u10 : xr port map (a=>a,b=>b,c=>t10); u11 : xnr port map (a=>a,b=>b,c=>t11); u12 :cir port map (a=>a,b=>t12); u13 : lft port map (a=>a,b=>t13); u14 : cmn port map (a=>a,b=>b,c=>t14); u15 : mul1 port map (a=>a,b=>b,mul=>t15); u16 : bf port map(a=>a,b=>t16); process(sel) begin case sel is when "0000"=>result<=t16; when "0001" =>result<=t9; when "0010" =>result<=t8; when "0011" =>result<=t7; when "0100" =>result<=t5; when "0101" =>result<=t6; when "0110" =>result<=t10; when "0111" =>result<=t11; when "1000" =>result<=t4; when "1001" =>result<=t3; when "1010" =>result<=t12; when "1011" =>result<=t13; when "1100" =>result<=t1; cout<=ta; when "1101" =>result<=t2; cout<=tb; when "1110" =>r<=t14;

when 1111=>result<=t15; when others =>result<="00000000000000000000000000000000"; end case; end process; end Behavioral;