Scribd
Upload
5 views6 pages

VHDL Code

The document contains VHDL code for various digital components including a 4-to-1 multiplexer, basic logic gates, a D flip-flop, a 4-bit ripple carry adder, and a 4-bit subtractor. Each component is defined with its respective entity and architecture, detailing the inputs, outputs, and the logic operations performed. The code demonstrates fundamental digital design principles using VHDL syntax.

Uploaded by

cevase9272
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
5 views6 pages

VHDL Code

The document contains VHDL code for various digital components including a 4-to-1 multiplexer, basic logic gates, a D flip-flop, a 4-bit ripple carry adder, and a 4-bit subtractor. Each component is defined with its respective entity and architecture, detailing the inputs, outputs, and the logic operations performed. The code demonstrates fundamental digital design principles using VHDL syntax.

Uploaded by

cevase9272
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 6

1.

VHDL code for Multiplexer (MUX):


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MUX4to1 is
Port (
A, B, C, D : in STD_LOGIC; -- Inputs
S : in STD_LOGIC_VECTOR (1 downto 0); -- Select lines
Y : out STD_LOGIC -- Output
);
end MUX4to1;

architecture Dataflow of MUX4to1 is


begin
Y <= A when S = "00" else
B when S = "01" else
C when S = "10" else
D;
end Dataflow;
2. VHDL code for Basic Logic Gates:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity BasicGates is
Port (
A, B : in STD_LOGIC; -- Inputs
AND_OUT, OR_OUT : out STD_LOGIC; -- Outputs
NOT_OUT : out STD_LOGIC -- Output for NOT gate
);
end BasicGates;

architecture Behavioral of BasicGates is


begin
AND_OUT <= A AND B; -- AND Gate
OR_OUT <= A OR B; -- OR Gate
NOT_OUT <= NOT A; -- NOT Gate
end Behavioral;
3. VHDL code for Flip-Flop:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity DFlipFlop is
Port (
D, CLK : in STD_LOGIC; -- Data and Clock
Q : out STD_LOGIC; -- Output
Q_bar : out STD_LOGIC -- Complementary Output
);
end DFlipFlop;

architecture Behavioral of DFlipFlop is


begin
process (CLK)
begin
if rising_edge(CLK) then
Q <= D;
Q_bar <= NOT D;
end if;
end process;
end Behavioral;
4. VHDL code for 4-Bit Ripple Carry Adder:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FullAdder is
Port (
A, B, Cin : in STD_LOGIC; -- Inputs
Sum, Cout : out STD_LOGIC -- Outputs
);
end FullAdder;

architecture Behavioral of FullAdder is


begin
Sum <= A XOR B XOR Cin;
Cout <= (A AND B) OR (B AND Cin) OR (A AND Cin);
end Behavioral;

-- Ripple Carry Adder


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity RippleCarryAdder is
Port (
A, B : in STD_LOGIC_VECTOR(3 downto 0); -- 4-bit Inputs
Cin : in STD_LOGIC; -- Carry In
Sum : out STD_LOGIC_VECTOR(3 downto 0); -- Sum Output
Cout : out STD_LOGIC -- Carry Out
);
end RippleCarryAdder;

architecture Structural of RippleCarryAdder is


signal Carry: STD_LOGIC_VECTOR(3 downto 0);
begin
U0: entity work.FullAdder
port map (A(0), B(0), Cin, Sum(0), Carry(0));
U1: entity work.FullAdder
port map (A(1), B(1), Carry(0), Sum(1), Carry(1));
U2: entity work.FullAdder
port map (A(2), B(2), Carry(1), Sum(2), Carry(2));
U3: entity work.FullAdder
port map (A(3), B(3), Carry(2), Sum(3), Cout);
end Structural;
5. VHDL code for 4-Bit Subtractor:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Subtractor is
Port (
A, B : in STD_LOGIC_VECTOR(3 downto 0); -- Inputs
Borrow : in STD_LOGIC; -- Borrow Input
Diff : out STD_LOGIC_VECTOR(3 downto 0); -- Difference Output
Bout : out STD_LOGIC -- Borrow Output
);
end Subtractor;

architecture Dataflow of Subtractor is


begin
process (A, B, Borrow)
begin
Diff <= A - B - Borrow; -- Perform subtraction
Bout <= '1' when A < (B + Borrow) else '0';
end process;
end Dataflow;

You might also like