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CA Lab COdes

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Fardeen Ansari
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22 views11 pages

CA Lab COdes

Uploaded by

Fardeen Ansari
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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1.

Half Adder [Dataflow]


Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity HalfAdder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end HalfAdder;

architecture Dataflow of HalfAdder is

begin

sum <= a xor b;


cout <= a and b;

end Dataflow;

2. Half Adder [Structural]


Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity HalfAdderStruct is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end HalfAdderStruct;

architecture Structural of HalfAdderStruct is

component XorGate
port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end component;

component AndGate
port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end component;
begin

Xor1 : XorGate port map ( a, b, sum);


And1 : AndGate port map ( a, b, carry);

end Structural;

3. Full Adder [Structural]


Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FullAdderStruct is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end FullAdderStruct;

architecture Structural of FullAdderStruct is

component HalfAdder
port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end component;

signal s1, s2, s3 : STD_LOGIC;

begin

HalfAdder1 : HalfAdder port map ( a, b, s1, s2);


HalfAdder2 : HalfAdder port map ( s1, cin, sum, s3);
Carry <= s2 or s3;

end Structural;

4. 2 bit adder
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TwoBitAdder is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
b : in STD_LOGIC_VECTOR (1 downto 0);
sum : out STD_LOGIC_VECTOR (1 downto 0);
carry : out STD_LOGIC);
end TwoBitAdder;

architecture Dataflow of TwoBitAdder is

signal result : STD_LOGIC_VECTOR (2 downto 0);

begin

result <= ('0' & a) + ('0' & b);


sum <= result (1 downto 0);
carry <= result (2);

end Dataflow;

5. 8 bit adder
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity EightBitAdder is
Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
b : in STD_LOGIC_VECTOR (7 downto 0);
sum : out STD_LOGIC_VECTOR (7 downto 0);
carry : out STD_LOGIC);
end EightBitAdder;

architecture Dataflow of EightBitAdder is

signal result : STD_LOGIC_VECTOR (8 downto 0);

begin

result <= ('0' & a) + ('0' & b);


sum <= result (7 downto 0);
carry <= result (8);

end Dataflow;

6. 2 bit multiplication
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TwoBitMultiplication is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
b : in STD_LOGIC_VECTOR (1 downto 0);
product : out STD_LOGIC_VECTOR (3 downto 0));
end TwoBitMultiplication;

architecture Dataflow of TwoBitMultiplication is

begin

product <= a * b;

end Dataflow;

7. 8 bit multiplication
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity EightBitMultiplication is
Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
b : in STD_LOGIC_VECTOR (7 downto 0);
product : out STD_LOGIC_VECTOR (15 downto 0));
end EightBitMultiplication;

architecture Dataflow of EightBitMultiplication is

begin

product <= a * b;

end Dataflow;

8. Decoder
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Decoder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
enable : in STD_LOGIC;
z : out STD_LOGIC_VECTOR (3 downto 0));
end Decoder;

architecture Behavioral of Decoder is

begin
process (a, b, enable)
variable abar, bbar : STD_LOGIC;
begin
abar := not a;
bbar := not b;
if enable = '1' then
z(3) <= a and b;
z(2) <= a and bbar;
z(1) <= abar and b;
z(0) <= abar and bbar;
else
z <= "0000";
end if;
end process;

end Behavioral;

9. Half Adder [Behavioral]


Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity HalfAdderBehave is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end HalfAdderBehave;

architecture Behavioral of HalfAdderBehave is

begin

process (a, b)

begin
if (a = '0') then
sum <= b;
carry <= '0';
else
sum <= not b;
carry <= b;
end if;
end process;

end Behavioral;

10. Four Bit Division


Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FourBitDivision is
Port ( ain : in STD_LOGIC_VECTOR (3 downto 0);
bin : in STD_LOGIC_VECTOR (3 downto 0);
quotient : out STD_LOGIC_VECTOR (3 downto 0);
remainder : out STD_LOGIC_VECTOR (3 downto 0));
end FourBitDivision;

architecture Behavioral of FourBitDivision is

begin

process (ain,bin)
variable qtemp: STD_LOGIC_VECTOR(3 downto 0);
variable rtemp: STD_LOGIC_VECTOR(3 downto 0);
begin
if(ain<bin)then
qtemp := "0000";
rtemp := Ain;
elsif (ain = bin) then
qtemp := "0001";
rtemp := "0000";
elsif (ain > bin) then
qtemp := "0001";
rtemp := ain - bin;
while (rtemp >= bin) loop
rtemp := rtemp - bin;
qtemp := qtemp + "0001";
end loop;
end if;
quotient <= qtemp;
remainder <= rtemp;
end process;

end Behavioral;
11. JK FF
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity JKFF is
Port ( clk : in STD_LOGIC;
re : in STD_LOGIC;
j : in STD_LOGIC;
k : in STD_LOGIC;
q : inout STD_LOGIC;
qbar : out STD_LOGIC);
end JKFF;

architecture Behavioral of JKFF is

begin

process (clk, re)


begin
if(re = '1') then
q <= '0';
elsif clk'event and clk = '0' then
q <= (j and (not q)) or ((not k) and q);
end if;
end process;
qbar <= not q;

end Behavioral;

12. D FF
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DFF is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
d : in STD_LOGIC;
q : out STD_LOGIC);
end DFF;

architecture Behavioral of DFF is

begin

process (clk, reset)


begin
if (reset = '1') then
q <= '0';
elsif clk'event and clk = '0' then
q <= d;
end if;
end process;

end Behavioral;

13. SR FF
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SRFF is
Port ( s : in STD_LOGIC;
r : in STD_LOGIC;
clk : in STD_LOGIC;
q : inout STD_LOGIC;
qbar : out STD_LOGIC);
end SRFF;

architecture Behavioral of SRFF is

begin

process (clk)
begin
if clk'event and clk = '1' then
if s = '0' and r = '0' then
q <= q;
elsif s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
else
q <= 'X';
end if;
end if;
end process;
qbar <= not q;

end Behavioral;

14. T FF
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TFF is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
t : in STD_LOGIC;
q : out STD_LOGIC);
end TFF;

architecture Behavioral of TFF is


signal qtemp : STD_LOGIC;
begin

process(clk, reset)
begin
if (reset = '1') then
qtemp <= '0';
elsif clk'event and clk = '0' then
if (t = '1') then
qtemp <= not qtemp;
end if;
end if;
end process;
q <= qtemp;

end Behavioral;

15. PIPO
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity PIPO is
Port ( d : in STD_LOGIC_VECTOR (3 downto 0);
reset : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0));
end PIPO;

architecture Structural of PIPO is

component DFF is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
d : in STD_LOGIC;
q : out STD_LOGIC);
end component;

begin

DFF1 : DFF port map (clk, reset, d(0), q(0));


DFF2 : DFF port map (clk, reset, d(1), q(1));
DFF3 : DFF port map (clk, reset, d(2), q(2));
DFF4 : DFF port map (clk, reset, d(3), q(3));

end Structural;

16. SISO
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SISO is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
d : in STD_LOGIC;
q : out STD_LOGIC);
end SISO;

architecture Structural of SISO is

component DFF is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
d : in STD_LOGIC;
q : out STD_LOGIC);
end component;

signal q0, q1, q2, q3 : STD_LOGIC;

begin

DFF1 : DFF port map (clk, reset, d, q0);


DFF2 : DFF port map (clk, reset, q0, q1);
DFF3 : DFF port map (clk, reset, q1, q2);
DFF4 : DFF port map (clk, reset, q2, q3);
q <= q3;

end Structural;
17. ALU
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ALUData is
Port ( sel : in STD_LOGIC_VECTOR (2 downto 0);
a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC_VECTOR (3 downto 0);
carry : out STD_LOGIC);
end ALUData;

architecture Dataflow of ALUData is

signal logic : STD_LOGIC_VECTOR (3 downto 0);


signal arith : STD_LOGIC_VECTOR (4 downto 0);
begin

with sel(1 downto 0) select


arith <= ('0' & a) + ('0' & b) when "00",
('0' & a) + ((not ('1' & b)) + 1) when "01",
('0' & a) when "10",
('0' & a) + 1 when others;
with sel(1 downto 0) select
logic <= a and b when "00",
a or b when "01",
a xor b when "10",
not a when others;
with sel(2) select
y <= arith(3 downto 0) when '0',
logic when others;
carry <= arith(4);

end Dataflow;

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