CA Lab COdes
CA Lab COdes
entity HalfAdder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end HalfAdder;
begin
end Dataflow;
entity HalfAdderStruct is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end HalfAdderStruct;
component XorGate
port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end component;
component AndGate
port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end component;
begin
end Structural;
entity FullAdderStruct is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end FullAdderStruct;
component HalfAdder
port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end component;
begin
end Structural;
4. 2 bit adder
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TwoBitAdder is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
b : in STD_LOGIC_VECTOR (1 downto 0);
sum : out STD_LOGIC_VECTOR (1 downto 0);
carry : out STD_LOGIC);
end TwoBitAdder;
begin
end Dataflow;
5. 8 bit adder
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity EightBitAdder is
Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
b : in STD_LOGIC_VECTOR (7 downto 0);
sum : out STD_LOGIC_VECTOR (7 downto 0);
carry : out STD_LOGIC);
end EightBitAdder;
begin
end Dataflow;
6. 2 bit multiplication
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TwoBitMultiplication is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
b : in STD_LOGIC_VECTOR (1 downto 0);
product : out STD_LOGIC_VECTOR (3 downto 0));
end TwoBitMultiplication;
begin
product <= a * b;
end Dataflow;
7. 8 bit multiplication
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity EightBitMultiplication is
Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
b : in STD_LOGIC_VECTOR (7 downto 0);
product : out STD_LOGIC_VECTOR (15 downto 0));
end EightBitMultiplication;
begin
product <= a * b;
end Dataflow;
8. Decoder
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Decoder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
enable : in STD_LOGIC;
z : out STD_LOGIC_VECTOR (3 downto 0));
end Decoder;
begin
process (a, b, enable)
variable abar, bbar : STD_LOGIC;
begin
abar := not a;
bbar := not b;
if enable = '1' then
z(3) <= a and b;
z(2) <= a and bbar;
z(1) <= abar and b;
z(0) <= abar and bbar;
else
z <= "0000";
end if;
end process;
end Behavioral;
entity HalfAdderBehave is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end HalfAdderBehave;
begin
process (a, b)
begin
if (a = '0') then
sum <= b;
carry <= '0';
else
sum <= not b;
carry <= b;
end if;
end process;
end Behavioral;
entity FourBitDivision is
Port ( ain : in STD_LOGIC_VECTOR (3 downto 0);
bin : in STD_LOGIC_VECTOR (3 downto 0);
quotient : out STD_LOGIC_VECTOR (3 downto 0);
remainder : out STD_LOGIC_VECTOR (3 downto 0));
end FourBitDivision;
begin
process (ain,bin)
variable qtemp: STD_LOGIC_VECTOR(3 downto 0);
variable rtemp: STD_LOGIC_VECTOR(3 downto 0);
begin
if(ain<bin)then
qtemp := "0000";
rtemp := Ain;
elsif (ain = bin) then
qtemp := "0001";
rtemp := "0000";
elsif (ain > bin) then
qtemp := "0001";
rtemp := ain - bin;
while (rtemp >= bin) loop
rtemp := rtemp - bin;
qtemp := qtemp + "0001";
end loop;
end if;
quotient <= qtemp;
remainder <= rtemp;
end process;
end Behavioral;
11. JK FF
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity JKFF is
Port ( clk : in STD_LOGIC;
re : in STD_LOGIC;
j : in STD_LOGIC;
k : in STD_LOGIC;
q : inout STD_LOGIC;
qbar : out STD_LOGIC);
end JKFF;
begin
end Behavioral;
12. D FF
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DFF is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
d : in STD_LOGIC;
q : out STD_LOGIC);
end DFF;
begin
end Behavioral;
13. SR FF
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRFF is
Port ( s : in STD_LOGIC;
r : in STD_LOGIC;
clk : in STD_LOGIC;
q : inout STD_LOGIC;
qbar : out STD_LOGIC);
end SRFF;
begin
process (clk)
begin
if clk'event and clk = '1' then
if s = '0' and r = '0' then
q <= q;
elsif s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
else
q <= 'X';
end if;
end if;
end process;
qbar <= not q;
end Behavioral;
14. T FF
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TFF is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
t : in STD_LOGIC;
q : out STD_LOGIC);
end TFF;
process(clk, reset)
begin
if (reset = '1') then
qtemp <= '0';
elsif clk'event and clk = '0' then
if (t = '1') then
qtemp <= not qtemp;
end if;
end if;
end process;
q <= qtemp;
end Behavioral;
15. PIPO
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PIPO is
Port ( d : in STD_LOGIC_VECTOR (3 downto 0);
reset : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0));
end PIPO;
component DFF is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
d : in STD_LOGIC;
q : out STD_LOGIC);
end component;
begin
end Structural;
16. SISO
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SISO is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
d : in STD_LOGIC;
q : out STD_LOGIC);
end SISO;
component DFF is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
d : in STD_LOGIC;
q : out STD_LOGIC);
end component;
begin
end Structural;
17. ALU
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALUData is
Port ( sel : in STD_LOGIC_VECTOR (2 downto 0);
a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC_VECTOR (3 downto 0);
carry : out STD_LOGIC);
end ALUData;
end Dataflow;