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ALU

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5 views4 pages

ALU

Uploaded by

haircaretik
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
USE ieee.std_logic_unsigned.all;

entity adder is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
b : in STD_LOGIC_VECTOR (1 downto 0);
c : out STD_LOGIC_VECTOR (2 downto 0));
end adder;

architecture Arch of adder is


Begin
c <= ('0' & a) + ( '0' & b );
end Arch;
----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
USE ieee.std_logic_unsigned.all;

entity mul is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
b : in STD_LOGIC_VECTOR (1 downto 0);
c : out STD_LOGIC_VECTOR (3 downto 0));
end mul;

architecture arch of mul is


Begin
c <= ("00" & a) * ("00" & b);
end arch;
-----------------------------------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity min is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
b : in STD_LOGIC_VECTOR (1 downto 0);
c : out STD_LOGIC_VECTOR (1 downto 0));
end min;

architecture arch of min is


Begin
c <= a when (a < b) else b;
end arch;
------------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ALU is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
b : in STD_LOGIC_VECTOR (1 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
cout : out STD_LOGIC_VECTOR (3 downto 0));
end ALU;

architecture multiplexer of ALU is

component add Port ( a : in STD_LOGIC_VECTOR (1 downto 0);


b : in STD_LOGIC_VECTOR (1 downto 0);
c : out STD_LOGIC_VECTOR (2 downto 0));
end component;
for all : add use entity work.adder(arch);

component mul Port ( a : in STD_LOGIC_VECTOR (1 downto 0);


b : in STD_LOGIC_VECTOR (1 downto 0);
c : out STD_LOGIC_VECTOR (3 downto 0));
end component;
for all : mul use entity work.mul(arch);

component min Port ( a : in STD_LOGIC_VECTOR (1 downto 0);


b : in STD_LOGIC_VECTOR (1 downto 0);
c : out STD_LOGIC_VECTOR (1 downto 0));
end component;
for all : min use entity work.min(arch);
signal outadd : STD_LOGIC_VECTOR(2 downto 0);
signal outmul : STD_LOGIC_VECTOR(3 downto 0);
signal outmin : STD_LOGIC_VECTOR(1 downto 0);

Begin

label1 : add port map(a,b,outadd);


label2 : mul port map(a,b,outmul);
label3 : min port map(a,b,outmin);

with s select
cout <= ('0' & outadd) when "00",
outmul when "01",
("00" & outmin) when "10",
"0000" when others;

end multiplexer;

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