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Fadder

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sarah
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10 views3 pages

Fadder

Uploaded by

sarah
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity fuladd is

Port(

a : in STD_LOGIC;

b : in STD_LOGIC;

cin : in STD_LOGIC;

sum,cout : out STD_LOGIC);

end fuladd;

architecture Behavioral of fuladd is

begin

process(a, b, cin)

variable aa : STD_LOGIC_VECTOR(1 downto 0);

variable bb : STD_LOGIC_VECTOR(1 downto 0);

variable cc : STD_LOGIC_VECTOR(1 downto 0);

variable result : UNSIGNED(1 downto 0);

begin

aa := "0" & a;

bb := "0" & b;

cc := "0" & cin;

result := UNSIGNED(aa) + UNSIGNED(bb) + UNSIGNED(cc);

sum <= result(0);

cout <= result(1);

end process;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity ripple_carry_adder is

port(

s_1,s_2 : in std_logic_vector(3 downto 0);

s_3 : in std_logic;

s_out : out std_logic_vector(3 downto 0);

c_out : out std_logic);

end ripple_carry_adder;

architecture struct of ripple_carry_adder is

component fuladd is port

( a : in STD_LOGIC;

b : in STD_LOGIC;

cin : in STD_LOGIC;

sum,cout : out STD_LOGIC

);

end component;

signal carry : std_logic_vector(3 downto 0);

begin

x1 : fuladd port map (a=> s_1(0),b=> s_2(0), cin=> s_3, sum=>s_out(0), cout=> carry(0));

x2 : fuladd port map (a=> s_1(1),b=> s_2(1), cin=> carry(0), sum=>s_out(1), cout=> carry(1));

x3 : fuladd port map (a=> s_1(2),b=> s_2(2), cin=> carry(1), sum=>s_out(2), cout=> carry(2));

x4 : fuladd port map (a=> s_1(3),b=> s_2(3), cin=> carry(2), sum=>s_out(3), cout=> carry(3));

c_out <= carry(3);

end struct;

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