EECS 318 CAD EECS 318 CAD Computer Aided Design Computer Aided Design

LECTURE 3: LECTURE 3: The VHDL N-bit Adder The VHDL N-bit Adder
Instructor: Francis G. Wolff [email protected] Case Western Reserve University CWRU EECS 318

Full Adder: Truth Table

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Combinatorial Logic Operators

NOT AND NAND OR NOR XOR XNOR z <= NOT (x); z<= NOT x; z <= x AND y; z <= NOT (x AND y); z <= x OR y; z <= NOT (x OR Y); z <= (x and NOT y) OR (NOT x AND y); z <= (x and y) OR (NOT x AND NOT y);

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Full Adder: Architecture

ENTITY full_adder IS ENTITY full_adder IS PORT (x, y, z: PORT (x, y, z: Sum, Carry: Sum, Carry: ); END full_adder; ); END full_adder;

Entity Declaration Entity Declaration

IN std_logic; IN std_logic; OUT std_logic OUT std_logic Optional Entity END name; Optional Entity END name; Architecture Declaration Architecture Declaration

ARCHITECTURE full_adder_arch_1 OF full_adder IS ARCHITECTURE full_adder_arch_1 OF full_adder IS BEGIN BEGIN Sum <= ((((x XOR y ))XOR z ); Sum <= x XOR y XOR z ); Carry <= (( x AND y ))OR (z AND (x AND y))); Carry <= (( x AND y OR (z AND (x AND y))); END full_adder_arch_1; END full_adder_arch_1; Optional Architecture END name; Optional Architecture END name;
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SIGNAL: Scheduled Event

SIGNAL
Like variables in a programming language such as C, signals can be assigned values, e.g. 0, 1

However, SIGNALs also have an associated time value

A signal receives a value at a specific point in time and retains that value until it receives a new value at a future point in time (i.e. scheduled event) The waveform of the signal is a sequence of values assigned to a signal over time

For example
wave <= 0, 1 after 10 ns, 0 after 15 ns, 1 after 25 ns;

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Full Adder: Architecture with Delay

ARCHITECTURE full_adder_arch_2 OF full_adder IS ARCHITECTURE full_adder_arch_2 OF full_adder IS SIGNAL S1, S2, S3: std_logic; SIGNAL S1, S2, S3: std_logic; Signals (like wires) Signals (like wires) BEGIN BEGIN are not PORTs they s1 after 15 ns; are not PORTs they s1 <= ((a XOR b )) <= a XOR b after 15 ns; s2 do not have s2 <= ((c_in AND s1 ))after 5 ns; <= c_in AND s1 after 5 ns; do not have s3 after 5 ns; direction s3 <= ((a AND b )) <= a AND b after 5 ns; direction Sum <= ((s1 XOR c_in ))after 15 ns; Sum <= s1 XOR c_in after 15 ns; (i.e. IN, OUT) (i.e. IN, OUT) Carry <= ((s2 OR s3 )) after 5 ns; Carry <= s2 OR s3 after 5 ns; END; END; CWRU EECS 318

Signal order: Does it matter? No

ARCHITECTURE full_adder_arch_2 OF full_adder IS ARCHITECTURE full_adder_arch_2 OF full_adder IS SIGNAL S1, S2, S3: std_logic; SIGNAL S1, S2, S3: std_logic; BEGIN BEGIN s1 after 15 ns; s1 <= ((a XOR b )) <= a XOR b after 15 ns; s2 s2 <= ((c_in AND s1 ))after 5 ns; <= c_in AND s1 after 5 ns; s3 after 5 ns; s3 <= ((a AND b )) <= a AND b after 5 ns; Sum <= ((s1 XOR c_in ))after 15 ns; Sum <= s1 XOR c_in after 15 ns; Carry <= ((s2 OR s3 )) after 5 ns; Carry <= s2 OR s3 after 5 ns; END; END; ARCHITECTURE full_adder_arch_3 OF full_adder IS ARCHITECTURE full_adder_arch_3 OF full_adder IS SIGNAL S1, S2, S3: std_logic; SIGNAL S1, S2, S3: std_logic; BEGIN BEGIN Carry <= ((s2 OR s3 )) after 5 ns; Carry <= s2 OR s3 after 5 ns; Sum <= ((s1 XOR c_in ))after 15 ns; Sum <= s1 XOR c_in after 15 ns; s3 after 5 ns; s3 <= ((a AND b )) <= a AND b after 5 ns; s2 s2 <= ((c_in AND s1 ))after 5 ns; <= c_in AND s1 after 5 ns; s1 after 15 ns; s1 <= ((a XOR b )) <= a XOR b after 15 ns; END; END;

No, No, this this is is not not C! C! NetNetlists lists have have same same beha beha vior vior & & paral paral lel lel
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The Ripple-Carry n-Bit Binary Parallel Adder

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Hierarchical design: 2-bit adder

The design interface to a two bit adder is

LIBRARY IEEE; LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_1164.ALL; ENTITY adder_bits_2 IS ENTITY adder_bits_2 IS PORT (Cin: PORT (Cin: a0, b0, a1, b1: a0, b0, a1, b1: S0, S1: S0, S1: Cout: Cout: ); END; ); END;

IN std_logic; IN std_logic; IN std_logic; IN std_logic; OUT std_logic; OUT std_logic; OUT std_logic OUT std_logic

Note: that the ports are positional dependant

(Cin, a0, b0, a1, b1, S0, S1, Cout)
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Hierarchical design: Component Instance

Component Declaration Component Declaration ARCHITECTURE ripple_2_arch OF adder_bits_2 IS COMPONENT full_adder PORT (x, y, z: IN std_logic; Sum, Carry: OUT std_logic); END COMPONENT; SIGNAL t1: std_logic; BEGIN FA1: full_adder PORT MAP (Cin, a0, b0, S0, t1); FA2: full_adder PORT MAP (t1, a1, b1, s1, Cout); END; Component instance #1 called FA1 Component instance #1 called FA1 Component instance #2 called FA2 Component instance #2 called FA2
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Positional versus Named Association

Positional Association (must match the port order)

FA1: full_adder PORT MAP (Cin, a0, b0, S0, t1);

Named Association: signal => port_name

FA1: full_adder PORT FA1: full_adder PORT MAP (Cin=>x, a0=>y, b0=>z, S0=>Sum, t1=>Carry); MAP (Cin=>x, a0=>y, b0=>z, S0=>Sum, t1=>Carry); FA1: full_adder PORT FA1: full_adder PORT MAP (Cin=>x, a0=>y, b0=>z, t1=>Carry, S0=>Sum); MAP (Cin=>x, a0=>y, b0=>z, t1=>Carry, S0=>Sum); FA1: full_adder PORT FA1: full_adder PORT MAP (t1=>Carry, S0=>Sum, a0=>y, b0=>z, Cin=>x); MAP (t1=>Carry, S0=>Sum, a0=>y, b0=>z, Cin=>x);
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Component by Named Association

ARCHITECTURE ripple_2_arch OF adder_bits_2 IS COMPONENT full_adder PORT (x, y, z: IN std_logic; Sum, Carry: OUT std_logic); END COMPONENT; SIGNAL t1: std_logic; -- Temporary carry signal BEGIN -- Named association FA1: full_adder PORT MAP (Cin=>x, a0=>y, b0=>z, S0=>Sum, t1=>Carry); -- Positional association FA2: full_adder PORT MAP (t1, a1, b1, s1, Cout); END; -- Comments start with a double dash -- Comments start with a double dash
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Using vectors: std_logic_vector

ENTITY adder_bits_2 IS ENTITY adder_bits_2 IS PORT (Cin: PORT (Cin: a0, b0, a1, b1: a0, b0, a1, b1: S0, S1: S0, S1: Cout: Cout: ); END; ); END; IN std_logic; IN std_logic; IN std_logic; IN std_logic; OUT std_logic; OUT std_logic; OUT std_logic OUT std_logic

By using vectors, there is less typing of variables, a0, a1, ...

ENTITY adder_bits_2 IS ENTITY adder_bits_2 IS PORT (Cin: IN std_logic; PORT (Cin: IN std_logic; a, b: IN std_logic_vector(1 downto 0); a, b: IN std_logic_vector(1 downto 0); S: OUT std_logic_vector(1 downto 0); S: OUT std_logic_vector(1 downto 0); Cout: OUT std_logic Cout: OUT std_logic ); END; ); END;
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2-bit Ripple adder using std_logic_vector

Note, the signal variable usage is now different:

a0 becomes a(0) ARCHITECTURE ripple_2_arch OF adder_bits_2 IS COMPONENT full_adder PORT (x, y, z: IN std_logic; Sum, Carry: OUT std_logic); END COMPONENT; SIGNAL t1: std_logic; -- Temporary carry signal BEGIN FA1: full_adder PORT MAP (Cin, a(0), b(0), S(0), t1); FA2: full_adder PORT MAP (t1, a(1), b(1), s(1), Cout); END;
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4-bit Ripple adder using std_logic_vector

ARCHITECTURE ripple_4_arch OF adder_bits_4 IS COMPONENT full_adder PORT (x, y, z: IN std_logic; Sum, Carry: OUT std_logic); END COMPONENT; SIGNAL t: std_logic_vector(3 downto 1); BEGIN FA1: full_adder PORT MAP (Cin, a(0), b(0), S(0), t(1)); FA2: full_adder PORT MAP (t(1), a(1), b(1), S(1), t(2)); FA3: full_adder PORT MAP (t(2), a(2), b(2), S(2), t(3)); FA4: full_adder PORT MAP (t(3), a(3), b(3), S(3), Cout); END;

std_vectors make it easier to replicate structures std_vectors make it easier to replicate structures
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For-Generate statement: first improvement

ARCHITECTURE ripple_4_arch OF adder_bits_4 IS COMPONENT full_adder PORT (x, y, z: IN std_logic; Sum, Carry: OUT std_logic); END COMPONENT; SIGNAL t: std_logic_vector(3 downto 1); CONSTANT n: INTEGER := 4; Constants never change value BEGIN Constants never change value FA1: full_adder PORT MAP (Cin, a(0), b(0), S(0), t(1)); FA2: for i in 1 to n-2 generate FA_f:full_adder PORT MAP (t(1), a(1), b(1), S(1), t(2)); FA_i: full_adder PORT (t(2), a(2), b(2), S(2), t(3)); FA3: full_adder PORT MAPMAP (t(i), a(i), b(i), S(i), t(i+1)); end generate; FA4: full_adder PORT MAP (t(n), a(n), b(n), S(n), Cout); END; LABEL: before the for is not optional LABEL: before the for is not optional
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For-Generate statement: second improvement

ARCHITECTURE ripple_4_arch OF adder_bits_4 IS COMPONENT full_adder PORT (x, y, z: IN std_logic; Sum, Carry: OUT std_logic); END COMPONENT; SIGNAL t: std_logic_vector(4 downto 0); CONSTANT n: INTEGER := 4; BEGIN t(0) <= Cin; Cout <= t(n); Keep track of vector sizes Keep track of vector sizes FA_f: for i in 0 to n-1 generate FA_i: full_adder PORT MAP (t(i), a(i), b(i), S(i), t(i+1)); end generate; END;
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N-bit adder using generic

ENTITY adder_bits_4 IS ENTITY adder_bits_4 IS PORT (Cin: IN std_logic; PORT (Cin: IN std_logic; a, b: IN std_logic_vector(3 downto 0); a, b: IN std_logic_vector(3 downto 0); S: OUT std_logic_vector(3 downto 0); S: OUT std_logic_vector(3 downto 0); Cout: OUT std_logic Cout: OUT std_logic ); END; ); END; By using generics, the design can be generalized Default case is 2 Default case is 2 ENTITY adder_bits_n IS ENTITY adder_bits_n IS GENERIC(n: INTEGER := 2); PORT (Cin: IN std_logic; PORT (Cin: IN std_logic; a, b: IN std_logic_vector(n-1 downto 0); a, b: IN std_logic_vector(n-1 downto 0); S: OUT std_logic_vector(n-1 downto 0); S: OUT std_logic_vector(n-1 downto 0); Cout: OUT std_logic Cout: OUT std_logic ); END; ); END;

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For-Generate statement: third improvement

ARCHITECTURE ripple_n_arch OF adder_bits_n IS COMPONENT full_adder PORT (x, y, z: IN std_logic; Sum, Carry: OUT std_logic); END COMPONENT; SIGNAL t: std_logic_vector(n downto 0); BEGIN t(0) <= Cin; Cout <= t(n); FA: for i in 0 to n-1 generate FA_i: full_adder PORT MAP (t(i), a(i), b(i), S(i), t(i+1)); end generate; END;
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Stimulus Only Test Bench Architecture

ARCHITECTURE tb OF tb_adder_4 IS
COMPONENT adder_bits_n GENERIC(n: INTEGER := 2); PORT ( Cin: IN std_logic; a, b: IN std_logic_vector(n-1 downto 0); S: OUT std_logic_vector(n-1 downto 0); Cout: OUT std_logic END COMPONENT; SIGNAL x, y, Sum: std_logic_vector(n downto 0); SIGNAL c, Cout: std_logic;

BEGIN x <= 0000, 0001 after 50 ns, 0101, after 100 ns; y <= 0010, 0011 after 50 ns, 1010, after 100 ns; c <= 1, 0 after 50 ns; Override UUT_ADDER_4: adder_bits_n GENERIC MAP(4) Override default default PORT MAP (c, x, y, Sum, Cout); END;

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Stimulus Only Test Bench Entity

ENTITY tb_adder_4 IS PORT (Sum: Cout: ); END;

std_logic_vector(3 downto 0); std_logic

The output of the testbench will be observe by the digital waveform of the simulator.

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