SST26WF064C: 1.8V, 64 Mbit Serial Quad I/O (SQI) Flash Memory

SST26WF064C
1.8V, 64 Mbit Serial Quad I/O (SQI) Flash Memory

Features • Software Protection
- Individual-Block Write Protection with permanent
• Single Voltage Read and Write Operations
lock-down capability
- 1.65-1.95V
- 64 KByte blocks, two 32 KByte blocks, and
• Serial Interface Architecture eight 8 KByte parameter blocks
- Mode 0 and Mode 3 - Read Protection on top and bottom 8 KByte
- Nibble-wide multiplexed I/O’s with SPI-like serial parameter blocks
command structure • Security ID
- x1/x2/x4 Serial Peripheral Interface (SPI) Protocol
- One-Time Programmable (OTP) 2 KByte,
- Dual-Transfer Rate (DTR) Operation
Secure ID
• High Speed Clock Frequency - 64 bit unique, factory pre-programmed identifier
- 104 MHz max - User-programmable area
- 54 MHz max (DTR) • Temperature Range
• Burst Modes - Industrial: -40°C to +85°C
- Continuous linear burst • Packages Available
- 8/16/32/64 Byte linear burst with wrap-around - 8-contact WDFN (6mm x 5mm)
• Superior Reliability - 8-lead SOIJ (5.28 mm)
- Endurance: 100,000 Cycles (min) - 16-lead SOIC (7.50 mm)
- Greater than 100 years Data Retention - 24-ball TBGA (8mm x 6mm)
• Low Power Consumption: • All devices are RoHS compliant
- Active Read current: 15 mA (typical @ 104 MHz)
- Standby current: 10 µA (typical) Product Description
- Deep Power-Down current: 2.5 µA (typical) The Serial Quad I/O™ (SQI™) family of flash-memory
• Fast Erase Time devices features a six-wire, 4-bit I/O interface that
- Sector/Block Erase: 18 ms (typ), 25 ms (max) allows for low-power, high-performance operation in a
- Chip Erase: 35 ms (typ), 50 ms (max) low pin-count package. The SST26WF064C also sup-
• Page-Program ports full command-set compatibility to traditional Serial
Peripheral Interface (SPI) protocol. System designs
- 256 Bytes per page in x1 or x4 mode
using SQI flash devices occupy less board space and
• End-of-Write Detection ultimately lower system costs.
- Software polling the BUSY bit in status register
All members of the 26 Series, SQI family are manufac-
• Flexible Erase Capability tured with proprietary, high-performance CMOS Super-
- Uniform 4 KByte sectors Flash® technology. The split-gate cell design and thick-
- Four 8 KByte top and bottom parameter overlay oxide tunneling injector attain better reliability and man-
blocks ufacturability compared with alternate approaches.
- One 32 KByte top and bottom overlay block
The SST26WF064C significantly improves performance
- Uniform 64 KByte overlay blocks
and reliability, while lowering power consumption. These
• Write-Suspend devices write (Program or Erase) with a single power sup-
- Suspend Program or Erase operation to access ply of 1.65-1.95V. The total energy consumed is a function
another block/sector of the applied voltage, current, and time of application. For
• Software Reset (RST) mode any given voltage range, the SuperFlash technology uses
• Hardware Reset Pin less current to program and has a shorter erase time.
Therefore, the total energy consumed during any Erase or
• Supports JEDEC-compliant Serial Flash Discov-
Program operation is less than alternative flash memory
erable Parameter (SFDP) table
technologies.
 2016-2017 Microchip Technology Inc. Preliminary DS20005430B-page 1

SST26WF064C
The SST26WF064C is offered in 8-contact WDFN See “I/O Configuration (IOC)” on page 13 for more
(6 mm x 5 mm), 8-lead SOIJ (5.28 mm), 16-lead SOIC information about configuring the WP#, RESET/
(7.50 mm), and 24-ball TBGA (8mm x 6mm) packages. HOLD#, SIO2, and SIO3 pins.
See Figure 2-1 for pin assignments.
The following configuration is available upon order:
• SST26WF064C default at power-up has the WP#
and RESET#/HOLD# pins enabled, with the SIO2
and SIO3 pins disabled, to initiate SPI-protocol.
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DS20005430B-page 2 Preliminary  2016-2017 Microchip Technology Inc.

SST26WF064C
1.0 BLOCK DIAGRAM
FIGURE 1-1: FUNCTIONAL BLOCK DIAGRAM
OTP
SuperFlash
X - Decoder Memory
Address
Buffers
and
Latches
Y - Decoder
Page Buffer,
Control Logic I/O Buffers
and
Data Latches
Serial Interface
WP# HOLD# SCK CE# SIO [3:0] RESET#

20005430 B1.0

SST26WF064C
2.0 PIN DESCRIPTION
FIGURE 2-1: PIN DESCRIPTIONS
CE# 1 8 VDD
RESET#
SO/SIO1 2 7 /HOLD#/SIO3
Top View 8-Lead SOIJ
WP#/SIO2 3 6 SCK
VSS 4 5 SI/SIO0
08-soic S2A P1.0
CE# 1 8 VDD
RESET#
SO/SIO1 2 7 /HOLD#/SIO3
Top View
8-Contact WDFN
WP#/SIO2 3 6 SCK
VSS 4 5 SI/SIO0
08-wson QA P1.0
RESET#/
HOLD#/SIO3 SCK
VDD SI/SIO0
RESET# Top View NC
NC NC
16-lead SOIC
NC NC
NC NC
CE# VSS
SO/SIO1 WP#/SIO2
16-SOIC P1.0
Top View
4
RESET#/
RESET# VDD WP#/ HOLD#/ NC NC
SIO2 SIO3
3
NC VSS NC SI/ NC NC
SIO0 24-Ball TBGA
2
NC SCK CE# S0/ NC NC
SIO1
1
NC NC NC NC NC NC
A B C D E F T4D-P1.0

SST26WF064C
TABLE 2-1: PIN DESCRIPTION

Symbol Pin Name Functions
Provide the timing of the serial interface.
SCK Serial Clock Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
Transfer commands, addresses, or data serially into the device or data out of
Serial Data the device. Inputs are latched on the rising edge of the serial clock. Data is
SIO[3:0]
Input/Output shifted out on the falling edge of the serial clock. The Enable Quad I/O (EQIO)
command instruction configures these pins for Quad I/O mode.
Transfer commands, addresses or data serially into the device. Inputs are
Serial Data Input
SI latched on the rising edge of the serial clock. SI is the default state after a
for SPI mode
power on reset or hardware reset.
Serial Data Output Transfer data serially out of the device. Data is shifted out on the falling edge of
SO
for SPI mode the serial clock. SO is the default state after a power on reset or hardware reset.
The device is enabled by a high to low transition on CE#. CE# must remain low
CE# Chip Enable for the duration of any command sequence; or in the case of Write operations,
for the command/data input sequence.
The WP# pin is used in conjunction with the WPEN and IOC bits in the configu-
WP# Write Protect ration register to prohibit Write operations to the Block-Protection register. This
pin only works in SPI, single-bit and dual-bit Read mode.
Temporarily stops serial communication with the SPI Flash memory while the
HOLD# Hold device is selected. This pin only works in SPI, single-bit and dual-bit Read
mode and must be tied high when not in use.
RESET# Reset Reset the operation and internal logic of the device.
VDD Power Supply Provide power supply voltage.
VSS Ground

SST26WF064C
3.0 MEMORY ORGANIZATION

The SST26WF064C SQI memory array is organized in
uniform, 4 KByte erasable sectors with the following
erasable blocks: eight 8 KByte parameters, two 32
KByte overlays, and one hundred twenty-six 64 KByte
overlay blocks. See Figure 3-1.
FIGURE 3-1: MEMORY MAP

Top of Memory Block
8 KByte
8 KByte
8 KByte
8 KByte
32 KByte
64 KByte
2 Sectors for 8 KByte blocks

...
4 KByte
4 KByte
64 KByte
...
4 KByte
4 KByte
64 KByte
32 KByte
8 KByte
8 KByte
8 KByte
8 KByte
Bottom of Memory Block

20005430 F41.0

SST26WF064C
4.0 DEVICE OPERATION signal is high for Mode 3. For both modes, the Serial
Data I/O (SIO[3:0]) is sampled at the rising edge of the
The SST26WF064C supports both Serial Peripheral SCK clock signal for input, and driven after the falling
Interface (SPI) bus protocol and a 4-bit multiplexed SQI edge of the SCK clock signal for output. The traditional
bus protocol. To provide backward compatibility to tra- SPI protocol uses separate input (SI) and output (SO)
ditional SPI Serial Flash devices, the device’s initial data signals as shown in Figure 4-1. The SQI protocol
state after a power-on reset is SPI mode which sup- uses four multiplexed signals, SIO[3:0], for both data in
ports multi-I/O (x1/x2/x4) Read/Write commands. A and data out, as shown in Figure 4-2. This means the
command instruction configures the device to SQI SQI protocol quadruples the traditional bus transfer
mode. The dataflow in the SQI mode is similar to the speed at the same clock frequency, without the need
SPI mode, except it uses four multiplexed I/O signals for more pins on the package.
for command, address, and data sequence.
The SST26WF064C also supports Dual-Transfer Rate
SQI Flash Memory supports both Mode 0 (0,0) and (DTR) SPI and SQI commands, during which data is
Mode 3 (1,1) bus operations. The difference between sampled on both the rising and the falling edge of the
the two modes is the state of the SCK signal when the clock, and data is driven out on both the rising and fall-
bus master is in stand-by mode and no data is being ing edge of the clock.
transferred. The SCK signal is low for Mode 0 and SCK
FIGURE 4-1: SPI PROTOCOL (TRADITIONAL 25 SERIES SPI DEVICE)

CE#
MODE 3 MODE 3
SCK MODE 0 MODE 0
SI Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DON'T CARE
MSB
HIGH IMPEDANCE
SO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB 20005430 F03.0
FIGURE 4-2: SQI SERIAL QUAD I/O PROTOCOL

CE#
MODE 3 MODE 3
CLK
MODE 0 MODE 0
SIO(3:0) C1 C0 A5 A4 A3 A2 A1 A0 H0 L0 H1 L1 H2 L2 H3 L3
MSB
1432 F04.0
4.1 Device Protection 4.1.1 INDIVIDUAL BLOCK PROTECTION

The SST26WF064C offers a flexible memory protection The SST26WF064C has a Block-Protection register
scheme that allows the protection state of each individ- which provides a software mechanism to write-lock the
ual block to be controlled separately. In addition, the individual memory blocks and write-lock, and/or read-
Write-Protection Lock-Down register prevents any lock, the individual parameter blocks. The Block-Pro-
change of the lock status during device operation. To tection register is 144 bits wide: two bits each for the
avoid inadvertent writes during power-up, the device is eight 8 KByte parameter blocks (write-lock and read-
write-protected by default after a power-on reset cycle. A lock), and one bit each for the remaining 32 KByte and
Global Block-Protection Unlock command offers a single 64 KByte overlay blocks (write-lock). See Table 5-6 for
command cycle that unlocks the entire memory array for address range protected per register bit.
faster manufacturing throughput. Each bit in the Block-Protection register (BPR) can be
For extra protection, there is an additional non-volatile written to a ‘1’ (protected) or ‘0’ (unprotected). For the
register that can permanently write-protect the Block- parameter blocks, the most significant bit is for read-lock,
Protection register bits for each individual block. Each and the least significant bit is for write-lock. Read-locking
of the corresponding lock-down bits are one time pro- the parameter blocks provides additional security for sen-
grammable (OTP)—once written, they cannot be sitive data after retrieval (e.g., after initial boot). If a block
erased. Data that had been previously programmed is read-locked all reads to the block return data 00H.
into these blocks cannot be altered by programming or
erase and is not reversible

SST26WF064C
The Write Block-Protection Register command is a two- Writing a ‘0’ in any location in the nVWLDR has no
cycle command which requires that Write-Enable (WREN) effect on either the nVWLDR or the corresponding
is executed prior to the Write Block-Protection Register com- Write-Lock bit in the BPR.
mand. The Global Block-Protection Unlock command clears Note that if the Block-Protection register had been pre-
all write protection bits in the Block-Protection register. viously locked down, see “Write-Protection Lock-Down
(Volatile)”, the device must be power cycled before
4.1.2 WRITE-PROTECTION LOCK-DOWN
using the nVWLDR. If the Block-Protection Register is
(VOLATILE) locked down and the Write nVWLDR command is
To prevent changes to the Block-Protection register, accessed, the command will be ignored.
use the Lock-Down Block-Protection Register (LBPR)
command to enable Write-Protection Lock-Down. 4.2 Hardware Write Protection
Once Write-Protection Lock-Down is enabled, the
Block-Protection register can not be changed. To avoid The hardware Write Protection pin (WP#) is used in con-
inadvertent lock down, the WREN command must be junction with the WPEN and IOC bits in the configuration
executed prior to the LBPR command. register to prohibit write operations to the Block-Protec-
tion and Configuration registers. The WP# pin function
To reset Write-Protection Lock-Down, performing a
only works in SPI single-bit and dual-bit read mode when
power cycle or hardware reset on the device is
the IOC bit in the configuration register is set to ‘0’.
required. The Write-Protection Lock-Down status may
be read from the Status register. The WP# pin function is disabled when the WPEN bit in
the configuration register is ‘0’. This allows installation of
4.1.3 WRITE-LOCK LOCK-DOWN (NON- the SST26WF064C in a system with a grounded WP# pin
VOLATILE) while still enabling Write to the Block-Protection register.
The Lock-Down function of the Block-Protection Register
The non-Volatile Write-Lock Lock-Down register is an
supersedes the WP# pin, see Table 4-1 for Write Protec-
alternate register that permanently prevents changes
tion Lock-Down states.
to the block-protect bits. The non-Volatile Write-Lock
Lock-Down register (nVWLDR) is 136 bits wide per The factory default setting at power-up of the WPEN bit
device: one bit each for the eight 8-KByte parameter is ‘0’, disabling the Write Protect function of the WP#
blocks, and one bit each for the remaining 32 KByte after power-up. WPEN is a non-volatile bit; once the bit
and 64 KByte overlay blocks. See Table 5-6 for address is set to ‘1’, the Write Protect function of the WP# pin
range protected per register bit. continues to be enabled after power-up. The WP# pin
only protects the Block-Protection Register and Config-
Writing ‘1’ to any or all of the nVWLDR bits disables the
uration Register from changes. Therefore, if the WP#
change mechanism for the corresponding Write-Lock
pin is set to low before or after a Program or Erase
bit in the BPR, and permanently sets this bit to a ‘1’
command, or while an internal Write is in progress, it
(protected) state. After this change, both bits will be set
will have no effect on the Write command.
to ‘1’, regardless of the data entered in subsequent
writes to either the nVWLDR or the BPR. Subsequent The IOC bit takes priority over the WPEN bit in the con-
writes to the nVWLDR can only alter available locations figuration register. When the IOC bit is ‘1’, the function
that have not been previously written to a ‘1’. This of the WP# pin is disabled and the WPEN bit serves no
method provides write-protection for the corresponding function. When the IOC bit is ‘0’ and WPEN is ‘1’, set-
memory-array block by protecting it from future pro- ting the WP# pin active low prohibits Write operations
gram or erase operations. to the Block Protection Register.
TABLE 4-1: WRITE PROTECTION LOCK-DOWN STATES

WP# IOC WPEN WPLD Block Protection Register Configuration Register
L 0 1 1 Protected Protected
L 0 0 1 Protected Writable
L 0 1 0 Protected Protected
L 01 02 0 Writable Writable
H 0 X 1 Protected Writable
H 0 X 0 Writable Writable
X 1 X 1 Protected Writable
X 1 02 0 Writable Writable
1. Default at power-up Register settings for SST26WF064C

2. Factory default setting is ‘0’. This is a non-volatile bit; default at power-up is the value set prior to power-down.

SST26WF064C
4.3 Security ID SST26WF064C ships with the IOC bit set to ‘0’ and the
HOLD# pin function enabled. The HOLD# pin is always
The SST26WF064C offers a 2 KByte Security ID (Sec disabled in SQI mode and only works in SPI single-bit
ID) feature. The Security ID space is divided into two and dual-bit read mode.
parts – one factory-programmed, 64-bit segment and
one user-programmable segment. The factory-pro- To activate the Hold mode, CE# must be in active low
grammed segment is programmed during manufactur- state. The Hold mode begins when the SCK active low
ing with a unique number and cannot be changed. The state coincides with the falling edge of the HOLD# sig-
user-programmable segment is left unprogrammed for nal. The Hold mode ends when the HOLD# signal’s ris-
the customer to program as desired. ing edge coincides with the SCK active low state.
Use the Program Security ID (PSID) command to pro- If the falling edge of the HOLD# signal does not coin-
gram the Security ID using the address shown in Table cide with the SCK active low state, then the device
5-5. The Security ID can be locked using the Lockout enters Hold mode when the SCK next reaches the
Security ID (LSID) command. This prevents any future active low state. Similarly, if the rising edge of the
write operations to the Security ID. HOLD# signal does not coincide with the SCK active
low state, then the device exits Hold mode when the
The factory-programmed portion of the Security ID SCK next reaches the active low state. See Figure 4-3.
can’t be programmed by the user; neither the factory-
programmed nor user-programmable areas can be Once the device enters Hold mode, SO will be in high
erased. impedance state while SI and SCK can be VIL or VIH.
If CE# is driven active high during a Hold condition, it
4.4 Hold Operation resets the internal logic of the device. As long as
HOLD# signal is low, the memory remains in the Hold
The HOLD# pin pauses active serial sequences without condition. To resume communication with the device,
resetting the clocking sequence. The RESET#/HOLD#/ HOLD# must be driven active high, and CE# must be
SIO3 pin provides HOLD capability when configured as driven active low.
a HOLD pin. One factory configuration is available: The
FIGURE 4-3: HOLD CONDITION WAVEFORM.
SCK
HOLD#
Active Hold Active Hold Active
20005430 F46.0
4.5 Reset Operation 4.5.1 HARDWARE RESET OPERATION

The SST26WF064C supports both hardware and soft- To configure the RESET#/HOLD#/SIO3 pin as a
ware reset operations. Hardware reset is only allowed RESET# pin in 8-pin SOIC and 8-contact WDFN pack-
using SPI x1 and x2 protocol in 8-pin SOIC and 8-con- ages, bit 6 of the configuration register must be set to
tact WDFN packages. 16-lead SOIC and 24-ball TBGA ‘1’. The factory default setting of bit 6 is ‘0’–HOLD# pin
packages have a dedicated Hardware Reset pin which enabled. This is a non-volatile bit, so the register value
is allowed in all modes of operations. Software reset at power-up will be the value prior to power-down. Any
commands 66H and 99H are supported in all package pin marked with only RESET# (16-lead SOIC and 24-
options and protocols. See Table 4-2 on page 10 for ball TFBGA packages) is a dedicated RESET# pin and
hardware and software reset functionality. has the same functionality as the multiplex I/O pins.
A device reset during an active Program or Erase oper- Driving the RESET# pin high puts the device in normal
ation aborts the operation, which can cause the data of operating mode. The RESET# pin must be driven low
the targeted address range to be corrupted or lost. for a minimum of TRST time to reset the device. The
Depending on the prior operation, the reset timing may SIO1 pin (SO) is in high impedance state while the
vary. Recovery from a Write operation requires more device is in reset. A successful Reset operation will
latency time than recovery from other operations. reset the protocol to SPI mode, clear status register bits
(BUSY=0, WEL=0, WSE=0, WSP=0 and WPLD=0)
except SEC bit, reset the burst length to 8 Bytes, and
write-protect Block-Protection Register bits. A device

SST26WF064C
reset during an active Program or Erase operation Once the Reset-Enable and Reset commands are suc-
aborts the operation, and data of the targeted address cessfully executed, the device returns to normal opera-
range may be corrupted or lost due to the aborted tion Read mode and then does the following: resets the
Erase or Program operation protocol to SPI mode, resets the burst length to 8
Bytes, clears all the bits, except for bit 4 (WPLD) and
4.5.2 SOFTWARE RESET OPERATION bit 5 (SEC), in the Status register to their default states,
The Reset operation requires the Reset-Enable com- and clears bit 1 (IOC) in the configuration register to its
mand followed by the Reset command. Any command default state.
other than the Reset command after the Reset-Enable
command will disable the Reset-Enable.
TABLE 4-2: HARDWARE AND SOFTWARE FUNCTIONALITY

Situation After Power Cycle After Hardware Reset After Software Reset
Write Protection bits in protection register are set to 1 are set to 1 are not affected
Read Protection bits in protection register are set to 0 are set to 0 are not affected
If the device was in SQI mode and was in a Yes Yes Mode Read has to be
Read mode with configuration bits M[7:0] = exited before Reset com-
AXH, then it will enter SPI mode mand will be accepted
If the device was in SQI mode and was not Yes Yes Yes
in a Read mode with configuration bits
M[7:0] = AXH, then it will enter SPI mode
Read Burst length is reset to 8 bytes Yes Yes Yes
Status register:
Busy=0, WEL=0, WSE=0, WSP=0 Yes Yes Yes
WPLD in status register equal to 0 equal to 0 is not affected
SEC bit is not affected. is not affected. is not affected.
Configuration register:
If the device was in SQI mode and was in a will equal to 0 will equal to 0 Mode Read has to be
Read mode with configuration bits M[7:0] = exited before Reset com-
AXH, then the IOC bit mand will be accepted
If the device was in SQI mode and was not will equal to 0 will equal to 0 will equal to 0
in a Read mode with configuration bits
M[7:0] = AXH, then the IOC bit
BPNV bit, RSTHLD bit and WPEN bit is not affected. is not affected. is not affected.

SST26WF064C
4.6 Status Register Protection register and/or Security ID are locked down.
During an internal Erase or Program operation, the Sta-
The Status register is a read-only register that provides tus register may be read to determine the completion of
the following status information: whether the flash an operation in progress. Table 4-3 describes the func-
memory array is available for any Read or Write oper- tion of each bit in the Status register.
ation, if the device is write-enabled, whether an erase
or program operation is suspended, and if the Block-
TABLE 4-3: STATUS REGISTER

Default at Read/Write (R/
Bit Name Function Power-up W)
0 BUSY Write operation status 0 R
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1 WEL Write-Enable Latch status 0 R
1 = Device is write-enabled
0 = Device is not write-enabled
2 WSE Write Suspend-Erase status 0 R
1 = Erase suspended
0 = Erase is not suspended
3 WSP Write Suspend-Program status 0 R
1 = Program suspended
0 = Program is not suspended
4 WPLD Write Protection Lock-Down status 0 R
1 = Write Protection Lock-Down enabled
0 = Write Protection Lock-Down disabled
5 SEC1 Security ID status 01 R
1 = Security ID space locked
0 = Security ID space not locked
6 RES Reserved for future use 0 R
7 BUSY Write operation status 0 R
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1. The Security ID status will always be ‘1’ at power-up after a successful execution of the Lockout Security ID instruction,
otherwise default at power-up is ‘0’.
4.6.1 WRITE-ENABLE LATCH (WEL) • Program Security ID instruction completion

The Write-Enable Latch (WEL) bit indicates the status • Lockout Security ID instruction completion
of the internal memory’s Write-Enable Latch. If the • Write-Suspend instruction
WEL bit is set to ‘1’, the device is write enabled. If the • SPI Quad Page Program
bit is set to ‘0’ (reset), the device is not write enabled • Write Status Register
and does not accept any memory Program or Erase,
Protection Register Write, or Lock-Down commands. 4.6.2 WRITE SUSPEND ERASE STATUS
The Write-Enable Latch bit is automatically reset under (WSE)
the following conditions:
The Write Suspend-Erase status (WSE) indicates
• Power-up when an Erase operation has been suspended. The
• Reset WSE bit is ‘1’ after the host issues a suspend command
• Write-Disable (WRDI) instruction during an Erase operation. Once the suspended Erase
• Page-Program instruction completion resumes, the WSE bit is reset to ‘0’.
• Sector-Erase instruction completion
• Block-Erase instruction completion
• Chip-Erase instruction completion
• Write-Block-Protection register instruction
• Lock-Down Block-Protection register instruction

SST26WF064C
4.6.3 WRITE SUSPEND PROGRAM

STATUS (WSP)
The Write Suspend-Program status (WSP) bit indicates
when a Program operation has been suspended. The
WSP is ‘1’ after the host issues a suspend command
during the Program operation. Once the suspended
Program resumes, the WSP bit is reset to ‘0’.
4.6.4 WRITE PROTECTION LOCK-DOWN

STATUS (WPLD)
The Write Protection Lock-Down status (WPLD) bit
indicates when the Block-Protection register is locked-
down to prevent changes to the protection settings.
The WPLD is ‘1’ after the host issues a Lock-Down
Block-Protection command. After a power cycle, the
WPLD bit is reset to ‘0’.
4.6.5 SECURITY ID STATUS (SEC)

The Security ID Status (SEC) bit indicates when the
Security ID space is locked to prevent a Write com-
mand. The SEC is ‘1’ after the host issues a Lockout
SID command. Once the host issues a Lockout SID
command, the SEC bit can never be reset to ‘0.’
4.6.6 BUSY
The Busy bit determines whether there is an internal
Erase or Program operation in progress. If the BUSY
bit is ‘1’, the device is busy with an internal Erase or
Program operation. If the bit is ‘0’, no Erase or Program
operation is in progress.

SST26WF064C
4.7 Configuration Register

The Configuration register is a Read/Write register that
stores a variety of configuration information. See Table
4-4 for the function of each bit in the register.
TABLE 4-4: CONFIGURATION REGISTER

Bit Name Function Default at Power-up Read/Write (R/W)
0 RES Reserved 0 R
IOC I/O Configuration
1 1 = WP# and RESET# or HOLD# pins disabled 01 R/W
0 = WP# and RESET# or HOLD# pins enabled
2 RES Reserved 0 R
BPNV Block-Protection Volatility State
3 1 = No memory block has been permanently locked 1 R
0 = Any block has been permanently locked
4 RES Reserved 0 R
5 RES Reserved 0 R
RSTHLD RESET# pin or HOLD# pin Enable
6 1 = RESET# pin enabled 02 R/W
0 = HOLD# pin enabled
WPEN Write-Protection Pin (WP#) Enable
7 1 = WP# enabled 02 R/W
0 = WP# disabled
1. SST26WF064C default at Power-up is ‘0’

2. Factory default setting. This is a non-volatile bit; default at power-up will be the setting prior to power-down.
4.7.1 I/O CONFIGURATION (IOC) 4.7.3 RESET/HOLD ENABLE (RSTHLD)

The I/O Configuration (IOC) bit re-configures the I/O The Reset/Hold Enable (RSTHLD) bit is a non-volatile
pins. The IOC bit is set by writing a ‘1’ to Bit 1 of the bit that configures RESET#/HOLD#/SIO3 pin to be
Configuration register. When IOC bit is ‘0’ the WP# pin either Reset# pin or Hold# pin.
and HOLD# pin are enabled (SPI or Dual Configuration
setup). When IOC bit is set to ‘1’ the SIO2 pin and SIO3 4.7.4 WRITE-PROTECT ENABLE (WPEN)
pin are enabled (SPI Quad I/O Configuration setup). The Write-Protect Enable (WPEN) bit is a non-volatile
The IOC bit must be set to ‘1’ before issuing the follow- bit that enables the WP# pin.
ing SPI commands: SQOR (6BH), SQIOR (EBH),
RBSPI (ECH), SPI Quad page program (32H), SQOR- The Write-Protect (WP#) pin and the Write-Protect
DTR (6DH), and SQIOR-DTR (EDH). Without setting Enable (WPEN) bit control the programmable hard-
the IOC bit to ‘1’, those SPI commands are not valid. ware write-protect feature. Setting the WP# pin to low,
The I/O configuration bit does not apply when in SQI and the WPEN bit to ‘1’, enables Hardware write-pro-
mode. The default at power-up for the SST26WF064C tection. To disable Hardware write protection, set either
is ‘0’. the WP# pin to high or the WPEN bit to ‘0’. There is
latency associated with writing to the WPEN bit. Poll
4.7.2 BLOCK-PROTECTION VOLATILITY the BUSY bit in the Status register, or wait TWPEN, for
STATE (BPNV) the completion of the internal, self-timed Write opera-
tion. When the chip is hardware write protected, only
The Block-Protection Volatility State bit indicates Write operations to Block-Protection and Configuration
whether any block has been permanently locked with registers are disabled.See “Hardware Write Protection”
the non-Volatile Write-Lock Lock-Down register on page 8 and Table 4-1 for more information about the
(nVWLDR). When no bits in the nVWLDR have been functionality of the WPEN bit.
set (the default state from the factory) the BPNV bit is
`1'; when one or more bits in the nVWLDR are set to `1'
the BPNV bit will also be `0' from that point forward,
even after power-up.

SST26WF064C
5.0 INSTRUCTIONS
Instructions are used to read, write (erase and pro-
gram), and configure the SST26WF064C. The com-
plete list of the instructions is provided in Table 5-1.
TABLE 5-1: DEVICE OPERATION INSTRUCTIONS FOR SST26WF064C (1 OF 2)

Command Mode Address Dummy Data Max
Instruction Description
Cycle1 SPI SQI Cycle(s)2, 3 Cycle(s)3 Cycle(s)3 Freq
Configuration
NOP No Operation 00H X X 0 0 0
RSTEN Reset Enable 66H X X 0 0 0
RST 4
Reset Memory 99H X X 0 0 0
EQIO Enable Quad I/O 38H X 0 0 0
RSTQIO5 Reset Quad I/O FFH X X 0 0 0 104
X 0 0 1 to  MHz
RDSR Read Status Register 05H
X 0 1 1 to 
WRSR Write Status Register 01H X X 0 0 2
Read Configuration X 0 0 1 to 
RDCR 35H
Register X 0 1 1 to 
Read
Read Read Memory 03H X 3 0 1 to  40 MHz
High-Speed Read Memory at X 3 3 1 to 
0BH
Read Higher Speed X 3 1 1 to 
104
SQOR6 SPI Quad Output Read 6BH X 3 1 1 to 
MHz
SQIOR7 SPI Quad I/O Read EBH X 3 3 1 to 
SDOR8 SPI Dual Output Read 3BH X 3 1 1 to 
SDIOR9 SPI Dual I/O Read BBH X 3 1 1 to  80 MHz
SB Set Burst Length C0H X X 0 0 1
SQI nB Burst with
RBSQI 0CH X 3 3 n to  104
Wrap
MHz
SPI nB Burst with
RBSPI7 ECH X 3 3 n to 
Wrap
High-Speed Read Memory at X 12 6 1 to 
0DH
Read - DTR10 Higher Speed - DTR X 3 6 1 to 
SQOR - SPI Quad Output Read -
6DH X 12 6 1 to 
DTR10,11 DTR
SQIOR -
SPI Quad I/O Read - DTR EDH X 3 6 1 to  54 MHz
DTR10,11
SDOR - SPI Dual-Output Read -
3DH X 12 6 1 to 
DTR10 DTR
SDIOR -
SPI Dual-I/O Read - DTR BDH X 6 6 1 to 
DTR10
Identification
JEDEC-ID JEDEC-ID Read 9FH X 0 0 3 to 
Quad J-ID Quad I/O J-ID Read AFH X 0 1 3 to  104
Serial Flash Discover- MHz
SFDP 5AH X 3 1 1 to 
able Parameters

SST26WF064C
TABLE 5-1: DEVICE OPERATION INSTRUCTIONS FOR SST26WF064C (CONTINUED) (2 OF 2)

Command Mode Address Dummy Data Max
Instruction Description
Cycle1 SPI SQI Cycle(s)2, 3 Cycle(s)3 Cycle(s)3 Freq
Write
WREN Write Enable 06H X X 0 0 0
WRDI Write Disable 04H X X 0 0 0
Erase 4 KBytes of
SE12 20H X X 3 0 0
Memory Array
104
Erase 64, 32 or 8 MHz
13
BE KBytes of Memory D8H X X 3 0 0
Array
CE Erase Full Array C7H X X 0 0 0
PP Page Program 02H X X 3 0 1 to 256
SPI Quad SPI Quad Page
32H X 3 0 1 to 256
PP7 Program
104
Suspends Program/
WRSU B0H X X 0 0 0 MHz
Erase
Resumes Program/
WRRE 30H X X 0 0 0
Erase
Protection
Read Block-Protection X 0 0 1 to18
RBPR 72H
Register X 0 1 1 to18
Write Block-Protection
WBPR 42H X X 0 0 1 to 18
Register
Lock Down Block-
LBPR 8DH X X 0 0 0
Protection Register
non-Volatile Write
nVWLDR E8H X X 0 0 1 to 18
Lock-Down Register 104
Global Block Protec- MHz
ULBPR 98H X X 0 0 0
tion Unlock
X 2 1 1 to 2048
RSID Read Security ID 88H
X 2 3 1 to 2048
Program User
PSID A5H X X 2 0 1 to 256
Security ID area
Lockout Security ID
LSID 85H X X 0 0 0
Programming
Power Saving
DPD Deep Power-down Mode B9H X X 0 0 0
104
Release from Deep
RDPD ABH X X 3 0 1 to  MHz
Power-down and Read ID
1. Command cycle is two clock periods in SQI mode and eight clock periods in SPI mode.
2. Address bits above the most significant bit of each density can be VIL or VIH.
3. Address, Dummy/Mode bits, and Data cycles are two clock periods in SQI and eight clock periods in SPI mode.
4. RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset.
5. Device accepts eight-clock command in SPI mode, or two-clock command in SQI mode.
6. Data cycles are two clock periods. IOC bit must be set to ‘1’ before issuing the command.
7. Address, Dummy/Mode bits, and data cycles are two clock periods. IOC bit must be set to ‘1’ before issuing the command.
8. Data cycles are four clock periods.
9. Address, Dummy/Mode bits, and Data cycles are four clock periods.
10. For DTR commands, the number of clocks is listed for address and dummy.
11. IOC bit must be set to ‘1’ before issuing the command.
12. Sector Addresses: Use AMS - A12, remaining address are don’t care, but must be set to VIL or VIH.
13. Blocks are 64 KByte, 32 KByte, or 8KByte, depending on location. Block Erase Address: AMS - A16 for 64 KByte; AMS - A15
for 32 KByte; AMS - A13 for 8 KByte. Remaining addresses are don’t care, but must be set to VIL or VIH.

SST26WF064C
5.1 No Operation (NOP) To reset the SST26WF064C, the host drives CE# low,
sends the Reset-Enable command (66H), and drives
The No Operation command only cancels a Reset- CE# high. Next, the host drives CE# low again, sends
Enable command. NOP has no impact on any other the Reset command (99H), and drives CE# high, see
command. Figure 5-1.
A device reset during an active Program or Erase oper-
5.2 Reset-Enable (RSTEN) and Reset ation aborts the operation, which can cause the data of
(RST) the targeted address range to be corrupted or lost.
The Reset operation is used as a system (software) Depending on the prior operation, the reset timing may
reset that puts the device in normal operating Ready vary. Recovery from a Write operation requires more
mode. This operation consists of two commands: latency time than recovery from other operations. See
Reset-Enable (RSTEN) followed by Reset (RST). Table 8-3 on page 54 for Rest timing parameters.
FIGURE 5-1: RESET SEQUENCE

TCPH
CE#
MODE 3 MODE 3 MODE 3
CLK
SIO(3:0) C1 C0 C3 C2
20005430 F05.0
Note: C[1:0] = 66H; C[3:2] = 99H
5.3 Read (40 MHz) will automatically increment until the highest memory
address is reached. Once the highest memory address
The Read instruction, 03H, is supported in SPI bus pro- is reached, the address pointer will automatically return
tocol only with clock frequencies up to 40 MHz. This to the beginning (wrap-around) of the address space.
command is not supported in SQI bus protocol. The
device outputs the data starting from the specified Initiate the Read instruction by executing an 8-bit com-
address location, then continuously streams the data mand, 03H, followed by address bits A[23:0]. CE# must
output through all addresses until terminated by a low- remain active low for the duration of the Read cycle.
to-high transition on CE#. The internal address pointer See Figure 5-2 for Read Sequence.
FIGURE 5-2: READ SEQUENCE (SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 70
SCK MODE 0
SI 03 ADD. ADD. ADD.

MSB MSB
N N+1 N+2 N+3 N+4
HIGH IMPEDANCE DOUT DOUT DOUT DOUT DOUT
SO
MSB
5.4 Enable Quad I/O (EQIO)

The Enable Quad I/O (EQIO) instruction, 38H, enables
the flash device for SQI bus operation. Upon comple-
tion of the instruction, all instructions thereafter are
expected to be 4-bit multiplexed input/output (SQI
mode) until a power cycle or a “Reset Quad I/O instruc-
tion” is executed. See Figure 5-3.

SST26WF064C
FIGURE 5-3: ENABLE QUAD I/O SEQUENCE
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SIO0 38
SIO[3:1]
20005430 F43.0
Note: SIO[3:1] must be driven VIH
5.5 Reset Quad I/O (RSTQIO) where it can accept new SQI command instruction. An
additional RSTQIO is required to reset the device to
The Reset Quad I/O instruction, FFH, resets the device SPI mode.
to 1-bit SPI protocol operation or exits the Set Mode
configuration during a read sequence. This command To execute a Reset Quad I/O operation, the host drives
allows the flash device to return to the default I/O state CE# low, sends the Reset Quad I/O command cycle
(SPI) without a power cycle, and executes in either 1- (FFH) then, drives CE# high. Execute the instruction in
bit or 4-bit mode. If the device is in the Set Mode con- either SPI (8 clocks) or SQI (2 clocks) command
figuration, while in SQI High-Speed Read mode, the cycles. For SPI, SIO[3:1] are don’t care for this com-
RSTQIO command will only return the device to a state mand, but should be driven to VIH or VIL. See Figures
5-4 and 5-5.
FIGURE 5-4: RESET QUAD I/O SEQUENCE (SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SIO0 FF
SIO[3:1]
20005430 F73.0
Note: SIO[3:1]
FIGURE 5-5: RESET QUAD I/O SEQUENCE (SQI)

CE#
MODE 3 0 1
SCK MODE 0
SIO(3:0) F F
20005430 F74.0

SST26WF064C
5.6 High-Speed Read (104 MHz) Initiate High-Speed Read by executing an 8-bit com-
mand, 0BH, followed by address bits A[23-0] and a
The High-Speed Read instruction, 0BH, is supported in dummy byte. CE# must remain active low for the dura-
both SPI bus protocol and SQI protocol. On power-up, tion of the High-Speed Read cycle. See Figure 5-6 for
the device is set to use SPI. the High-Speed Read sequence for SPI bus protocol.
FIGURE 5-6: HIGH-SPEED READ SEQUENCE (SPI) (C[1:0] = 0BH)

CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 80
SCK MODE 0
SI/SIO0 0B ADD. ADD. ADD. X
N N+1 N+2 N+3 N+4

HIGH IMPEDANCE
SO/SIO1 DOUT DOUT DOUT DOUT DOUT
MSB
20005430 F31.0
In SQI protocol, the host drives CE# low then sends the mand, 0BH, and does not require the op-code to be
Read command cycle command, 0BH, followed by entered again. The host may initiate the next Read
three address cycles, a Set Mode Configuration cycle, cycle by driving CE# low, then sending the four-bits
and two dummy cycles. Each cycle is two nibbles input for address A[23:0], followed by the Set Mode
(clocks) long, most significant nibble first. configuration bits M[7:0], and two dummy cycles. After
After the dummy cycles, the device outputs data on the the two dummy cycles, the device outputs the data
falling edge of the SCK signal starting from the speci- starting from the specified address location. There are
fied address location. The device continually streams no restrictions on address location access.
data output through all addresses until terminated by a When M[7:0] is any value other than AXH, the device
low-to-high transition on CE#. The internal address expects the next instruction initiated to be a command
pointer automatically increments until the highest mem- instruction. To reset/exit the Set Mode configuration,
ory address is reached, at which point the address execute the Reset Quad I/O command, FFH. While in
pointer returns to address location 000000H. During the Set Mode configuration, the RSTQIO command will
this operation, blocks that are Read-locked will output only return the device to a state where it can accept
data 00H. new SQI command instruction. An additional RSTQIO
The Set Mode Configuration bits M[7:0] indicates if the is required to reset the device to SPI mode. See Figure
next instruction cycle is another SQI High-Speed Read 5-10 for the SPI Quad I/O Mode Read sequence when
command. When M[7:0] = AXH, the device expects the M[7:0] = AXH.
next continuous instruction to be another Read com-
FIGURE 5-7: HIGH-SPEED READ SEQUENCE (SQI)

CE#
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 20 21
SCK
MODE 0 MSN LSN
SIO(3:0) C0 C1 A5 A4 A3 A2 A1 A0 M1 M0 X X X X H0 L0 H8 L8
Command Address Mode Dummy Data Byte 0 Data Byte 7
20005430 F47.0
Note: MSN= Most Significant Nibble, LSN = Least Significant Nibble
Hx = High Data Nibble, Lx = Low Data Nibble C[1:0] = 0BH

SST26WF064C
5.7 SPI Quad-Output Read Following the dummy byte, the device outputs data
from SIO[3:0] starting from the specified address loca-
The SPI Quad-Output Read instruction supports up to tion. The device continually streams data output
104 MHz frequency. The SST26WF064C requires the through all addresses until terminated by a low-to-high
IOC bit in the configuration register to be set to ‘1’ prior transition on CE#. The internal address pointer auto-
to executing the command. Initiate SPI Quad-Output matically increments until the highest memory address
Read by executing an 8-bit command, 6BH, followed is reached, at which point the address pointer returns
by address bits A[23-0] and a dummy byte. CE# must to the beginning of the address space.
remain active low for the duration of the SPI Quad Out-
put Read. See Figure 5-8 for the SPI Quad Output
Read sequence.
FIGURE 5-8: SPI QUAD OUTPUT READ
CE#
MODE 3
0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 41
SCK MODE 0
SIO0 6BH A[23:16] A[15:8] A[7:0] X b4 b0 b4 b0

Data Data
OP Code Address Dummy Byte 0 Byte N
SIO1 b5 b1 b5 b1
SIO2 b6 b2 b6 b2
SIO3 b7 b3 b7 b3
20005430 F48.3

SST26WF064C
5.8 SPI Quad I/O Read The Set Mode Configuration bits M[7:0] indicates if the
next instruction cycle is another SPI Quad I/O Read
The SPI Quad I/O Read (SQIOR) instruction supports up command. When M[7:0] = AXH, the device expects the
to 104 MHz frequency. The SST26WF064C requires the next continuous instruction to be another Read com-
IOC bit in the configuration register to be set to ‘1’ prior to mand, EBH, and does not require the op-code to be
executing the command. Initiate SQIOR by executing an entered again. The host may set the next SQIOR cycle
8-bit command, EBH. The device then switches to 4-bit I/ by driving CE# low, then sending the four-bit wide input
O mode for address bits A[23-0], followed by the Set for address A[23:0], followed by the Set Mode configu-
Mode configuration bits M[7:0], and two dummy ration bits M[7:0], and two dummy cycles. After the two
bytes.CE# must remain active low for the duration of the dummy cycles, the device outputs the data starting
SPI Quad I/O Read. See Figure 5-9 for the SPI Quad I/ from the specified address location. There are no
O Read sequence. restrictions on address location access.
Following the dummy bytes, the device outputs data When M[7:0] is any value other than AXH, the device
from the specified address location. The device contin- expects the next instruction initiated to be a command
ually streams data output through all addresses until instruction. To reset/exit the Set Mode configuration,
terminated by a low-to-high transition on CE#. The execute the Reset Quad I/O command, FFH. See Fig-
internal address pointer automatically increments until ure 5-10 for the SPI Quad I/O Mode Read sequence
the highest memory address is reached, at which point when M[7:0] = AXH.
the address pointer returns to the beginning of the
address space.
FIGURE 5-9: SPI QUAD I/O READ SEQUENCE

CE#
MODE 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK MODE 0
SIO0 EBH A20 A16 A12 A8 A4 A0 M4 M0 X X X X b4 b0 b4 b0
SIO1 A21 A17 A13 A9 A5 A1 M5 M1 X X X X b5 b1 b5 b1

MSN LSN

Set Data Data
Address Mode Dummy Byte 0 Byte 1
20005430 F49.2
Note: MSN

SST26WF064C
FIGURE 5-10: BACK-TO-BACK SPI QUAD I/O READ SEQUENCES WHEN M[7:0] = AXH
CE#
0 1 2 3 4 5 6 7 8 9 10 11 12 13
SCK
SIO0 b4 b0 b4 b0 A20 A16 A12 A8 A4 A0 M4 M0 X X X X b4 b0

MSN LSN
Data Data Set Data
Byte Byte Address Mode Dummy Byte 0
N N+1
20005430 F50.2
Note: MSN= Most Sig-
5.9 Set Burst sends the Set Burst command cycle (C0H) and one
data cycle, then drives CE# high. After power-up or
The Set Burst command specifies the number of bytes reset, the burst length is set to eight Bytes (00H). See
to be output during a Read Burst command before the Table 5-2 for burst length data and Figures 5-11 and 5-
device wraps around. It supports both SPI and SQI pro- 12 for the sequences.
tocols. To set the burst length the host drives CE# low,
TABLE 5-2: BURST LENGTH DATA

Burst Length High Nibble (H0) Low Nibble (L0)
8 Bytes 0h 0h
16 Bytes 0h 1h
32 Bytes 0h 2h
64 Bytes 0h 3h
FIGURE 5-11: SET BURST LENGTH SEQUENCE (SQI)
CE#
MODE 3 0 1 2 3
SCK MODE 0
SIO(3:0) C1 C0 H0 L0
MSN LSN
20005430 F32.0
Note: MSN = Most Significant Nibble,
LSN = Least Significant Nibble, C[1:0] = C0H

SST26WF064C
FIGURE 5-12: SET BURST LENGTH SEQUENCE (SPI)

CE#
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK MODE 0
SIO0 C0 DIN
SIO[3:1]
20005430 F51.0
Note: SIO[3:1] must be
5.10 SQI Read Burst with Wrap (RBSQI) 5.11 SPI Read Burst with Wrap (RBSPI)
SQI Read Burst with wrap is similar to High Speed SPI Read Burst with Wrap (RBSPI) is similar to SPI
Read in SQI mode, except data will output continuously Quad I/O Read except the data will output continuously
within the burst length until a low-to-high transition on within the burst length until a low-to-high transition on
CE#. To execute a SQI Read Burst operation, drive CE#. To execute a SPI Read Burst with Wrap opera-
CE# low then send the Read Burst command cycle tion, drive CE# low, then send the Read Burst com-
(0CH), followed by three address cycles, and then mand cycle (ECH), followed by three address cycles,
three dummy cycles. Each cycle is two nibbles (clocks) and then three dummy cycles.
long, most significant nibble first. After the dummy cycle, the device outputs data on the
After the dummy cycles, the device outputs data on the falling edge of the SCK signal starting from the speci-
falling edge of the SCK signal starting from the specified address location. The data output stream is contin-
fied address location. The data output stream is continuous through all addresses until terminated by a low-to-
uous through all addresses until terminated by a low-to- high transition on CE#.
high transition on CE#. During RBSPI, the internal address pointer automati-
During RBSQI, the internal address pointer automatically increments until the last byte of the burst is
cally increments until the last byte of the burst is reached, then it wraps around to the first byte of the
reached, then it wraps around to the first byte of the burst. All bursts are aligned to addresses within the
burst. All bursts are aligned to addresses within the burst length, see Table 5-3. For example, if the burst
burst length, see Table 5-3. For example, if the burst length is eight Bytes, and the start address is 06h, the
length is eight Bytes, and the start address is 06h, the burst sequence would be: 06h, 07h, 00h, 01h, 02h,
burst sequence would be: 06h, 07h, 00h, 01h, 02h, 03h, 04h, 05h, 06h, etc. The pattern repeats until the
03h, 04h, 05h, 06h, etc. The pattern repeats until the command is terminated by a low-to-high transition on
command is terminated by a low-to-high transition on CE#.
CE#. During this operation, blocks that are Read-locked will
During this operation, blocks that are Read-locked will output data 00H.
output data 00H.
TABLE 5-3: BURST ADDRESS RANGES

Burst Length Burst Address Ranges
8 Bytes 00-07H, 08-0FH, 10-17H, 18-1FH...
16 Bytes 00-0FH, 10-1FH, 20-2FH, 30-3FH...
32 Bytes 00-1FH, 20-3FH, 40-5FH, 60-7FH...
64 Bytes 00-3FH, 40-7FH, 80-BFH, C0-FFH

SST26WF064C
5.12 SPI Dual-Output Read Following the dummy byte, the SST26WF064C outputs
data from SIO[1:0] starting from the specified address
The SPI Dual-Output Read instruction supports up to location. The device continually streams data output
104 MHz frequency. Initiate SPI Dual-Output Read by through all addresses until terminated by a low-to-high
executing an 8-bit command, 3BH, followed by address transition on CE#. The internal address pointer auto-
bits A[23-0] and a dummy byte. CE# must remain matically increments until the highest memory address
active low for the duration of the SPI Dual-Output Read is reached, at which point the address pointer returns
operation. See Figure 5-13 for the SPI Quad Output to the beginning of the address space.
Read sequence.
FIGURE 5-13: FAST READ, DUAL-OUTPUT SEQUENCE

CE#
MODE 3
0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 41
SCK MODE 0
SIO0 3BH A[23:16] A[15:8] A[7:0] X b6 b5 b3 b1 b6 b5 b3 b1

MSB
SIO1 b7 b4 b2 b0 b7 b4 b2 b0
Data Data
OP Code Address Dummy Byte 0 Byte N
Note: MSB = Most Significant Bit. 20005430 F52.3
5.13 SPI Dual I/O Read execute the Reset Quad I/O command, FFH. See Fig-
ure 5-15 for the SPI Dual I/O Read sequence when
The SPI Dual I/O Read (SDIOR) instruction supports M[7:0] = AXH.
up to 80 MHz frequency. Initiate SDIOR by executing
an 8-bit command, BBH. The device then switches to
2-bit I/O mode for address bits A[23-0], followed by the
Set Mode configuration bits M[7:0]. CE# must remain
active low for the duration of the SPI Dual I/O Read.
See Figure 5-14 for the SPI Dual I/O Read sequence.
Following the Set Mode configuration bits M[7:0], the
SST26WF064C outputs data from the specified
address location. The device continually streams data
output through all addresses until terminated by a low-
to-high transition on CE#. The internal address pointer
automatically increments until the highest memory
address is reached, at which point the address pointer
returns to the beginning of the address space.
The Set Mode Configuration bit M[7:0] indicates if the
next instruction cycle is another SPI Dual I/O Read
command. When M[7:0] = AXH, the device expects the
next continuous instruction to be another SDIOR com-
mand, BBH, and does not require the op-code to be
entered again. The host may set the next SDIOR cycle
by driving CE# low, then sending the two-bit wide input
for address A[23:0], followed by the Set Mode configu-
ration bits M[7:0]. After the Set Mode configuration bits,
the device outputs the data starting from the specified
address location. There are no restrictions on address
location access.
When M[7:0] is any value other than AXH, the device
expects the next instruction initiated to be a command
instruction. To reset/exit the Set Mode configuration,

SST26WF064C
FIGURE 5-14: SPI DUAL I/O READ SEQUENCE

CE#
MODE 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK MODE 0
SIO0 BBH 6 4 2 0 6 4 2 0 6 4 2 0 6 4
SIO1 7 5 3 1 7 5 3 1 7 5 3 1 7 5
A[23:16] A[15:8] A[7:0] M[7:0]
CE#(cont’)
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK(cont’)
I/O Switches from Input to Output
SIO0(cont’) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
MSB MSB MSB MSB
SIO1(cont’) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
Byte 0 Byte 1 Byte 2 Byte 3
20005430 F53.1
Note: MSN=
FIGURE 5-15: BACK-TO-BACK SPI DUAL I/O READ SEQUENCES WHEN M[7:0] = AXH
CE#
MODE 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK MODE 0
I/O Switch
SIO0 6 4 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4
MSB MSB
SIO1 7 5 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5
A[23:16] A[15:8] A[7:0] M[7:0]
CE#(cont’)
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK(cont’)
I/O Switches from Input to Output
SIO0(cont’) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
MSB MSB MSB MSB
SIO1(cont’) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
Byte 0 Byte 1 Byte 2 Byte 3
20005430 F54.1
Note: MSN= Most

SST26WF064C
5.14 Dual-Transfer Rate (DTR) The Set Mode Configuration bits M[7:0] indicate if the
next instruction cycle is another DTR Read command.
Initiate all Dual-Transfer Rate read modes by executing When M[7:0] = AXH, the device expects the next con-
an 8-bit DTR Read command. The device then tinuous instruction to be another DTR Read command,
switches to dual-data rate for the address, set mode and does not require the op-code to be entered again.
configuration bits M[7:0], and dummy clock cycles. Fol- Set the next DTR cycle by driving CE# low, then send-
lowing the dummy bytes, the device outputs data from ing the address A[23:0], followed by the Set Mode con-
the specified address location. The device continually figuration bits M[7:0], and dummy clock cycles. After
streams data output through all addresses until termi- the dummy cycles, the device outputs the data starting
nated by a low-to-high transition on CE#. The internal from the specified address location. There are no
address pointer automatically increments until the high- restrictions on address location access.
est memory address is reached, at which point the
address pointer returns to the beginning of the address
space.
CE#
MODE 3 0 7 8 9 10 11 12 16 17 18
SCK MODE 0
SIO0 EDH A20 A16 A12 A8 A4 A0 M4 M0 X X b4 b0 b4 b0
SIO1 A21 A17 A13 A9 A5 A1 M5 M1 X X b5 b1 b5 b1

MSN LSN
Address Set Dummy Data Data

Mode Byte0 Byte1
20005430 DTR 1.1
FIGURE 5-16: SPI QUAD I/O READ – DTR
CE#
MODE 3 0 7 8 18 19 20 25 26 27
SCK MODE 0
SIO0 3D A23 A22 A21 A1 A0 X X b6 b4 b2 b0
Address Dummy
SIO1 b7 b5 b3 b1
MSN LSN
Data Byte0
20005430 DTR 2.0
FIGURE 5-17: SPI DUAL OUTPUT READ – DTR

SST26WF064C
CE#
MODE 3 0 7 8 18 19 20 25 26 27
SCK MODE 0
SIO0 6D A23 A22 A21 A1 A0 X X b4 b0 b4 b0
Address Dummy
SIO1 b5 b1 b5 b1
SIO2 b6 b2 b6 b2
SIO3 b7 b3 b7 b3
MSN LSN
Data Data
Byte0 Byte1
20005430 DTR 3.0
FIGURE 5-18: SPI QUAD OUTPUT READ – DTR
CE#
MODE 3 0 1 2 3 4 5 6 10 11 12
SCK MODE 0
Command = 0DH
SIO0 0 1 A20 A16 A12 A8 A4 A0 M4 M0 X X b4 b0 b4 b0

MSN LSN
Address Set Dummy Data Data

Mode Byte0 Byte1
20005430 DTR 4.0
FIGURE 5-19: SQI HIGH-SPEED READ – DTR

SST26WF064C
CE#
MODE 3 0 7 8 13 14 15 16 19 20 21
SCK MODE 0
SIO0 BDH A22 A20 A2 A0 M6 M4 M2 M0 X X b6 b4 b2 b0
SIO1 A23 A21 A3 A1 M7 M5 M3 M1 X X b7 b5 b3 b1

MSN LSN
Set
Address Mode Dummy Data Byte0
20005430 DTR 5.0

FIGURE 5-20: SPI DUAL I/O READ – DTR
CE#
MODE 3 0 7 8 18 19 20 25 26 27 28 29
SCK MODE 0
SIO0 0D A23 A22 A21 A1 A0 X
Address Dummy
SIO1 b7 b6 b5 b4 b3 b2 b1 b0
MSN LSN
Data Byte0
20005430 DTR 6.0
FIGURE 5-21: SPI HIGH-SPEED READ – DTR

SST26WF064C
5.15 JEDEC-ID Read (SPI Protocol) Immediately following the command cycle,
SST26WF064C outputs data on the falling edge of the
Using traditional SPI protocol, the JEDEC-ID Read SCK signal. The data output stream is continuous until
instruction identifies the device as SST26WF064C and terminated by a low-to-high transition on CE#. The
the manufacturer as Microchip. To execute a JECEC- device outputs three bytes of data: manufacturer,
ID operation the host drives CE# low then sends the device type, and device ID, see Table 5-4. See Figure
JEDEC-ID command cycle (9FH). 5-22 for instruction sequence.
TABLE 5-4: DEVICE ID DATA OUTPUT

Device ID
Product Manufacturer ID (Byte 1) Device Type (Byte 2) Device ID (Byte 3)
SST26WF064C BFH 26H 53H
FIGURE 5-22: JEDEC-ID SEQUENCE (SPI MODE)

CE#
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCK MODE 0
SI 9F
HIGH IMPEDANCE
SO BF 26 Device ID
MSB MSB
2005430 F38.0
5.16 Read Quad J-ID Read (SQI Immediately following the command cycle, and one
Protocol) dummy cycle, SST26WF064C outputs data on the fall-
ing edge of the SCK signal. The data output stream is
The Read Quad J-ID Read instruction identifies the continuous until terminated by a low-to-high transition
device as SST26WF064C and manufacturer as Micro- of CE#. The device outputs three bytes of data: manu-
chip. To execute a Quad J-ID operation the host drives facturer, device type, and device ID, see Table 5-4. See
CE# low and then sends the Quad J-ID command cycle Figure 5-23 for instruction sequence.
(AFH). Each cycle is two nibbles (clocks) long, most
significant nibble first.
FIGURE 5-23: QUAD J-ID READ SEQUENCE

CE#
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 N
SCK
MODE 0 MSN LSN
SIO(3:0) C0 C1 X X H0 L0 H1 L1 H2 L2 H0 L0 H1 L1 HN LN
Dummy BFH 26H Device ID BFH 26H N
2005430 F55.0
Note: MSN = Most significant Nibble; LSN= Least Significant Nibble, C[1:0]=AFH

SST26WF064C
5.17 Serial Flash Discoverable ware support for all future Serial Flash device families.
Parameters (SFDP) See Table 11-1 on page 72 for address and data val-
ues.
The Serial Flash Discoverable Parameters (SFDP)
Initiate SFDP by executing an 8-bit command, 5AH, fol-
contain information describing the characteristics of the
lowed by address bits A[23-0] and a dummy byte. CE#
device. This allows device-independent, JEDEC ID-
must remain active low for the duration of the SFDP
independent, and forward/backward compatible soft-
cycle. For the SFDP sequence, see Figure 5-24.
FIGURE 5-24: SERIAL FLASH DISCOVERABLE PARAMETERS SEQUENCE

CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 80
SCK MODE 0
SI 5A ADD. ADD. ADD. X
N N+1 N+2 N+3 N+4

HIGH IMPEDANCE
SO DOUT DOUT DOUT DOUT DOUT
MSB
2005430 F56.0
5.18 Sector-Erase To execute a Sector-Erase operation, the host drives

CE# low, then sends the Sector Erase command cycle
The Sector-Erase instruction clears all bits in the (20H) and three address cycles, and then drives CE#
selected 4 KByte sector to ‘1,’ but it does not change a high. Address bits [AMS:A12] (AMS = Most Significant
protected memory area. Prior to any write operation, Address) determine the sector address (SAX); the
the Write-Enable (WREN) instruction must be exe- remaining address bits can be VIL or VIH. To identify the
cuted. completion of the internal, self-timed, Write operation,
poll the BUSY bit in the Status register, or wait TSE. See
Figures 5-25 and 5-26 for the Sector-Erase sequence.
FIGURE 5-25: 4 KBYTE SECTOR-ERASE SEQUENCE– SQI MODE (C[1:0] = 20 H)

CE#
MODE 3 0 1 2 4 6
SCK MODE 0
SIO(3:0) C1 C0 A5 A4 A3 A2 A1 A0
MSN LSN
2005430 F07.0
Note: MSN = Most Signifi-
cant Nibble LSN = Least Significant Nibble C[1:0]=20H
FIGURE 5-26: 4 KBYTE SECTOR-ERASE SEQUENCE (SPI)

CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31
SCK MODE 0
SI 20 ADD. ADD. ADD.

MSB MSB
SO HIGH IMPEDANCE
20005430 F57.0

SST26WF064C
5.19 Block-Erase To execute a Block-Erase operation, the host drives

CE# low then sends the Block-Erase command cycle
The Block-Erase instruction clears all bits in the (D8H), three address cycles, then drives CE# high.
selected block to ‘1’. Block sizes can be 8 KByte, 32 Address bits AMS-A13 determine the block address
KByte or 64 KByte depending on address, see Figure (BAX); the remaining address bits can be VIL or VIH. For
3-1, Memory Map, for details. A Block-Erase instruction 32 KByte blocks, A14:A13 can be VIL or VIH; for 64
applied to a protected memory area will be ignored. KByte blocks, A15:A13 can be VIL or VIH. Poll the BUSY
Prior to any write operation, execute the WREN instruc- bit in the Status register, or wait TBE, for the completion
tion. Keep CE# active low for the duration of any com- of the internal, self-timed, Block-Erase operation. See
mand sequence. Figures 5-27 and 5-28 for the Block-Erase sequence.
FIGURE 5-27: BLOCK-ERASE SEQUENCE (SQI)
CE#
MODE 3 0 1 2 4 6
SCK MODE 0
SIO(3:0) C1 C0 A5 A4 A3 A2 A1 A0
MSN LSN
20005430 F08.0
Note: MSN = Most Significant Nibble,

LSN = Least Significant Nibble
C[1:0] = D8H
FIGURE 5-28: BLOCK-ERASE SEQUENCE (SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31
SCK MODE 0
SI D8 ADDR ADDR ADDR

MSB MSB
SO HIGH IMPEDANCE
20005430 F58.0

SST26WF064C
5.20 Chip-Erase To execute a Chip-Erase operation, the host drives

CE# low, sends the Chip-Erase command cycle (C7H),
The Chip-Erase instruction clears all bits in the device then drives CE# high. Wait TSCE, for the completion of
to ‘1.’ The Chip-Erase instruction is ignored if any of the the internal, self-timed, Write operation. Alternatively,
memory area is protected. Prior to any write operation, wait 20 µs and then poll the BUSY bit in the status reg-
execute the WREN instruction. ister. See Figures 5-29 and 5-30 for the Chip Erase
sequence.
FIGURE 5-29: CHIP-ERASE SEQUENCE (SQI)
CE#
MODE 3 0 1
SCK MODE 0
SIO(3:0) C1 C10
20005430 F09.1
Note: C[1:0] = C7H
FIGURE 5-30: CHIP-ERASE SEQUENCE (SPI)

CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SI C7
MSB
SO HIGH IMPEDANCE
20005430 F59.0

SST26WF064C
5.21 Page-Program partial Byte to be ignored. Poll the BUSY bit in the Sta-
tus register, or wait TPP, for the completion of the inter-
The Page-Program instruction programs up to 256 nal, self-timed, Block-Erase operation. See Figures 5-
Bytes of data in the memory, and supports both SPI 31 and 5-32 for the Page-Program sequence.
and SQI protocols. The data for the selected page
address must be in the erased state (FFH) before initi- When executing Page-Program, the memory range for
ating the Page-Program operation. A Page-Program the SST26WF064C is divided into 256 Byte page
applied to a protected memory area will be ignored. boundaries. The device handles shifting of more than
Prior to the program operation, execute the WREN 256 Bytes of data by maintaining the last 256 Bytes of
instruction. data as the correct data to be programmed. If the target
address for the Page-Program instruction is not the
To execute a Page-Program operation, the host drives beginning of the page boundary (A[7:0] are not all
CE# low then sends the Page Program command cycle zero), and the number of bytes of data input exceeds or
(02H), three address cycles followed by the data to be overlaps the end of the address of the page boundary,
programmed, then drives CE# high. The programmed the excess data inputs wrap around and will be pro-
data must be between 1 to 256 Bytes and in whole Byte grammed at the start of that target page.
increments; sending less than a full Byte will cause the
FIGURE 5-31: PAGE-PROGRAM SEQUENCE (SQI)

CE#
MODE 3 0 2 4 6 8 10 12
SCK MODE 0
SIO(3:0) C1 C0 A5 A4 A3 A2 A1 A0 H0 L0 H1 L1 H2 L2 HN LN
MSN LSN
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 255
20005430 F10.1
Note:
MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = 02H
FIGURE 5-32: PAGE-PROGRAM SEQUENCE (SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39
SCK MODE 0
SI 02 ADD. ADD. ADD. Data Byte 0

MSB LSB MSB LSB MSB LSB
SO
HIGH IMPEDANCE
CE#(cont’)
2072
2073
2074
2075
2076
2077
2078
2079
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCK(cont’)
SI(cont’) Data Byte 1 Data Byte 2 Data Byte 255

MSB LSB MSB LSB MSB LSB
SO(cont’)
HIGH IMPEDANCE
20005430 F60.1
Note: C[1:0] =
02H

SST26WF064C
5.22 SPI Quad Page-Program mand cycle is eight clocks long, the address and data
cycles are each two clocks long, most significant bit
The SPI Quad Page-Program instruction programs up first. Poll the BUSY bit in the Status register, or wait TPP,
to 256 Bytes of data in the memory. The data for the for the completion of the internal, self-timed, Write
selected page address must be in the erased state operation.See Figure 5-33.
(FFH) before initiating the SPI Quad Page-Program
operation. A SPI Quad Page-Program applied to a pro- When executing SPI Quad Page-Program, the memory
tected memory area will be ignored. The range for the SST26WF064C is divided into 256 Byte
SST26WF064C requires the ICO bit in the configura- page boundaries. The device handles shifting of more
tion register to be set to ‘1’ prior to executing the com- than 256 Bytes of data by maintaining the last 256
mand.Prior to the program operation, execute the Bytes of data as the correct data to be programmed. If
WREN instruction. the target address for the SPI Quad Page-Program
instruction is not the beginning of the page boundary
To execute a SPI Quad Page-Program operation, the (A[7:0] are not all zero), and the of bytes of data input
host drives CE# low then sends the SPI Quad Page- exceeds or overlaps the end of the address of the page
Program command cycle (32H), three address cycles boundary, the excess data inputs wrap around and will
followed by the data to be programmed, then drives be programmed at the start of that target page.
CE# high. The programmed data must be between 1 to
256 Bytes and in whole Byte increments. The com-
FIGURE 5-33: SPI QUAD PAGE-PROGRAM SEQUENCE

CE#
MODE 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SCK MODE 0
SIO0 32H A20A16A12 A8 A4 A0 b4 b0 b4 b0 b4 b0
SIO1 A21 A17A13 A9 A5 A1 b5 b1 b5 b1 b5 b1
SIO2 A22 A18A14A10 A6 A2 b6 b2 b6 b2 b6 b2

MSN LSN
SIO3 A23 A19 A15 A11 A7 A3 b7 b3 b7 b3 b7 b3

Data Data Data
Address Byte 0 Byte 1 Byte
255
20005430 F61.1
5.23 Write-Suspend and Write-Resume 5.24 Write-Suspend During Sector-

Write-Suspend allows the interruption of Sector-Erase,
Erase or Block-Erase
Block-Erase, SPI Quad Page-Program, or Page-Pro- Issuing a Write-Suspend instruction during Sector-
gram operations in order to erase, program, or read Erase or Block-Erase allows the host to program or
data in another portion of memory. The original opera- read any sector that was not being erased. The device
tion can be continued with the Write-Resume com- will ignore any programming commands pointing to the
mand. This operation is supported in both SQI and SPI suspended sector(s). Any attempt to read from the sus-
protocols. pended sector(s) will output unknown data because the
Only one write operation can be suspended at a time; Sector- or Block-Erase will be incomplete.
if an operation is already suspended, the device will To execute a Write-Suspend operation, the host drives
ignore the Write-Suspend command. Write-Suspend CE# low, sends the Write Suspend command cycle
during Chip-Erase is ignored; Chip-Erase is not a valid (B0H), then drives CE# high. The Status register indi-
command while a write is suspended. The Write- cates that the erase has been suspended by changing
Resume command is ignored until any write operation the WSE bit from ‘0’ to ‘1,’ but the device will not accept
(Program or Erase) initiated during the Write-Suspend another command until it is ready. To determine when
is complete. The device requires a minimum of 500 µs the device will accept a new command, poll the BUSY
between each Write-Suspend command. bit in the Status register or wait TWS.

SST26WF064C
5.25 Write Suspend During Page a Read Security ID operation in SQI mode, the host
Programming or SPI Quad Page drives CE# low and then sends the Read Security ID
command, two address cycles, and three dummy
Programming
cycles.
Issuing a Write-Suspend instruction during Page Pro- After the dummy cycles, the device outputs data on the
gramming allows the host to erase or read any sector falling edge of the SCK signal, starting from the speci-
that is not being programmed. Erase commands point- fied address location. The data output stream is contin-
ing to the suspended sector(s) will be ignored. Any uous through all SID addresses until terminated by a
attempt to read from the suspended page will output low-to-high transition on CE#. See Table 5-5 for the
unknown data because the program will be incomplete. Security ID address range.
To execute a Write Suspend operation, the host drives
CE# low, sends the Write Suspend command cycle 5.28 Program Security ID
(B0H), then drives CE# high. The Status register indi-
cates that the programming has been suspended by The Program Security ID instruction programs one to
changing the WSP bit from ‘0’ to ‘1,’ but the device will 2040 Bytes of data in the user-programmable, Security
not accept another command until it is ready. To deter- ID space. This Security ID space is one-time program-
mine when the device will accept a new command, poll mable (OTP). The device ignores a Program Security
the BUSY bit in the Status register or wait TWS. ID instruction pointing to an invalid or protected
address, see Table 5-5. Prior to the program operation,
execute WREN.
5.26 Write-Resume
To execute a Program SID operation, the host drives
Write-Resume restarts a Write command that was sus- CE# low, sends the Program Security ID command
pended, and changes the suspend status bit in the Sta- cycle (A5H), two address cycles, the data to be pro-
tus register (WSE or WSP) back to ‘0’. grammed, then drives CE# high. The programmed data
To execute a Write-Resume operation, the host drives must be between 1 to 256 Bytes and in whole Byte
CE# low, sends the Write Resume command cycle increments.
(30H), then drives CE# high. To determine if the inter- The device handles shifting of more than 256 Bytes of
nal, self-timed Write operation completed, poll the data by maintaining the last 256 Bytes of data as the
BUSY bit in the Status register, or wait the specified correct data to be programmed. If the target address for
time TSE, TBE, or TPP for Sector-Erase, Block-Erase, or the Program Security ID instruction is not the beginning
Page-Programming, respectively. The total write time of the page boundary, and the number of data input
before suspend and after resume will not exceed the exceeds or overlaps the end of the address of the page
uninterrupted write times TSE, TBE, or TPP. boundary, the excess data inputs wrap around and will
be programmed at the start of that target page.
5.27 Read Security ID The Program Security ID operation is supported in both
The Read Security ID operation is supported in both SPI and SQI mode. To determine the completion of the
SPI and SQI modes. To execute a Read Security ID internal, self-timed Program SID operation, poll the
(SID) operation in SPI mode, the host drives CE# low, BUSY bit in the software status register, or wait TPSID
sends the Read Security ID command cycle (88H), two for the completion of the internal self-timed Program
address cycles, and then one dummy cycle. To execute Security ID operation.
TABLE 5-5: PROGRAM SECURITY ID

Program Security ID Address Range
Unique ID Pre-Programmed at factory 0000 – 0007H
User Programmable 0008H – 07FFH
5.29 Lockout Security ID To execute a Lockout SID, the host drives CE# low,
sends the Lockout Security ID command cycle (85H),
The Lockout Security ID instruction prevents any future then drives CE# high. Poll the BUSY bit in the software
changes to the Security ID, and is supported in both status register, or wait TPSID, for the completion of the
SPI and SQI modes. Prior to the operation, execute Lockout Security ID operation.
WREN.

SST26WF064C
5.30 Read-Status Register (RDSR) and bit before sending any new commands to assure that
Read-Configuration Register the new commands are properly received by the
device.
(RDCR)
To Read the Status or Configuration registers, the host
The Read-Status Register (RDSR) and Read Configu- drives CE# low, then sends the Read-Status-Register
ration Register (RDCR) commands output the contents command cycle (05H) or the Read Configuration Reg-
of the Status and Configuration registers. These com- ister command (35H). A dummy cycle is required in
mands function in both SPI and SQI modes. The Status SQI mode. Immediately after the command cycle, the
register may be read at any time, even during a Write device outputs data on the falling edge of the SCK sig-
operation. When a Write is in progress, poll the BUSY nal. The data output stream continues until terminated
by a low-to-high transition on CE#. See Figures 5-34
and 5-35 for the RDSR instruction sequence.
FIGURE 5-34: READ-STATUS-REGISTER AND READ CONFIGURATION REGISTER

SEQUENCE (SQI)
CE#
MODE 3 0 2 4 6 8
SCK MODE 0
MSN LSN
SIO(3:0) C1 C0 X X H0 L0 H0 L0 H0 L0
Dummy Status Byte Status Byte Status Byte
20005430 F11.0
Note: MSN = Most Signifi-
cant Nibble; LSN = Least Significant Nibble, C[1:0]=05H or 35H
FIGURE 5-35: READ-STATUS-REGISTER AND READ CONFIGURATION REGISTER

SEQUENCE (SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SCK MODE 0
SI 05 or 35H
MSB
HIGH IMPEDANCE
SO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB Status or Configuration
Register Out
20005430 F62.1

SST26WF064C
5.31 Write-Status Register (WRSR) (01H), two cycles of data, and then drives CE# high.
The first cycle of data points to the Status register, the
The Write-Status Register (WRSR) command writes second points to the Configuration register. See Fig-
new values to the Status register. To execute a Write- ures 5-36 and 5-37.
Status Register operation, the host drives CE# low,
then sends the Write-Status Register command cycle
FIGURE 5-36: WRITE-STATUS-REGISTER AND WRITE CONFIGURATION REGISTER

SEQUENCE (SQI)
CE#
MODE 3 0 1 2 3 4 5
SCK MODE 0
MSN LSN
SIO[3:0] C1 C0 H0 L0 H0 L0
Command Status Config-
Byte uration
20005430 F63.1
Note: MSN = Most Significant

Nibble; LSN = Least
FIGURE 5-37: WRITE-STATUS-REGISTER AND WRITE CONFIGURATION REGISTER

SEQUENCE (SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7 MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK MODE 0 MODE 0
STATUS STATUS
REGISTER 0 IN REGISTER 1 IN
SI 06 01 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB MSB MSB
SO HIGH IMPEDANCE
20005430 F64.0
Note: XX = Don’t Care

SST26WF064C
5.32 Write-Enable (WREN) 5.33 Write-Disable (WRDI)

The Write Enable (WREN) instruction sets the Write- The Write-Disable (WRDI) instruction sets the Write-
Enable-Latch bit in the Status register to ‘1,’ allowing Enable-Latch bit in the Status register to ‘0,’ preventing
Write operations to occur. The WREN instruction must Write operations. The WRDI instruction is ignored
be executed prior to any of the following operations: during any internal write operations. Any Write opera-
Sector Erase, Block Erase, Chip Erase, Page Program, tion started before executing WRDI will complete. Drive
Program Security ID, Lockout Security ID, Write Block- CE# high before executing WRDI.
Protection Register, Lock-Down Block-Protection Reg- To execute a Write-Disable, the host drives CE# low,
ister, and Non-Volatile Write-Lock Lock-Down Register, sends the Write Disable command cycle (04H), then
SPI Quad Page Program, and Write Status Register. To drives CE# high. See Figures 5-40 and 5-41.
execute a Write Enable the host drives CE# low then
sends the Write Enable command cycle (06H) then
FIGURE 5-40: WRITE-DISABLE (WRDI)
drives CE# high. See Figures 5-38 and 5-39 for the
WREN instruction sequence. See Figures 5-38 and 5- SEQUENCE (SQI)
39 for the WREN instruction sequence.
CE#
MODE 3 0 1
FIGURE 5-38: WRITE-ENABLE
SCK
SEQUENCE (SQI) MODE 0
SIO(3:0) 0 4
CE#
20005430 F33.1
MODE 3 0 1
SCK MODE 0
FIGURE 5-41: WRITE-DISABLE (WRDI)

SIO[3:0] 0 6
SEQUENCE (SPI)
20005430 F12.1
CE#
FIGURE 5-39: WRITE-ENABLE MODE 3 0 1 2 3 4 5 6 7

SEQUENCE (SPI) SCK MODE 0
CE#
SI 04
MODE 3 0 1 2 3 4 5 6 7 MSB
SCK MODE 0
SO HIGH IMPEDANCE
20005430 F19.0
SI 06
MSB
SO HIGH IMPEDANCE
20005430 F18.0

SST26WF064C
5.34 Read Block-Protection Register After the command cycle, the device outputs data on
(RBPR) the falling edge of the SCK signal starting with the most
significant nibble, see Table 5-6 for definitions of each
The Read Block-Protection Register instruction outputs bit in the Block-Protection register. The RBPR com-
the Block-Protection register data which determines mand does not wrap around. After all data has been
the protection status. To execute a Read Block-Protec- output, the device will output 0H until terminated by a
tion Register operation, the host drives CE# low, and low-to-high transition on CE#. Figures 5-42 and 5-43.
then sends the Read Block-Protection Register com-
mand cycle (72H). A dummy cycle is required in SQI
mode.
FIGURE 5-42: READ BLOCK-PROTECTION REGISTER SEQUENCE (SQI)
CE#
MODE 3 0 2 4 6 8 10 12
SCK
SIO[3:0] C1 C0 X X H0 L0 H1 L1 H2 L2 H3 L3 H4 L4 HN LN
MSN LSN
BPR [m:m-7] BPR [7:0] 20005430 F34.2
Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble

Block-Protection Register (BPR) m = 143 for SST26WF064C
C[1:0]=72H
FIGURE 5-43: READ BLOCK-PROTECTION REGISTER SEQUENCE (SPI)

CE#
MODE 3
0 1 2 3 4 5 6 7 8 15 16 23 24 32 33
SCK MODE 0
SIO0 72H
OP Code
SIO Data Byte 0 Data Byte 1 Data Byte 2 Data Byte N
20005430 F65.1

SST26WF064C
5.35 Write Block-Protection Register To execute a Write Block-Protection Register operation

(WBPR) the host drives CE# low, sends the Write Block-Protec-
tion Register command cycle (42H), sends six cycles of
The Write Block-Protection Register (WBPR) com- data, and finally drives CE# high. Data input must be
mand changes the Block-Protection register data to most significant nibble first. See Table 5-6 for defini-
indicate the protection status. Execute WREN before tions of each bit in the Block-Protection register. See
executing WBPR. Figures 5-44 and 5-45.
FIGURE 5-44: WRITE BLOCK-PROTECTION REGISTER SEQUENCE (SQI)
CE#
MODE 3 0 2 4 6 8 10 12
SCK MODE 0
SIO(3:0) C1 C0 H0 L0 H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 HN LN
MSN LSN
BPR [143:136] BPR [7:0]
20005430 F35.1
Note: MS
N = Most Significant Nibble, LSN = Least Significant Nibble
Block-Protection Register (BPR) m = 143 for SST26WF064C
FIGURE 5-45: WRITE BLOCK-PROTECTION REGISTER SEQUENCE (SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32
SCK MODE 0
OP Code
SI 42H Data Byte0 Data Byte1 Data Byte2 Data ByteN
SO
20005430 F66.1
Note: C[1:0]=42H

SST26WF064C
5.36 Lock-Down Block-Protection FIGURE 5-46: LOCK-DOWN BLOCK-

Register (LBPR) PROTECTION REGISTER
(SQI)
The Lock-Down Block-Protection Register instruction
prevents changes to the Block-Protection register CE#
during device operation. Lock-Down resets after power MODE 3 0 1
cycling or hardware reset; this allows the Block-Protec- SCK MODE 0
tion register to be changed. Execute WREN before ini-
tiating the Lock-Down Block-Protection Register SIO(3:0) C1 C0
instruction. 20005430 F30.1
To execute a Lock-Down Block-Protection Register, the

host drives CE# low, then sends the Lock-Down Block- N t C[1 0] 8DH
Protection Register command cycle (8DH), then drives
CE# high.
FIGURE 5-47: LOCK-DOWN BLOCK-PROTECTION REGISTER (SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SIO0 8D
SIO[3:1]
20005430 F67.0

SST26WF064C
5.37 Non-Volatile Write-Lock Lock- 18 cycles of data, and then drives CE# high.
Down Register (nVWLDR) After CE# goes high, the non-volatile bits are pro-
grammed and the programming time-out must com-
The Non-Volatile Write-Lock Lock-Down Register
plete before any additional commands, other than
(nVWLDR) instruction controls the ability to change the
Read Status Register, can be entered. Poll the BUSY
Write-Lock bits in the Block-Protection register. Exe-
bit in the Status register, or wait TPP, for the completion
cute WREN before initiating the nVWLDR instruction.
of the internal, self-timed, Write operation. Data inputs
To execute nVWLDR, the host drives CE# low, then must be most significant bit(s) first.
sends the nVWLDR command cycle (E8H), followed by
FIGURE 5-48: WRITE-LOCK LOCK-DOWN REGISTER SEQUENCE (SQI)
CE#
MODE 3 0 2 4 6 8 10 12
SCK MODE 0
SIO(3:0) E 8 H0 L0 H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 HN LN
MSN LSN
nVWLDR[m:m-7] BPR [7:0]
20005430 F36.0
Note:
MSN= Most Significant Nibble; LSN = Least Significant Nibble
Write Lock Lock Down Register (nVWLDR) m = 143
FIGURE 5-49: WRITE-LOCK LOCK-DOWN REGISTER SEQUENCE (SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32
SCK MODE 0
OP Code
SI E8H Data Byte0 Data Byte1 Data Byte2 Data ByteN
SO
20005430 F69.1

SST26WF064C
5.38 Global Block-Protection Unlock FIGURE 5-50: GLOBAL BLOCK-

(ULBPR) PROTECTION UNLOCK
(SQI)
The Global Block-Protection Unlock (ULBPR) instruc-
tion clears all write-protection bits in the Block-Protec- CE#
tion register, except for those bits that have been MODE 3 0 1
locked down with the nVWLDR command. Execute SCK MODE 0
WREN before initiating the ULBPR instruction.
To execute a ULBPR instruction, the host drives CE# SIO(3:0) C1 C0
low, then sends the ULBPR command cycle (98H), and 20005430 F20.1
then drives CE# high. Note: C[1:0]=98H
FIGURE 5-51: GLOBAL BLOCK-PROTECTION UNLOCK (SPI)
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SIO0 98
SIO[3:1]
20005430 F68.0

SST26WF064C
TABLE 5-6: BLOCK-PROTECTION REGISTER FOR SST26WF064C (1 OF 4)1

BPR Bits
Write Lock/ Protected Block
Read Lock nVWLDR2 Address Range Size
143 142 7FE000H - 7FFFFFH 8 KByte
141 140 7FC000H - 7FDFFFH 8 KByte
139 138 7FA000H - 7FBFFFH 8 KByte
137 136 7F8000H - 7F9FFFH 8 KByte
135 134 006000H - 007FFFH 8 KByte
133 132 004000H - 005FFFH 8 KByte
131 130 002000H - 003FFFH 8 KByte
129 128 000000H - 001FFFH 8 KByte
127 7F0000H - 7F7FFFH 32 KByte
126 008000H - 00FFFFH 32 KByte
125 7E0000H - 7EFFFFH 64 KByte
124 7D0000H - 7DFFFFH 64 KByte
123 7C0000H - 7CFFFFH 64 KByte
122 7B0000H - 7BFFFFH 64 KByte
121 7A0000H - 7AFFFFH 64 KByte
120 790000H - 79FFFFH 64 KByte
119 780000H - 78FFFFH 64 KByte
118 770000H - 77FFFFH 64 KByte
117 760000H - 76FFFFH 64 KByte
116 750000H - 75FFFFH 64 KByte
115 740000H - 74FFFFH 64 KByte
114 730000H - 73FFFFH 64 KByte
113 720000H - 72FFFFH 64 KByte
112 710000H - 71FFFFH 64 KByte
111 700000H - 70FFFFH 64 KByte
110 6F0000H - 6FFFFFH 64 KByte
104 690000H - 69FFFFH 64 KByte
103 680000H - 68FFFFH 64 KByte
102 670000H - 67FFFFH 64 KByte
101 660000H - 66FFFFH 64 KByte
100 650000H - 65FFFFH 64 KByte
99 640000H - 64FFFFH 64 KByte
98 630000H - 63FFFFH 64 KByte
97 620000H - 62FFFFH 64 KByte
96 610000H - 61FFFFH 64 KByte
95 600000H - 60FFFFH 64 KByte

SST26WF064C
TABLE 5-6: BLOCK-PROTECTION REGISTER FOR SST26WF064C (CONTINUED) (2 OF 4)1

BPR Bits
88 590000H - 59FFFFH 64 KByte
87 580000H - 58FFFFH 64 KByte
86 570000H - 57FFFFH 64 KByte
85 560000H - 56FFFFH 64 KByte
84 550000H - 55FFFFH 64 KByte
83 540000H - 54FFFFH 64 KByte
82 530000H - 53FFFFH 64 KByte
81 520000H - 52FFFFH 64 KByte
80 510000H - 51FFFFH 64 KByte
79 500000H - 50FFFFH 64 KByte
72 490000H - 49FFFFH 64 KByte
71 480000H - 48FFFFH 64 KByte
70 470000H - 47FFFFH 64 KByte
69 460000H - 46FFFFH 64 KByte
68 450000H - 45FFFFH 64 KByte
67 440000H - 44FFFFH 64 KByte
66 430000H - 43FFFFH 64 KByte
65 420000H - 42FFFFH 64 KByte
64 410000H - 41FFFFH 64 KByte
63 400000H - 40FFFFH 64 KByte
56 390000H - 39FFFFH 64 KByte
55 380000H - 38FFFFH 64 KByte
54 370000H - 37FFFFH 64 KByte
53 360000H - 36FFFFH 64 KByte
52 350000H - 35FFFFH 64 KByte
51 340000H - 34FFFFH 64 KByte
50 330000H - 33FFFFH 64 KByte

SST26WF064C

BPR Bits
49 320000H - 32FFFFH 64 KByte
48 310000H - 31FFFFH 64 KByte
47 300000H - 30FFFFH 64 KByte
40 290000H - 29FFFFH 64 KByte
39 280000H - 28FFFFH 64 KByte
38 270000H - 27FFFFH 64 KByte
37 260000H - 26FFFFH 64 KByte
36 250000H - 25FFFFH 64 KByte
35 240000H - 24FFFFH 64 KByte
34 230000H - 23FFFFH 64 KByte
33 220000H - 22FFFFH 64 KByte
32 210000H - 21FFFFH 64 KByte
31 200000H - 20FFFFH 64 KByte
24 190000H - 19FFFFH 64 KByte
23 180000H - 18FFFFH 64 KByte
22 170000H - 17FFFFH 64 KByte
21 160000H - 16FFFFH 64 KByte
20 150000H - 15FFFFH 64 KByte
19 140000H - 14FFFFH 64 KByte
18 130000H - 13FFFFH 64 KByte
17 120000H - 12FFFFH 64 KByte
16 110000H - 11FFFFH 64 KByte
15 100000H - 10FFFFH 64 KByte
8 090000H - 09FFFFH 64 KByte
7 080000H - 08FFFFH 64 KByte

SST26WF064C

BPR Bits
6 070000H - 07FFFFH 64 KByte
5 060000H - 06FFFFH 64 KByte
4 050000H - 05FFFFH 64 KByte
3 040000H - 04FFFFH 64 KByte
2 030000H - 03FFFFH 64 KByte
1 020000H - 02FFFFH 64 KByte
0 010000H - 01FFFFH 64 KByte
1. The default state after a power-on reset or hardware reset is write-protected BPR[143:0] = 5555 FFFFFFFF FFFFFFFF FFFFFFFF
FFFFFFFF
2. nVWLDR bits are one-time-programmable. Once a nVWLDR bit is set, the protection state of that particular block is perma-
nently write-locked.

SST26WF064C
5.39 Deep Power-Down Enter Deep Power-down mode by initiating the Deep
Power-down (DPD) instruction (B9H) while driving CE#
The Deep Power-down (DPD) instruction puts the low. CE# must be driven high before executing the
device in the lowest power consumption mode–the DPD instruction. After CE# is driven high, it requires a
Deep Power-down mode. The Deep Power-down delay of TDPD before the standby current ISB is reduced
instruction is ignored during an internal write operation. to deep power-down current IDPD. See Table 5-7 for
While the device is in Deep Power-down mode, all Deep Power-down timing. If the device is busy perform-
instructions will be ignored except for the Release ing an internal erase or program operation, initiating a
Deep Power-down instruction. Deep Power-down instruction will not placed the device
in Deep Power-down mode. See Figures 5-52 and 5-53
for the DPD instruction sequence.
TABLE 5-7: DEEP POWER-DOWN

Symbol Parameter Min Max Units
TDPD CE# High to Deep Power-down 3 µs
TSBR CE# High to Standby Mode 10 µs
FIGURE 5-52: DEEP POWER-DOWN (DPD) SEQUENCE (SQI)
CE# TDPD
MODE 3 0 1
SCK MODE 0
SIO(3:0) B 9
MSN LSN
Standby Mode Deep Power-Down Mode

20005430 F100.0
Note: MSN= Most Significant Nibble; LSN = Least Significant Nibble
FIGURE 5-53: DEEP POWER-DOWN (DPD) (SPI)
CE#
TDPD
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SI B9
MSB
SO HIGH IMPEDANCE
Standby Mode Deep Power-Down Mode
20005430 F101.0

SST26WF064C
5.40 Release from Deep Power-Down To execute RDPD and read the Device ID, the host
and Read ID drives CE# low then sends the Deep Power-Down
command cycle (ABH), three dummy clock cycles, and
Release from Deep Power-Down (RDPD) and Read ID then drives CE# high. The device outputs the Device ID
instruction exits Deep Power-down mode. To exit Deep on the falling edge of the SCK signal following the
Power down mode, execute the RDPD. During this dummy cycles. The data output stream is continuous
command, the host drives CE# low, then sends the until terminated by a low-to-high transition on CE, and
Deep Power-Down command cycle (ABH), and then will return to Standby mode and be ready for the next
drives CE# high. The device will return to Standby instruction after TSBR. See Figures 5-54 and 5-55 for
mode and be ready for the next instruction after TSBR. the command sequence.
FIGURE 5-54: RELEASE FROM DEEP POWER-DOWN (RDPD) AND READ ID SEQUENCE (SQI)
TSBR
CE#
MODE 3 0 1
SCK MODE 0
Op Code
SIO[3:0] C1 C0 X X X X X X D1 D0
MSN LSN Device ID
Deep Power-Down Mode Standby Mode

20005430 F102.0
Note: C[1:0]=ABH
FIGURE 5-55: RELEASE FROM DEEP POWER-DOWN (RDPD) AND READ ID SEQUENCE (SPI)
TSBR
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 32 33 40
SCK MODE 0
Op Code
SIO[3:0] AB XX XX XX
Device ID
Deep Power-Down Mode Standby Mode

20005430 F103.0

SST26WF064C
6.0 ELECTRICAL SPECIFICATIONS
Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause perma-
nent damage to the device. This is a stress rating only and functional operation of the device at these con-
ditions or conditions greater than those defined in the operational sections of this data sheet is not implied.
Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Output shorted for no more than one second. No more than one output shorted at a time.
TABLE 6-1: OPERATING RANGE

Range Ambient Temp VDD
Industrial -40°C to +85°C 1.65-1.95V
TABLE 6-2: AC CONDITIONS OF TEST1

Input Rise/Fall Time Output Load
3ns CL = 30 pF
1. See Figure 8-6
6.1 Power-Up Specifications When VDD drops from the operating voltage to below
the minimum VDD threshold at power-down, all opera-
All functionalities and DC specifications are specified tions are disabled and the device does not respond to
for a VDD ramp rate of greater than 1V per 100 ms (0V commands. Data corruption may result if a power-down
to 1.95V in less than 195 ms). occurs while a Write-Registers, program, or erase
operation is in progress. See Figure 6-2.
TABLE 6-3: RECOMMENDED SYSTEM POWER-UP/DOWN TIMINGS

Symbol Parameter Minimum Max Units Condition
TPU-READ1 VDD Min to Read Operation 100 µs
TPU-WRITE1 VDD Min to Write Operation 100 µs
TPD1 Power-down Duration 100 ms
VOFF VDD off time 0.3 V 0V recommended
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

SST26WF064C
FIGURE 6-1: POWER-UP TIMING DIAGRAM
VDD
VDD Max
Chip selection is not allowed.
Commands may not be accepted or properly
interpreted by the device.
VDD Min
TPU-READ
TPU-WRITE Device fully accessible
Time
20005430 F27.0
FIGURE 6-2: POWER-DOWN AND VOLTAGE DROP DIAGRAM

VDD
VDD Max
No Device Access Allowed
VDD Min
TPU Device
Access
Allowed
VOFF
TPD
Time
20005430 F72.0

SST26WF064C
7.0 DC CHARACTERISTICS
TABLE 7-1: DC OPERATING CHARACTERISTICS (VDD = 1.65V–1.95V)

Limits
Symbol Parameter Min Typ Max Units Test Conditions
IDDR1 Read Current 8 10 mA VDD=VDD Max,
CE#=0.1 VDD/0.9 VDD@40 MHz,
SO=open
IDDR2 Read Current 20 mA VDD = VDD Max,
CE#=0.1 VDD/0.9 VDD@104 MHz,
SO=open
IDDW Program and Erase Cur- 25 mA VDD Max
rent
IDDDTR Read Current DTR 20 mA
@ 50 MHz
ISB Standby Current 13 40 µA CE#=VDD, VIN=VDD or VSS
IDPD Deep Power-down Cur- 3 15 µA CE#=VDD, VIN=VDD or VSS
rent
ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
ILO Output Leakage Current 1 µA VOUT=GND to VDD, VDD=VDD Max
VIL Input Low Voltage 0.3 V VDD=VDD Min
VIH Input High Voltage 0.7 VDD V VDD=VDD Max
VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min
VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min
TABLE 7-2: CAPACITANCE (TA = 25°C, F=1 MHZ, OTHER PINS OPEN)
Parameter Description Test Condition Maximum
COUT1 Output Pin Capacitance VOUT = 0V 8 pF
CIN1 Input Capacitance VIN = 0V 6 pF
TABLE 7-3: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method
NEND1 Endurance 100,000 Cycles JEDEC Standard A117
TDR1 Data Retention 100 Years JEDEC Standard A103
ILTH1 Latch Up 100 + IDD mA JEDEC Standard 78
TABLE 7-4: WRITE TIMING PARAMETERS (VDD = 1.65V–1.95V)

Symbol Parameter Minimum Maximum Units
TSE Sector-Erase 25 ms
TBE Block-Erase 25 ms
TSCE Chip-Erase 50 ms
TPP Page-Program 1.5 ms
TPSID Program Security-ID 1.5 ms
TWS Write-Suspend Latency 25 µs
TWpen Write-Protection Enable Bit Latency 25 ms

SST26WF064C
8.0 AC CHARACTERISTICS
TABLE 8-1: AC OPERATING CHARACTERISTICS (VDD = 1.65V–1.95V)

Limits - 40 MHz Limits - 80 MHz Limits - 104 MHz
Symbol Parameter Min Max Min Max Min Max Units
FCLK Serial Clock Frequency 40 80 104 MHz
TCLK Serial Clock Period 25 12.5 9.6 ns
TSCKH Serial Clock High Time 11 5.5 4.5 ns
TSCKL Serial Clock Low Time 11 5.5 4.5 ns
TSCKR1 Serial Clock Rise Time (slew rate) 0.1 0.1 0.1 V/ns
TSCKF1 Serial Clock Fall Time (slew rate) 0.1 0.1 0.1 V/ns
TCES2 CE# Active Setup Time 8 5 5 ns
TCEH2 CE# Active Hold Time 8 5 5 ns
TCHS2 CE# Not Active Setup Time 8 5 5 ns
TCHH2 CE# Not Active Hold Time 8 5 5 ns
TCPH CE# High Time 25 12.5 12 ns
TCHZ CE# High to High-Z Output 19 12.5 12 ns
TCLZ SCK Low to Low-Z Output 0 0 0 ns
THLS HOLD# Low Setup Time 8 5 5 ns
THHS HOLD# High Setup Time 8 5 5 ns
THLH HOLD# Low Hold Time 8 5 5 ns
THHH HOLD# High Hold Time 8 5 5 ns
THZ HOLD# Low-to-High-Z Output 8 8 8 ns
TLZ HOLD# High-to-Low-Z Output 8 8 8 ns
TDS Data In Setup Time 3 3 3 ns
TDH Data In Hold Time 4 4 4 ns
TOH Output Hold from SCK Change 0 0 0 ns
TV Output Valid from SCK 8/5 3 8/5 3 8/5 3 ns
1. Maximum Rise and Fall time may be limited by TSCKH and TSCKL requirements
2. Relative to SCK.
3. 30 pF/10 pF
TABLE 8-2: AC OPERATING CHARACTERISTICS – DTR (50 MHz))

Symbol Parameter Min Max Units
FCLKDTR Serial Clock Frequency 50 MHz
TDSDTR Data in Setup Time 3 ns
TDHDTR Data in Hold Time 4 ns
TUDTR Output valid from SCK edge 8/51 ns
1. 30 pF/10 pF output loading

SST26WF064C
FIGURE 8-1: HOLD TIMING DIAGRAM
CE#
THHH THLS THHS
SCK
THLH
THZ TLZ
SO
SI
HOLD#
20005430 F104.0
FIGURE 8-2: SERIAL INPUT TIMING DIAGRAM

TCPH
CE#
TCHH TCES TCEH TCHS

TSCKF
SCK
TDS TDH
TSCKR
SIO[3:0] MSB LSB
20005430 F105.0
FIGURE 8-3: SERIAL OUTPUT TIMING DIAGRAM
CE#
TSCKH TSCKL
SCK
TOH
TCLZ TCHZ
SIO[3:0] MSB LSB

TV
20005430 F106.0

SST26WF064C
FIGURE 8-4: HARDWARE RESET TIMING DIAGRAM
CE#
TRECR
TRECP
TRECE
SCK
TRST
RST#
TRHZ
SO
SI
20005430 F28.0
TABLE 8-3: RESET TIMING PARAMETERS

TR(i) Parameter Minimum Maximum Units
TRECR Reset to Read (non-data operation) 20 ns
TRECP Reset Recovery from Program or Suspend 100 µs
TRECE Reset Recovery from Erase 1 ms
TRST Reset Pulse Width (Hardware Reset) 100 ns
TRHZ Reset to High-Z Output 105 ns
FIGURE 8-5: RESET TIMING DIAGRAM

TCPH
CE#
CLK
SIO(3:0) C1 C0 C3 C2
20005430 F14.0
Note: C[1:0] = 66H; C[3:2] = 99H

SST26WF064C
FIGURE 8-6: AC INPUT/OUTPUT REFERENCE WAVEFORMS
VIHT
VHT VHT
INPUT REFERENCE POINTS OUTPUT
VLT VLT
VILT
20005430 F128.0
AC test inputs are driven at VIHT (0.9VDD) for a logic ‘1’ and VILT (0.1VDD) for a logic ‘0’. Measure-
ment reference points for inputs and outputs are VHT (0.5VDD) and VLT (0.5VDD). Input rise and
fall times (10%  90%) are <3 ns.
Note: VHT - VHIGH Test
VLT - VLOW Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test

SST26WF064C
9.0 PACKAGING DIAGRAMS

9.1 Package Marking
8-Lead SOIJ (5.28 mm) Example
26WF064C
I/SM e3
1506343
8-Lead WDFN (5x6 mm) Example
XXXXXXXX 26WF064C
XXXXXXXX I/MF e3
YYWWNNN 1506343
24-Ball TBGA (6x8 mm) Example
XXXXXXXXXX 26WF064C
XXXXXXXXXX I/TD e3
XXXXXXXXXX 1506343
YYWWNNN
16-Lead SOIC (7.50 mm) Example
26WF064C
I/SO e3
1506343
Continued

SST26WF064C
1st Line Marking Codes

Part Number
SOIJ WDFN TBGA SOIC
SST26WF064C 26WF064C 26WF064C 26WF064C 26WF064C
Legend: XX...X Part number or part number code

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
e3 Pb-free JEDEC® designator for Matte Tin (Sn)
Note: For very small packages with no room for the Pb-free JEDEC® designator
e3 , the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

SST26WF064C
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

SST26WF064C

SST26WF064C

SST26WF064C
8-Lead Plastic Very, Very Thin Small Outline No-Lead (MF) - 5x6 mm Body [WDFN]
D A B
N
(DATUM A)
(DATUM B)
E
NOTE 1
2X
0.15 C
1 2
2X
0.15 C
TOP VIEW
A1
C 0.10 C
SEATING A
PLANE
A3
SIDE VIEW 0.08 C
0.10 C A B
D2
e
1 2
0.10 C A B
NOTE 1
E2
K N
8Xb
0.10 C A B
SEE DETAIL A
0.05 C
BOTTOM VIEW
Microchip Technology Drawing C04-210B Sheet 1 of 2

SST26WF064C
(DATUM A)
e/2
e
DETAIL A
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Terminals N 8
Pitch e 1.27 BSC
Overall Height A 0.70 0.75 0.80
Standoff A1 0.00 0.02 0.05
Terminal Thickness A3 0.20 REF
Overall Width D 5.00 BSC
Exposed Pad Width D2 4.00 BSC
Overall Length E 6.00 BSC
Exposed Pad Length E2 3.40 BSC
Terminal Width b 0.35 0.42 0.48
Terminal Length L 0.50 0.60 0.70
Terminal-to-Exposed-Pad K 0.20 - -
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-210B Sheet 2 of 2

SST26WF064C
C
X2
X1
Y2
Y1
SILK SCREEN
RECOMMENDED LAND PATTERN
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 1.27 BSC
Optional Center Pad Width X2 3.50
Optional Center Pad Length Y2 4.10
Contact Pad Spacing C 5.70
Contact Pad Width (X8) X1 0.45
Contact Pad Length (X8) Y1 1.10
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2210A

SST26WF064C

SST26WF064C

SST26WF064C
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SST26WF064C
TABLE 9-1: REVISION HISTORY

Revision Description Date
A • Initial release of data sheet May 2016
B • Corrected a typo in Section 10.0, Product Identification System that July 2017
incorrectly listed the SOIJ body size.

SST26WF064C
THE MICROCHIP WEB SITE CUSTOMER SUPPORT

Microchip provides online support via our WWW site at Users of Microchip products can receive assistance
www.microchip.com. This web site is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the web site contains the following informa-
tion: • Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata, appli-
cation notes and sample programs, design Customers should contact their distributor, representa-
resources, user’s guides and hardware support tive or Field Application Engineer (FAE) for support.
documents, latest software releases and archived Local sales offices are also available to help custom-
software ers. A listing of sales offices and locations is included in
• General Technical Support – Frequently Asked the back of this document.
Questions (FAQ), technical support requests, Technical support is available through the web site
online discussion groups, Microchip consultant at: http://microchip.com/support
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Micro-
chip sales offices, distributors and factory repre-
sentatives
CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a spec-
ified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on “Cus-
tomer Change Notification” and follow the registration
instructions.
DS20005430B-page 70  2016-2017 Microchip Technology Inc.

SST26WF064C
10.0 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
X – XXX XX Valid Combinations:

PART NO. X /
SST26WF064C-104I/MF
Device Tape/Reel Operating Temperature Package SST26WF064CT-104I/MF
Indicator Frequency
SST26WF064C-104I/SM
SST26WF064CT-104I/SM
Device: SST26WF064C = 64 Mbit, 1.8V, SQI Flash Memory
WP#/HOLD#/RESET# pin Enable at
power-up SST26WF064C-104I/SO
SST26WF064CT-104I/SO
Tape and T = Tape and Reel
Reel Flag: SST26WF064C-104I/TD
SST26WF064CT-104I/TD
Operating 104 = 104 MHz
Frequency:
Temperature: I = -40°C to +85°C
Package: MF = WDFN (6mm x 5mm Body), 8-contact

SM = SOIJ (5.28 mm Body), 8-contact
SO = SOIC (7.50 mm Body), 16-contact
TD = TBGA (6 mm x 8 mm Body), 24-contact
 2016-2017 Microchip Technology Inc. DS20005430B-page 71

SST26WF064C
11.0 APPENDIX
TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (1 OF 16)

Address Bit Address Data Comments
SFDP Header
st
SFDP Header: 1 DWORD
00H A7:A0 53H SFDP Signature
01H A15:A8 46H SFDP Signature=50444653H
02H A23:A16 44H
03H A31:A24 50H
SFDP Header: 2nd DWORD
04H A7:A0 06H SFDP Minor Revision Number
05H A15:A8 01H SFDP Major Revision Number
06H A23:A16 02H Number of Parameter Headers (NPH)=3
07H A31:A24 FFH Unused. Contains FF and can not be changed.
Parameter Headers
JEDEC Flash Parameter Header: 1st DWORD
Parameter ID Least Significant Bit (LSB) Number.
When this field is set to 00H, it indicates a JEDEC-specified header. For
08H A7:A0 00H
vendor-specified headers, this field must be set to the vendor’s manufac-
turer ID.
Parameter Table Minor Revision Number
Minor revisions are either clarifications or changes that add parameters
09H A15:A8 06H
in existing Reserved locations. Minor revisions do NOT change overall
structure of SFDP. Minor Revision starts at 00H.
Parameter Table Major Revision Number
Major revisions are changes that reorganize or add parameters to loca-
0AH A23:A16 01H tions that are NOT currently Reserved. Major revisions would require
code (BIOS/firmware) or hardware change to get previously defined dis-
coverable parameters. Major Revision starts at 01H
Parameter Table Length
0BH A31:A24 10H
Number of DWORDs that are in the Parameter table
JEDEC Flash Parameter Header: 2nd DWORD
0CH A7:A0 30H Parameter Table Pointer (PTP)
A 24-bit address that specifies the start of this header’s Parameter table
0DH A15:A8 00H
in the SFDP structure. The address must be DWORD-aligned.
0EH A23:A16 00H
0FH A31:A24 FFH Parameter ID Most Significant Bit (MSB) Number
JEDEC Sector Map Parameter Header: 3rd DWORD
Parameter ID LSB Number.
10H A7:A0 81H
Sector map, function-specific table is assigned 81H
Parameter Table Minor Revision Number
Minor revisions are either clarifications or changes that add parameters
11H A15:A8 00H
in existing Reserved locations. Minor revisions do NOT change overall
structure of SFDP. Minor Revision starts at 00H.
Parameter Table Major Revision Number
Major revisions are changes that reorganize or add parameters to loca-
12H A23:A16 01H tions that are NOT currently Reserved. Major revisions would require
code (BIOS/firmware) or hardware change to get previously defined dis-
coverable parameters. Major Revision starts at 01H

SST26WF064C
TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (2 OF 16)

Parameter Table Length
13H A31:A24 06H
Number of DWORDs that are in the Parameter table
JEDEC Sector Map Parameter Header: 4th DWORD
14H A7:A0 00H Parameter Table Pointer (PTP)
This 24-bit address specifies the start of this header’s Parameter Table in
15H A15:A8 01H
the SFDP structure. The address must be DWORD-aligned.
16H A23:A16 00H
17H A31:A24 FFH Parameter ID MSB Number
Microchip (Vendor) Parameter Header: 5th DWORD
ID Number
18H A7:A0 BFH
Manufacture ID (vendor specified header)
19H A15:A8 00H Parameter Table Minor Revision Number
1AH A23:A16 01H Parameter Table major Revision Number, Revision 1.0
1BH A31:A24 18H Parameter Table Length, 24 Double Words
Microchip (Vendor) Parameter Header: 6th DWORD
1CH A7:A0 00H Parameter Table Pointer (PTP)
1DH A15:A8 02H This 24-bit address specifies the start of this header’s Parameter Table in
the SFDP structure. The address must be DWORD-aligned.
1EH A23:A16 00H
1FH A31:A24 01H Used to indicate bank number (vendor specific)
JEDEC Flash Parameter Table
JEDEC Flash Parameter Table: 1st DWORD
Block/Sector Erase Sizes
00: Reserved
A1:A0 01: 4 KByte Erase
10: Reserved
11: Use this setting only if the 4 KByte erase is unavailable.
Write Granularity
0: Single-byte programmable devices or buffer programmable devices
A2 with buffer is less than 64 bytes (32 Words).
1: For buffer programmable devices when the buffer size is 64
30H FDH bytes (32 Words) or larger.
Volatile Status Register
0: Target flash has nonvolatile status bit. Write/Erase commands do
A3
not require status register to be written on every power on.
1: Target flash volatile status bits
Write Enable Opcode Select for Writing to Volatile Status Register
A4 0: 0x50. Enables a status register write when bit 3 is set to 1.
1: 0x06 Enables a status register write when bit 3 is set to 1.
A7:A5 Unused. Contains 111b and can not be changed
31H A15:A8 20H 4 KByte Erase Opcode

SST26WF064C

Supports (1-1-2) Fast Read
A16 0: (1-1-2) Fast Read NOT supported
1: (1-1-2) Fast Read supported
Address Bytes
Number of bytes used in addressing flash array read, write and erase
00: 3-Byte only addressing
A18:A17 01: 3- or 4-Byte addressing (e.g. defaults to 3-Byte mode; enters 4-Byte
mode on command)
10: 4-Byte only addressing
11: Reserved
Supports Double Transfer Rate (DTR) Clocking
Indicates the device supports some type of double transfer rate clocking.
A19
0: DTR NOT supported
1: DTR Clocking supported
32H F9H Supports (1-2-2) Fast Read

Device supports single input opcode, dual input address, and dual output
A20 data Fast Read.
0: (1-2-2) Fast Read NOT supported.
1: (1-2-2) Fast Read supported.
Device supports single input opcode, quad input address, and quad out-
A21 put data Fast Read
Device supports single input opcode & address and quad output data
A22 Fast Read.
A23 Unused. Contains ‘1’ can not be changed.
33H A31:A24 FFH Unused. Contains FF can not be changed
JEDEC Flash Parameter Table: 2nd DWORD
34H A7:A0 FFH Flash Memory Density
35H A15:A8 FFH SST26WF064C = 03FFFFFFH
36H A23:A16 FFH
37H A31:A24 03H
JEDEC Flash Parameter Table: 3rd DWORD
(1-4-4) Fast Read Number of Wait states (dummy clocks) needed
before valid output
A4:A0
00100b: 4 dummy clocks (16 dummy bits) are needed with a quad input
address phase instruction
38H 44H
Quad Input Address Quad Output (1-4-4) Fast Read Number of Mode
Bits
A7:A5
010b: 2 dummy clocks (8 mode bits) are needed with a single input
opcode, quad input address and quad output data Fast Read Instruction.
(1-4-4) Fast Read Opcode
39H A15:A8 EBH Opcode for single input opcode, quad input address, and quad output
data Fast Read.

SST26WF064C

before valid output
A20:A16
01000b: 8 dummy bits are needed with a single input opcode & address
3AH 08H and quad output data Fast Read Instruction
(1-1-4) Fast Read Number of Mode Bits
A23:A21 000b: No mode bits are needed with a single input opcode & address and
quad output data Fast Read Instruction
3BH A31:A24 6BH Opcode for single input opcode & address and quad output data Fast
Read.
JEDEC Flash Parameter Table: 4th DWORD
before valid output
A4:A0
01000b: 8 dummy clocks are needed with a single input opcode, address
3CH 08H and dual output data fast read instruction.
A7:A5 000b: No mode bits are needed with a single input opcode & address and
quad output data Fast Read Instruction
3DH A15:A8 3BH
Opcode for single input opcode& address and dual output data Fast Read.
A20:A16 before valid output
3EH 80H 00000b: 0 clocks of dummy cycle.
(1-2-2) Fast Read Number of Mode Bits (in clocks)
A23:A21
100b: 4 clocks of mode bits are needed
3FH A31:A24 BBH Opcode for single input opcode, dual input address, and dual output data
Fast Read.
Device supports dual input opcode& address and dual output data Fast
A0 Read.
A3:A1 Reserved. Bits default to all 1’s.
40H FEH
Device supports Quad input opcode & address and quad output data
A4 Fast Read.
41H A15:A8 FFH Reserved. Bits default to all 1’s.

SST26WF064C

th
JEDEC Flash Parameter Table: 6 DWORD
46H 00H 00000b: No dummy bit is needed
A23:A21
000b: No mode bits are needed
47H A31:A24 FFH Opcode for dual input opcode& address and dual output data Fast Read.
(not supported)
before valid output
A20:A16
00100b: 4 clocks dummy are needed with a quad input opcode &
4AH 44H address and quad output data Fast Read Instruction
A23:A21 010b: 2 clocks mode bits are needed with a quad input opcode & address
and quad output data Fast Read Instruction
4BH A31:A24 0BH
Opcode for quad input opcode/address, quad output data Fast Read
Sector Type 1 Size
4CH A7:A0 0CH
4 KByte, Sector/block size = 2N bytes
Sector Type 1 Opcode
4DH A15:A8 20H Opcode used to erase the number of bytes specified by Sector Type 1
Size
Sector Type 2 Size
4EH A23:A16 0DH
4FH A31:A24 D8H Opcode used to erase the number of bytes specified by Sector Type 2
Size
Sector Type 3 Size
50H A7:A0 0FH
51H A15:A8 D8H Opcode used to erase the number of bytes specified by Sector Type 3
Size
Sector Type 4 Size
52H A23:A16 10H
53H A31:A24 D8H Opcode used to erase the number of bytes specified by Sector Type 4
Size

SST26WF064C

th
Multiplier from typical erase time to maximum erase time
Maximum time = 2*(count + 1)*Typical erase time
A3:A0
Count = 0
A3:A0= 0000b
54H 20H Erase Type 1 Erase, Typical time

Typical Time = (count +1)*units
1ms to 32ms, 16ms to 512ms, 128ms to 4096ms, 1s to 32s
A7:A4
A10:A9 units (00b:1ms, 01b: 16ms, 10b:128ms, 11b:1s)
A8:A4 count = 18 = 10010b
A10:A9 unit = 1ms = 00b
A10:A8 A10:A8=001b
Erase Type 2 Erase, Typical time
Typical time = (count+1)*units
55H 91H 1ms to 32ms, 16ms to 512ms, 128ms to 4096ms, 1s to 32s
A15:A11
A17:A16 units (00b:1ms, 01b:16ms, 10b:128ms, 11b:1s)
A15:A11 count = 18 =10010b
A17:A16 unit = 1ms =00b
A17:A16 A17:A16=00b
A23:A18
A24:A23 units (00b: 1ms, 01b: 16ms, 10b:128ms, 11b:1s)
A22:A18 count = 18 = 10010b
A24:A23 unit = 1ms = 00b
A24 A24=0b
A31:A25
A31:A30 units (00b: 1ms, 01b: 16ms, 10b:128ms, 11b:1s)
A29:A25 count=18=10010b
A31:A30 unit = 1ms =00b
Multiplier from Typical Program Time to Maximum Program Time
A3:A0 Maximum time = 2*(count +1)*Typical program time.
Count =0.
A3:A0=0000b
58H 80H
Page Size
Page size = 2N bytes.
A7:A4
N=8
A7:A4 =1000b
Page Program Typical time
Program time = (count+1)*units
A13:A8 A13 units (0b: 8µs, 1b: 64µs)
A12:A8 count=11 = 01111b
A13 unit = 64µs = 1b
59H 6FH
Byte Program Typical time, first byte
A15:A14 A18 units (0b: 1µs, 1b: 8µs)
A17:A14 count = 5 = 0101b
A18 =8µs=1b

SST26WF064C

A18:A16 A18:A16=101b
Byte Program Typical time, Additional Byte
5AH 1DH Typical time = (count+1)*units
A23:A19 A23 units (0b: 1µs, 1b: 8µs)
A22:A19 count = 3 = 0011b
A23=1μs=0b
Chip Erase Typical Time
A30:A:24 16ms to 512ms, 256ms to 8192ms, 4s to 128s, 64s to 2048s
5BH 81H A28:A24 count =1=00001b
A30:A29 units =16ms=00b
Reserved
A31
A31=1b
Prohibited Operations During Program Suspend
xxx0b: May not initiate a new erase anywhere
xxx1b:May not initiate a new erase in the program suspended page size
xx0xb:May not initiate a new page program anywhere
A3:A0 xx1xb: May not initiate a new page program in program suspended page size.
x0xxb:Refer to the Data Sheet
x1xxb: May not initiate a read in the program suspended page size
0xxxb: Additional erase or program restrictions apply
1xxxb: The erase and program restrictions in bits 1:0 are sufficient
5CH EDH Prohibited Operation During Erase Suspend
xxx0b: May not initiate a new erase anywhere
xxx1b:May not initiate a new erase in the erase suspended page size
xx0xb:May not initiate a new page program anywhere
A7:A4 xx1xb: May not initiate a new page program in erase suspended
erase type size.
x0xxb:Refer to the Data Sheet
x1xxb: May not initiate a read in the erase suspended page size
0xxxb: Additional erase or program restrictions apply
1xxxb: The erase and program restrictions in bits 5:4 are sufficient
A8 Reserved = 1b
Program Resume to Suspend Interval
The device requires this typical amount of time to make progress on the
A12:A9 program operation before allowing another suspend.
Interval =500µs
Program resume to suspend interval =(count+1)*64µs
A12:A9= 7 =0111b
5DH 0FH Suspend In-progress Program Max Latency

Maximum time required by the flash device to suspend an in-progress
program and be ready to accept another command which accesses the
flash array.
A15:A13 Max latency = 25µs
program max latency =(count+1)*units
units (00b:128ns, 01b:1µs, 10b:8µs, 11b:64µs)
A17:A13= count = 24 = 11000b
A19:A18 = 1µs =01b

SST26WF064C

A19:A16 0111b
Erase Resume to Suspend Interval
The device requires this typical amount of time to make progress on the
5EH 77H erase operation before allowing another suspend.
A23:A20
Interval = 500µs
Erase resume to suspend interval =(count+1)*64µs
A23:A20= 7 =0111b
Suspend In-progress Erase Max Latency
Maximum time required by the flash device to suspend an in-progress
erase and be ready to accept another command which accesses the
flash array.
A30:A24 Max latency = 25µs
Erase max latency =(count+1)*units
5FH 38H
units (00b:128ns, 01b:1µs, 10b:8µs, 11b:64µs)
A28:A24= count = 24 = 11000b
A30:A29 = 1µs =01b
Suspend/Resume supported
A31 0:supported
1:not supported
60H A7:A0 30H Program Resume Instruction
61H A15:A8 B0H Program Suspend Instruction
62H A23:A16 30H Resume Instruction
63H A31:A24 B0H Suspend Instruction
A1:A0 Reserved = 11b
64H F7H Status Register Polling Device Busy

A7:A2 111101b: Use of legacy polling is supported by reading the status register
with 05h instruction and checking WIP bit [0] (0=ready, 1=busy)
Exit Deep Power-down to next operation delay - 10µs
Delay = (count +1)*unit
A14:A8
A12:A8 = count = 9 = 01001b
65H A9H A14:A13 units = 01b = 1µs
Exit Power-down Instruction - ABH = 10101011b
A15
A15 = 1b
A22:A16 A22:A16 = 1010101b
66H D5H Enter Power-down Instruction - B9H = 10111001b
A23
A23 = 1b
A30:A24 A30:A24 = 1011100
67H 5CH Deep Power-down Supported

A31 0:supported
1:not supported

SST26WF064C

th
4-4-4 mode disable sequences
A3:A0 Xxx1b: issue FF instruction
68H 29H 1xxxb: issue the Soft Reset 66/99 sequence.
4-4-4 mode enable sequences
A7:A4
X_xx1xb: issue instruction 38h
4-4-4 mode enable sequences
A8
A8 = 0
0-4-4 mode supported
A9 0:not supported
69H C2H
1:supported
0-4-4 Mode Exit Method
A15:A10 X1_xxxx:Mode Bit[7:0] Not= AXh
1x_xxxx Reserved = 1
0-4-4 Mode Entry Method
A19:A16 X1xxb: M[7:0]=AXh
1xxxb:Reserved =1
6AH 5CH Quad Enable Requirements (QER)
A22:A20
101b: Quad Enable is bit 1 of the configuration register.
HOLD and Reset Disable
A23
0:feature is not supported
6BH A31:A24 FFH Reserved bits = 0xFF
Volatile or Non-Volatile Register and Write Enable Instructions for
Status Register 1
Xx1_xxxxb:Status Register 1 contains a mix of volatile and non-volatile
A6:A0
6C F0H bits. The 06h instruction is used to enable writing to the register.
X1x_xxxxb: Reserved = 1
1xx_xxxxb: Reserved = 1
A7 Reserved =1b
Soft Reset and Rescue Sequence Support
X1_xxxxb: reset enable instruction 66h is issued followed by reset
A13:A8
instruction 99h.
6D 30H 1x_xxxxb: exit 0-4-4 mode is required prior to other reset sequences.
Exit 4-Byte Addressing
A15:A14
Not supported
Exit 4-Byte Addressing
6E A23:A16 C0H Not supported
A23 and A22 are Reserved bits which are = 1
Enter 4-Byte Addressing
6F A31:A24 80H Not supported
1xxx_xxxx: Reserved = 1
JEDEC Sector Map Parameter Table
Sector Map
A7:A2=Reserved=111111b
100H A7:A0 FFH
A1=Descriptor Type = Map=1b
A0=Last map = 1b
101H A15:A8 00H Configuration ID = 00h
102H A23:A16 04H Region Count = 5 Regions
103H A31:A24 FFH Reserved = FFh

SST26WF064C
Region 0 supports 4Kbyte erase and 8Kbyte erase
104H A7:A0 F3H A3:A0=0011b
Region 0 Size
4 * 8Kbytes = 32Kbytes
105H A15:A8 7FH Count=32Kbytes/256 bytes= 128
Value = count -1 =127
A31:A8 = 00007Fh
106H A23:A16 00H
107H A31:A24 00H
Region 1 supports 4Kbyte erase and 32Kbyte erase
108H A7:A0 F5H A3:A0 = 0101b
A7:A4=Reserved = 1111b
Region 1 size
1 * 32Kbytes = 32Kbytes
A31:A8 = 00007Fh
10AH A23:A16 00H
10BH A31:A24 00H
Region 2 supports 4 KByte erase and 64 KByte erase
10CH A7:A0 F9H A3:A0 = 1001b
Region 2 size
126 * 64 KBytes = 8064 KBytes
10DH A15:A8 FFH Count=8064Kbytes/256 bytes= 32256
A31:A8 = 007DFFh
10EH A23:A16 7DH
10FH A31:A24 00H
110H A7:A0 F5H A3:A0 = 0101b
Region 3 size
111H A15:A8 7FH Count=32 KBytes/256 bytes= 128
A31:A8 = 00007Fh
112H A23:A16 00H
113H A31:A24 00H
114H A7:A0 F3H A3:A0=0011b
Region 4 Size
A31:A8 = 00007Fh
116H A23:A16 00H
117H A31:A24 00H

SST26WF064C
SST26WF064C (Vendor) Parameter Table
SST26WF064C Identification
200H A7:A0 BFH Manufacturer ID
201H A15:A8 26H Memory Type
202H A23:A16 53H Device ID
SST26WF064C=53H
SST26WF064C Interface
Interfaces Supported
000: SPI only
001: Power up default is SPI; Quad can be enabled/disabled
A2:A0
010: Reserved
: :
111: Reserved
Supports Enable Quad
A3 0: not supported
204H B9H 1: supported
Supports Hold#/Reset# Function
000: Hold#
A6:A4 001: Reset#
010: HOLD/Reset#
011: Hold# & I/O when in SQI(4-4-4), 1-4-4 or 1-1-4 Read
Supports Software Reset
A7 0: not supported
1: supported
Supports Quad Reset
A8 0: not supported
1: supported
A10:A9 Reserved. Bits default to all 1’s
Byte-Program or Page-Program (256 Bytes)
A13:A11 011: Byte Program/Page Program in SPI and Quad Page Program once
205H DFH Quad is enabled
Program-Erase Suspend Supported
A14 0: Not Supported
1: Program/Erase Suspend Supported
Deep Power-Down Mode Supported
A15 0: Not Supported
1: Deep Power-Down Mode Supported

SST26WF064C
OTP Capable (Security ID) Supported
A16 0: not supported
1: supported
Supports Block Group Protect
1: supported
Supports Independent Block Protect
206H FDH
1: supported
Supports Independent non Volatile Lock (Block or Sector becomes
OTP)
A19
0: not supported
1: supported
208H A7:A0 65H VDD Minimum Supply Voltage
209H A15:A8 F1H 1.65V (F165)
20AH A23:A16 95H VDD Maximum Supply Voltage
20BH A31:A24 F1H 1.95V (F195H)
Typical time out for Byte-Program: 50 µs
20CH A7:A0 32H Typical time out for Byte Program is in µs. Represented by conversion of
the actual time from the decimal to hexadecimal number.
20DH A15:A8 FFH Reserved. Bits default to all 1’s.
20EH A23:A16 0AH Typical time out for page program: 1.0ms (xxH*(0.1ms)
Typical time out for Sector-Erase/Block-Erase: 18 ms
20FH A31:A24 12H Typical time out for Sector/Block-Erase is in ms. Represented by conversion
of the actual time from the decimal to hexadecimal number.
Typical time out for Chip-Erase: 35 ms
210H A7:A0 23H Typical time out for Chip-Erase is in ms. Represented by conversion of
Max. time out for Byte-Program: 70 µs
211H A15:A8 46H Typical time out for Byte Program is in µs. Represented by conversion of
Max time out for Page-Program: 1.5ms.
213H A31:A24 0FH
Typical time out for Page Program in xxH * (0.1ms) ms
Max. time out for Sector Erase/Block Erase: 25ms.
214H A7:A0 19H
Max time out for Sector/Block Erase in ms
Max. time out for Chip Erase: 50ms.
215H A15:A8 32H
Max time out for Chip Erase in ms.
Max. time out for Program Security ID: 1.5 ms
216H A23:A16 0FH
Max time out for Program Security ID in xxH*(0.1ms) ms
Max. time out for Write-Protection Enable Latency: 25 ms
217H A31:A24 19H Max time out for Write-Protection Enable Latency is in ms. Represented by con-
version of the actual time from the decimal to hexadecimal number.
Max. time Write-Suspend Latency: 25 µs
218H A23:A16 19H Max time out for Write-Suspend Latency is in µs. Represented by conversion of
Max. time to Deep Power-Down
219H A31:A24 03H
3 µs = 03H

SST26WF064C
Max. time out from Deep Power-Down mode to Standby mode
21AH A23:A16 0AH
10 µs = 0AH
21BH A31:A24 FFH Reserved. Bits default to all 1’s.
21CH A23:A16 FFH Reserved. Bits default to all 1’s.
21DH A31:A24 FFH Reserved. Bits default to all 1’s.
21EH A23:A16 FFH Reserved. Bits default to all 1’s.
21FH A31:A24 FFH Reserved. Bits default to all 1’s.
Supported Instructions
220H A7:A0 00H No Operation
221H A15:A8 66H Reset Enable
222H A23:A16 99H Reset Memory
223H A31:A24 38H Enable Quad I/O
224H A7:A0 FFH Reset Quad I/O
225H A15:A8 05H Read Status Register
226H A23:A16 01H Write Status Register
227H A31:A24 35H Read Configuration Register
228H A7:A0 06H Write Enable
229H A15:A8 04H Write Disable
22AH A23:A16 02H Byte Program or Page Program
22BH A31:A24 32H SPI Quad Page Program
22CH A7:A0 B0H Suspends Program/Erase
22DH A15:A8 30H Resumes Program/Erase
22EH A23:A16 72H Read Block-Protection register
22FH A31:A24 42H Write Block Protection Register
230H A7:A0 8DH Lock Down Block Protection Register
231H A15:A8 E8H non-Volatile Write-Lock Down Register
232H A23:A16 98H Global Block Protection Unlock
233H A31:A24 88H Read Security ID
234H A7:A0 A5H Program User Security ID Area
235H A15:A8 85H Lockout Security ID Programming
236H A23:A16 C0H Set Burst Length
237H A31:A24 9FH JEDEC-ID
238H A7:A0 AFH Quad J-ID
239H A15:A8 5AH SFDP
23AH A23:A16 B9H Deep Power-Down Mode
23BH A31:A24 ABH Release Deep Power-Down Mode
(1-4-4) SPI nB Burst with Wrap Number of Wait states (dummy
A4:A0 clocks) needed before valid output
23CH 06H 00110b: 6 clocks of dummy cycle
(1-4-4) SPI nB Burst with Wrap Number of Mode Bits
A7:A5
000b: Set Mode bits are not supported
23DH A15:A8 ECH (1-4-4) SPI nB Burst with Wrap Opcode

SST26WF064C
(4-4-4) SQI nB Burst with Wrap Number of Wait states (dummy
A20:A16 clocks) needed before valid output
23EH 06H 00110b: 6 clocks of dummy cycle
(4-4-4) SQI nB Burst with Wrap Number of Mode Bits
A23:A21
000b: Set Mode bits are not supported
23FH A31:A24 0CH (4-4-4) SQI nB Burst with Wrap Opcode
(1-1-1) Read Memory Number of Wait states (dummy clocks) needed
240H 00H 00000b: Wait states/dummy clocks are not supported.
(1-1-1) Read Memory Number of Mode Bits
A7:A5
000b: Mode bits are not supported,
241H A15:A8 03H (1-1-1) Read Memory Opcode
(1-1-1) Read Memory at Higher Speed Number of Wait states
A20:A16 (dummy clocks) needed before valid output
242H 08H 01000: 8 clocks (8 bits) of dummy cycle
(1-1-1) Read Memory at Higher Speed Number of Mode Bits
A23:A21
000b: Mode bits are not supported,
243H A31:A24 0BH (1-1-1) Read Memory at Higher Speed Opcode
Security ID
248H A7:A0 FFH Security ID size in bytes
Example: If the size is 2 KBytes, this field would be 07FFH
Security ID Range
249H A15:A8 07H Unique ID
0000H - 0007H
(Pre-programmed at factory)
User Programmable 0008H - 07FFH
24AH A23:A16 FFH Reserved. Bits default to all 1’s.

24BH A31:A24 FFH Reserved. Bits default to all 1’s.
Memory Organization/Block Protection Bit Mapping 1
Section 1: Sector Type Number:
24CH A7:A0 02H
Sector type in JEDEC Parameter Table (bottom, 8 KByte)
Section 1 Number of Sectors
24DH A15:A8 02H
Four of 8KB block (2n)
Section 1 Block Protection Bit Start
((2m) +1)+ c, c=FFH or -1, m= 7 for 64 Mb
Address bits are Read Lock bit locations and Even Address bits are Write
24EH A23:A16 FFH Lock bit locations. The most significant (left-most) bit indicates the sign of
the integer; it is sometimes called the sign bit. If the sign bit is zero, then
the number is greater than or equal to zero, or positive. If the sign bit is
one then the number is less than zero or negative.

SST26WF064C
Section 1 (bottom) Block Protection Bit End
((2m) +1)+ c, c=06H or 6, m= 7 for 64 Mb
24FH A31:A24 06H Lock bit locations. The most significant (left-most) bit indicates the sign of
Section 2: Sector Type Number
250H A7:A0 03H
Sector type in JEDEC Parameter Table (32KB Block)
251H A15:A8 00H
One of 32KB Block (2n, n=0)
((2m) +1)+ c, c=FDH or -3, m= 7 for 64 Mb
The most significant (left-most) bit indicates the sign of the integer; it is
252H A23:A16 FDH
sometimes called the sign bit. If the sign bit is zero, then the number is
greater than or equal to zero, or positive. If the sign bit is one then the
number is less than zero or negative.
Section 2 Block Protection Bit End
((2m) +1)+ c, c=FDH or -3, m= 7 for 64 Mb
253H A31:A24 FDH
254H A7:A0 04H
255H A15:A8 07H
126 of 64KB Block (2m-2, m= 7 for 64 Mb)
256H A23:A16 00H
Section 3 Block Protection Bit starts at 00H
257H A31:A24 FCH
((2m) +1)+ c, c=FCH or -4, m= 7 for 64 Mb
258H A7:A0 03H
259H A15:A8 00H
One of 32KB Block (2n, n=0)
((2m) +1)+ c, c=FEH or -2, m= 7 for 64 Mb
25AH A23:A16 FEH
((2m) +1)+ c, c=FEH or -2, m= 7 for 64 Mb
25BH A31:A24 FEH
Section 5 Sector Type Number:
25CH A7:A0 02H
Sector type in JEDEC Parameter Table (top, 8 KByte)
25DH A15:A8 02H
Four of 8KB block (2n)

SST26WF064C
((2m) +1)+ c, c=07H or 7, m= 7 for 64 Mb
25EH A23:A16 07H Lock bit locations. The most significant (left-most) bit indicates the sign of
Section 5 (Top) Block Protection Bit End
(((2m) +1)+ c, c=0EH or 14, m= 7 for 64 Mb,
25FH A31:A24 0EH Lock bit locations. The most significant (left-most) bit indicates the sign of
1. See “Mapping Guidance Details” for more detailed mapping information

SST26WF064C
11.1 Mapping Guidance Details number of these uniform and different sectors/blocks
from address 000000H to the full range of Memory and
The SFDP Memory Organization/Block Protection Bit the associated Block Locking Register bits of each sec-
Mapping defines the memory organization including tor/block.
uniform sector/block sizes and different contiguous
sectors/blocks sizes. In addition, this bit defines the Each major Section is defined as follows:
TABLE 11-2: SECTION DEFINITION

Major Section X Section X: Sector Type Number
Section X: Number of Sectors
Section X: Block-Protection Register Bit Start Location
Section X: Block-Protection Register Bit End Location
A Major Section consists of Sector Type Number, Num-

ber of Sector of this type, and the Block-Protection Bit
Start/End locations. This is tied directly to JEDEC Flash
Parameter Table Sector Size Type (in 7th DWORD and
8th DWORD section). Note that the contiguous 4KByte
Sectors across the full memory range are not included
on this section because they are not defined in the
JEDEC Flash Parameter Table Sector Size Type sec-
tion. Only the sectors/blocks that are dependently tied
with the Block-Protection Register bits are defined. A
major section is a partition of contiguous same-size
sectors/blocks. There will be several Major Sections as
you dissect across memory from 000000h to the full
range. Similar sector/block size that re-appear may be
defined as a different Major Section.
11.1.1 SECTOR TYPE NUMBER

Sector Type Number is the sector/block size typed
defined in JEDEC Flash Parameter Table: SFDP
address locations 4CH, 4EH, 50H, and 52H. For SFDP
address location 4CH, which is Sector Type 1, the size
is represented by 01H; SFDP address location 4EH,
Sector Type 2, size is represented by 02H; SFDP
address location 50H, Sector Type 3, size is repre-
sented by 03H; and SFDP address location 52H, Sec-
tor Type 4, size is represented by 04H. Contiguous
Same Sector Type # Size can re-emerge across the
memory range and this Sector Type # will indicate that
it is a separate/independent Major Section from the
previous contiguous sectors/blocks.
11.1.2 NUMBER OF SECTORS

Number of Sectors represents the number of contigu-
ous sectors/blocks with similar size. A formula calcu-
lates the contiguous sectors/blocks with similar size.
Given the sector/block size, type, and the number of
sectors, the address range of these sectors/blocks can
be determined along with specific Block Locking Reg-
ister bits that control the read/write protection of each
sectors/blocks.

SST26WF064C
11.1.3 BLOCK-PROTECTION REGISTER 11.1.4 BLOCK PROTECTION REGISTER

BIT START LOCATION (BPSL) BIT END LOCATION (BPEL)
Block-Protection Register Bit Start Location (BPSL) Block Protection Register Bit End Location designates
designates the start bit location in the Block-Protection the end bit location in the Block Protection Register bit
Register where the first sector/block of this Major Sec- where the last sector/block of this Major Section ends.
tion begins. If the value of BPSL is 00H, this location is The value in this field is a constant value adder (c) for
the 0 bit location. If the value is other than 0, then this a given formula or equation, (2m + 1) + (c). See “Mem-
value is a constant value adder (c) for a given formula, ory Configuration”
(2m + 1) + (c). See “Memory Configuration”.
11.1.5 MEMORY CONFIGURATION
From the initial location, there will be a bit location for
every increment by 1 until it reaches the Block Protec- For the SST26WF064C family, the memory configura-
tion Register Bit End Location (BPEL). This number tion is setup with different contiguous block sizes from
range from BPSL to BPEL will correspond to, and be bottom to the top of the memory. For example, starting
equal to, the number of sectors/blocks on this Major from bottom of memory it has four 8KByte blocks, one
Section. 32KByte block, x number of 64KByte blocks depending
on memory size, then one 32KByte block, and four
8KByte block on the top of memory. See Table 11-3.
TABLE 11-3: MEMORY BLOCK DIAGRAM REPRESENTATION

8 KByte Bottom Block Section 1: Sector Type Number
(from 000000H) Section 1: Number of Sectors
Section 1: Block-Protection Register Bit Start Location
Section 1: Block-Protection Register Bit End Location
32 KByte Section 2: Sector Type Number
Section 2: Number of Sectors
8 KByte (Top Block) Section 5: Sector Type Number
Classifying these sector/block sizes via the Sector For the Number of Sectors associated with the contig-
Type derived from JEDEC Flash Parameter Table: uous sectors/blocks, a formula is used to determine the
SFDP address locations 4EH, 50H, and 52H is as fol- number of sectors/blocks of these Sector Types:
lows: • 8KByte Block (Type 2) is calculated by 2n. n is a byte.
• 8KByte Blocks are classified as Sector Type 2 • 32KByte Block (Type 3) is calculated by 2n. n is a
(@4EH of SFDP) byte.
• 32KByte Blocks are classified as Sector Type 3 • 64KByte Block (Type 4) is calculated by (2m - 2). m
(@50H of SFDP) can either be a 4, 5, 6, 7 or 8 depending on the mem-
• 64KByte Blocks are classified as Sector Type 4 ory size. This m field is going to be used for the
(@52H of SFDP) 64KByte Block Section and will also be used for the
Block Protection Register Bit Location formula.

SST26WF064C
m will have a constant value for specific densities and going to be placed in the Block Protection Bit Start/End
is defined as: field table are the constant value adder (c) in the for-
• 8Mbit = 4 mula and are represented in two’s compliment except
when the value is 00H. If the value is 00H, this location
• 16Mbit = 5
is the 0 bit location. If the value is other than 0, then this
• 32Mbit = 6 is a constant value adder (c) that will be used in the for-
• 64Mbit = 7 mula. The most significant (left most) bit indicates the
• 128Mbit = 8 sign of the integer; it is sometimes called the sign bit.
If the sign bit is zero, then the number is greater than or
Block Protect Register Start/End Bits are mapped in the
equal to zero, or positive. If the sign bit is one, then the
SFDP by using the formula (2m + 1) + (c). “m” is a con-
number is less than zero, or negative.
stant value that represents the different densities from
8Mbit to 128Mbit (used also in the formula calculating See Table 11-4 for an example of this formula.
number of 64Kbyte Blocks above). The values that are
TABLE 11-4: BPSL/BPEL EQUATION WITH ACTUAL CONSTANT ADDER DERIVED FROM THE
FORMULA (2M + 1) + (C)
Block Size 8 Mbit to 128 Mbit Comments
8 KByte (Type 2) Bottom BPSL = (2m + 1) + 0FFH 0FFH = -1; 06H = 6
BPEL = (2m + 1) + 04H Odd address bits are Read-Lock bit
locations and even address bits are
Write-Lock bit locations.
32 KByte (Type 3) BPSL = BPEL= (2m + 1) + 0FDH 0FDH= -3
64 KByte (Type 4) BPSL = 00H 00H is Block-Protection Register bit 0
BPEL = (2m + 1) + 0FCH location; 0FCH = -4
32 KByte (Type 3) BPSL = BPEL= (2m + 1) + 0FEH 0FEH=-2
8 KByte (Type 2) Top BPSL = (2m
+ 1) + 07H 07H = 7; 0EH = 14
BPEL = (2m + 1) + 0EH Odd address bits are Read-Lock bit
locations and even address bits are
Write-Lock bit locations.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, AVR,
and may be superseded by updates. It is your responsibility to AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
ensure that your application meets with your specifications. CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
MICROCHIP MAKES NO REPRESENTATIONS OR KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
IMPLIED, WRITTEN OR ORAL, STATUTORY OR OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
OTHERWISE, RELATED TO THE INFORMATION, Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST
INCLUDING BUT NOT LIMITED TO ITS CONDITION, Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
QUALITY, PERFORMANCE, MERCHANTABILITY OR trademarks of Microchip Technology Incorporated in the U.S.A.
FITNESS FOR PURPOSE. Microchip disclaims all liability and other countries.
arising from this information and its use. Use of Microchip ClockWorks, The Embedded Control Solutions Company,
devices in life support and/or safety applications is entirely at EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
the buyer’s risk, and the buyer agrees to defend, indemnify and mTouch, Precision Edge, and Quiet-Wire are registered
hold harmless Microchip from any and all damages, claims, trademarks of Microchip Technology Incorporated in the U.S.A.
suits, or expenses resulting from such use. No licenses are Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
conveyed, implicitly or otherwise, under any Microchip Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
intellectual property rights unless otherwise stated. CodeGuard, CryptoAuthentication, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
Microchip received ISO/TS-16949:2009 certification for its worldwide the U.S.A.
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California Silicon Storage Technology is a registered trademark of Microchip
and India. The Company’s quality system processes and procedures Technology Inc. in other countries.
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and GestIC is a registered trademark of Microchip Technology
analog products. In addition, Microchip’s quality system for the design Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
and manufacture of development systems is ISO 9001:2000 certified.
Inc., in other countries.
All other trademarks mentioned herein are property of their
QUALITY MANAGEMENT SYSTEM respective companies.

© 2016-2017, Microchip Technology Incorporated, All Rights
CERTIFIED BY DNV Reserved.
ISBN: 978-1-5224-1787-3
== ISO/TS 16949 ==

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SST26WF064C-104I/TD SST26WF064CT-104I/TD SST26WF064CT-104I/SM SST26WF064C-104I/MF
SST26WF064CT-104I/MF SST26WF064C-104I/SM SST26WF064C-104I/SO SST26WF064CT-104I/SO

SST26WF064C: 1.8V, 64 Mbit Serial Quad I/O (SQI) Flash Memory

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SST26WF064C: 1.8V, 64 Mbit Serial Quad I/O (SQI) Flash Memory

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SST26WF064C

1.8V, 64 Mbit Serial Quad I/O (SQI) Flash Memory

 2016-2017 Microchip Technology Inc. Preliminary DS20005430B-page 1

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Customer Notification System

DS20005430B-page 2 Preliminary  2016-2017 Microchip Technology Inc.

1.0 BLOCK DIAGRAM

FIGURE 1-1: FUNCTIONAL BLOCK DIAGRAM

WP# HOLD# SCK CE# SIO [3:0] RESET#

 2016-2017 Microchip Technology Inc. Preliminary DS20005430B-page 3

2.0 PIN DESCRIPTION

FIGURE 2-1: PIN DESCRIPTIONS

DS20005430B-page 4 Preliminary  2016-2017 Microchip Technology Inc.

TABLE 2-1: PIN DESCRIPTION

 2016-2017 Microchip Technology Inc. Preliminary DS20005430B-page 5

3.0 MEMORY ORGANIZATION

FIGURE 3-1: MEMORY MAP

2 Sectors for 8 KByte blocks

16 Sectors for 64 KByte blocks

Bottom of Memory Block

DS20005430B-page 6 Preliminary  2016-2017 Microchip Technology Inc.

FIGURE 4-1: SPI PROTOCOL (TRADITIONAL 25 SERIES SPI DEVICE)

FIGURE 4-2: SQI SERIAL QUAD I/O PROTOCOL

4.1 Device Protection 4.1.1 INDIVIDUAL BLOCK PROTECTION

 2016-2017 Microchip Technology Inc. Preliminary DS20005430B-page 7

TABLE 4-1: WRITE PROTECTION LOCK-DOWN STATES

1. Default at power-up Register settings for SST26WF064C

DS20005430B-page 8 Preliminary  2016-2017 Microchip Technology Inc.

FIGURE 4-3: HOLD CONDITION WAVEFORM.

Active Hold Active Hold Active

4.5 Reset Operation 4.5.1 HARDWARE RESET OPERATION

 2016-2017 Microchip Technology Inc. Preliminary DS20005430B-page 9

TABLE 4-2: HARDWARE AND SOFTWARE FUNCTIONALITY

DS20005430B-page 10 Preliminary  2016-2017 Microchip Technology Inc.

TABLE 4-3: STATUS REGISTER

4.6.1 WRITE-ENABLE LATCH (WEL) • Program Security ID instruction completion

 2016-2017 Microchip Technology Inc. Preliminary DS20005430B-page 11

4.6.3 WRITE SUSPEND PROGRAM

4.6.4 WRITE PROTECTION LOCK-DOWN

4.6.5 SECURITY ID STATUS (SEC)

DS20005430B-page 12 Preliminary  2016-2017 Microchip Technology Inc.

4.7 Configuration Register

TABLE 4-4: CONFIGURATION REGISTER

1. SST26WF064C default at Power-up is ‘0’

4.7.1 I/O CONFIGURATION (IOC) 4.7.3 RESET/HOLD ENABLE (RSTHLD)

 2016-2017 Microchip Technology Inc. Preliminary DS20005430B-page 13

TABLE 5-1: DEVICE OPERATION INSTRUCTIONS FOR SST26WF064C (1 OF 2)

DS20005430B-page 14 Preliminary  2016-2017 Microchip Technology Inc.

TABLE 5-1: DEVICE OPERATION INSTRUCTIONS FOR SST26WF064C (CONTINUED) (2 OF 2)

 2016-2017 Microchip Technology Inc. Preliminary DS20005430B-page 15

FIGURE 5-1: RESET SEQUENCE

Note: C[1:0] = 66H; C[3:2] = 99H

FIGURE 5-2: READ SEQUENCE (SPI)

SI 03 ADD. ADD. ADD.

5.4 Enable Quad I/O (EQIO)

DS20005430B-page 16 Preliminary  2016-2017 Microchip Technology Inc.