8 Mbit (x8) Multi-Purpose Flash

SST39LF080 / SST39VF080
SST39LF/VF0803.0 & 2.7V 8Mb (x8) MPF memories EOL Data Sheet
FEATURES:
• Organized as 1M x8 • Latched Address and Data
• Single Voltage Read and Write Operations • Fast Erase and Byte-Program:
– 3.0-3.6V for SST39LF080 – Sector-Erase Time: 18 ms (typical)
– 2.7-3.6V for SST39VF080 – Block-Erase Time: 18 ms (typical)
• Superior Reliability – Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Endurance: 100,000 Cycles (typical)
– Chip Rewrite Time:
– Greater than 100 years Data Retention 15 seconds (typical) for SST39LF/VF080
• Low Power Consumption • Automatic Write Timing
(typical values at 14 MHz)
– Internal VPP Generation
– Active Current: 12 mA (typical)
– Standby Current: 4 µA (typical) • End-of-Write Detection
– Auto Low Power Mode: 4 µA (typical) – Toggle Bit
• Sector-Erase Capability – Data# Polling
– Uniform 4 KByte sectors • CMOS I/O Compatibility
• Block-Erase Capability • JEDEC Standard
– Uniform 64 KByte blocks – Flash EEPROM Pinouts and command sets
• Fast Read Access Time: • Packages Available
– 55 ns for SST39LF080 – 40-lead TSOP (10mm x 20mm)
– 70 and 90 ns for SST39VF080 – 48-ball TFBGA (6mm x 8mm)

PRODUCT DESCRIPTION
The SST39LF/VF080 devices are 1M x8 CMOS Multi-Pur- native flash technologies. The total energy consumed is a
pose Flash (MPF) manufactured with SST’s proprietary, function of the applied voltage, current, and time of applica-
high-performance CMOS SuperFlash technology. The tion. Since for any given voltage range, the SuperFlash
split-gate cell design and thick-oxide tunneling injector technology uses less current to program and has a shorter
attain better reliability and manufacturability compared with erase time, the total energy consumed during any Erase or
alternate approaches. The SST39LF080 write (Program or Program operation is less than alternative flash technolo-
Erase) with a 3.0-3.6V power supply. The SST39VF080 gies. They also improve flexibility while lowering the cost for
write (Program or Erase) with a 2.7-3.6V power supply. program, data, and configuration storage applications.
They conform to JEDEC standard pinouts for x8 memories.
The SuperFlash technology provides fixed Erase and Pro-
Featuring high performance Byte-Program, the SST39LF/ gram times, independent of the number of Erase/Program
VF080 devices provide a typical Byte-Program time of 14 cycles that have occurred. Therefore the system software
µsec. The devices use Toggle Bit or Data# Polling to indi- or hardware does not have to be modified or de-rated as is
cate the completion of Program operation. To protect necessary with alternative flash technologies, whose Erase
against inadvertent write, they have on-chip hardware and and Program times increase with accumulated Erase/Pro-
Software Data Protection schemes. Designed, manufac- gram cycles.
tured, and tested for a wide spectrum of applications,
To meet high density, surface mount requirements, the
these devices are offered with a guaranteed typical
SST39LF/VF080 are offered in 40-lead TSOP and 48-
endurance of 10,000 cycles. Data retention is rated at
ball TFBGA packages. See Figures 1 and 2 for pin
greater than 100 years.
assignments.
The SST39LF/VF080 devices are suited for applications
that require convenient and economical updating of pro-
gram, configuration, or data memory. For all system appli-
cations, they significantly improve performance and
reliability, while lowering power consumption. They inher-
ently use less energy during Erase and Program than alter-

©2007 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
S71146-07-EOL 6/07 MPF is a trademark of Silicon Storage Technology, Inc.
1 These specifications are subject to change without notice.
 8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet
Device Operation operation, the host is free to perform additional tasks. Any
commands issued during the internal Program operation
Commands are used to initiate the memory operation func-
are ignored.
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE# Sector/Block-Erase Operation
low. The address bus is latched on the falling edge of WE# The Sector- (or Block-) Erase operation allows the system
or CE#, whichever occurs last. The data bus is latched on to erase the device on a sector-by-sector (or block-by-
the rising edge of WE# or CE#, whichever occurs first. block) basis. The SST39LF/VF080 offer both Sector-Erase
The SST39LF/VF080 also have the Auto Low Power and Block-Erase mode. The sector architecture is based
mode which puts the device in a near standby mode after on uniform sector size of 4 KByte. The Block-Erase mode
data has been accessed with a valid Read operation. This is based on uniform block size of 64 KByte. The Sector-
reduces the IDD active read current from typically 15 mA to Erase operation is initiated by executing a six-byte com-
typically 4 µA. The Auto Low Power mode reduces the typi- mand sequence with Sector-Erase command (30H) and
cal IDD active read current to the range of 1 mA/MHz of sector address (SA) in the last bus cycle. The Block-Erase
Read cycle time. The device exits the Auto Low Power operation is initiated by executing a six-byte command
mode with any address transition or control signal transition sequence with Block-Erase command (50H) and block
used to initiate another Read cycle, with no access time address (BA) in the last bus cycle. The sector or block
penalty. Note that the device does not enter Auto Low address is latched on the falling edge of the sixth WE#
Power mode after power-up with CE# held steadily low until pulse, while the command (30H or 50H) is latched on the
the first address transition or CE# is driven high. rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-of-
Erase operation can be determined using either Data#
Read Polling or Toggle Bit methods. See Figures 9 and 10 for tim-
The Read operation of the SST39LF/VF080 is controlled ing waveforms. Any commands issued during the Sector-
by CE# and OE#, both have to be low for the system to or Block-Erase operation are ignored.
obtain data from the outputs. CE# is used for device selec-
tion. When CE# is high, the chip is deselected and only Chip-Erase Operation
standby power is consumed. OE# is the output control and
is used to gate data from the output pins. The data bus is in The SST39LF/VF080 provide a Chip-Erase operation,
high impedance state when either CE# or OE# is high. which allows the user to erase the entire memory array to
Refer to the Read cycle timing diagram for further details the “1” state. This is useful when the entire device must be
(Figure 3). quickly erased.
The Chip-Erase operation is initiated by executing a six-
Byte-Program Operation byte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
The SST39LF/VF080 are programmed on a byte-by-byte
operation begins with the rising edge of the sixth WE# or
basis. Before programming, the sector where the byte
CE#, whichever occurs first. During the Erase operation,
exists must be fully erased. The Program operation is
the only valid read is Toggle Bit or Data# Polling. See Table
accomplished in three steps. The first step is the three-byte
4 for the command sequence, Figure 8 for timing diagram,
load sequence for Software Data Protection. The second
and Figure 19 for the flowchart. Any commands issued dur-
step is to load byte address and byte data. During the Byte-
ing the Chip-Erase operation are ignored.
Program operation, the addresses are latched on the falling
edge of either CE# or WE#, whichever occurs last. The
data is latched on the rising edge of either CE# or WE#, Write Operation Status Detection
whichever occurs first. The third step is the internal Pro- The SST39LF/VF080 provide two software means to detect
gram operation which is initiated after the rising edge of the the completion of a write (Program or Erase) cycle, in order
fourth WE# or CE#, whichever occurs first. The Program to optimize the system Write cycle time. The software
operation, once initiated, will be completed within 20 µs. detection includes two status bits: Data# Polling (DQ7) and
See Figures 4 and 5 for WE# and CE# controlled Program Toggle Bit (DQ6). The End-of-Write detection mode is
operation timing diagrams and Figure 16 for flowcharts. enabled after the rising edge of WE#, which initiates the
During the Program operation, the only valid reads are internal Program or Erase operation.
Data# Polling and Toggle Bit. During the internal Program

©2007 Silicon Storage Technology, Inc. S71146-07-EOL 6/07

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8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet
The actual completion of the nonvolatile write is asynchro- Data Protection
nous with the system; therefore, either a Data# Polling or
The SST39LF/VF080 provide both hardware and soft-
Toggle Bit read may be simultaneous with the completion
ware features to protect nonvolatile data from inadvertent
of the Write cycle. If this occurs, the system may possibly
writes.
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine Hardware Data Protection
should include a loop to read the accessed location an Noise/Glitch Protection: A WE# or CE# pulse of less than 5
additional two (2) times. If both reads are valid, then the ns will not initiate a Write cycle.
device has completed the Write cycle, otherwise the rejec-
tion is valid. VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Data# Polling (DQ7) Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
When the SST39LF/VF080 are in the internal Program
ent writes during power-up or power-down.
operation, any attempt to read DQ7 will produce the com-
plement of the true data. Once the Program operation is
completed, DQ7 will produce true data. Note that even Software Data Protection (SDP)
though DQ7 may have valid data immediately following the The SST39LF/VF080 provide the JEDEC approved Soft-
completion of an internal Write operation, the remaining ware Data Protection scheme for all data alteration opera-
data outputs may still be invalid: valid data on the entire tions, i.e., Program and Erase. Any Program operation
data bus will appear in subsequent successive Read requires the inclusion of the three-byte sequence. The
cycles after an interval of 1 µs. During internal Erase opera- three-byte load sequence is used to initiate the Program
tion, any attempt to read DQ7 will produce a ‘0’. Once the operation, providing optimal protection from inadvertent
internal Erase operation is completed, DQ7 will produce a Write operations, e.g., during the system power-up or
‘1’. The Data# Polling is valid after the rising edge of fourth power-down. Any Erase operation requires the inclusion of
WE# (or CE#) pulse for Program operation. For Sector-, six-byte sequence. The SST39LF/VF080 devices are
Block- or Chip-Erase, the Data# Polling is valid after the ris- shipped with the Software Data Protection permanently
ing edge of sixth WE# (or CE#) pulse. See Figure 6 for enabled. See Table 4 for the specific software command
Data# Polling timing diagram and Figure 17 for a flowchart. codes. During SDP command sequence, invalid com-
mands will abort the device to Read mode within TRC.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any con- Common Flash Memory Interface (CFI)
secutive attempts to read DQ6 will produce alternating 1s The SST39LF/VF080 also contain the CFI information to
and 0s, i.e., toggling between 1 and 0. When the internal describe the characteristics of the device. In order to enter
Program or Erase operation is completed, the DQ6 bit will the CFI Query mode, the system must load the three-byte
stop toggling. The device is then ready for the next opera- sequence, similar to the Software ID Entry command. The
tion. The Toggle Bit is valid after the rising edge of fourth last byte cycle of this command loads 98H (CFI Query
WE# (or CE#) pulse for Program operation. For Sector-, command) to address 5555H. Once the device enters the
Block-, or Chip-Erase, the Toggle Bit is valid after the rising CFI Query mode, the system can read CFI data at the
edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle addresses given in Tables 5 through 7. The system must
Bit timing diagram and Figure 17 for a flowchart. write the CFI Exit command to return to Read mode from
the CFI Query mode.

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 8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet
Product Identification Product Identification Mode Exit/
The Product Identification mode identifies the device as CFI Mode Exit
SST39LF080 or SST39VF080 and manufacturer as SST. In order to return to the standard Read mode, the Software
This mode may be accessed by software operations. Product Identification mode must be exited. Exit is accom-
Users may use the Software Product Identification opera- plished by issuing the Software ID Exit command
tion to identify the part (i.e., using the device ID) when using sequence, which returns the device to the Read operation.
multiple manufacturers in the same socket. For details, see This command may also be used to reset the device to the
Table 4 for software operation, Figure 11 for the Software Read mode after any inadvertent transient condition that
ID Entry and Read timing diagram and Figure 18 for the apparently causes the device to behave abnormally, e.g.,
Software ID Entry command sequence flowchart. not read correctly. Please note that the Software ID Exit/
CFI Exit command is ignored during an internal Program or
TABLE 1: PRODUCT IDENTIFICATION Erase operation. See Table 4 for software command
Address Data codes, Figure 13 for timing waveform and Figure 18 for a
flowchart.
Manufacturer’s ID 0000H BFH
Device ID
SST39LF/VF080 0001H D8H
T1.3 1146

FUNCTIONAL BLOCK DIAGRAM

SuperFlash
X-Decoder Memory

Memory
Address Buffer & Latches
Address
Y-Decoder

CE#
OE# Control Logic I/O Buffers and Data Latches
WE#
DQ7 - DQ0
1146 B1.2

©2007 Silicon Storage Technology, Inc. S71146-07-EOL 6/07

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8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet

A16 1 40 A17
A15 2 39 VSS
A14 3 38 NC
A13 4 37 A19
A12 5 36 A10
A11 6 35 DQ7
A9 7 34 DQ6
A8 8 33 DQ5
WE# 9 Standard Pinout 32 DQ4
NC 10 31 VDD
NC 11 Top View 30 VDD
NC 12 29 NC
A18 13 Die Up 28 DQ3
A7 14 27 DQ2
A6 15 26 DQ1
A5 16 25 DQ0
A4 17 24 OE#
A3 18 23 VSS
A2 19 22 CE#
A1 20 21 A0

1146 F01.3

FIGURE 1: Pin Assignments for 40-lead TSOP

TOP VIEW (balls facing down)

6
A14 A13 A15 A16 A17 NC NC VSS
5
A9 A8 A11 A12 A19 A10 DQ6 DQ7
4
WE# NC NC NC DQ5 NC VDD DQ4
3
NC NC NC NC DQ2 DQ3 VDD NC
1146 48-tfbga P2.2

2
A7 A18 A6 A5 DQ0 NC NC DQ1
1
A3 A4 A2 A1 A0 CE# OE# VSS

A B C D E F G H

FIGURE 2: Pin Assignments for 48-ball TFBGA

©2007 Silicon Storage Technology, Inc. S71146-07-EOL 6/07

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 8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet
TABLE 2: PIN DESCRIPTION
Symbol Pin Name Functions
AMS1-A0 Address Inputs To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the
sector. During Block-Erase AMS-A16 address lines will select the block.
DQ7-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the Write operations.
VDD Power Supply To provide power supply voltage: 3.0-3.6V for SST39LF080
2.7-3.6V for SST39VF080
VSS Ground
NC No Connection Unconnected pins.
T2.4 1146
1. AMS = Most significant address
AMS = A19 for SST39LF/VF080

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address
Read VIL VIL VIH DOUT AIN
Program VIL VIH VIL DIN AIN
Erase VIL VIH VIL X1 Sector or Block address,
XXH for Chip-Erase
Standby VIH X X High Z X
Write Inhibit X VIL X High Z/ DOUT X
X X VIH High Z/ DOUT X
Product Identification
Software Mode VIL VIL VIH See Table 4
T3.4 1146
1. X can be VIL or VIH, but no other value.

©2007 Silicon Storage Technology, Inc. S71146-07-EOL 6/07

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8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command 1st Bus 2nd Bus 3rd Bus 4th Bus 5th Bus 6th Bus
Sequence Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle
Addr1 Data Addr1 Data Addr1 Data Addr1 Data Addr1 Data Addr1 Data
Byte-Program 5555H AAH 2AAAH 55H 5555H A0H WA2 Data
Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX3 30H
Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX 3 50H
Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Software ID Entry4,5 5555H AAH 2AAAH 55H 5555H 90H
CFI Query Entry4 5555H AAH 2AAAH 55H 5555H 98H
Software ID Exit6/ XXH F0H
CFI Exit
Software ID Exit6/ 5555H AAH 2AAAH 55H 5555H F0H
CFI Exit
T4.4 1146
1. Address format A14-A0 (Hex),
Addresses A19-A15 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF080.
2. WA = Program Byte address
3. SAX for Sector-Erase; uses AMS-A12 address lines
BAX for Block-Erase; uses AMS-A16 address lines
AMS = Most significant address
AMS = A19 for SST39LF/VF080
4. The device does not remain in Software Product ID mode if powered down.
5. With AMS-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0
SST39LF/VF080 Device ID = D8H, is read with A0 = 1
6. Both Software ID Exit operations are equivalent

TABLE 5: CFI QUERY IDENTIFICATION STRING1 FOR SST39LF/VF080

Address Data Data
10H 51H Query Unique ASCII string “QRY”
11H 52H
12H 59H
13H 01H Primary OEM command set
14H 07H
15H 00H Address for Primary Extended Table
16H 00H
17H 00H Alternate OEM command set (00H = none exists)
18H 00H
19H 00H Address for Alternate OEM extended Table (00H = none exits)
1AH 00H
T5.4 1146
1. Refer to CFI publication 100 for more details.

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 8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet
TABLE 6: SYSTEM INTERFACE INFORMATION FOR SST39LF/VF080
Address Data Data
1BH 27H1 VDD Min (Program/Erase)
30H1 DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH 36H VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH 00H VPP min (00H = no VPP pin)
1EH 00H VPP max (00H = no VPP pin)
1FH 04H Typical time out for Byte-Program 2N µs (24 = 16 µs)
20H 00H Typical time out for min size buffer program 2N µs (00H = not supported)
21H 04H Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
22H 06H Typical time out for Chip-Erase 2N ms (26 = 64 ms)
23H 01H Maximum time out for Byte-Program 2N times typical (21 x 24 = 32 µs)
24H 00H Maximum time out for buffer program 2N times typical
25H 01H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)
26H 01H Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)
T6.2 1146
1. 0030H for SST39LF080 and 0027H for SST39VF080

TABLE 7: DEVICE GEOMETRY INFORMATION FOR SST39LF/VF080

Address Data Data
27H 14H Device size = 2N Bytes (14H = 20; 220 = 1 MByte)
28H 00H Flash Device Interface description; 0000H = x8-only asynchronous interface
29H 00H
2AH 00H Maximum number of bytes in multi-byte write = 2N (00H = not supported)
2BH 00H
2CH 02H Number of Erase Sector/Block sizes supported by device
2DH FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
2EH 00H y = 255 + 1 = 256 sectors (00FFH = 255)
2FH 10H
30H 00H z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
31H 0FH Block Information (y + 1 = Number of blocks; z x 256B = block size)
32H 00H y = 15 + 1 = 16 blocks (000FH = 15)
33H 00H
34H 01H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T7.0 1146

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8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE FOR SST39LF080

Range Ambient Temp VDD
Commercial 0°C to +70°C 3.0-3.6V

OPERATING RANGE FOR SST39VF080

Range Ambient Temp VDD
Commercial 0°C to +70°C 2.7-3.6V
Industrial -40°C to +85°C 2.7-3.6V

AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF for SST39LF080
Output Load . . . . . . . . . . . . . . . . . . . . CL = 100 pF for SST39VF080
See Figures 14 and 15

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 8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet
TABLE 8: DC OPERATING CHARACTERISTICS
VDD = 3.0-3.6V FOR SST39LF080 AND 2.7-3.6V FOR SST39VF0801
Limits
Symbol Parameter Min Max Units Test Conditions
IDD Power Supply Current Address input=VILT/VIHT, at f=1/TRC Min
VDD=VDD Max
Read2 20 mA CE#=VIL, OE#=WE#=VIH, all I/Os open
Program and Erase 30 mA CE#=WE#=VIL, OE#=VIH
ISB Standby VDD Current 20 µA CE#=VIHC, VDD=VDD Max
IALP Auto Low Power 20 µA CE#=VILC, VDD=VDD Max
All inputs=VSS or VDD, WE#=VIHC
ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max
VIL Input Low Voltage 0.8 V VDD=VDD Min
VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max
VIH Input High Voltage 0.7VDD V VDD=VDD Max
VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max
VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min
VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min
T8.7 1146
1. Typical conditions for the Active Current shown on the front data sheet page are average values at 25°C
(room temperature), and VDD = 3V for VF devices. Not 100% tested.
2. Values are for 70 ns conditions. See the Multi-Purpose Flash Power Rating application note for further information.

TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units
TPU-READ1 Power-up to Read Operation 100 µs
TPU-WRITE 1 Power-up to Program/Erase Operation 100 µs
T9.1 1146
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 10: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter Description Test Condition Maximum
CI/O 1 I/O Pin Capacitance VI/O = 0V 12 pF
CIN1 Input Capacitance VIN = 0V 6 pF
T10.0 1146
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 11: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method
NEND 1,2 Endurance 10,000 Cycles JEDEC Standard A117
TDR1 Data Retention 100 Years JEDEC Standard A103
ILTH1 Latch Up 100 + IDD mA JEDEC Standard 78
T11.2 1146
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a
higher minimum specification.

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8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet
AC CHARACTERISTICS

TABLE 12: READ CYCLE TIMING PARAMETERS

VDD = 3.0-3.6V FOR SST39LF080 AND 2.7-3.6V FOR SST39VF080
SST39LF080-55 SST39VF080-70 SST39VF080-90
Symbol Parameter Min Max Min Max Min Max Units
TRC Read Cycle Time 55 70 90 ns
TCE Chip Enable Access Time 55 70 90 ns
TAA Address Access Time 55 70 90 ns
TOE Output Enable Access Time 30 35 45 ns
TCLZ1 CE# Low to Active Output 0 0 0 ns
TOLZ1 OE# Low to Active Output 0 0 0 ns
TCHZ 1 CE# High to High-Z Output 15 20 30 ns
TOHZ1 OE# High to High-Z Output 15 20 30 ns
TOH1 Output Hold from Address Change 0 0 0 ns
T12.4 1146
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 13: PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units
TBP Byte-Program Time 20 µs
TAS Address Setup Time 0 ns
TAH Address Hold Time 30 ns
TCS WE# and CE# Setup Time 0 ns
TCH WE# and CE# Hold Time 0 ns
TOES OE# High Setup Time 0 ns
TOEH OE# High Hold Time 10 ns
TCP CE# Pulse Width 40 ns
TWP WE# Pulse Width 40 ns
TWPH1 WE# Pulse Width High 30 ns
TCPH1 CE# Pulse Width High 30 ns
TDS Data Setup Time 30 ns
TDH1 Data Hold Time 0 ns
TIDA1 Software ID Access and Exit Time 150 ns
TSE Sector-Erase 25 ms
TBE Block-Erase 25 ms
TSCE Chip-Erase 100 ms
T13.0 1146
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

©2007 Silicon Storage Technology, Inc. S71146-07-EOL 6/07

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 8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet

TRC TAA

ADDRESS AMS-0

TCE
CE#

TOE

OE#

VIH TOLZ TOHZ

WE#
TCHZ
TOH
HIGH-Z TCLZ HIGH-Z
DQ7-0 DATA VALID DATA VALID

1146 F02.2

FIGURE 3: Read Cycle Timing Diagram

INTERNAL PROGRAM OPERATION STARTS

TBP

ADDRESS AMS-0 5555 2AAA 5555 ADDR

TAH
TDH
TWP
WE#
TAS TWPH TDS

OE#
TCH

CE#
TCS

DQ7-0 AA 55 A0 DATA

SW0 SW1 SW2 BYTE

(ADDR/DATA) 1146 F03.2

FIGURE 4: WE# Controlled Program Cycle Timing Diagram

©2007 Silicon Storage Technology, Inc. S71146-07-EOL 6/07

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8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet

INTERNAL PROGRAM OPERATION STARTS

TBP

ADDRESS AMS-0 5555 2AAA 5555 ADDR

TAH
TDH
TCP
CE#
TAS TCPH TDS

OE#
TCH

WE#
TCS

DQ7-0 AA 55 A0 DATA

SW0 SW1 SW2 BYTE

(ADDR/DATA)
1146 F04.2

FIGURE 5: CE# Controlled Program Cycle Timing Diagram

ADDRESS AMS-0

TCE

CE#
TOES
TOEH

OE#
TOE

WE#

DQ7 DATA DATA# DATA# DATA

1146 F05.2

FIGURE 6: Data# Polling Timing Diagram

©2007 Silicon Storage Technology, Inc. S71146-07-EOL 6/07

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 8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet

ADDRESS AMS-0

TCE

CE#

TOE TOES
TOEH

OE#

WE#

DQ6

TWO READ CYCLES

WITH SAME OUTPUTS
1146 F06.2

FIGURE 7: Toggle Bit Timing Diagram

TSCE
SIX-BYTE CODE FOR CHIP-ERASE

ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA 5555

CE#

OE#

TWP

WE#

DQ7-0 AA 55 80 AA 55 10

SW0 SW1 SW2 SW3 SW4 SW5 1146 F08.3

FIGURE 8: WE# Controlled Chip-Erase Timing Diagram

©2007 Silicon Storage Technology, Inc. S71146-07-EOL 6/07

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8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet

TBE
SIX-BYTE CODE FOR BLOCK-ERASE

5555 2AAA 5555 5555 2AAA BAX

ADDRESS AMS-0

CE#

OE#

TWP

WE#

DQ7-0 AA 55 80 AA 55 50

SW0 SW1 SW2 SW3 SW4 SW5

1146 F09.3

FIGURE 9: WE# Controlled Block-Erase Timing Diagram

SIX-BYTE CODE FOR SECTOR-ERASE TSE

ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA SAX

CE#

OE#

TWP

WE#

DQ7-0 AA 55 80 AA 55 30

SW0 SW1 SW2 SW3 SW4 SW5 1146 F10.3

FIGURE 10: WE# Controlled Sector-Erase Timing Diagram

©2007 Silicon Storage Technology, Inc. S71146-07-EOL 6/07

15
 8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet

THREE-BYTE SEQUENCE FOR

SOFTWARE ID ENTRY

ADDRESS A14-0 5555 2AAA 5555 0000 0001

CE#

OE#

TWP TIDA

WE#
TWPH
TAA

DQ7-0 AA 55 90 BF Device ID

SW0 SW1 SW2

1146 F11.4

Note: Device ID = D8H for SST39LF/VF080

FIGURE 11: Software ID Entry and Read

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

ADDRESS A14-0 5555 2AAA 5555

CE#

OE#

TWP TIDA

WE#

TWPH
TAA
DQ7-0
AA 55 98
1146 F12.0
SW0 SW1 SW2

FIGURE 12: CFI Query Entry and Read

©2007 Silicon Storage Technology, Inc. S71146-07-EOL 6/07

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8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

ADDRESS A14-0 5555 2AAA 5555

DQ7-0 AA 55 F0

TIDA
CE#

OE#

TWP
WE#
TWHP

SW0 SW1 SW2

1146 F13.0

FIGURE 13: Software ID Exit/CFI Exit

©2007 Silicon Storage Technology, Inc. S71146-07-EOL 6/07

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 8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet

VIHT

INPUT VIT REFERENCE POINTS VOT OUTPUT

VILT

1146 F14.1

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: VIT - VINPUT Test

VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test

FIGURE 14: AC Input/Output Reference Waveforms

TO TESTER

TO DUT

CL

1146 F15.1

FIGURE 15: A Test Load Example

©2007 Silicon Storage Technology, Inc. S71146-07-EOL 6/07

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8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet

Start

Load data: AAH

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: A0H

Address: 5555H

Load Byte
Address/Byte
Data

Wait for end of

Program (TBP,
Data# Polling
bit, or Toggle bit
operation)

Program
Completed

1146 F16.1

FIGURE 16: Byte-Program Algorithm

©2007 Silicon Storage Technology, Inc. S71146-07-EOL 6/07

19
 8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet

Internal Timer Toggle Bit Data# Polling

Program/Erase Program/Erase Program/Erase

Initiated Initiated Initiated

Wait TBP, Read byte Read DQ7

TSCE, TSE
or TBE

Read same No Is DQ7 =

Program/Erase byte true data?
Completed
Yes

No Does DQ6 Program/Erase

match? Completed

Yes

Program/Erase
Completed
1146 F17.0

FIGURE 17: Wait Options

©2007 Silicon Storage Technology, Inc. S71146-07-EOL 6/07

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8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet

CFI Query Entry Software Product ID Entry Software ID Exit/CFI Exit

Command Sequence Command Sequence Command Sequence

Load data: AAH Load data: AAH Load data: AAH Load data: F0H
Address: 5555H Address: 5555H Address: 5555H Address: XXH

Load data: 55H Load data: 55H Load data: 55H

Wait TIDA
Address: 2AAAH Address: 2AAAH Address: 2AAAH

Load data: 98H Load data: 90H Load data: F0H Return to normal
Address: 5555H Address: 5555H Address: 5555H operation

Wait TIDA Wait TIDA Wait TIDA

Read CFI data Read Software ID Return to normal

operation
1146 F18.1

FIGURE 18: Software ID/CFI Command Flowcharts

©2007 Silicon Storage Technology, Inc. S71146-07-EOL 6/07

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 8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet

Chip-Erase Sector-Erase Block-Erase

Command Sequence Command Sequence Command Sequence

Load data: AAH Load data: AAH Load data: AAH

Address: 5555H Address: 5555H Address: 5555H

Load data: 55H Load data: 55H Load data: 55H

Address: 2AAAH Address: 2AAAH Address: 2AAAH

Load data: 80H Load data: 80H Load data: 80H

Address: 5555H Address: 5555H Address: 5555H

Load data: AAH Load data: AAH Load data: AAH

Address: 5555H Address: 5555H Address: 5555H

Load data: 55H Load data: 55H Load data: 55H

Address: 2AAAH Address: 2AAAH Address: 2AAAH

Load data: 10H Load data: 30H Load data: 50H

Address: 5555H Address: SAX Address: BAX

Wait TSCE Wait TSE Wait TBE

Chip erased Sector erased Block erased

to FFH to FFH to FFH

1146 F19.1

FIGURE 19: Erase Command Sequence

©2007 Silicon Storage Technology, Inc. S71146-07-EOL 6/07

22
8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet
PRODUCT ORDERING INFORMATION

SST 39 VF 080 - 70 - 4C - B3K E

XX XX XXXX - XXX - XX - XXX X
Environmental Attribute
E = non-Pb
Package Modifier
I = 40 leads
K = 48 balls
Package Type
B3 = TFBGA (0.8mm pitch, 6mm x 8mm)
E = TSOP (type 1, die up, 10mm x 20mm)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
55 = 55 ns
70 = 70 ns
90 = 90 ns
Device Density
080 = 8 Mbit
Voltage
L = 3.0-3.6V
V = 2.7-3.6V
Product Series
39 = Multi-Purpose Flash

Valid combinations for SST39LF080

SST39LF080-55-4C-EI SST39LF080-55-4C-B3K
SST39LF080-55-4C-EIE SST39LF080-55-4C-B3KE

Valid combinations for SST39VF080

SST39VF080-70-4C-EI SST39VF080-70-4C-B3K
SST39VF080-70-4C-EIE SST39VF080-70-4C-B3KE
SST39VF080-90-4C-EI SST39VF080-90-4C-B3K
SST39VF080-90-4C-EIE SST39VF080-90-4C-B3KE
SST39VF080-70-4I-EI SST39VF080-70-4I-B3K
SST39VF080-70-4I-EIE SST39VF080-70-4I-B3KE
SST39VF080-90-4I-EI SST39VF080-90-4I-B3K
SST39VF080-90-4I-EIE SST39VF080-90-4I-B3KE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.

©2007 Silicon Storage Technology, Inc. S71146-07-EOL 6/07

23
 8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet
PACKAGING DIAGRAMS

1.05
0.95
Pin # 1 Identifier
0.50
BSC

0.27
10.10 0.17
9.90

18.50 0.15
0.05
18.30

DETAIL
1.20
max.
0.70
0.50 20.20
19.80

0˚- 5˚
0.70
Note: 1. Complies with JEDEC publication 95 MO-142 CD dimensions, 0.50
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm 1mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 40-tsop-EI-7

FIGURE 20: 40-lead Thin Small Outline Package (TSOP) 10mm x 20mm
SST Package Code: EI

©2007 Silicon Storage Technology, Inc. S71146-07-EOL 6/07

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8 Mbit Multi-Purpose Flash
SST39LF080 / SST39VF080
EOL Data Sheet

TOP VIEW BOTTOM VIEW

8.00 ± 0.20 5.60
0.80 0.45 ± 0.05
(48X)

6 6
5 5
4 4.00 4
6.00 ± 0.20
3 3
2 2
1 1
0.80

A B C D E F G H H G F E D C B A

A1 CORNER A1 CORNER
1.10 ± 0.10
SIDE VIEW

0.12
SEATING PLANE 1mm
0.35 ± 0.05

Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm (± 0.05 mm) 48-tfbga-B3K-6x8-450mic-4

FIGURE 21: 48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm
SST Package Code: B3K

TABLE 14: REVISION HISTORY

Number Description Date
03 • 2002 Data Book May 2002
04 • B3K package no longer offered for SST39LF/VF016 Mar 2003
• Part number changes - see page 23 for additional information
• Changes to Table 8 on page 10
– Added footnote for MPF power usage and Typical conditions
– Changed the IALP test onditions
– Clarified the test conditions for Power Supply Current and Read parameters
– Corrected the IDD Read Current from 15 mA to 20 mA
– Corrected the IDD Program and Erase Current from 20 mA to 30 mA
05 • Removed 16 Mbit parts (SST39LF/VF016); refer to SST39VF1681/1682 (S71243) Aug 2003
06 • 2004 Data Book Nov 2003
• Updated B3K package diagram
07 • End of Life Data Sheet for all devices in S71146 June 2007

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com

©2007 Silicon Storage Technology, Inc. S71146-07-EOL 6/07

25
Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Microchip:
SST39LF080-55-4C-EI SST39LF080-55-4C-EIE SST39VF080-70-4C-EI SST39VF080-70-4C-EIE SST39VF080-90-
4C-EI