32 Mbit SPI Serial Flash

PCT25VF032B
SST25VF032B32Mb Serial Peripheral Interface (SPI) flash memory Data Sheet
FEATURES:
• Single Voltage Read and Write Operations • End-of-Write Detection
– 2.7-3.6V – Software polling the BUSY bit in Status Register
• Serial Interface Architecture – Busy Status readout on SO pin
– SPI Compatible: Mode 0 and Mode 3 • Hold Pin (HOLD#)
• High Speed Clock Frequency – Suspends a serial sequence to the memory
without deselecting the device
– 80 MHz Max
• Write Protection (WP#)
• Superior Reliability
– Enables/Disables the Lock-Down function of the
– Endurance: 100,000 Cycles (typical)
status register
– Greater than 100 years Data Retention
• Software Write Protection
• Low Power Consumption:
– Write protection through Block-Protection bits in
– Active Read Current: 10 mA (typical)
status register
– Standby Current: 5 µA (typical)
• Temperature Range
• Flexible Erase Capability
– Industrial: -40°C to +85°C
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks • Packages Available
– Uniform 64 KByte overlay blocks – 8-lead SOIC (200 mils)
• Fast Erase and Byte-Program: – 8-contact WSON (5 X 6 mm)
– Chip-Erase Time: 35 ms (typical) • All devices are RoHS compliant
– Sector-/Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 7 µs (typical)
• Auto Address Increment (AAI) Word Programming
– Decrease total chip programming time over
Byte-Program operations

PRODUCT DESCRIPTION
The PCT 25 series Serial Flash family features a four-wire, supply of 2.7-3.6V for PCT25VF032B. The total energy
SPI-compatible interface that allows for a low pin-count consumed is a function of the applied voltage, current, and
package which occupies less board space and ultimately time of application. Since for any given voltage range, the
lowers total system costs. PCT25VF032B SPI serial flash SuperFlash technology uses less current to program and
memories are manufactured with SST’s proprietary, high- has a shorter erase time, the total energy consumed during
performance CMOS SuperFlash technology. The split-gate any Erase or Program operation is less than alternative
cell design and thick-oxide tunneling injector attain better flash memory technologies.
reliability and manufacturability compared with alternate
The PCT25VF032B device is offered in 8-lead SOIC (200
approaches.
mils) and 8-contact WSON packages. See Figure 2 for pin
The PCT25VF032B devices significantly improve perfor- assignments.
mance and reliability, while lowering power consumption.
The devices write (Program or Erase) with a single power

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 32 Mbit SPI Serial Flash
3&T25VF032B
Data Sheet

SuperFlash
X - Decoder Memory
Address
Buffers
and
Latches

Y - Decoder

I/O Buffers
Control Logic and
Data Latches

Serial Interface

CE# SCK SI SO WP# HOLD#

1327 B1.0

Note: 1. In AAI mode, the SO pin can act as a RY/BY# pin when configured as a ready/busy status pin. See “End-of-
Write Detection” on page 11 for details

FIGURE 1: Functional Block Diagram

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32 Mbit SPI Serial Flash
3&T25VF032B
Data Sheet
PIN DESCRIPTION

CE# 1 8 VDD CE# 1 8 VDD

SO 2 7 HOLD# SO 2 7 HOLD#
Top View Top View
WP# 3 6 SCK WP# 3 6 SCK

VSS 4 5 SI VSS 4 5 SI

1327 8-SOIC P1.0 1327 8-WSON P1.0

Notes: 1. In AAI mode, the SO pin can act as a RY/BY# pin when configured as a ready/busy status pin. See “End-of-
Write Detection” on page 11 for details.

FIGURE 2: Pin Assignments for 8-Lead SOIC

TABLE 1: Pin Description

Symbol Pin Name Functions
SCK Serial Clock To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
SI Serial Data Input To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO Serial Data Output To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
RY/BY# Ready / Busy pin Flash busy status pin in AAI mode if SO is configured as a hardware RY/BY# pin.
CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for the
duration of any command sequence.
WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting the
device.
VDD Power Supply To provide power supply voltage: 2.7-3.6V
VSS Ground
T1.0 1327

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 32 Mbit SPI Serial Flash
3&T25VF032B
Data Sheet

MEMORY ORGANIZATION select the device, and data is accessed through the Serial
Data Input (SI), Serial Data Output (SO), and Serial Clock
The 3&T25VF032B SuperFlash memory array is orga- (SCK).
nized in uniform 4 KByte erasable sectors with 32 KByte
overlay blocks and 64 KByte overlay erasable blocks. The 3&T25VF032B supports both Mode 0 (0,0) and Mode
3 (1,1) of SPI bus operations. The difference between the
two modes, as shown in Figure 3, is the state of the SCK
DEVICE OPERATION signal when the bus master is in Stand-by mode and no
The 3&T25VF032B is accessed through the SPI (Serial data is being transferred. The SCK signal is low for Mode 0
Peripheral Interface) bus compatible protocol. The SPI bus and SCK signal is high for Mode 3. For both modes, the
consist of four control lines; Chip Enable (CE#) is used to Serial Data In (SI) is sampled at the rising edge of the SCK
clock signal and the Serial Data Output (SO) is driven after
the falling edge of the SCK clock signal.

CE#
MODE 3 MODE 3

SCK MODE 0 MODE 0

SI Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DON'T CARE
MSB
HIGH IMPEDANCE
SO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB 1327 F04.0

FIGURE 3: SPI Protocol

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32 Mbit SPI Serial Flash
3&T25VF032B
Data Sheet
Hold Operation
The HOLD# pin is used to pause a serial sequence using coincide with the SCK active low state, then the device
the SPI flash memory, but without resetting the clocking exits from Hold mode when the SCK next reaches the
sequence. To activate the HOLD# mode, CE# must be in active low state. See Figure 4 for Hold Condition waveform.
active low state. The HOLD# mode begins when the SCK
Once the device enters Hold mode, SO will be in high-
active low state coincides with the falling edge of the
impedance state while SI and SCK can be VIL or VIH.
HOLD# signal. The HOLD mode ends when the HOLD#
signal’s rising edge coincides with the SCK active low state. If CE# is driven high during a Hold condition, the device
returns to Standby mode. As long as HOLD# signal is low,
If the falling edge of the HOLD# signal does not coincide
the memory remains in the Hold condition. To resume
with the SCK active low state, then the device enters Hold
communication with the device, HOLD# must be driven
mode when the SCK next reaches the active low state.
active high, and CE# must be driven active low. See Figure
Similarly, if the rising edge of the HOLD# signal does not
4 for Hold timing.

SCK

HOLD#

Active Hold Active Hold Active

1327 F05.0

FIGURE 4: Hold Condition Waveform

Write Protection TABLE 2: Conditions to execute Write-Status-

Register (WRSR) Instruction
3&T25VF032B provides software Write protection. The
Write Protect pin (WP#) enables or disables the lock-down WP# BPL Execute WRSR Instruction
function of the status register. The Block-Protection bits L 1 Not Allowed
(BP3, BP2, BP1, BP0, and BPL) in the status register pro- L 0 Allowed
vide Write protection to the memory array and the status H X Allowed
register. See Table 4 for the Block-Protection description. T2.0 1327

Write Protect Pin (WP#)

The Write Protect (WP#) pin enables the lock-down func-
tion of the BPL bit (bit 7) in the status register. When WP#
is driven low, the execution of the Write-Status-Register
(WRSR) instruction is determined by the value of the BPL
bit (see Table 2). When WP# is high, the lock-down func-
tion of the BPL bit is disabled.

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 32 Mbit SPI Serial Flash
3&T25VF032B
Data Sheet

Status Register
The software status register provides status on whether the Program operation, the status register may be read only to
flash memory array is available for any Read or Write oper- determine the completion of an operation in progress.
ation, whether the device is Write enabled, and the state of Table 3 describes the function of each bit in the software
the Memory Write protection. During an internal Erase or status register.

TABLE 3: Software Status Register

Default at
Bit Name Function Power-up Read/Write
0 BUSY 1 = Internal Write operation is in progress 0 R
0 = No internal Write operation is in progress
1 WEL 1 = Device is memory Write enabled 0 R
0 = Device is not memory Write enabled
2 BP0 Indicate current level of block write protection (See Table 4) 1 R/W
3 BP1 Indicate current level of block write protection (See Table 4) 1 R/W
4 BP2 Indicate current level of block write protection (See Table 4) 1 R/W
5 BP3 Indicate current level of block write protection (See Table 4) 0 R/W
6 AAI Auto Address Increment Programming status 0 R
1 = AAI programming mode
0 = Byte-Program mode
7 BPL 1 = BP3, BP2, BP1, BP0 are read-only bits 0 R/W
0 = BP3, BP2, BP1, BP0 are readable/writable
T3.0 1327

Busy Auto Address Increment (AAI)

The Busy bit determines whether there is an internal Erase The Auto Address Increment Programming-Status bit pro-
or Program operation in progress. A ‘1’ for the Busy bit indi- vides status on whether the device is in AAI programming
cates the device is busy with an operation in progress. A ‘0’ mode or Byte-Program mode. The default at power up is
indicates the device is ready for the next valid operation. Byte-Program mode.

Write Enable Latch (WEL)

The Write-Enable-Latch bit indicates the status of the inter-
nal memory Write Enable Latch. If the Write-Enable-Latch
bit is set to ‘1’, it indicates the device is Write enabled. If the
bit is set to ‘0’ (reset), it indicates the device is not Write
enabled and does not accept any memory Write (Program/
Erase) commands. The Write-Enable-Latch bit is automati-
cally reset under the following conditions:
• Power-up
• Write-Disable (WRDI) instruction completion
• Byte-Program instruction completion
• Auto Address Increment (AAI) programming is
completed or reached its highest unprotected
memory address
• Sector-Erase instruction completion
• Block-Erase instruction completion
• Chip-Erase instruction completion
• Write-Status-Register instructions

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32 Mbit SPI Serial Flash
3&T25VF032B
Data Sheet
Block Protection (BP3,BP2, BP1, BP0) Block Protection Lock-Down (BPL)
The Block-Protection (BP3, BP2, BP1, BP0) bits define the WP# pin driven low (VIL), enables the Block-Protection-
size of the memory area, as shown in Table 4, to be soft- Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
ware protected against any memory Write (Program or further alteration of the BPL, BP3, BP2, BP1, and BP0 bits.
Erase) operation. The Write-Status-Register (WRSR) When the WP# pin is driven high (VIH), the BPL bit has no
instruction is used to program the BP3, BP2, BP1 and BP0 effect and its value is “Don’t Care”. After power-up, the BPL
bits as long as WP# is high or the Block-Protect-Lock bit is reset to 0.
(BPL) bit is 0. Chip-Erase can only be executed if Block-
Protection bits are all 0. After power-up, BP3, BP2, BP1
and BP0 are set to the defaults specified in Table 4.

TABLE 4: Software Status Register Block Protection FOR PCT25VF032B1

Status Register Bit2 Protected Memory Address
Protection Level BP3 BP2 BP1 BP0 32 Mbit
None X 0 0 0 None
Upper 1/64 X 0 0 1 3F0000H-3FFFFFH
Upper 1/32 X 0 1 0 3E0000H-3FFFFFH
Upper 1/16 X 0 1 1 3C0000H-3FFFFFH
Upper 1/8 X 1 0 0 380000H-3FFFFFH
Upper 1/4 X 1 0 1 300000H-3FFFFFH
Upper 1/2 X 1 1 0 200000H-3FFFFFH
All Blocks X 1 1 1 000000H-3FFFFFH
T4.0 1327
1. X = Don’t Care (RESERVED) default is “0
2. Default at power-up for BP2, BP1, and BP0 is ‘111’. (All Blocks Protected)

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 32 Mbit SPI Serial Flash
PCT25VF032B
Data Sheet

INSTRUCTIONS
Instructions are used to read, write (Erase and Program), low before an instruction is entered and must be driven
and configure the PCT25VF032B. The instruction bus high after the last bit of the instruction has been shifted in
cycles are 8 bits each for commands (Op Code), data, and (except for Read, Read-ID, and Read-Status-Register
addresses. The Write-Enable (WREN) instruction must be instructions). Any low to high transition on CE#, before
executed prior any Byte-Program, Auto Address Increment receiving the last bit of an instruction bus cycle, will termi-
(AAI) programming, Sector-Erase, Block-Erase, Write-Sta- nate the instruction in progress and return the device to
tus-Register, or Chip-Erase instructions. The complete list standby mode. Instruction commands (Op Code),
of instructions is provided in Table 5. addresses, and data are all input from the most significant
bit (MSB) first.
All instructions are synchronized off a high to low transition
of CE#. Inputs will be accepted on the rising edge of SCK
starting with the most significant bit. CE# must be driven

TABLE 5: Device Operation Instructions

Address Dummy Data Maximum
Instruction Description Op Code Cycle1 Cycle(s)2 Cycle(s) Cycle(s) Frequency
Read Read Memory 0000 0011b (03H) 3 0 1 to ∞ 25 MHz
High-Speed Read Read Memory at higher speed 0000 1011b (0BH) 3 1 1 to ∞ 80 MHz
4 KByte Sector-Erase3 Erase 4 KByte of 0010 0000b (20H) 3 0 0 80 MHz
memory array
32 KByte Block-Erase4 Erase 32KByte block 0101 0010b (52H) 3 0 0 80 MHz
of memory array
64 KByte Block-Erase5 Erase 64 KByte block 1101 1000b (D8H) 3 0 0 80 MHz
of memory array
Chip-Erase Erase Full Memory Array 0110 0000b (60H) or 0 0 0 80 MHz
1100 0111b (C7H)
Byte-Program To Program One Data Byte 0000 0010b (02H) 3 0 1 80 MHz
AAI-Word-Program6 Auto Address Increment 1010 1101b (ADH) 3 0 2 to ∞ 80 MHz
Programming
RDSR7 Read-Status-Register 0000 0101b (05H) 0 0 1 to ∞ 80 MHz
EWSR Enable-Write-Status-Register 0101 0000b (50H) 0 0 0 80 MHz
WRSR Write-Status-Register 0000 0001b (01H) 0 0 1 80 MHz
WREN Write-Enable 0000 0110b (06H) 0 0 0 80 MHz
WRDI Write-Disable 0000 0100b (04H) 0 0 0 80 MHz
RDID8 Read-ID 1001 0000b (90H) or 3 0 1 to ∞ 80 MHz
1010 1011b (ABH)
JEDEC-ID JEDEC ID read 1001 1111b (9FH) 0 0 3 to ∞ 80 MHz
EBSY Enable SO as an output RY/BY# 0111 0000b (70H) 0 0 0 80 MHz
status during AAI programming
DBSY Disable SO as an output RY/BY# 1000 0000b (80H) 0 0 0 80 MHz
status during AAI programming
T5.0 1327
1. One bus cycle is eight clock periods.
2. Address bits above the most significant bit can be either VIL or VIH.
3. 4KByte Sector Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH.
4. 32KByte Block Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH.
5. 64KByte Block Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH.
6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data to be
programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be programmed into the
initial address [A23-A1] with A0 = 1.
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
8. Manufacturer’s ID is read with A0 = 0, and Device ID is read with A0 = 1. All other address bits are 00H. The Manufacturer’s ID and
device ID output stream is continuous until terminated by a low-to-high transition on CE#.

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32 Mbit SPI Serial Flash
PCT25VF032B
Data Sheet
Read (25 MHz)
The Read instruction, 03H, supports up to 25 MHz Read. ple, once the data from address location 3FFFFFH has
The device outputs the data starting from the specified been read, the next output will be from address location
address location. The data output stream is continuous 000000H.
through all addresses until terminated by a low to high tran-
The Read instruction is initiated by executing an 8-bit com-
sition on CE#. The internal address pointer will automati-
mand, 03H, followed by address bits [A23-A0]. CE# must
cally increment until the highest memory address is
remain active low for the duration of the Read cycle. See
reached. Once the highest memory address is reached,
Figure 5 for the Read sequence.
the address pointer will automatically increment to the
beginning (wrap-around) of the address space. For exam-

CE#

MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 70
SCK MODE 0

SI 03 ADD. ADD. ADD.

MSB MSB
N N+1 N+2 N+3 N+4
HIGH IMPEDANCE DOUT DOUT DOUT DOUT DOUT
SO
MSB
1327 F06.0

FIGURE 5: Read Sequence

High-Speed-Read (80 MHz)

The High-Speed-Read instruction supporting up to 80 MHz addresses until terminated by a low to high transition on
Read is initiated by executing an 8-bit command, 0BH, fol- CE#. The internal address pointer will automatically incre-
lowed by address bits [A23-A0] and a dummy byte. CE# ment until the highest memory address is reached. Once
must remain active low for the duration of the High-Speed- the highest memory address is reached, the address
Read cycle. See Figure 6 for the High-Speed-Read pointer will automatically increment to the beginning (wrap-
sequence. around) of the address space. For example, once the data
from address location 3FFFFFH has been read, the next
Following a dummy cycle, the High-Speed-Read instruc-
output will be from address location 000000H.
tion outputs the data starting from the specified address
location. The data output stream is continuous through all

CE#

MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 78
SCK MODE 0

SI 0B ADD. ADD. ADD. X

N N+1 N+2 N+3 N+4

HIGH IMPEDANCE
SO DOUT DOUT DOUT DOUT DOUT
MSB
1327 F07.1

FIGURE 6: High-Speed-Read Sequence

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 32 Mbit SPI Serial Flash
PCT25VF032B
Data Sheet

Byte-Program
The Byte-Program instruction programs the bits in the Program instruction is initiated by executing an 8-bit com-
selected byte to the desired data. The selected byte must mand, 02H, followed by address bits [A23-A0]. Following the
be in the erased state (FFH) when initiating a Program address, the data is input in order from MSB (bit 7) to LSB
operation. A Byte-Program instruction applied to a pro- (bit 0). CE# must be driven high before the instruction is
tected memory area will be ignored. executed. The user may poll the Busy bit in the software
status register or wait TBP for the completion of the internal
Prior to any Write operation, the Write-Enable (WREN)
self-timed Byte-Program operation. See Figure 7 for the
instruction must be executed. CE# must remain active low
Byte-Program sequence.
for the duration of the Byte-Program instruction. The Byte-

CE#

MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39
SCK MODE 0

SI 02 ADD. ADD. ADD. DIN

MSB LSB

SO HIGH IMPEDANCE

1327 F08.0

FIGURE 7: Byte-Program Sequence

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32 Mbit SPI Serial Flash
PCT25VF032B
Data Sheet
Auto Address Increment (AAI) Word-Program Hardware End-of-Write Detection
The AAI program instruction allows multiple bytes of data to The hardware end-of-write detection method eliminates the
be programmed without re-issuing the next sequential overhead of polling the Busy bit in the Software Status
address location. This feature decreases total program- Register during an AAI Word program operation. The 8-bit
ming time when multiple bytes or entire memory array is to command, 70H, configures the Serial Output (SO) pin to
be programmed. An AAI Word program instruction pointing indicate Flash Busy status during AAI Word programming,
to a protected memory area will be ignored. The selected as shown in Figure 8. The 8-bit command, 70H, must be
address range must be in the erased state (FFH) when ini- executed prior to executing an AAI Word-Program instruc-
tiating an AAI Word Program operation. While within AAI tion. Once an internal programming operation begins,
Word Programming sequence, the only valid instructions asserting CE# will immediately drive the status of the inter-
are AAI Word (ADH), RDSR (05H), or WRDI (04H). Users nal flash status on the SO pin. A ‘0’ indicates the device is
have three options to determine the completion of each busy and a ‘1’ indicates the device is ready for the next
AAI Word program cycle: hardware detection by reading instruction. De-asserting CE# will return the SO pin to tri-
the Serial Output, software detection by polling the BUSY state.
bit in the software status register or wait TBP. Refer to End- The 8-bit command, 80H, prevents the Serial Output (SO)
Of-Write Detection section for details. pin from outputting Busy status during AAI-Word-program
Prior to any write operation, the Write-Enable (WREN) operation and re-configures SO as an output pin. The
instruction must be executed. The AAI Word Program device can only accept the 80H command when the device
instruction is initiated by executing an 8-bit command, is not in AAI mode. Once SO is an output pin, in AAI mode
ADH, followed by address bits [A23-A0]. Following the the device can accept both RDSR instruction for polling
addresses, two bytes of data is input sequentially, each one and Software Status Register data outputs through the SO
from MSB (Bit 7) to LSB (Bit 0). The first byte of data (D0) pin. This is shown in Figure 9.
will be programmed into the initial address [A23-A1] with A0
= 0, the second byte of Data (D1) will be programmed into
the initial address [A23-A1] with A0 = 1. CE# must be driven CE#
high before the AAI Word Program instruction is executed.
The user must check the BUSY status before entering the MODE 3 0 1 2 3 4 5 6 7
next valid command. Once the device indicates it is no SCK MODE 0
longer busy, data for the next two sequential addresses
may be programmed and so on. When the last desired
byte had been entered, check the busy status using the SI 70
hardware method or the RDSR instruction and execute the MSB

Write-Disable (WRDI) instruction, 04H, to terminate AAI. SO HIGH IMPEDANCE

Check the busy status after WRDI to determine if the 1327 F09.0
device is ready for any command. See Figures 10 and 11
FIGURE 8: Enable SO as Hardware RY/BY#
for AAI Word programming sequence.
during AAI Programming
There is no wrap mode during AAI programming; once the
highest unprotected memory address is reached, the
device will exit AAI operation and reset the Write-Enable- CE#
Latch bit (WEL = 0) and the AAI bit (AAI = 0).
MODE 3 0 1 2 3 4 5 6 7
End-of-Write Detection SCK MODE 0

There are three methods to determine completion of a pro-

gram cycle during AAI Word programming: hardware
detection by reading the Serial Output, software detection SI 80
MSB
by polling the BUSY bit in the Software Status Register or
wait TBP. The hardware end-of-write detection method is SO HIGH IMPEDANCE
described in the section below. 1327 F10.0

FIGURE 9: Disable SO as Hardware RY/BY#

during AAI Programming

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 32 Mbit SPI Serial Flash
3&T25VF032B
Data Sheet

CE#

MODE 3 0 7 8 15 16 23 24 31 32 39 40 47 0 7 8 15 16 23 0 7 8 15 16 23 0 7 0 7 8 15
SCK MODE 0

SI AD A A A D0 D1 AD D2 D3 AD Dn-1 Dn WRDI RDSR

Load AAI command, Address, 2 bytes data Last 2 WDRI to exit

Data Bytes AAI Mode

SO DOUT

Wait TBP or poll

Check for Flash Busy Status to load next valid1 command Software Status register
to load any command

Note: 1. Valid commands during AAI programming: AAI command or WRDI command
2. User must configure the SO pin to output Flash Busy status during AAI programming
1327 AAI.HW.0

FIGURE 10: Auto Address Increment (AAI) Word-Program Sequence with

Hardware End-of-Write Detection

Wait TBP or poll Software Status

register to load next valid1 command

CE#

MODE 3 0 7 8 15 16 23 24 31 32 39 40 47 0 7 8 15 16 23 0 7 8 15 16 23 0 7 0 7 8 15
SCK MODE 0

SI AD A A A D0 D1 AD D2 D3 AD Dn-1 Dn WRDI RDSR

Load AAI command, Address, 2 bytes data Last 2 WDRI to exit

Data Bytes AAI Mode

SO DOUT

Note: 1. Valid commands during AAI programming: AAI command or WRDI command Wait TBP or poll
Software Status register
to load any command

1327 AAI.SW.0

FIGURE 11: Auto Address Increment (AAI) Word-Program Sequence with

Software End-of-Write Detection

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32 Mbit SPI Serial Flash
3&T25VF032B
Data Sheet
Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4 address bits [A23-A0]. Address bits [AMS-A12] (AMS = Most
KByte sector to FFH. A Sector-Erase instruction applied to Significant address) are used to determine the sector
a protected memory area will be ignored. Prior to any Write address (SAX), remaining address bits can be VIL or VIH.
operation, the Write-Enable (WREN) instruction must be CE# must be driven high before the instruction is executed.
executed. CE# must remain active low for the duration of Poll the Busy bit in the software status register or wait TSE
any command sequence. The Sector-Erase instruction is for the completion of the internal self-timed Sector-Erase
initiated by executing an 8-bit command, 20H, followed by cycle. See Figure 12 for the Sector-Erase sequence.

CE#

MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31
SCK MODE 0

SI 20 ADD. ADD. ADD.

SO HIGH IMPEDANCE
1327 F13.0

FIGURE 12: Sector-Erase Sequence

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 32 Mbit SPI Serial Flash
3&T25VF032B
Data Sheet

32-KByte and 64-KByte Block-Erase

The 32-KByte Block-Erase instruction clears all bits in the determine block address (BAX), remaining address bits can
selected 32 KByte block to FFH. A Block-Erase instruction be VIL or VIH. CE# must be driven high before the instruction
applied to a protected memory area will be ignored. The is executed. The 64-Kbyte Block-Erase instruction is initi-
64-KByte Block-Erase instruction clears all bits in the ated by executing an 8-bit command D8H, followed by
selected 64 KByte block to FFH. A Block-Erase instruction address bits [A23-A0]. Address bits [AMS-A16] are used to
applied to a protected memory area will be ignored. Prior to determine block address (BAX), remaining address bits can
any Write operation, the Write-Enable (WREN) instruction be VIL or VIH. CE# must be driven high before the instruction
must be executed. CE# must remain active low for the is executed. Poll the Busy bit in the software status register
duration of any command sequence. The 32-Kbyte Block- or wait TBE for the completion of the internal self-timed 32-
Erase instruction is initiated by executing an 8-bit com- KByte Block-Erase or 64-KByte Block-Erase cycles. See
mand, 52H, followed by address bits [A23-A0]. Address bits Figure 13 for the 32-KByte Block-Erase sequence and Fig-
[AMS-A15] (AMS = Most Significant Address) are used to ure 14 for the 64-KByte Block-Erase sequence.

CE#

MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31
SCK MODE 0

SI 52 ADDR ADDR ADDR

MSB MSB

SO HIGH IMPEDANCE
1327 32KBklEr.0

FIGURE 13: 32-KByte Block-Erase Sequence

CE#

MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31
SCK MODE 0

SI D8 ADDR ADDR ADDR

MSB MSB

SO HIGH IMPEDANCE
1327 63KBlkEr.0

FIGURE 14: 64-KByte Block-Erase Sequence

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32 Mbit SPI Serial Flash
3&T25VF032B
Data Sheet
Chip-Erase
The Chip-Erase instruction clears all bits in the device to executing an 8-bit command, 60H or C7H. CE# must be
FFH. A Chip-Erase instruction will be ignored if any of the driven high before the instruction is executed. Poll the Busy
memory area is protected. Prior to any Write operation, the bit in the software status register or wait TCE for the comple-
Write-Enable (WREN) instruction must be executed. CE# tion of the internal self-timed Chip-Erase cycle. See Figure
must remain active low for the duration of the Chip-Erase 15 for the Chip-Erase sequence.
instruction sequence. Initiate the Chip-Erase instruction by

CE#

MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0

SI 60 or C7
MSB

SO HIGH IMPEDANCE
1327 F16.0

FIGURE 15: Chip-Erase Sequence

Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows read- CE# must be driven low before the RDSR instruction is
ing of the status register. The status register may be read at entered and remain low until the status data is read. Read-
any time even during a Write (Program/Erase) operation. Status-Register is continuous with ongoing clock cycles
When a Write operation is in progress, the Busy bit may be until it is terminated by a low to high transition of the CE#.
checked before sending any new commands to assure that See Figure 16 for the RDSR instruction sequence.
the new commands are properly received by the device.

CE#
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SCK MODE 0

SI 05
MSB
HIGH IMPEDANCE
SO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB Status
Register Out
1327 F17.0

FIGURE 16: Read-Status-Register (RDSR) Sequence

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 32 Mbit SPI Serial Flash
3&T25VF032B
Data Sheet

Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write- the Write-Enable-Latch bit in the Status Register will be
Enable-Latch bit in the Status Register to ‘1’ allowing Write cleared upon the rising edge CE# of the WRSR instruction.
operations to occur. The WREN instruction must be exe- CE# must be driven high before the WREN instruction is
cuted prior to any Write (Program/Erase) operation. The executed.
WREN instruction may also be used to allow execution of
the Write-Status-Register (WRSR) instruction; however,

CE#

MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0

SI 06
MSB

SO HIGH IMPEDANCE
1327 F18.0

FIGURE 17: Write Enable (WREN) Sequence

Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write- operation in progress may continue up to TBP after execut-
Enable-Latch bit and AAI bit to ‘0,’ therefore, preventing any ing the WRDI instruction. CE# must be driven high before
new Write operations. The WRDI instruction will not termi- the WRDI instruction is executed.
nate any programming operation in progress. Any program

CE#

MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0

SI 04
MSB

SO HIGH IMPEDANCE
1327 F19.0

FIGURE 18: Write Disable (WRDI) Sequence

Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction must be driven low before the EWSR instruction is entered
arms the Write-Status-Register (WRSR) instruction and and must be driven high before the EWSR instruction is
opens the status register for alteration. The Write-Status- executed.
Register instruction must be executed immediately after the
execution of the Enable-Write-Status-Register instruction.
This two-step instruction sequence of the EWSR instruc-
tion followed by the WRSR instruction works like software
data protection (SDP) command structure which prevents
any accidental alteration of the status register values. CE#

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32 Mbit SPI Serial Flash
3&T25VF032B
Data Sheet
Write-Status-Register (WRSR)
The Write-Status-Register instruction writes new values to bit is disabled and the BPL, BP0, and BP1 and BP2 bits in
the BP3, BP2, BP1, BP0, and BPL bits of the status regis- the status register can all be changed. As long as BPL bit is
ter. CE# must be driven low before the command set to ‘0’ or WP# pin is driven high (VIH) prior to the low-to-
sequence of the WRSR instruction is entered and driven high transition of the CE# pin at the end of the WRSR
high before the WRSR instruction is executed. See Figure instruction, the bits in the status register can all be altered
19 for EWSR or WREN and WRSR instruction sequences. by the WRSR instruction. In this case, a single WRSR
instruction can set the BPL bit to ‘1’ to lock down the status
Executing the Write-Status-Register instruction will be
register as well as altering the BP0, BP1, and BP2 bits at
ignored when WP# is low and BPL bit is set to ‘1’. When
the same time. See Table 2 for a summary description of
the WP# is low, the BPL bit can only be set from ‘0’ to ‘1’ to
WP# and BPL functions.
lock-down the status register, but cannot be reset from ‘1’ to
‘0’. When WP# is high, the lock-down function of the BPL

CE#

MODE 3 0 1 2 3 4 5 6 7 MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK MODE 0 MODE 0

STATUS
REGISTER IN
SI 50 or 06 01 7 6 5 4 3 2 1 0
MSB MSB MSB
SO HIGH IMPEDANCE
1327 F20.0

FIGURE 19: Enable-Write-Status-Register (EWSR) or

Write-Enable (WREN) and Write-Status-Register (WRSR) Sequence

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 32 Mbit SPI Serial Flash
3&T25VF032B
Data Sheet

Read-ID (RDID)
The Read-ID instruction (RDID) identifies the device as 00001H. Once the device is in Read-ID mode, the manu-
3&T25VF032B and manufacturer as 3&T. The device facturer’s and device ID output data toggles between
information can be read from executing an 8-bit command, address 00000H and 00001H until terminated by a low to
90H or ABH, followed by address bits [A23-A0]. Following high transition on CE#.
the Read-ID instruction, the manufacturer’s ID is located in
Refer to Tables 6 and 7 for device identification data.
address 00000H and the device ID is located in address

CE#

MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63
SCK MODE 0

SI 90 or AB 00 00 ADD1
MSB MSB
HIGH
HIGH IMPEDANCE IMPEDANCE
SO BF Device ID BF Device ID
MSB
Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#.
1. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two.
1327 F21.0

FIGURE 20: Read-ID Sequence

TABLE 6: Product Identification

Address Data
Manufacturer’s ID 00000H BFH
Device ID
3&T25VF032B0001HAH
T6.0 1327

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32 Mbit SPI Serial Flash
3&T25VF032B
Data Sheet
JEDEC Read-ID
The JEDEC Read-ID instruction identifies the device as BFH, identifies the manufacturer as 3&T. Byte 2, 25H, iden-
3&T25VF032B and the manufacturer as 3&T. The device tifies the memory type as SPI Serial Flash. Byte 3, 4AH,
information can be read from executing the 8-bit command, identifies the device as 3&T25VF032B. The instruction
9FH. Following the JEDEC Read-ID instruction, the 8-bit sequence is shown in Figure 21. The JEDEC Read ID
manufacturer’s ID, BFH, is output from the device. After instruction is terminated by a low to high transition on CE#
that, a 24-bit device ID is shifted out on the SO pin. Byte 1, at any time during data output.

CE#

MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCK MODE 0

SI 9F

HIGH IMPEDANCE
SO BF 25 4A
MSB MSB
1327 F22.0

FIGURE 21: JEDEC Read-ID Sequence

TABLE 7: JEDEC Read-ID Data

Manufacturer’s ID Device ID
Memory Type Memory Capacity
Byte1 Byte 2 Byte 3
BFH 25H 4AH
T7.0 1327

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 32 Mbit SPI Serial Flash
3&T25VF032B
Data Sheet

ELECTRICAL SPECIFICATIONS

Absolute Maximum Stress Ratings Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Output shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE AC CONDITIONS OF TEST

Range Ambient Temp VDD Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns
Industrial -40°C to +85°C 2.7-3.6V Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figure 26

TABLE 8: DC Operating Characteristics (VDD = 2.7-3.6V)

Limits
Symbol Parameter Min Max Units Test Conditions
IDDR Read Current 10 mA CE# = 0.1 VDD/0.9 VDD@25 MHz, SO = open
IDDR2 Read Current 20 mA CE# = 0.1 VDD/0.9 VDD@66 MHz, SO = open
IDDR3 Read Current 25 mA CE# = 0.1 VDD/0.9 VDD@80 MHz, SO = open
IDDW Program and Erase Current 30 mA CE# = VDD
ISB Standby Current 20 µA CE# = VDD, VIN = VDD or VSS
ILI Input Leakage Current 1 µA VIN = GND to VDD, VDD = VDD Max
ILO Output Leakage Current 1 µA VOUT = GND to VDD, VDD = VDD Max
VIL Input Low Voltage 0.8 V VDD = VDD Min
VIH Input High Voltage 0.7 VDD V VDD = VDD Max
VOL Output Low Voltage 0.2 V IOL = 100 µA, VDD = VDD Min
VOL2 Output Low Voltage 0.4 V IOL = 1.6 mA, VDD = VDD Min
VOH Output High Voltage VDD-0.2 V IOH = -100 µA, VDD = VDD Min
T8.0 1327

TABLE 9: Recommended System Power-up Timings

Symbol Parameter Minimum Units
TPU-READ1 VDD Min to Read Operation 100 µs
TPU-WRITE 1 VDD Min to Write Operation 100 µs
T9.0 1327
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

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32 Mbit SPI Serial Flash
3&T25VF032B
Data Sheet
TABLE 10: Capacitance (TA = 25°C, f = 1 Mhz, other pins open)
Parameter Description Test Condition Maximum
COUT1 Output Pin Capacitance VOUT = 0V 12 pF
CIN 1 Input Capacitance VIN = 0V 6 pF
T10.0 1327
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 11: Reliability Characteristics

Symbol Parameter Minimum Specification Units Test Method
NEND1 Endurance 10,000 Cycles JEDEC Standard A117
TDR 1 Data Retention 100 Years JEDEC Standard A103
ILTH1 Latch Up 100 + IDD mA JEDEC Standard 78
T11.0 1327
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 12: AC Operating Characteristics

25 MHz 66 MHz 80 MHz
Symbol Parameter Min Max Min Max Min Max Units
FCLK 1 Serial Clock Frequency 25 66 80 MHz
TSCKH Serial Clock High Time 18 6.5 6 ns
TSCKL Serial Clock Low Time 18 6.5 6 ns
TSCKR2 Serial Clock Rise Time (Slew Rate) 0.1 0.1 0.1 V/ns
TSCKF Serial Clock Fall Time (Slew Rate) 0.1 0.1 0.1 V/ns
TCES3 CE# Active Setup Time 10 5 5 ns
TCEH 3 CE# Active Hold Time 10 5 5 ns
TCHS3 CE# Not Active Setup Time 10 5 5 ns
TCHH 3 CE# Not Active Hold Time 10 5 5 ns
TCPH CE# High Time 100 50 50 ns
TCHZ CE# High to High-Z Output 15 7 7 ns
TCLZ SCK Low to Low-Z Output 0 0 0 ns
TDS Data In Setup Time 5 2 2 ns
TDH Data In Hold Time 5 4 4 ns
THLS HOLD# Low Setup Time 10 5 5 ns
THHS HOLD# High Setup Time 10 5 5 ns
THLH HOLD# Low Hold Time 10 5 5 ns
THHH HOLD# High Hold Time 10 5 5 ns
THZ HOLD# Low to High-Z Output 20 7 7 ns
TLZ HOLD# High to Low-Z Output 15 7 7 ns
TOH Output Hold from SCK Change 0 0 0 ns
TV Output Valid from SCK 15 6 6 ns
TSE Sector-Erase 25 25 25 ms
TBE Block-Erase 25 25 25 ms
TSCE Chip-Erase 50 50 50 ms
TBP4 Byte-Program 10 10 10 µs
T12.0 1327
1. Maximum clock frequency for Read Instruction, 03H, is 25 MHz
2. Maximum Rise and Fall time may be limited by TSCKH and TSCKL requirements
3. Relative to SCK.
4. TBP of AAI-Word Programming is also 10 µs maximum time.

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 32 Mbit SPI Serial Flash
3&T25VF032B
Data Sheet

TCPH

CE#
TCES TCHS
TCHH TCEH

SCK

TDS TDH TSCKF

TSCKR

SI MSB LSB

HIGH-Z HIGH-Z
SO
1327 F23.0

FIGURE 22: Serial Input Timing Diagram

CE#

TSCKH
TSCKL

SCK
TOH
TCLZ TCHZ

SO MSB LSB

TV

SI

1327 F24.0

FIGURE 23: Serial Output Timing Diagram

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32 Mbit SPI Serial Flash
3&T25VF032B
Data Sheet

CE#
THHH THLS THHS

SCK
THLH
THZ TLZ

SO

SI

HOLD#
1327 F25.0

FIGURE 24: Hold Timing Diagram

VDD

VDD Max
Chip selection is not allowed.
All commands are rejected by the device.

VDD Min

TPU-READ
Device fully accessible
TPU-WRITE

Time

1327 F26.0

FIGURE 25: Power-up Timing Diagram

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 32 Mbit SPI Serial Flash
3&T25VF032B
Data Sheet

VIHT
VHT VHT
INPUT REFERENCE POINTS OUTPUT
VLT VLT
VILT
1327 IORef.0

AC test inputs are driven at VIHT (0.9VDD) for a logic “1” and VILT (0.1VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VHT (0.6VDD) and VLT (0.4VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: VHT - VHIGH Test

VLT - VLOW Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test

FIGURE 26: AC Input/Output Reference Waveforms

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32 Mbit SPI Serial Flash
3&T25VF032B
Data Sheet
PRODUCT ORDERING INFORMATION

3&T59F32% -6 - 4I - S2A F

XX XX XXX X - XX - XX - XXX X
Environmental Attribute
F1 = non-Pb / non-Sn contact (lead) finish:
Nickel plating with Gold top (outer) layer
E = non-Pb
Package Modifier
A = 8 leads or contacts
Package Type
S2 = SOIC 200 mil body width
Q = WSON (5 x 6 mm)
Temperature Range
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Operating Frequency
66 = 66 MHz
80 = 80 MHz
Device Density
032 = 32 Mbit
Voltage
V = 2.7-3.6V
Product Series
25 = Serial Peripheral Interface flash memory

1. Environmental suffix “F” denotes non-Pb/non-SN solder;

“E” denotes non-Pb solder. PCT non-Pb/non-Sn solder
devices are “RoHS Compliant”.

Valid combinations for PCT25VF032B

PCT25VF032B-66-4I-S2AF
PCT25VF032B-80-4I-S2AF
PCT25VF032B-80-4I-QAE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your PCT sales
representative to confirm availability of valid combinations and to determine availability of new combinations.

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 32 Mbit SPI Serial Flash
PCT25VF032B
Data Sheet

PACKAGING DIAGRAMS

Pin #1 TOP VIEW SIDE VIEW

Identifier

0.50
0.35
5.40
5.15

1.27 BSC

0.25
0.05 END VIEW
5.40
5.15
2.16
8.10 1.75
7.70
0.25 0˚
0.19
8˚
Note: 1. All linear dimensions are in millimeters (max/min). 0.80
2. Coplanarity: 0.1 mm 08-soic-EIAJ-S2A-3 0.50
3. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.

1mm

FIGURE 27: 8-lead Small-outline Integrated Circuit (SOIC) 200 mil body width (5.2mm x 8mm)
PCT Package Code: S2A

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32 Mbit SPI Serial Flash
PCT25VF032B
Data Sheet

TOP VIEW SIDE VIEW BOTTOM VIEW

Pin #1
0.2
Pin #1
Corner
1.27 BSC

5.00 ± 0.10 4.0

0.076 0.48
0.35
3.4

0.70
0.05 Max 0.50
6.00 ± 0.10
0.80
0.70
CROSS SECTION
Note: 1. All linear dimensions are in millimeters (max/min).
2. Untoleranced dimensions (shown with box surround)
are nominal target dimensions. 0.80
3. The external paddle is electrically connected to the 0.70
die back-side and possibly to certain VSS leads. 1mm
This paddle can be soldered to the PC board;
it is suggested to connect this paddle to the VSS of the unit. 8-wson-5x6-QA-9.0
Connection of this paddle to any other voltage potential can
result in shorts and/or electrical malfunction of the device.

FIGURE 28: 8-Contact Very-very-thin, Small-outline, No-lead (WSON)

PCT Package Code: QA

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 32 Mbit SPI Serial Flash
PCT25VF032B
Data Sheet

TABLE 13: Revision History

Number Description Date
00 • Initial release of data sheet Oct 2006
01 • Changed clock frequency from 50 MHz to 66 MHz globally Mar 2008
• Revised Table 12 AC Operating Characteristics
• Revised Product Ordering Information and Valid Combinations on page 25
• Revised Figure 10 and Figure 11
• Changed IDDR2 from Max 15 mA to Max 20 mA in Table 8
• Changed TDH from Min 5 ns to Min 4 ns (66MHz) in Table 12
02 • Removed SC package Jul 2008
• Removed Commercial Temperature.
03 • Added new valid combination with 80 MHz Clock Frequency May 2009
• Added QA package
• Edited Features, page 1
• Edited Product Description, page 1
• Edited Table 5 on page 8
• Edited Figure 6 on page 9
• Edited Table 8 on page 20
• Edited Table 12 on page 21

Professional Computer Technology Limited

©2010 Professional Computer Technology Limited

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