Embedded Systems - An Introduction
Embedded Systems - An Introduction
Embedded Systems - An Introduction
-An Introduction
Examples
HARDWARE SOFTWARE
CPU APPLICATION
MEMORY + OS
I\O DEVICES DEVICE DRIVERS
EMBEDDED SYSTEMS
Memory constrained
Time constrained
Highly reliable
Robust
actuators
Program memory
General
General datapath with large register file IR PC ALU
and general ALU
User benefits Program Data
Low time-to-market and NRE costs memory memory
High flexibility Assembly code
for:
Examples
total = 0
Pentium, Athlon, PowerPC for i =1 to …
Consumer electronics
Appliances, office electronics, and home/office automation
Medical instruments
Patient monitoring, MRI, and artificial hearts
E-Business
ATM, wending machines
Energy Efficient
Distributed
Specialized Processing
Apart from the core, presence of various co-processors and
specialized processing units can help achieving necessary
processing performance.
Co-processors execute the instructions fetched by the primary
processor thereby reducing the load on the primary.
Wireless Technology
Automation
Security
Power Consumption
The third piece of the PCB is the solder mask, which is a layer of
polymer that helps protect the copper so that it doesn’t short-circuit
from coming into contact with the environment.
Silkscreen
Optimized execution
For this reason, some programming bugs are not discovered until
the program is tested in a "live" environment – Runtime error
Preprocessor directives change the text of the source code and the
result is a new source code without these directives.
What is Vaporware?
What is Malware?
What is Spyware?
What is Ransomware?
Why „asynchronous‟ ?
It doesn‟t have a clock
Format of Communication
If the baud rate is 4800 and there are 2 bits per symbol, then bit
rate R = 4800 * 2 = 9600 bits/sec
Sequence of Transmission
Stop Parity Data Data Data Data Data Data Data Data Start
Bit Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit
1. The master pulls the slave select low and then issues clock
cycles.
2. The clock frequency is not specified in the SPI protocol and
can be anything from 0 up to 70MHz depending on the
characteristics of the slave device.
3. The data transfer then takes place.
4. The master then de-selects the slave.
If individual shift registers are 8 bit long, after 8 clock cycles data is
transferred from master to slave.
The registers within the master and slave act like shift
registers shifting one bit on every cycle of the SCLK.
SS
Limitations
Require more pins in the IC package
No slave acknowledge
Multi master buses are rare and awkward. Normally
limited to single slave.
ECE4010 Winter 2021-2022 21
I2C Protocol
I2C
I2C : Inter - Integrated Circuit
I2C is a serial protocol for two wire interface to connect low speed
devices
SDA SDA
SCL SCL
Start Stop
Condition Condition
One node “broadcasts” the message and every other node uses it.
Unlike I2C , none of the nodes have address.
The message has a field with identifier, which indicates priority. The
receiving node do an acceptance test for the identifier of the
message to verify if the message is relevant for it.
The identifier ( 11 bit or 29 bit) have a dominant bit (0) and recessive
bit (1). The logic is wired AND.
Next is the 11-bit identifier, which establishes the priority of the CAN
message. The smaller the identifier, the higher the priority of the
message.
The data length code (DLC) nibble signifies how many bytes of data
are in this message.
The end of frame (EOF) signifies the end of the CAN message and
is 7 bits wide, for detecting bit-stuffing errors.
The last part of a CAN message is used as a time delay. This time
delay is precisely the amount of time needed for a CAN controller to
move the received message into a buffer for further processing.
USB1.1
USB 1.1 came out in September 1998. USB 1.1 is also known as
full-speed USB.
Initially all packets are sent from the host, via the root hub and
possibly more hubs, to devices.
It can send data to any of its slaves and request data from them as
well.
Slaves are only allowed to transmit to and receive from their master.
They can‟t talk to other slaves in the piconet.
The also share a common secret key, which allows them to bond
whenever they‟re together in the future.
It is easily upgradeable.
The NFC software stack is fully integrated into Android, iOS and
Windows, mobile operating systems that natively provide a number
of services, creating the opportunity for many applications to use
NFC without the need to install any specific software
Mesh networking allows for redundancy in node links, so that if one node
goes down, devices can find an alternative path to communicate with one
another.
The power of the mesh, devices tend to connect with every near
device, that makes every node of the network reachable from every
other node and expanding the network geographically, also
providing self healing, if the preferable path to a node fails there are
other path to reach the node. The more devices you have the more
reliable the network is.
#include <EEPROM.h>
EEPROM Read: Read the EEPROM and send its values to the computer.
EEPROM Get: Get values from EEPROM and prints as float on serial.
EEPROM Update: Stores values read from A0 into EEPROM, writing the
value only if different, to increase EEPROM life.
Revised twice into version 2.1 which is the 64-bit standard that it is
today.
PCI provides direct access to system memory for the devices that
are connected to the bus which is then connected through a bridge
that connects to the front side bus.
Extensions to the base PCI specification can boost this by a factor of four to
528 Mbytes/sec.
Any device on the bus can be a bus master and initiate transactions. One
consequence of this is that there is no need for the traditional notion of
DMA.
Disadvantages
64 48 48 16 32
Repeater
Hub
As the network cannot set priority for the packets, it is not suitable
for a client-server architecture.
• Single-functioned
• Executes a single program, repeatedly
• Tightly-constrained
• Low cost, low power, small, fast, etc.
• Reactive and real-time
• Continually reacts to changes in the system’s
environment
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• Must compute certain results in real-time without delay
An embedded system example -- a
digital camera
Digital camera chip
CCD
lens
6
Design metric competition -- improving
one may worsen others •Expertise with both
Power software and
hardware is needed to
Performance Size
optimize design
metrics
• Not just a hardware
NRE cost or software expert,
as is common
• A designer must be
CCD
Digital camera chip comfortable with
A2D
CCD preprocessor Pixel coprocessor D2A various technologies
lens
JPEG codec Microcontroller Multiplier/Accum
in order to choose
DMA controller Display ctrl Hardware the best for a given
application and
Software
Memory controller ISA bus interface UART LCD ctrl constraints 7
Time-to-market: a
demanding design metric
•Time required to develop a
product to the point it can be
sold to customers
•Market window
• Period during which the
product would have highest
Revenues ($)
sales
•Average time-to-market
constraint is about 8 months
Time (months) •Delays can be costly 8
Losses due to delayed market
entry
•Simplified revenue model
Peak revenue
• Product life = 2W, peak at W
Peak revenue from
• Time of market entry defines a
Revenues ($)
delayed entry
On-time triangle, representing market
Market rise Market fall penetration
Delayed • Triangle area equals revenue
•Loss
D W 2W • The difference between the on-
On-time Delayed Time time and delayed triangle areas
entry entry
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Losses due to delayed market entry
(cont.)
•Area = 1/2 * base * height
Peak revenue • On-time = 1/2 * 2W * W
Peak revenue from
• Delayed = 1/2 * (W-D+W)*(W-D)
Revenues ($)
On-time
delayed entry
•Percentage revenue loss = (D(3W-
Market rise Market fall D)/2W2)*100%
Delayed •Try some examples
– Lifetime 2W=52 wks, delay D=4 wks
D W 2W
– (4*(3*26 –4)/2*26^2) = 22%
On-time Delayed Time – Lifetime 2W=52 wks, delay D=10 wks
entry entry – (10*(3*26 –10)/2*26^2) = 50%
– Delays are costly!
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NRE and unit cost metrics
•Costs:
• Unit cost: the monetary cost of manufacturing each copy of the system, excluding NRE
cost
• NRE cost (Non-Recurring Engineering cost): The one-time monetary cost of designing the
system
• total cost = NRE cost + unit cost * # of units
• per-product cost = total cost / # of units
= (NRE cost / # of units) + unit cost
• Example
– NRE=$2000, unit=$100
– For 10 units
– total cost = $2000 + 10*$100 = $3000
– per-product cost = $2000/10 + $100 = $300
Amortizing NRE cost over the units results in an
additional $200 per unit 11
NRE and unit cost metrics
•Compare technologies by costs -- best depends on quantity
• Technology A: NRE=$2,000, unit=$100
• Technology B: NRE=$30,000, unit=$30
• Technology C: NRE=$100,000, unit=$2
$200,000 $200
A A
B B
$160,000 $160
C C
tota l c ost (x1000)
p er p rod uc t c ost
$120,000 $120
$80,000 $80
$40,000 $40
$0 $0
0 800 1600 2400 0 800 1600 2400
Numb er of units (volume) Numb er of units (volume)
total = 0 total = 0
for i =1 to … for i =1 to …
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General-purpose (“software”) Application-specific Single-purpose (“hardware”)
Processor technology
• Processors vary in their customization for the problem at hand
total = 0
for i = 1 to N loop
total += M[i]
end loop
Desired
functionality
general ALU
• User benefits Program
memory
Data
memory
• Low time-to-market and NRE costs
Assembly code
• High flexibility for:
• Benefits
• Fast
• Low power
• Small size
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Application-specific processors
• Programmable processor optimized for a Controller Datapath
particular class of applications having Control Registers
common characteristics logic and
State register
• Compromise between general-purpose and Custom
single-purpose processors ALU
IR PC
• Features
Data
• Program memory Program memory
• Optimized datapath memory
• Special functional units Assembly code
• Benefits
for:
total = 0
• Some flexibility, good performance, size and for i =1 to …
power
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IC technology
The manner in which a digital (gate-level) implementation is mapped
onto an IC
• IC: Integrated circuit, or “chip”
• IC technologies differ in their customization to a design
• IC’s consist of numerous layers (perhaps 10 or more)
• IC technologies differ with respect to who builds each layer and when
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gate
IC package IC oxide
source channel drain
Silicon substrate
IC technology
• Three types of IC technologies
• Full-custom/VLSI
• Semi-custom ASIC (gate array and standard cell)
• PLD (Programmable Logic Device)
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Semi-custom
• Lower layers are fully or partially built
• Designers are left with routing of wires and maybe placing some
blocks
• Benefits
• Good performance, good size, less NRE cost than a full-custom
implementation (perhaps $10k to $100k)
• Drawbacks
• Still require weeks to months to develop
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PLD (Programmable Logic
Device)
All layers already exist
• Designers can purchase an IC
• Connections on the IC are either created or destroyed to implement
desired functionality
• Field-Programmable Gate Array (FPGA) very popular
Benefits
• Low NRE costs, almost instant IC availability
Drawbacks
• Bigger, expensive (perhaps $30 per unit), power hungry, slower
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Moore’s law
Moore’s law Moore’s law
• The most important trend in embedded systems
• Predicted in 1965 by Intel co-founder Gordon Moore
IC transistor capacity has doubled roughly every 18 months for the past several
decades
10,000
1,000
0.001
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Moore’s law
• Wow
• This growth rate is hard to imagine, most people underestimate
• How many ancestors do you have from 20 generations ago
• i.e., roughly how many people alive in the 1500’s did it take to make you?
• 220 = more than 1 million people
• (This underestimation is the key to pyramid schemes!)
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Graphical illustration of Moore’s
law
1981 1984 1987 1990 1993 1996 1999 2002
10,000 150,000,000
transistors transistors
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Design Technology
• The manner in which we convert our concept of desired system
functionality into an implementation
To final implementation 29
Design productivity exponential
increase
100,000
10,000
Productivity
100
10
0.1
0.01
2005
2003
1987
2001
1983
1993
1985
1991
1989
1999
1997
1995
2007
2009
• Exponential increase over the past few decades
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The co-design ladder
• In the past: Sequential program code (e.g., C, VHDL)
• Hardware/software
Implementation
“codesign” Microprocessor plus
program bits: “software”
VLSI, ASIC, or PLD
implementation: “hardware”
The choice of hardware versus software for a particular function is simply a tradeoff among various
design metrics, like performance, power, size, NRE cost, and especially flexibility; there is no
fundamental difference between what hardware or software can implement. 31
Independence of processor and IC
technologies
• Basic tradeoff
• General vs. custom
• With respect to processor technology or IC technology
• The two technologies are independent
General- Single-
purpose ASIP purpose
General, processor processor Customized,
providing improved: providing improved:
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Design productivity gap
• 1981 leading edge chip required 100 designer months
• 10,000 transistors / 100 transistors/month
• 2002 leading edge chip requires 30,000 designer months
• 150,000,000 / 5000 transistors/month
• Designer cost increase from $1M to $300M
10,000 100,000
1,000 10,000
Logic transistors 100 1000
10 Gap 100 Productivity
per chip IC capacity
(in millions) 1 10 (K) Trans./Staff-Mo.
0.1 1
productivity
0.01 0.1
0.001 0.01
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The mythical man-month
The situation is even worse than the productivity gap indicates
In theory, adding designers to team reduces project completion time
In reality, productivity per designer decreases due to complexities of team management
and communication
In the software community, known as “the mythical man-month” (Brooks 1975)
At some point, can actually lengthen project completion time! (“Too many cooks”)
Team
60000 15
• 1M transistors, 1 16 16
18
50000 19
designer=5000
40000 24 23
trans/month
30000
Months until completion
• Each additional designer 20000 43
reduces for 100 10000 Individual
trans/month
0 10 20 30 40
• So 2 designers produce Number of designers 35
4900 trans/month each
Microelectronic Circuits
• General-purpose processors:
• High-volume sales.
• High performance.
• Application-Specific Integrated Circuits (ASICs):
• Varying volumes and performances.
• Large market share.
• Prototypes.
• Special applications (e.g. space).
Microelectronics Design Styles
• Adapt circuit design style to market requirements
• Parameters:
• Cost.
• Performance.
• Volume.
• Full custom
• Maximal freedom
• High performance blocks
• Slow
• Semi-custom
• Standard Cells
• Gate Arrays
• Mask Programmable (MPGAs)
• Field Programmable (FPGAs)) • Silicon Compilers & Parametrizable Modules
(adder, multiplier,
• memories)
• Standard Cells
• Cell library:
• Cells are designed once.
• Cells are highly optimized.
• Layout style:
• Cells are placed in rows.
• Channels are used for wiring.
• Over the cell routing.
• Compatible with macro-cells (e.g. RAMs).
• Macro-cells
• Module generators:
• Synthesized layout.
• Variable area and aspect-ratio.
• Examples:
• RAMs, ROMs, PLAs, general logic blocks.
• Features:
• Layout can be highly optimized.
• Structured-custom design.
Array-based design
Pre-diffused arrays:
• Personalization by metalization/contacts.
• Mask-Programmable Gate-Arrays.
Pre-wired arrays:
• Personalization on the field.
• Field-Programmable Gate-Arrays.
MPGAs & FPGAs
MPGAs:
• Array of sites:
• Each site is a set of transistors. • Batches of wafers can be pre-fabricated.
• Few masks to personalize chip.
• Lower cost than cell-based design.
FPGAs:
• Array of cells:
• Each cell performs a logic function. • Personalization:
• Soft: memory cell (e.g. Xilinx).
• Hard: Anti-fuse (e.g. Actel). • Immediate turn-around (for low volumes).
• Inferior performances and density.
• Good for prototyping.
Semi-custom style
trade-off
Example: DEC AXP Chip designed using Macro Cells
Example: Field Programmable
Gate Array from Actel
Summary
Embedded systems are everywhere
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