Homework of A.E.

-I for practise

Analog Electronics Circuit simulation

using Mutisim

Electronics Circuit simulation Lab 1

 Experiment # 1

To simulate and study half-wave, and bridge- rectifier

Half-wave rectifier: -
In half-wave rectification, the rectifier conducts current only during the positive half-cycles
of input A.C. supply. The negative half-cycles of A.C. supply are suppressed i.e. during
negative half-cycles, no current is conducted and hence no voltage appears across the load.
Therefore, current always flows in one direction through the load though after every half-
cycle.
XSC1
G

A B

U1
V16 D1 + -
2 1 3
T1 0.367m A
220 V 1N4149
50 Hz DC 1e-009 R1
0Deg 10k
5 TS_POWER_25_TO_1 0

Half-wave rectifier

Electronics Circuit simulation Lab 2

 Simulation Results

Description: -
First Take the components from multisim database library, for example if you want to
select a NPN transistor 2N222A then click on place > component, now from component
menu ensure that database is selected to master data base, select the group as transistors,
click on BJT-NPN, a list of available transistors will appear from where you can select
your desired transistor. You can also see the spice parameters and other details about the
selected device, on clicking the detail report tab. similarly select all the components and
power sources and ground and do the connection as shown in the schematic diagram. Take
one oscilloscope from simulate > instruments > oscilloscope. Connect the channel A to
input and channel B to output. You can also change the color of wire for output (so that
you can clearly distinguish between input and output) by right click on wire and select wire
colors from pop-up menu select any color. Run the simulation. Observe the output on
oscilloscope on double click on it. You can also see the output on grapher, where you can
zoom to any particular part of waveform.

SPICE Model of Half-wave rectifier: -

** halfwave_rectfier **
*
* !!!BEGIN-INTERACT
* (External state variables)
* 1e-12 constant low
* : Rshunt ++++f1 ;
* : Mode ++++i3 ;
* (Internal state variables )
* 0.0 VARIABLE r1Cur
* 0 VARIABLE nTime
* 0 VARIABLE nTimeCur
*
* high VARIABLE r1_resistance
Electronics Circuit simulation Lab 3
*
* .( Loading the ammeter.. ) cr
*
* : RESET
* 0.0 VALUE SET_ANIMATION_TEXT
* Rshunt SET_INSTANCE Resistor ::R r1 resistance
* 1 RESET_ACDC
* GET_LOCAL_TIME ==>_*nTime
* ;
* :BEGIN_PLOT
* RESET
* ;
* :OUT_DATA
* (( GET_INSTANCE Resistor ::R r1 i )) 1 ADD_ACDC
* GET_LOCAL_TIME ==>_*nTimeCur

* *nTimeCur *nTime - 2 >= if

* ((if Mode 1 GET_AC 1 GET_DC ))if VALUE SET_ANIMATION_TEXT
* *nTimeCur ==>_*nTime
* endif
* ;
* : BEGIN_ANALYSIS
* RESET
* ;
* 1 ACDC::ALLOC_INDEX
*
* :SIMULATION_CHANGED
* ACDC::CIRCUIT_CHANGE
* GET_LOCAL_TIME ==>_*nTime
*;
* !!!END-INTERACT
xU1 1 3 AmmeterU1
.subckt AmmeterU1 1 2
R1 1 2 1e-9
.ends

VV1 6 5 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin(0 311.127 50 0 0 0)
dD1 2 1 1N4149__DIODE__1
xT1 6 5 2 0 T1_OPEN_5 TS_PWR_25_TO_1__TRANSFORMER__1
rR1 3 0 1.000e+004
.MODEL 1N4149__DIODE__1 D(Is=0.1p Rs=8 CJO=1p Tt=12n Bv=100 Ibv=0.1p )

Electronics Circuit simulation Lab 4

.SUBCKT TS_PWR_25_TO_1__TRANSFORMER__1 1 2 3 4 5
* EWB Version 4 - Transformer Model
* n= 25 Le= 0.001 Lm= 5 Rp= 1e-006 Rs= 1e-006
Rp 1 6 1e-006ohm
Rs1 10 3 1e-006ohm
Rs2 11 5 5e-007ohm
Le 6 7 0.001H
Lm 7 2 5H
E1 9 8 7 2 0.02
E2 8 4 7 2 0.02
V1 9 10 DC 0V
V2 8 11 DC 0V
F1 7 2 V1 0.04
F2 7 2 V2 0.04
.ENDS

Full-wave rectifier using center-tapped transformer: -

In the full-wave rectification, current flows through the load in the same direction for both
half-cycles of input A.C. voltage. This can be achieved with two diodes working
alternately. For the positive half cycles of input A.C. voltage, one diode supplies current to
the load and for the negative half-cycle, the other diode does so; current always being the
same direction through the load. Therefore, a full-wave rectifier utilizes both half-cycles of
input a.c. voltage to produce the D.C. output.

XSC1
G

D1 A B

4
1 1BH62
V1 T1
R1
230 V 0 3

50 Hz 10k
0Deg TS_AUDIO_10_TO_1
D2
5 2

1BH62

Full-wave rectifier

Electronics Circuit simulation Lab 5

 Simulation results

SPICE Model of full-wave rectifier: -

** fullwave_rectifier **

VV1 4 5 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin(0 325.269 50 0 0 0)

xT1 4 5 1 2 0 TS_AUDIO_10_TO_1__TRANSFORMER__1

dD1 1 3 1BH62__DIODE__1

dD2 2 3 1BH62__DIODE__1

rR1 3 0 1.000e+004

.SUBCKT TS_AUDIO_10_TO_1__TRANSFORMER__1 1 2 3 4 5
* EWB Version 4 - Transformer Model
* n= 10 Le= 1e-006 Lm= 0.001 Rp= 1e-006 Rs= 1e-006
Rp 1 6 1e-006ohm
Rs1 10 3 1e-006ohm
Rs2 11 5 5e-007ohm
Le 6 7 1e-006H
Lm 7 2 0.001H
E1 9 8 7 2 0.05
E2 8 4 7 2 0.05

Electronics Circuit simulation Lab 6

 V1 9 10 DC 0V
V2 8 11 DC 0V
F1 7 2 V1 0.1
F2 7 2 V2 0.1
.ENDS

.MODEL 1BH62__DIODE__1 D
+ IS=5.950e-006 N=4.031e+000 RS=2.677e-002
+ BV=1.200e+002
+ EG=1.110e+000 XTI=3.000e+000 TT=5.760e-007
+ FC=5.000e-001 KF=0.000e+000 AF=1.000e+000

Bridge rectifier: -

The need for a center tapped power transformer is eliminated in the bridge rectifier. It contains four
diodes D1, D2, D3 and D4 connected to form bridge as shown in figure. the a.c. supply is to be
rectified is applied to the diagonally opposite ends of the bridge through the transformer. Between
two other ends of the bridge the load resistance RL is connected.

XSC1
G

A B
2
5
T1
V1 TS_PQ4_10 2 D1
120 V 4

60 Hz 4 1 R1
0
0Deg 1k 

1 3 1B4B42 0
3

Bridge rectifier

Electronics Circuit simulation Lab 7

 Simulation results

SPICE Model of bridge rectifier: -

** bridgerectifier **

xD1 4 2 0 3 1B4B42__FWB__1

VV1 5 1 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin(0 169.706 60 0 0 0)

xT1 5 1 2 3 T1_OPEN_5 TS_PQ4_10

rR1 4 0 1000 vresR1

.model vresR1 r( )

.subckt 1B4B42__FWB__1 1 2 3 4
d1 4 1 D1B4B42
d2 2 1 D1B4B42
d3 3 4 D1B4B42
d4 3 2 D1B4B42
.MODEL D1B4B42 D
+ IS=6.543e-005 N=4.386e+000 RS=4.150e-002
+ BV=150
+ EG=1.110e+000 XTI=3.000e+000
+ FC=5.000e-001 KF=0.000e+000 AF=1.000e+000
.ends 1B4B42

Electronics Circuit simulation Lab 8

.SUBCKT ts_pq4_10 1 2 3 4 5
* *1, 2-- primary winding, *3,4-- secondary terminal, 5-- neutural
Rs1 1 11 6.600e+001
Rl2 31 3 2.500e-001
Rl3 41 4 2.500e-001
L1 11 2 1.015e+001
L2 31 5 7.672e-002
L3 5 41 7.672e-002
K12 L1 L2 9.856e-001
K13 L1 L3 9.856e-001
K23 L2 L3 9.856e-001
.ENDS

Experiment # 2

To simulate and study diode clipper and clamper circuits

Clipper circuit: -

A clipper is used to clip off or remove a portion of an A.C. signal. The half-wave rectifier
is basically a clipper that eliminates one of the alternations of an A.C. signal. clippers find
extensive use in radar, digital and other electronic systems. Clippers can be subdivided into
two categories.

1) Series clipper
2) Parallel clipper

When the diode is connected in series with the load, it is called as series clipper. And when
it is connected in parallel with the load it is called as parallel clipper. A parallel biased
clipper is shown in the figure and its corresponding waveforms also drawn.

Electronics Circuit simulation Lab 9

 4

R1 XSC2
5 G
1k 
V2 T
D3
10 V D4 A B

1kHz 2 1
0Deg
V5 V4
4 V 4 V

Parallel biased clipper

Simulation results

SPICE Model of parallel biased clipper: -

** clipper **

VV2 4 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin(0 10 1000 0 0 0)

VV4 1 0 dc 4 ac 0 0
+ distof1 0 0
+ distof2 0 0

VV5 0 2 dc 4 ac 0 0
+ distof1 0 0
+ distof2 0 0

dD3 2 5 IDEALD__DIODES_VIRTUAL__1
Electronics Circuit simulation Lab 10
dD4 5 1 IDEALD__DIODES_VIRTUAL__1

rR1 4 5 1000 vresR1

.model vresR1 r( )

.MODEL IDEALD__DIODES_VIRTUAL__1 D (
+ IS = 1.0e-14
+ RS = 0
+ N= 1
+ TT = 0
+ CJO = 0
+ VJ = 1
+ M = 0.5
+ EG = 1.11
+ XTI = 3.0
+ KF = 0
+ AF = 1
+ FC = 0.5
+ BV = 1.0e30
+ IBV = 1.0e-3
+ TNOM = 27
+)

Clamper circuit: -

A circuit that places either the positive or negative peak of a signal at a desired D.C. level
is known as a clamping circuit. A clamping circuit essentially adds a D.C. component to
the signal. The circuit must have a capacitor, a diode, and a resistive element, but it can
also employ an independent D.C. Supply to introduce an additional shift. The magnitude of
R and C must be chosen such that the time constant  = RC is large enough to ensure that
the voltage across the capacitor does not discharge significantly during the interval the
diode is no conducting.

Electronics Circuit simulation Lab 11

 XSC1
G

C1
A B

4 1.0uF 5

D1
V2 1N3494
R1
20 V 100k
1
1kHz
0Deg V1
10 V

Positive clamper

Simulation results

SPICE Model of positive clamper circuit: -

** clamper **

rR1 0 5 1.000e+005

dD1 1 5 D1N3491__DIODE__1

cC1 4 5 1.0E-6

VV1 1 0 dc 10 ac 0 0

Electronics Circuit simulation Lab 12

+ distof1 0 0
+ distof2 0 0

VV2 4 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin(0 20 1000 0 0 0)

.MODEL D1N3491__DIODE__1 D (
+ IS = 2.23e-13
+ RS = 0.004197
+ CJO = 1.932e-09
+ VJ = 0.3905
+ TT = 8.656e-06
+ M = 0.7998
+ BV = 100
+ N = 1.08
+ EG = 1.11
+ XTI = 3
+ KF = 0
+ AF = 1
+ FC = 0.5
+ IBV = 0.0001
+ TNOM = 27
+)

Experiment # 3

To simulate and study emitter bias and fixed bias BJT and JFET circuits and
determine quiescent conditions.

Biasing: -
For faithful amplification, a transistor amplifier must satisfy three basic conditions.
1) Establish the operating point in the center of the active region of the characteristics,
so that on Appling the input signal the instantaneous operating point does not move
either to the saturation region or to the cutoff region, even at the extreme values of
the input signal.
Electronics Circuit simulation Lab 13
 2) Stabilize the collector current against temperature variations.

3) Make the operating point independent of the transistor parameters.

Fixed bias BJT circuit: -

In this method, a high resistance RB is connected between the base and +ive end of supply
for NPN transistor. The required zero signal base current is provided by VCC and it flows
through RB, the base emitter junction is forward biased now.

Advantages of this circuit are:

1) Simple biasing circuit.
2) Biasing conditions can be easily set (simple calculations).
Disadvantages:
1) This method provides poor stabilization. It is because there is no means to stop a
self increase in collector current due to temperature rise and
individual variations.

Due to this disadvantage, this method of biasing is rarely employed.

XSC1
VCC
G
5V
T
VCC

R2 RC A B

82k 2.0k

C2 4
2
3
Q1 1.0uF
C1
1
V1

2mV 1.0uF
2N2712
1kHz
0Deg

Fixed bias BJT circuit

Electronics Circuit simulation Lab 14

 Simulation results

SPICE Model of fixed bias BJT circuit: -

** Circuit1 **

qQ1 2 3 0 Q2N2222A__BJT_NPN__1

cC1 1 3 1.0E-6
cC2 2 4 1.0E-6

VCCVCC VCC 0 dc 5

VV1 1 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin(0 0.002 1000 0 0 0)

rRB VCC 3 33k

rRC VCC 2 2.000e+003

Electronics Circuit simulation Lab 15

.MODEL Q2N2222A__BJT_NPN__1 NPN IS =3.0611E-14 NF =1.00124 BF =220
IKF=0.52
+ VAF=104 ISE=7.5E-15 NE =1.41 NR =1.005 BR =4 IKR=0.24
+ VAR=28 ISC=1.06525E-11 NC =1.3728 RB =0.13 RE =0.22
+ RC =0.12 CJC=9.12E-12 MJC=0.3508 VJC=0.4089
+ CJE=27.01E-12 TF =0.325E-9 TR =100E-9

Fixed bias JFET circuit: -

The simplest of biasing arrangements for the n-channel JFET as shown in figure is referred
to as the fixed bias configuration. In this arrangement two batteries are employed for
biasing.

Electronics Circuit simulation Lab 16

 VDD XSC1
12V G
VDD
T

R1
A B
2.0k
3

C2
Q1 5

C1
6 1.0uF

4 1.0uF R2 2N4341
V2 100k

10mV 2
1kHz
V1
0Deg 2V
0

Fixed bias JFET

Simulation results

SPICE Model of fixed bias JFET circuit: -

** FIXED BIAS JFET CKT **

cC1 4 6 1.0E-6

Electronics Circuit simulation Lab 17

cC2 3 5 1.0E-6

VDDVDD VDD 0 dc 12

VV1 0 2 dc 2 ac 0 0
+ distof1 0 0
+ distof2 0 0

VV2 4 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin(0 0.01 1000 0 0 0)

rR2 6 2 1.000e+005

jQ1 3 6 0 J2N4341__JFET_N__1

rR1 VDD 3 2.000e+003

.MODEL J2N4341__JFET_N__1 NJF(Beta=387.1u Betatce=-.5 Rd=1 Rs=1

Lambda=14m Vto=-3.336
+ Vtotc=-2.5m Is=114.5f Isr=1.091p N=1 Nr=2 Xti=3 Alpha=506.8u
+ Vk=251.7 Cgd=2.8p M=.2271 Pb=.5 Fc=.5 Cgs=2.916p Kf=1.407E-18
+ Af=1)

Emitter bias BJT circuit: -

We can modify the fixed bias circuit by connecting a resistor to the emitter terminal. A
feedback occurs through this resistor, the feedback voltage is proportional to the emitter

Electronics Circuit simulation Lab 18

current. Hence, this circuit is also called current feedback biasing circuit. This circuit does
provide some stabilization of the Q point.
XSC1
VCC
G
5V
T
VCC

RB RC A B

82k 2.0k

C2 4
2
3
Q1 1.0uF
C1
1
V1

2mV 1.0uF
2N2712
1kHz 5
0Deg RE
150

Emitter bias BJT

Simulation results

When no signal is applied is applied to the amplifier as shown in the schematic diagram
below. This condition is then referred to as quiescent condition.

Electronics Circuit simulation Lab 19

 VCC
10V
VCC

RB RC
82k 2.0k

1 2

V1
V2 0V
0V
4

Q1
3

2N2712
5
RE
150

You can find the quiescent conditions for this amplifier circuit by running DC operating
point analysis on this circuit. You can find out voltage and current in different nodes and
branches respectively, and from that Q point of the circuit.

For this circuit the practical values are: -

IB = 105.4670  A
IC = 4.56888 mA
VCE = 862.24032 mV

Experiment # 4
To simulate a common emitter amplifier using self biasing and study the effect of
variation in emitter resistor on voltage gain, input and output impedance using spice.
Electronics Circuit simulation Lab 20
Common emitter amplifier: -
A common emitter amplifier using voltage divider biasing is shown in the schematic
diagram below. Here the resistors R1, R2 and RE fix a certain Q point. The resistors RE
stabilize it against temperature variations. The capacitors CE bypass the resistor RE for the
ac signals. The resistor RE provides negative feedback. In the first figure the RE is chosen
as IK-OHM, and you can observe the corresponding gain of the amplifier in the waveform.
In the second diagram the RE is replaced with 4.7K-OHM,and you can now observe the
corresponding reduction in the gain.
XSC1
VCC
G
12V
T
VCC
A B
R1 R4
47k 1.6k
C2
1 4

Q1 1.0uF
C1
5 3

1.0uF
2N2222A
V1 2
1mV
CE
10kHz R2 R3 10uF
0Deg 4.7k 1.0k
0

CE amplifier with RE=1K-OHM

Simulation results

Electronics Circuit simulation Lab 21

 VCC
XSC1
12V
G
VCC
T

R1 R4
A B
47k 1.6k
C2
1 4

Q1 1.0uF
C1
5 3

1.0uF
2N2222A
V1 2
1mV
CE
10kHz R2 R3 10uF
0Deg 4.7k 4.7k
0

CE amplifier with RE=4.7K-OHM

Simulation results

Experiment # 5

Electronics Circuit simulation Lab 22

To determine the frequency response of VO/VS for CE BJT amplifier using spice
window. Study the effect of cascading of two stages on bandwidth.

Single Stage RC amplifier: -

A single stage RC amplifier is shown in the schematic diagram below, you can also see the
corresponding frequency response of this amplifier in the waveform. You can see the
bandwidth of this amplifier in the waveform window and it comes is approximately
39MHZ.
VCC
12V XBP1
VCC

R1 RC IN OUT
47k 2.0k
C2
1 6

Q1 1.0uF
C1
5 3

1.0uF 0
2N2222A R5
V1 2
5.1k
1mV
CE
10kHz R2 R3 10uF
0Deg 4.7k 1.0k

Single stage RC coupled amplifier

Frequency response

Two Stage RC Amplifier: -

Electronics Circuit simulation Lab 23

A transistor circuit containing more than one stage of amplification is known as multi-stage
transistor amplifier. In multi-stage amplifier, a number of single amplifiers are connected
in cascade arrangement through a suitable coupling device. A two stage RC coupled
amplifier is shown in the schematic diagram below. This is the most popular type of
coupling and provides excellent audio fidelity over a wide range of frequency. The
corresponding frequency response for this circuit is also shown in the graph.
VCC
12V XBP1

VCC
IN OUT
R1 RC R4 R6
47k 2.0k 47k 2.0k
C2 C4
1 7 6

Q1 1.0uF 4 Q2 1.0uF
C1
5 3

V1 1.0uF 2N2222A 2N2222A

2
1mV 8

10kHz C5
0Deg R2 R3 CE R5 R7 10uF
4.7k 1.0k 10uF 4.7k 1.0k
0

Two stage RC coupled amplifier

Frequency response

Experiment # 6

Electronics Circuit simulation Lab 24

To simulate and study Darlington pair amplifier using spice and determine DC bias
and output AC voltage.

Darlington pair: -

A Darlington emitter follower is shown in the schematic diagram. The ac input signal is
applied to the base of the Darlington transistor through capacitor C1, with the ac output
obtained from the emitter through capacitor C2. The main feature of the Darlington
connection is that the composite transistor acts as a single unit with a current gain that is
the product of the current gains of the individual transistors. If the connection is made
using two separate transistors having current gains of 1 and 2, the Darlington connection
provides a current gain of
D = 12

Darlington Pair VCC

VCC 18V XSC1
G
R2
3.3M T

U2 Q1 A B

+ - C1 4
6
1.770n A
Q2
2 510nF
DC 1e-009 BCP54
1
V1
5

1V BCP54
10kHz C2
0Deg 7

+ 510nF
U1
2.538m A AC 1e-009
-
3
R5
392
0

Darlington pair circuit

For this circuit: -

D of this Darlington connection is = 8000.

The base ac current is = 1.770 nA
The ac emitter current is = 2.538 mA

SPICE Model of darlington-pair circuit: -

Electronics Circuit simulation Lab 25

** darlington-pair **

VCCVCC VCC 0 dc 18

VV1 2 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin(0 1.41421 10000 0 0 0)

rR5 3 0 3.920e+002

cC1 6 4 5.1E-7

cC2 7 5 5.1E-7

qQ1 VCC 4 1 BC635__BJT_NPN__1

qQ2 VCC 1 7 BC635__BJT_NPN__1

* !!!BEGIN-INTERACT
*
* ( External state variables )
* 1e-12 constant low
* : Rshunt ++++f1 ;
* : Mode ++++i3 ;
*
* ( Internal state variables )
* 0.0 VARIABLE r1Cur
* 0 VARIABLE nTime
* 0 VARIABLE nTimeCur
*
* high VARIABLE r1_resistance
*
* .( Loading the ammeter.. ) cr
*
* : RESET
* 0.0 VALUE SET_ANIMATION_TEXT
* Rshunt SET_INSTANCE Resistor ::R r1 resistance
* 1 RESET_ACDC
* GET_LOCAL_TIME ==>_*nTime
* ;
*
* :BEGIN_PLOT
* RESET

* ;
Electronics Circuit simulation Lab 26
*
* :OUT_DATA
* (( GET_INSTANCE Resistor ::R r1 i )) 1 ADD_ACDC
* GET_LOCAL_TIME ==>_*nTimeCur
* *nTimeCur *nTime - 2 >= if
* ((if Mode 1 GET_AC 1 GET_DC ))if VALUE SET_ANIMATION_TEXT
* *nTimeCur ==>_*nTime
* endif
* ;
*
* : BEGIN_ANALYSIS
* RESET
* ;
* 1 ACDC::ALLOC_INDEX
*
* :SIMULATION_CHANGED
* ACDC::CIRCUIT_CHANGE
* GET_LOCAL_TIME ==>_*nTime
*;

* !!!END-INTERACT

xU1 7 3 AmmeterU1

.subckt AmmeterU1 1 2
R1 1 2 1e-9
.ends

* !!!BEGIN-INTERACT
*
* ( External state variables )
* 1e-12 constant low
* : Rshunt ++++f1 ;
* : Mode ++++i3 ;
*
* ( Internal state variables )
* 0.0 VARIABLE r1Cur
* 0 VARIABLE nTime
* 0 VARIABLE nTimeCur
*
* high VARIABLE r1_resistance
*
* .( Loading the ammeter.. ) cr
*

* : RESET
* 0.0 VALUE SET_ANIMATION_TEXT
Electronics Circuit simulation Lab 27
* Rshunt SET_INSTANCE Resistor ::R r1 resistance
* 1 RESET_ACDC
* GET_LOCAL_TIME ==>_*nTime
* ;
*
* :BEGIN_PLOT
* RESET
* ;
*
* :OUT_DATA
* (( GET_INSTANCE Resistor ::R r1 i )) 1 ADD_ACDC
* GET_LOCAL_TIME ==>_*nTimeCur
* *nTimeCur *nTime - 2 >= if
* ((if Mode 1 GET_AC 1 GET_DC ))if VALUE SET_ANIMATION_TEXT
* *nTimeCur ==>_*nTime
* endif
* ;
*
* : BEGIN_ANALYSIS
* RESET
* ;
* 1 ACDC::ALLOC_INDEX
*
* :SIMULATION_CHANGED
* ACDC::CIRCUIT_CHANGE
* GET_LOCAL_TIME ==>_*nTime
*;
*
* !!!END-INTERACT

xU2 2 6 AmmeterU2
.subckt AmmeterU2 1 2
R1 1 2 1e-9
.ends
rR2 VCC 4 3.3Meg

.MODEL BC635__BJT_NPN__1 NPN(

+ AF= 1.00E+00 BF= 1.29E+02 BR= 2.92E+00 CJC= 4.85E-11
+ CJE= 1.17E-10 CJS= 0.00E+00 EG= 1.11E+00 FC= 5.00E-01
+ IKF= 9.06E-01 IKR= 1.00E+00 IRB= 2.38E-02 IS= 3.06E-15
+ ISC= 4.08E-14 ISE= 1.62E-16 ITF= 5.64E-01 KF= 0.00E+00
+ MJC= 5.09E-01 MJE= 4.22E-01 MJS= 3.30E-01 NC= 1.00E+00
+ NE= 1.00E+00 NF= 8.55E-01 NR= 9.10E-01 PTF= 0.00E+00
+ RB= 1.65E+01 RBM= 1.73E-02 RC= 3.11E-01 RE= 1.26E-02
+ TF= 1.42E-09 TR= 0.00E+00 VAF= 7.24E+02 VAR= 5.46E+01
+ VJC= 3.00E-01 VJE= 3.00E-01 VJS= 7.50E-01 VTF= 9.99E+05
+ XCJC= 1.00E+00 XTB= 0.00E+00 XTF= 7.75E-01 XTI= 3.00E+00)

Experiment # 7

Electronics Circuit simulation Lab 28

To study an operational amplifier using spice and find out CMMR, gain bandwidth
product, slew rate, 3-db frequency, and input offset voltage.

Operational amplifier: -
An operational amplifier or op-amp is a very high gain differential amplifier with high
input impedance and low output impedance.

CMMR: - It is an acronym for common mode rejection ratio, it is said to be the ability of
differential amplifier to reject common mode signal.

CMMR = Ad / Ac
Ad = differential gain
Ac = common mode gain

Slew rate: -
It is defined as maximum rate at which amplifier output can change in volts per
microsecond. The slew rate provides a parameter specifying the maximum rate of change
of the output voltage when driven by a large voltage when driven by a large step-input
signal.

Gain-Bandwidth: -
Because of the internal compensation circuitry included in an op-amp, the voltage gain
drops off as frequency increases. Op-amp specifications provide a description of the gain
versus bandwidth

R1 XBP1
VEE 20k
-15V
VEE IN OUT

4 U1
R2 1
2
3
V1 1.0k
6
4
0
1mV 3
1kHz VCC R3
7 1 5 741
0Deg 15V 10k
2VCC

Inverting amplifier circuit

Electronics Circuit simulation Lab 29

 Frequency response

SPICE Model of inverting op-amp amplifier circuit: -

** OpAmp **

xU1 4 1 0 VEE VCC 741__OPAMP__1

rR2 3 1 1.000e+003

VV1 3 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin(0 0.001 1000 0 0 0)

VCCVCC VCC 0 dc 15

VEEVEE VEE 0 dc -15

rR1 1 4 2.000e+004

rR3 4 0 1.000e+004

.SUBCKT 741__OPAMP__1 1 2 3 4 5
* EWB Version 4 - 5 Terminal Opamp Model
* nodes: 3=+ 2=- 1=out 5=V+ 4=V-

Electronics Circuit simulation Lab 30

* VCC= 15 VEE= -15 CC= 3e-011 A= 200000 RI= 2e+006
* RO= 75 VOS= 0.001 IOS= 2e-008 IBS= 8e-008
* VSW+= 14 VSW-= -14 CMMR= 90
* ISC= 0.025 SR= 0.5 Fu= 1e+006 Pm= 6.09112e-007
VC 5 15 DC 1.68573V
VE 12 4 DC 1.68573V
IEE 10 4 DC 1.516e-005A
R1 10 0 10Gohm
R6 11 0 100Kohm
R7 5 4 1Kohm
Rc1 6 5 5305.16ohm
Rc2 5 7 5305.16ohm
Re1 9 10 1839.19ohm
Re2 8 10 1839.19ohm
Ro1 1 14 37.5ohm
Ro2 14 0 37.5ohm
Ree 10 0 1.31926e+007ohm
Rcc 0 13 2.20906e-005ohm
Cee 0 10 1e-012
Cc 14 11 3e-011
C1 6 7 1e-016
GA 11 0 6 7 0.000188496
GC 0 13 1 0 45268.1
GB 14 0 11 0 282.942
GCM 0 11 10 0 5.96075e-009
D1 14 13 Dopamp1
D2 13 14 Dopamp1
D3 1 15 Dopamp2
D4 12 1 Dopamp2
Qt1 6 2 9 Qopamp1
Qt2 7 3 8 Qopamp2
.MODEL Dopamp1 D (Is=7.53769e-014A Rs=0 Cjo=0F Vj=750mV Tt=0s M=0)
.MODEL Dopamp2 D (Is=8e-016A Rs=0 Cjo=0F Vj=750mV Tt=0s M=0)
.MODEL Qopamp1 NPN (Is=8e-016A BF=83.3333 BR=960m
+ Rb=0ohm Re=0ohm Rc=0ohm Cjs=0F Cje=0F Cjc=0F
+ Vje=750m Vjc=750m Tf=0 Tr=0 mje=0 mjc=0 VA=50)
.MODEL Qopamp2 NPN (Is=8.30948e-016A BF=107.143 BR=960m
+ Rb=0ohm Re=0ohm Rc=0ohm Cjs=0F Cje=0F Cjc=0F
+ Vje=750m Vjc=750m Tf=0 Tr=0 mje=0 mjc=0 VA=50)
.ENDS

Electronics Circuit simulation Lab 31

 Experiment # 8

To simulate and study active low pass, high pass, and band pass filters using spice

Filter: -

Filter is basically a frequency selective device, which passes a desired range of frequency,
and attenuates all others. This experiment presents the analysis and design of analog active
RC filters using op-amps.

An active filter offers the following advantages over a passive filter:

1. Gain and frequency adjustment flexibility.

2. No loading problem.
3. Cost.

Active low pass butter worth filter: -

A filter that provides a constant output from DC up to cutoff frequency, and then passes no
signal above that frequency is called a low pass filter. The frequency response of low pass
filter shown in the schematic diagram below is shown in the graph, and from that you can
see its pass band frequency. For this circuit the values of R and C are 16k and .01uf
respectively, and the corresponding cut-off frequency that you can observe in the graph is
1KHZ.

XBP1
VEE
-15V
IN OUT
VEE
R2 2
R3
0
16k 4 16k
U1

2
3
R1 6
5 1
3
16k
V1 R4
C1 7 1 5 741
16k
1V 10nF
VCC
1kHz VCC
0Deg 15V
0

Low Pass Filter

Electronics Circuit simulation Lab 32
 Frequency response graph

Description: -

To see the frequency response of the filter connect a bode plotter to input and out put terminals.
Adjust the horizontal and vertical scale of bode plotter accordingly, and run the simulation to see
the response. Now click on the grapher to better observe the response.

Active High Pass Butter Worth Filter:

A filter that provides or passes signals above a cutoff frequency is a high pass filter. A first
order high pass butter worth filter is shown in the schematic diagram below. For this circuit
the values of R and C are 16k and .01uf respectively, and the corresponding cut-off
frequency that you can observe in the graph is 1KHZ.
XBP1
VEE
-15V
IN OUT
VEE
R2 2
R3
0
16k 4 16k
U1

2
3
C2 6
5 1
3

V1 10nF R4
R1 7 1 5 741
16k
1V 16k VCC
1kHz VCC
0Deg 15V
0

Electronics Circuit simulation Lab 33

 1st order high pass filter

Frequency response

Band pass filter: -

A band pass filter has a pass band between two cut-off frequencies fH and fL such that
fH>fL . Any input frequency outside this pass band is attenuated. Basically, there are two
types of band-pass filters.

1. Wide band pass

2. Narrow band pass.
XBP1

VEE VEE IN OUT

-15V -15V

R2 2
VEE R3 R5 7
VEE R6
0 0
16k 4 16k 16k 4 16k 6
3
U1 U2
2 2
C2 6 R4 6 0
1
3 4 3
5
51nF 16k
V1 R7
R1 7 1 5 741 C1 7 1 5 741
16k
1V 16k 10nF
VCC
VCC VCC
VCC
1kHz
0Deg 15V 15V
0

Band pass filter

Electronics Circuit simulation Lab 34

 Frequency response
From observation on graph,

fH = 1.342KHZ - high cut-off frequency

fL = 146 HZ - low cut-off frequency

Experiment # 9

To simulate and study class A, B, C, and AB amplifier using spice.

Class-A Operation: -

A class-A amplifier is shown in the schematic diagram below. Class-A operation provides
collector current during the complete cycle of the input signal. The output of a class-A
amplifier is shown in the graph below. The operating point Q is so selected that collector
flows at all times throughout the full cycle of the applied signal. Class-A amplifiers have
least distortion. However, they have the disadvantage of the low power output and low
collector efficiency.

Electronics Circuit simulation Lab 35

 VCC XSC1
24V G

VCC T

A B
R1
R2 200
51.1k C2
6

10uF 5
Q1
C1
4
2
V1 R5
2.0uF 1.00k
BCP54
200mV
50 Hz
0Deg

Class-A amplifier

Simulation results

Class-B amplifier: -

A class-B amplifier is shown in the schematic diagram below. The Q point of this amplifier
is set at cut-off. The quiescent collector current is zero. The output current flows for only
180 of the input cycle. Since under no signal condition, the collector current is zero, no
power is dissipated by the transistor. The transistor handles an average4 collector current,
only when an input signal is applied.

Electronics Circuit simulation Lab 36

 XSC1
VCC
G
20V
VCC T

R2
A B
330

Q1
R1 R3
3 1 10k
V1
100k
4V PN930
1kHz
0Deg

Class-B amplifier

Simulation results

Class-C amplifier: -

In class-c operation, the collector current flows for less than 180. The average collector
current is much less, and as a result the collector losses are still less so that the efficiency is
very high. Class-C operation is used with the resonant or tuned circuits as for example, in
radio and television transmitters where efficiency is of utmost importance. The schematic
diagram and output response of a class-C amplifier is shown below.

Electronics Circuit simulation Lab 37

 VCC
XSC1
5V
G
VCC
T
R1
R3 75 A B
68k

6
1
Q1
C1

2 2.0uF
BCP54
V1
3

3V
R4
1000 Hz 200
0Deg
0

Class-C amplifier

Electronics Circuit simulation Lab 38

 Simulation results

Experiment # 10

To simulate and study different multivibrators using 555 using spice.

555 Timer: -

The 555 is a monolithic timing circuit that can produce accurate and highly stable time delays or
oscillation. IC 555 timer (available in 8 pin DIP or TO-99 package) is one of the most popular and
versatile sequential logic devices which can be used in monostable and astable modes. Its inputs

Electronics Circuit simulation Lab 39

and output are directly compatible with both TTL and CMOS logic circuits. Schematic diagram
given below shows the 555 timer connected as an astable multivibrator. For drawing this circuit in
multisim either you can individually pick and place the components from the library, or you can
take the help of wizard, where you have to fill the necessary parameters and it automatically
generates the circuit. The corresponding output for this circuit is also shown in the graph below.

Astable Multivibrator: -

12V
Vs 1

28.86k
R1 VCC

RST OUT
4 9
DIS

THR
7
TRI 100 
57.72k Rl
R2 CON
8
GND
555_VIRTUAL
Timer
10nF 10nF
C Cf
0

Astable multivibrator
For this circuit: -

Output frequency = 1KHZ

Duty cycle = 60%
VS = 12V

Electronics Circuit simulation Lab 40

Output waveform

Monostable Multivibrator: -

Electronics Circuit simulation Lab 41

 Simulation results

Bistable Multivibrator: -

Electronics Circuit simulation Lab 42

 Simulation result

Electronics Circuit simulation Lab 43

 Experiment # 11

To simulate logic expression and determine its truth table

Logic expression: -

A logic expression is shown in the schematic diagram below, and corresponding wave
form for this is also shown in the graph. For drawing a logic expression circuit either you
can individually pick and place the components from the library, or you can define truth
table, logic equation in the logic converter, which automatically implement that truth table,
or equation by NAND gates or AND+OR gates.

Truth table
A B C

135
136

137 138

140
139

141

Circuit implemented using AND+OR gates

Electronics Circuit simulation Lab 44

A B C

127
128

129 130
132
133
131

134

Circuit implemented using NAND gates

Corresponding waveforms

In the graph shown above red waveform represents input signals and green one represents
the output.

Electronics Circuit simulation Lab 45

 Experiment # 12

To simulate logic expression of full adder circuit and determine its truth table

Full adder: -

Full adder circuit can add two binary numbers, accepts a carry and yield a carry. The truth
table and schematic diagram of the adder circuit is shown below.

Truth table for sum

Truth table for carry

Electronics Circuit simulation Lab 46

A B C

27
28

29 32

30

33 35

31

38

25
36
2
34 SUM

39

37

A B C

41

40

43

44 45

1
CARRY
46

Full adder implemented using AND+OR gates

Corresponding waveforms

Electronics Circuit simulation Lab 47

 U7

A U2
EOR2

Sum
EOR2

V1
B U10
500 Hz U1
5 V U9
Cout
AND2
OR2
U10 OR2
V2
Cin
1kHz
AND2
5 V

U8
V3
40 Hz
AND2
5 V

XLA1
1

GND

F
C Q T

Full adder implemented using AND+OR+EXOR gates

Electronics Circuit simulation Lab 48

 Experiment # 13

To simulate a synchronous 4-bit counter and determine its count sequence

Synchronous counter: -
In case of synchronous counter all the flip-flops used in the circuit are clocked
simultaneously, resulting a significant improvement in the speed of operation. A 4-bit
synchronous counter using T flip flops in shown in the schematic diagram below, and the
corresponding output signals are also shown in the graph.
GND
U5
U6
3
GND U1 U2 U4 U3
VCC AND2 4
SET SET AND2 SET SET
5V 5 2
VCC T Q T Q T Q T Q
InPut
CLK ~Q CLK ~Q CLK ~Q CLK ~Q
RESET RESET RESET RESET
7
T_FF T_FF T_FF T_FF
1

CLK V3 6

1kHz
5V

Clear GND XLA1

GND 1

GND GND

F
C Q T

4-bit synchronous counter using T-flip flop

Corresponding waveforms
Electronics Circuit simulation Lab 49
 Experiment # 14

To simulate a master slave flip-flop using NAND gates and study its operation. Study
the operation of synchronous preset and clear.

Master-slave JK-flip flop: -

A master slave JK- flip flop is a cascade of two S-R flip flop with feedback from the
outputs of the second to the inputs of the first as shown in the schematic diagram below.
Master-slave configuration is basically used to overcome the race-around condition. The
corresponding waveforms for this circuit are also shown in the graph

13
Pr
V1
2kHz
5V U1 U3 U7
2 1 5 10 U5
J 14
NAND3 NAND3 NAND2
V3 V4 NAND2 16

4kHz 5V
GND
5V

CLK U2 GND U4
9
U6 6
GND 4 8 U8
11
K V2
NAND3 NAND3 NAND2
6kHz NAND2 XLA1
5V 1

MASTER Cr
7 U9 SLAVE
NAND2

F
CLK2(NOT OF CLK) C Q T

GND

Master-slave JK-flip flop

Corresponding waveforms

Electronics Circuit simulation Lab 50

 Experiment # 15

To simulate and study various oscillator circuits

Colpitts oscillator: -

In collpitts oscillator the sinusoidal signals are generated by feeding back the
amplified output of CE Amplifier to LC tank circuit here feedback is positive 90 degree
phase shift is provided by LC circuit and 90 degree phase shift is provided by the CE
amplifier circuit.

collpits oscillator

Simulation Results

Electronics Circuit simulation Lab 51

Procedure: -

1. Take the components from multisim database library, for example if you want to select a
NPN transistor 2N222A then click on place > component, now from component menu
ensure that database is selected to master data base, select the group as transistors, click on
BJT-NPN, a list of available transistors will appear from where you can select your desired
transistor. You can also see the spice parameters and other details about the selected
device, on clicking the detail report tab. similarly select all the components and power
sources and ground and do the connection as shown in the schematic diagram.

2. Take one oscilloscope from simulate > instruments > oscilloscope. Connect the channel
A to input and channel B to output. You can also change the color of wire for output (so
that you can clearly distinguish between input and output) by right click on wire and select
wire colors from pop-up menu select any color.

3. Run the simulation

4. Ovserve the output on oscilloscope on double click on it.

5. You can also see the output on grapher, where you can zoom to any particular part of
waveform.

SPICE Model of collpits oscillator: -

** Colpitts Oscillator **

lL1 1 3 1.0E-2
cC4 6 0 1.0E-8
rR3 6 0 510
rR2 5 0 5.1k
rR4 4 1 1.00e+002
rR1 4 5 1.000e+004
lL2 2 3 1.0E-3
cC1 2 5 1.0E-8
cC2 2 0 1.5E-7
cC3 0 3 2.0E-8
qQ1 3 5 6 2N3904__BJT_NPN__1
VV1 4 0 dc 5 ac 0 0
+ distof1 0 0
+ distof2 0 0
.MODEL 2N3904__BJT_NPN__1 NPN(Is=6.734f Xti=3 Eg=1.11 Vaf=74.03 Bf=416.4
Ne=1.259
+ Ise=6.734f Ikf=66.78m Xtb=1.5 Br=.7371 Nc=2 Isc=0 Ikr=0 Rc=1
+ Cjc=3.638p Mjc=.3085 Vjc=.75 Fc=.5 Cje=4.493p Mje=.2593 Vje=.75
+ Tr=239.5n Tf=301.2p Itf=.4 Vtf=4 Xtf=2 Rb=10)

Electronics Circuit simulation Lab 52

Hartley oscillator: -

Hartley oscillator

Simulation results

Electronics Circuit simulation Lab 53

SPICE Model of Hartley oscillator: -

** hartley oscillator **

cC1 5 8 7.5E-7
cC2 3 7 2.2E-6
rR5 6 0 160
rR2 7 0 3.6k
rR4 1 5 1.000e+003
rR3 1 7 16k
qQ1 5 7 6 BC107BP__BJT_NPN__1
cC4 8 3 1.0E-6
lL2 0 3 5.1E-4
lL1 8 0 5.1E-4
cC3 6 0 0.0003141 IC=0
VCC1 1 0 dc 10

.MODEL BC107BP__BJT_NPN__1 NPN IS =1.8E-14 ISE=5.0E-14 NF =.9955 NE =1.46 BF

=400 BR =35.5
+IKF=.14 IKR=.03 ISC=1.72E-13 NC =1.27 NR =1.005 RB =.56 RE =.6 RC =.25 VAF=80
+VAR=12.5 CJE=13E-12 TF =.64E-9 CJC=4E-12 TR =50.72E-9 VJC=.54 MJC=.33

RC Phase shift: -

RC Phase shift

Electronics Circuit simulation Lab 54

 Simulation results

SPICE Model of RC Phase shift: -

** phase shift **

xU1 2 6 1 IDEAL_5U1
.SUBCKT IDEAL_5U1 1 2 3
* in+ in- out
* A=200000, RI=2e6 ohm, RO=75 ohm, VSW+=21 v, VSW-=-21 v, VOS=0.001 v,
* IBS=8e-8 A, IOS=2e-8 A, SR=500000 v/s, FU=1.5e6 Hz, CC=10 pf
Vos 4 1 DC 0.001
Ib1 4 0 9e-008
Ib2 2 0 7e-008
Rin 4 2 3e+006
Cc 5 6 1e-011
R1 5 0 1meg
e1 40 0 4 2 1
a1 40 %i(5) hg1
.model hg1 limit (gain= 9.42478e-005,
+ out_upper_limit=5e-006,
+ out_lower_limit=-5e-006,
+ limit_range=0.1 fraction=true)
e2 0 6 5 0 -2122.07
a2 6 3 hg2

Electronics Circuit simulation Lab 55

.model hg2 limit (gain= 1,
+ out_upper_limit=21,
+ out_lower_limit=-21,
+ limit_range=0.1, fraction=true)
R3 3 0 75
.ENDS

rR6 6 0 1.000e+003
rR3 3 0 1.000e+003
rR2 5 2 1.000e+003
rR1 2 1 30k
rR5 5 0 1.000e+003
rR4 4 0 1.000e+003
cC3 4 5 1.0E-6
cC1 1 3 1.0E-6
cC2 3 4 1.0E-6

Wein Bridge oscillator:-

Wein Bridge oscillator

Electronics Circuit simulation Lab 56

 Simulation results

SPICE Model of Wein Bridge: -

** wein bridge **
* !!!BEGIN-INTERACT
* : increment ++++f4 ;
* 0.0 constant mindval
* 100.0 constant maxdval
* 0.0 VARIABLE resistance
* 50.0 VARIABLE setting
* 0.0 VARIABLE setfactor
* 0.0 VARIABLE zeroadj
* 50.0e3 constant tresistance
*
* :MAP_KEYBOARD_INPUT ++++k1 1 ++++K1 -1 ;
* : UPDATE_SETTINGS
* 0.01 *setting f.* ==>_*zeroadj
* *zeroadj PERCENT SET_ANIMATION_TEXT
* 0.000001 0.999999 *zeroadj f.min f.max ==>_*setfactor
* *setfactor tresistance f.* resistance GRADUAL_CHANGE_AT_RUN
* :GRADUAL_CHANGE_AT_RUN locals| ref value |
* value SET_INSTANCE Resistor ::R R1 resistance
* tresistance value f.- SET_INSTANCE Resistor ::R R2 resistance
* ;
* :KEYBOARD_INPUT locals| shift_state |
* shift_state (float) increment f.* *setting f.+ ==>_*setting
* mindval maxdval *setting f.min f.max ==>_*setting
* UPDATE_SETTINGS
* :BEGIN_PLOT

Electronics Circuit simulation Lab 57

* UPDATE_SETTINGS
* ;
*
* :BEGIN_ANALYSIS
* UPDATE_SETTINGS
*;
* !!!END-INTERACT
xR3 7 8 R3_OPEN_3 PotentiometerR3
.subckt PotentiometerR3 1 2 3
R1 1 2 1e-3
R2 2 3 1e-3
.ends

cC1 3 0 1.6E-8

rR4 3 0 1.000e+004

rR5 1 4 1.000e+004

cC2 4 3 1.6E-8

rR2 2 1 1.000e+004

* !!!BEGIN-INTERACT
* : increment ++++f4 ;
* 0.0 constant mindval
* 100.0 constant maxdval
* 0.0 VARIABLE resistance
* 50.0 VARIABLE setting
* 0.0 VARIABLE setfactor
* 0.0 VARIABLE zeroadj
* 50.0e3 constant tresistance
*
* :MAP_KEYBOARD_INPUT ++++k1 1 ++++K1 -1 ;
*
* : UPDATE_SETTINGS
* 0.01 *setting f.* ==>_*zeroadj
* *zeroadj PERCENT SET_ANIMATION_TEXT
* 0.000001 0.999999 *zeroadj f.min f.max ==>_*setfactor
* *setfactor tresistance f.* resistance GRADUAL_CHANGE_AT_RUN
* ;
*
* :GRADUAL_CHANGE_AT_RUN locals| ref value |
* value SET_INSTANCE Resistor ::R R1 resistance
* tresistance value f.- SET_INSTANCE Resistor ::R R2 resistance
* ;
*

Electronics Circuit simulation Lab 58

* :KEYBOARD_INPUT locals| shift_state |
* shift_state (float) increment f.* *setting f.+ ==>_*setting
* mindval maxdval *setting f.min f.max ==>_*setting
* UPDATE_SETTINGS
* ;
*
* :BEGIN_PLOT
* UPDATE_SETTINGS
* ;
*
* :BEGIN_ANALYSIS
* UPDATE_SETTINGS
* ;
*
* !!!END-INTERACT
xR1 0 9 2 PotentiometerR1
.subckt PotentiometerR1 1 2 3
R1 1 2 1e-3
R2 2 3 1e-3
.ends

xU1 3 9 1 3554AM__OPAMP__1

XMM1 7 8 XXMM1_319782224

dU3 1 2 D1N4148__DIODE__1

dU2 2 1 D1N4148__DIODE__1

VV2 5 0 dc 15 ac 0 0
+ distof1 0 0
+ distof2 0 0

VV1 0 6 dc 15 ac 0 0
+ distof1 0 0
+ distof2 0 0

.SUBCKT 3554AM__OPAMP__1 1 2 3
* EWB Version 4 - 3 Terminal Opamp Model
* A= 100000 RI= 1e+011 RO= 20 VSW+= 14 VSW-= -14
* Vos= 0.0005 Ibs= 1e-011 Ios= 4e-012 SR+= 1.2e+009
* fu= 9e+007 fp2= 1e+032 CC= 3e-011
Vos 4 1 DC 0.0005V
Ib1 4 0 1.2e-011A
Ib2 2 0 8e-012A

Electronics Circuit simulation Lab 59

 G1 0 5 4 2 0.0464159
G2 0 6 5 0 2.32079
G3 0 3 6 0 2.32079
Ri 4 2 1e+011ohm
R1 5 0 1000ohm
R2 6 0 20ohm
R3 3 0 20ohm
C1 5 0 1.76839e-007
C2 6 0 7.95775e-035
Cc 5 0 3e-011
.ENDS

.subckt XXMM1_319782224 2 1
I_multi_meter 1 2 DC 1.000000e-008
R_multi_meter 2 1 1.000000e+018
.ends

.model D1N4148__DIODE__1 D(
+Is=2.682n N=1.836 Rs=.5664 Ikf=44.17m
+Xti=3 Eg=1.11 Cjo=4p M=.3333 Vj=.5
+Fc=.5 Isr=1.565n Nr=2 Bv=100 Ibv=100u Tt=11.54n)

Electronics Circuit simulation Lab 60

 Experiment # 16

To simulate and study Differentiator and intigrator ,voltage follower and adder with op
amp using spice.

Differentiator: -

Simulation results

Electronics Circuit simulation Lab 61

Integrator: -

Simulation results

Electronics Circuit simulation Lab 62

Voltage follower: -

Simulation results

Adder: -
Electronics Circuit simulation Lab 63
 Simulation results

Experiment#17

To study the operation of Inverting Amplifier with A/C input signal and explain the polarity
of output voltage with respect to input signal.
Electronics Circuit simulation Lab 64
This circuit illustrates an inverting amplifier with AC voltage applied to the negative (-) input
terminal through the input resistor (Ri). This amplifier produces the output voltage (Vout), which
is 180 degree out of phase with respect to the input signal.
XSC1

Ext T rig
+
_
A B
+ _ + _

Rf

20kΩ
XFG1
VEE
-5V
Ei U1
Ri Vout
10kΩ

VCC
5V

Output:-

To study the operation of Inverting and Non inverting Adder

Electronics Circuit simulation Lab 65

 Inverting Adder
U3 Rf
R3 + -
0.056m A 100kΩ
90kΩ I3 V1
E3
5V DC 1e-009W XMM1
15 V
U4 U2 U1
R2 + - + -
It S
0.056m A 0.122m A
90kΩ I2 Vout
E2
5V DC 1e-009W DC 1e-009W

U5 741
R1 + - Rl
A V2 10kΩ
0.011m
90kΩ I1
E1
1V DC 1e-009W
15 V

Output:-

XSC1

Non-Invering Adder Ext T ri g

+
_
Rf A B
+ _ + _
20kΩ
VEE
-15V

U1
Ein
Ri

10kΩ

Vout

VCC
15V

R1 R2 R3
10kΩ 10kΩ 10kΩ

E1 E2 E3
2 Vrms 5 Vrms 2 Vrms
1 Hz 1 Hz 1 Hz
0° 0° 0°

Output:-

Electronics Circuit simulation Lab 66

 Experiment#18

To verify the operation of Precision clipper

Electronics Circuit simulation Lab 67

This circuit demonstrates a precision clipper and is constructed by adding resistor Rc to a
bipolar-output dead-zone circuit. (See file: 070 Bipola Dead-Zone Ciruit the
corresponding text.) It clips off all signals above the positive reference voltage and below
a negative reference voltage.

XSC1
Precision Clipper Ext Trig
+
_
A B
R1 R3 _ _
+ +

20kΩ 10kΩ
Vrefa
15 V XFG1
R2 D1
Ei
10kΩ
VEE U1
-20V

D2 Voa R10
R8
10kΩ VEE
10kΩ
-20V

U3
VCC R9
20V
R4 R6 10kΩ

10kΩ 10kΩ D3 Vout

VEE
-20V VCC
U2 20V
R5
D4 R7
30kΩ Vob
10kΩ
Vref
15 V

VCC
20V

Output

Experiment#19

To study the operation of Double Bounded Comparator

Electronics Circuit simulation Lab 68
 XSC2
Doubel Bounded Comparator
Ext T ri g
+
_
A B
+ _ + _

D1 D2
XFG1
5 V 5 V

Vin
Rin U1

5kΩ
Vout
OPAMP_3T_VIRTUAL
Rl
10kΩ

Output:-

Experiment#20

Electronics Circuit simulation Lab 69

 To study operation of Active Notch Filter.

XBP1 XSC1
Active Notch Filter Ext Trig
IN OUT +
_
A B
+ _ + _

C2

10nF

R3
R6
180kΩ Vout
12kΩ
Vin C1 U1
R1
R4 U2
V1 68kΩ
10nF
353.5mVrms R2 15kΩ
2.7kΩ
1kHz
0°

R5

12kΩ

Output:-

Experiment#21
Electronics Circuit simulation Lab 70
To verify and study the operation of Two Stage Common Collector, Common
Emitter, Common Base Amplifier

This circuit demonstrates a two-stage common-collector amplifier, designed by cascading

two common-collector amplifiers. The output voltage of the first transistor is coupled to
the base of the second transistor. Since the output follows the input, the overall voltage
gain is close to one.

XSC1

Ext T rig

Two-Stage Common-Collector Amplifier _

+

A B
+ _ + _

R1b
10kΩ
R1a
10kΩ

Q1 Q2
Vin C1

1uF
2N3904 C2 2N3904 C3
V2
V1
2 Vrms 1uF 1uF 10 V
1kHz
Re1 R2b
R2a 1kΩ 10kΩ Re2
0° 10kΩ 1kΩ
RL
500Ω

Output:-

Electronics Circuit simulation Lab 71

This circuit demonstrates a two-stage common-emitter amplifier. The output voltage of the
first transistor is coupled into the base of the second one. The final signal is amplified on
the second transistor. The total voltage gain equals the product of the individual voltage
gains.
XSC1

Two-Stage Common-Emitter AMplifier Ext Trig

_
+

A B
+ _ + _

Rc1 Rc2
5kΩ R4 5kΩ
60kΩ
R2 C2
60Ω B C5 C

Q1 1uF
C1 Q2 1uF
V1
A Rl 10 V
1uF 5kΩ
2N2221A
Rs 2N2221A
600Ω R1
10kΩ
V2 Re1 Re2
500Ω 500Ω
0.707 Vpk R3
10kΩ
1kHz
0°

R5 C3 R6 C4
500Ω 1uF 500Ω 1uF

Output:-

Electronics Circuit simulation Lab 72

 Two-Stage Common-Base Amplifier

V2 V1
9V 9V

Rc1 Re1 Rc2 Re2

2kΩ 10kΩ 1kΩ 10kΩ

Vout C1 C2 C3 C4
Q1 Q2 Vin

2.2uF 100uF 2.2uF 100uF

25mVrms
Rl R2 5kHz
5kΩ 2kΩ
0Deg

XSC1

Ext T rig
+
_
A B
+ _ + _

Output:-

Electronics Circuit simulation Lab 73

 Experiment#22

To study TTL Operation

Circuit:-

VCC XSC1
5V
Ext T rig
+

VCC _
A B
R1 R2 + _ + _
1kΩ 1kΩ
1
2
Q2
0 4
Q1
2N2222A 2N2222A

Output:-

Electronics Circuit simulation Lab 74

 Experiment#23

Determination of parameters and losses in a single-phase transformer by OC and SC

test.

Circuit Diagram:

1 4
V1 2
T1
+ U2 + U3 7
120 Vrms -3.967k V DC 10M W -3.967k V DC 10M W
60 Hz - - 0 T2 2
0° AUTO_XFORMER
- U5
263.774 V DC 10M W
1 3 +

5 0
U1 U4
+ - + -
3 A
6
0.000 891.458k A

DC 1e-009 W DC 1e-009 W

Step1: To check the output, go to simulate tab and check out the reading

Circuit Diagram SC test :

1 4
V1 2
T1
+ U2 + U3
120 Vrms 0.014n V DC 10M W 3.218n V DC 10M W
60 Hz - - 0 T2 2
0° AUTO_XFORMER
1 3 0
5
U1 U4
+ - + -
3 A
6 A
0.240 -3.062

DC 1e-009 W DC 1e-009 W

Step1: To check the output, go to simulate tab and check out the reading

Electronics Circuit simulation Lab 75

 Experiment#24

Measurement of efficiency of a single-phase transformer by load test.

Circuit diagram:
XSC1

Ext Trig
+
_
A B
_ _
V1 1
+ +

0 T1 2 3
120 Vrms L1
60 Hz 1mH
1 3
0° 0
2

Step1: To check the output go to simulate tab and double click on the oscilloscope and
Check the output

Experiment#25
Electronics Circuit simulation Lab 76
Analyze resistor networks that have several voltages and current sources and variable
load resistors.

Circuit Diagram:-

Electronics Circuit simulation Lab 77

Electronics Circuit simulation Lab 78
 Experiment#26

To Analyze a astable oscillator using 555 Timer

Circuit :-

A1
VCC R1
1kΩ XSC2
RST OUT
V1 DIS
Ext T rig
12 V THR +
_
TRI A B
+ _ + _
CON R2
GND 100kΩ

555_VIRTUAL

C1
10uF
IC=0V
U1

BUZZER Space Bar

200 Hz

Output:-

Electronics Circuit simulation Lab 79

 Experiment#27

To design a weighted Digital to Analog Converter

Circuit :-
Weighted Average digital to analog converter

Digital Value

0 Volt to 5 Volt
Output Range

MSB + - R1 - +
4.441m A 2.226 V
D 1kΩ

+ - R2
-0.011u A R7
C 2kΩ 10kΩ 50%
Key=G
+ - R3 R5 R6
-0.010u A U7
B 4kΩ 1kΩ 10kΩ

LSB + - R4
-0.010u A U6
A 8kΩ
V1
5 V

Electronics Circuit simulation Lab 80

 Experiment-28

To study the operation of Pulse Width Modulator and verify its output.

Pulse Width modulator

XSC2
U5
+ -
R1 4.496 V Ext T rig
+
_
1.5kΩ R3 DC 1M W A B
+ _ + _

50% U1
V1 2kΩ U2
12 V Key=A
D1
R4
R2
1kΩ DIODE_VIRTUAL
500Ω
V2 R6
5 V 1kΩ

R5
10kΩ
Key=A
50%

R11

11kΩ

V3 7 1 5 U4 7 1 5 U3
12 V
3 3
6 6
2 2
V4
12 V LM741EH LM741EH
4 4

50%

R10 R7
R9 2kΩ
1kΩ 10kΩ Key=A

C1
10nF
IC=0V
R8

1kΩ

Output:-

Electronics Circuit simulation Lab 81

 Experiment#29

To study a differential Amplifier and verify its output

Differential amplifier
Circuit

VDD
VDD

R1 R3
10kΩ 10kΩ

20kΩ C1
Vout1 Vout2
RBIAS V: -721 mV
Probe 3, Probe 1 Probe 4, Probe 2 I: -39. 0 uA
5pF
8 15 Q3 Q4
9
V1 1kΩ 2N2222
RS1 V: -588 mV 2N2222 1kΩ 0
5 1 Vpk I: -39. 0 uA RS2 V3
VDD
5MHz VDD
0Deg
0 12 V
10 0
V2
VEE
VEE
Q1 Q2
-12 V
2N2222
2N2222
Pow er Supply
VEE
VEE

Transient analysis

Electronics Circuit simulation Lab 82

 Experiment#-30

To design a speech filter and perform sensitivity analysis.

This circuit demonstrates the operation and characteristics of a speech filter, constructed by
cascading a high-pass and low-pass filter. As a result, a 300 Hz to 3 kHz bandpass voice
filter is formed. This circuit may be used to prove that there is no difference if the high-
pass is connected to the low-pass, or vice versa. Compare it with the BANDPASS.ms10
file.

Speech filter
Circuit
XBP1

IN OUT

C5
R7

270kΩ
560pF
5%
C8
R3

2MΩ
V1 130pF V3
5%

15 V 15 V
7 1 5 7 1 5

3 3 Probe 3, OUT
C4
R4
6 6 14 V: 2. 49 V
C1 C2 U1 U2
2 270kΩ
R5 2 I: -10. 1 uA
100nF
LF356BN* 5% LF356BN*
130kΩ
560pF 560pF
R1 R2 1%
V5 4 V2 4 V4
C3 C6 R6 C7
430kΩ 270kΩ
0V5V 10nF 560pF 47kΩ 2nF
5% 5%
0.1677msec 0.333msec 5%
15 V 15 V

Output

Electronics Circuit simulation Lab 83

Senstivity Analysis

Electronics Circuit simulation Lab 84

 Experiment#31

To verify the operation of Op-Amp Comparator.

Circuit
XSC2

Ext T rig
+
V1 _
VCC 0 A B
+ _ + _
5V
5V
REF 3
VCC R2
2V
5V
R1 1000 Ω
1.5kΩ 3
REF U1A
7
1 1
Probe1,OUT
6 LM339AD
V: 2.39 V
12 V(p-p): 186 pV
RT1 6 V(rms): 2.39 V
1kΩ 4 V2 V(dc): 2.39 V
0 I: 2.39 pA
0 I(p-p): 0 A
I(rms): 2.39 pA
0V
I(dc): 2.39 pA
Freq.: 10.7 kHz

Output

Electronics Circuit simulation Lab 85

 Experiment#32

To Design a Circuit of Peak Detector and Verify its output

This circuit illustrates a peak detector also called a follow-and-hold or positive peak
follower and is used only for analysis. It follows the voltage peaks of the input signal and
stores the highest value on a capacitor until discharged by a mechanical or electronic
switch. The voltage developed across the capacitor changes only when the input signal
exceeds the capacitor voltage.

Peak Detector
XSC1

Ext Trig
Rf +
XFG1 V3 _
10kΩ A B
V2 _ _
+ +

15 V

15 V
U2
U1
Ei
Vout
Vc

741
C1 Rl
741 100nF V4 10kΩ

V1
15 V
15 V

Output

Electronics Circuit simulation Lab 86

 Experiment-#33

To study the operation of servo Amplifier

The servo amplifier produces the output voltage (Vo) which is twice the input
signal (Ei). The voltage developed across the capacitor (Vcap) is three times the
input voltage.

Servo amplifier

+ -
5.800 V

C1
Rd
VEE
1uF 10kΩ
-15V
VEE
U1 -15V
Ri U3
100kΩ
Rc

10kΩ

Ei Ra
2V 10kΩ
VCC
15V VCC
15V
V: 1.93 V
Probe1,Probe1
I: 193 uA

Rb
10kΩ

I: 193 uA
Probe2,Probe2

Electronics Circuit simulation Lab 87

 Experiment#34

To Simulate a Window Detector

This circuit illustrates a window detector, also called a double-ended limit detector. It is
commonly used to detect if the input voltage goes outside the prescribed voltage
boundaries (between 4.5 V and 5.5 V in the sample circuit)

Window detector
XSC1

Ext T rig
+
_
A B
+ _ + _

U2

D1
V3
5.5 V

741
V1
Vin
U1 12 V

V5
D2 Vout
5 Vrms
1kHz
0Deg
V4 R1
741 V2 10kΩ
4.5 V

12 V

Output

Electronics Circuit simulation Lab 88

 Experiment#35

To analyze the operation of Traingular wave generator

This circuit demonstrates the operations and characteristics of a triangular-wave generator,

which produces triangle- and square-wave oscillator signals. The triangle wave is
generated at the output Va, while the square wave is available at the output Vb.
Please note that the oscillating circuits will not reach the stability state; therefore, it is
advisable to stop simulation after a few cycles.

Circuit

C1 pR

28kΩ
50nF
V3 V2

15 V U2 15 V
Ri U1
14kΩ Va R

10kΩ Vb

741
V4
V1 741

XSC1 15 V
15 V

Ext Trig
+
_
A B
+ _ + _

Output

Electronics Circuit simulation Lab 89

 Experiment#36

To analyze a Push-Pull amplifier and verify its voltage and current charcterstics
using Spice.

The coding of Push-Pull amplifier is done using Spice language.

The below graph shows the AC Analysis output of the Amplifier.

Electronics Circuit simulation Lab 90

 Experiment#37

To obtain Spice simulation for Variable gain Differntial Amplifier and draw Voltage
and Current Waveforms.

Spice Coding:-

Output

Electronics Circuit simulation Lab 91

 Experiment #38

To obtain spice simulation of a Phase Controlled Rectifier for closed loop control
system and Verify its output.

Circuit Diagram:
7 1 5
U13 U14
7 1 5
T3 U11 3
7 1 5 0
3 6
NLT_PQ_4_12
1 R34 7 3 0 6 R25 2
V15 C1 D12 R22 24 25
10kΩ 6 42 36 20 2 10kΩ
84.85 Vrms 5% 14 LF356BN
2 1N4148 10kΩ 4
60 Hz 270nF
R23 4 LF356BN V23
0° R20 V21
0 3 100Ω
4 LF356BN D11 12 0
10kΩ 1N4148 22 0
V18 12 V
5% 40 V17 0
0 12 V
0 R21
15 11 12 V
12 V 10kΩ R24 R26 28
U12 5%
XSC1 7 1 5 10kΩ 10kΩ
R27
0 34 10kΩ 3
D7 D8 Ext Trig 0 R30
+ 6
1N4001 1N4001
_
2 19
T4 A B V24510Ω
R1 16
+ _ + _ 0 V26
NLT_PQ_4_12
1kΩ 4 LF356BN 0
5% XSC2 V19 10 12 V
2 8 0
32 12 V
U16
17 6
Ext Trig
12 V 7 1 5 U15
5 +
_ 7 1 5
A B R28 3
0 R31
+ _ + _
6 23 3
10kΩ
2 10kΩ 6
D10 D9
1N4001 1N4001 R29 9 741 2
R19 27 100kΩ
100kΩ 33 4 26
Q3 V25 741
1% 0 4
30 V28
R32 31 0
C2 12 V 10kΩ
0 SXT3904
12 V
100nF
37

38
Q4
R33
100kΩ 50%
SXT3904 Key=A
Radj V27
4
10 V
0

Spice Coding:-

Electronics Circuit simulation Lab 92

Output

Electronics Circuit simulation Lab 93

 EXPERIMENT#39

To design Third order High Pass Filter and verify its output

Circuit

This circuit demonstrates the operation and characteristics of a third-order high-pass filter
and is constructed using a 40 dB/decade filter. The frequency response is 60 dB/decade
below the cutoff frequency. All signals below the cutoff frequency are attenuated
XSC1
XBP1
Ext Trig
+
IN OUT _
A B
+ _ + _

R2

5kΩ R5
R4 10kΩ

20kΩ
U2
XFG1
U1
C3
C1 C2
100nF
100nF 100nF
R3
10kΩ
R1
20kΩ

OUTPUT

Electronics Circuit simulation Lab 94

 EXPERIMENT#40

To design a Third Order Low pass Filter

Circuit

This circuit demonstrates the operation and characteristics of a third-order low-pass filter,
which was built by cascading a first-order low pass filter with a second order low-pass
filter. It produces a roll-off of -60 dB/decade. The overall closed-loop gain is the product
of the gains of the first and second filets.
XSC1
XBP1
Ext Trig
+
_
IN OUT A B
+ _ + _

C2
R5
20nF R3 15.91kΩ

31.83kΩ VEE
VEE -15V
XFG1
-15V U2
U1

R4
R1 R2 19.91kΩ
15.91kΩ 15.91kΩ C3
10nF
VCC
VCC 5V
C1
5nF 5V

Simulated Output

Electronics Circuit simulation Lab 95

 EXPERIMENT#41

To Design the circuit for a Substractor

Circuit

This circuit illustrates a subtractor, constructed by connecting an inverting amplifier to a

two-input inverting average. It produces an output voltage equal to the difference between
E1 and E2: Vo = E1-E2 (assuming Rf = R1).

Rf
R2

10kΩ
10kΩ XMM1

R1 U1

Ria U2
10kΩ

10kΩ
V1
4V OPAMP_3T_VIRTUAL Rib
OPAMP_3T_VIRTUAL
10kΩ
V2
1V

Output:

EXPERIMENT#42

Electronics Circuit simulation Lab 96

 To Verify the ouput of current to voltage convertor

Circuit

This circuit represents a current-to-voltage converter. As its name implies, it converts into
an output voltage all of the short-circuit current (Isc) that flows through the resistor (Rf).

Rf

40.8Ω

U1
Vo
R1 Isc
100Ω 100mA

+
R2
15kΩ -4.079 V
-

EXPERIMENT#43
Electronics Circuit simulation Lab 97
 To Design a Circuit for Overload Protection.
Circuit

This circuit demonstrates one of the most common methods of limiting current to percent
overloads in regulators. This method is known as a constant current limiting.
Q1
2N3904 R4 Vout
Probe1,Probe1
1Ω V:
V(dc):
I:
VCC
V1 R1 15V
15 V 1kΩ
U1
R2
10kΩ

Q2
2N3904

VEE
-15V

R5
100Ω
D1
5.1 V R3
10kΩ

Output can be seen in Probe:

EXPERIMENT#44
Electronics Circuit simulation Lab 98
 To Design a Bipolar Dead ZONE Circuit

Circuit

The bipolar dead-zone circuit is made up of a dead-zone circuit with negative output and a
dead-zone circuit with positive output. The outputs from these circuits, Voa and Vob, are
connected to an inverting adder, opamp B. The adder indicates by how much the input
signal Ei goes above or below the reference voltage (-Vref).

XFG1 XSC1

U1 Ext Trig
+

R1 Voa _
A B
Ei R5 + _ + _
10kΩ
10kΩ
741 U3

Vob
m R1 R3

30kΩ 10kΩ

741

V4 U2 R
15 V
10kΩ
R2
R6 10kΩ
Voa'
10kΩ
741

m R2 R4

30kΩ 10kΩ

V3
15 V

Simulated Output:

EXPERIMENT#45

Electronics Circuit simulation Lab 99

 To design a Dead Zone Circuit with Positive and negative Output.

Circuit Digram With Postive Output:

This circuit illustrates a dead-zone circuit with positive output. All input signals below the
reference voltage (-Vref) fall in a dead zone and are eliminated from the output; otherwise,
the equation for the out signal is Voa = -Ei -Vref. The output Vob is reinserted by the
opamp and indicates how many volts of the input signal (Ei) lie above -Vref.
XSC1

Ext T rig
+
_
A B
+ _ + _

Vpos
Vpos
Vpos
V2
U2 15 V
XFG1
U1
VoB
D2 VoA
R3
V3
Ei R1 10kΩ 15 V
741-DIV
10kΩ
741-DIV Vneg
Vneg
Vneg
D1 R4
mR
10kΩ
30kΩ R2
V1
15 V 10kΩ

Simulated Output:

Circuit Digram With Negative Output:-

Electronics Circuit simulation Lab 100

 XSC1

Ext Trig
+
_
A B
+ _ + _

V2
U2 15 V

XFG1 U1

D2 R3
V3
R1 10kΩ 15 V

10kΩ

m R1 D1 R4

30kΩ 10kΩ

V1 R2
15 V
10kΩ

This circuit illustrates a dead-zone circuit with negative output. All input signals above the
reference voltage (-Vref) fall in a dead zone and are eliminated from the output otherwise,
the equation for the output signal is Voa = -Ei -Vref. The output Vob is reinserted by the
opamp and indicates how many volts of the input signal (Ei) lie below -Vref.

Simulated Output

EXPERIMENT#46

Electronics Circuit simulation Lab 101

 To Design a Triangular to Sine wave Generator:-

Circuit

This circuit represents a triangular-to-sine-wave generator, and it may be used to

demonstrate the operation of the circuit as well to determine what parameters affect the
sinusoidal shape. As the circuit name implies, it converts the output of a triangular-
wave generator into a sine wave. The device used here is an amplifier with the gain
varying inversely with the amplitude of the output voltage. For the best sinusoidal
shape, R1, R2, R3, and the peak input voltage Ei must be adjusted.

R2 XSC1
1.1kΩ

Ext Trig
+
XFG1 _
V2 R4 A B
1.25kΩ + _ + _

15 V

U1
Ei R5
Vout
5kΩ

741

V1

15 V
R3 R6

5kΩ 5kΩ
R1
5kΩ

Output Waveforms:-

EXPERIMENT#47

Electronics Circuit simulation Lab 102

 To Design a Positive Voltage Detector

Circuit :-

This circuit demonstrates the operation of a non-inverting positive-voltage detector set up

as a comparator to detect a positive voltage. The positive reference voltage (Vref) is applied
to the inverting input terminal, while the input signal (1 kHz sine wave with 1 V peak) is
applied to the non-inverting input terminal. When the input signal exceeds the reference
voltage, the output equals the saturation voltage of the opamp.

XSC1
V1
Ext T rig
+
12 V U1 _
B
Vref A
_ _
+ +

Vout
Vref
1mV
Rl
741 10kΩ

V2

12 V

XFG1

Output:

EXPERIMENT#48

Electronics Circuit simulation Lab 103

 To Design a Inverting Positive Voltage Detector

Circuit

This circuit illustrates an inverting voltage detector setup as a comparator to detect a

positive voltage, and it is used to conduct circuit analysis. The positive reference voltage
(Vref) is applied to the non-inverting input terminal, while the input signal (1 kHz sine
wave with a 2 V peak) is applied to the inverting terminal. When the input signal exceeds
the value off the reference voltage, the output voltage reaches the value of the saturation
voltage (-Vsat).
XSC1

Ext T ri g
+
_
A B
+ _ + _

XFG1
V3

10 V

U1A
Ei

Vout
Vref

V1 Rl
1 V 10kΩ
V2
10 V

Output

EXPERIMENT#49

To Design a Non Zero Level Detector.

Electronics Circuit simulation Lab 104

 Circuit :-

This circuit represents a nonzero-level detector, which detects all voltages above the
preset reference voltage (Vref). The Zener diode is used to set the reference voltage.
When the sin-wave input voltage (Vin) is less than (Vref), the output remains at the
maximum negative level When Vin exceeds Vref, the output reaches its maximum
positive value
XSC1

Ext T rig
+
_
A B
+ _ + _

VEE
XMM1 -15V
R1
5kΩ

V1 U1
10 V Vz
Vout

Dref Vin RL
1N4730A 10kΩ

VCC
15V

XFG1

.
Output:-

EXPERIMENT#50

To design a Class A Power Amplifier.

Electronics Circuit simulation Lab 105
Circuit

This circuit illustrates a Class A common-emitter power amplifier, and is recommended for
conducting an analysis of a Class A power amplifier.For maximum output signal, the Q-
point must be centered. A noncentered Q-point limits the output swing.
XSC1

Ext Trig
+
_
+ B
A
R1 0.031 A
+ _ + _
5kΩ -

Rc
300Ω

C2

10uF
Q2 +
C -
+ 11.696 V
A RL V1
0.180m - 300Ω
24 V
10uF
2N3904
V2
30mVpk
5kHz
R2 +
1kΩ Re C3
0° 3.850 V
100Ω 100nF
-

Simulated Output:-

Electronics Circuit simulation Lab 106

Electronics Circuit simulation Lab 107