Scribd
Upload
34 views18 pages

Multisim Simulations

The document outlines the simulation of various logic gates including TTL NOR, TTL NAND, DL OR, DL AND, DTL NOR, DTL NAND, RTL OR, RTL NOR, and RTL AND gates. For each gate, the simulation lists the input combinations of A and B being 0 and 1 to test all possible input states.

Uploaded by

Sibghatullah Siyal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
34 views18 pages

Multisim Simulations

The document outlines the simulation of various logic gates including TTL NOR, TTL NAND, DL OR, DL AND, DTL NOR, DTL NAND, RTL OR, RTL NOR, and RTL AND gates. For each gate, the simulation lists the input combinations of A and B being 0 and 1 to test all possible input states.

Uploaded by

Sibghatullah Siyal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 18

TTL NOR Gate Simulation:

i) A=0 & B=0

ii) A=0 & B=1


iii) A=1 & B=0

iv) A=1 & B=1


TTL NAND Gate Simulation:

i) A=0 & B=0

ii) A=0 & B=1


iii) A=1 & B=0

iv) A=1 & B=1


DL OR Gate Simulation:

i) A=0 & B=0

ii) A=0 & B=1


iii) A=1 & B=0

iv) A=1 & B=1


DL AND Gate Simulation:

i) A=0 & B=0

ii) A=0 & B=1


iii) A=1 & B=0

iv) A=1 & B=1


DTL NOR Gate Simulation:

i) A=0 & B=0

ii) A=0 & B=1


iii) A=1 & B=0

iv) A=1 & B=1


DTL NAND Gate Simulation:

i) A=0 & B=0

ii) A=0 & B=1


iii) A=1 & B=0

iv) A=1 & B=1


RTL OR Gate Simulation:

i) A=0 & B=0

ii) A=0 & B=1


iii) A=1 & B=0

iv) A=1 & B=1


RTL NOR Gate Simulation:

i) A=0 & B=0

ii) A=0 & B=1


iii) A=1 & B=0

iv) A=1 & B=1


RTL AND Gate Simulation:

i) A=0 & B=0

ii) A=0 & B=1


iii) A=1 & B=0

iv) A=1 & B=1

You might also like