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1.
Methods for clock signal characterization using FPGA resources / Biereigel, S (CERN ; Leuven U. ; Brandenburg Tech. U.) ; Kulis, S (CERN) ; Moreira, P (CERN) ; Prinzie, J (Leuven U.) ; Leroux, P (Leuven U.) ; Koelpin, A (Brandenburg Tech. U.)
Reliable measurement of clock signal parameters is an important tool for calibration and validation of circuits used in precise-timing applications. Such parameters include frequency, phase, duty cycle and channel-to-channel skew. [...]
2020 - 13 p. - Published in : JINST 15 (2020) P03012 Fulltext: PDF;
2.
Radiation-tolerant all-digital clock generators for HEP applications / Biereigel, S (CERN ; Geel, Cathol. High Sch. Kempen ; Brandenburg Tech. U.) ; Kulis, S (CERN) ; Mendes, E (CERN) ; Hazell, P (CERN) ; Moreira, P (CERN) ; Prinzie, J (Geel, Cathol. High Sch. Kempen)
The emergence of high-precision timing systems in High Energy Physics motivates new developments in the domain of clock generation and distribution. Particularly, when considering the challenges arising from adopting advanced deep-submicron CMOS technology nodes, all-digital PLL and clock and data recovery (CDR) architectures constitute a promising option for future high energy physics (HEP) experiments. [...]
2023 - 8 p. - Published in : JINST 18 (2023) C01060 Fulltext: PDF;
In : Topical Workshop on Electronics for Particle Physics 2022 (TWEPP 2022), Bergen, Norway, 19 - 23 Sep 2022, pp.C01060
3.
Digital duty-cycle correction circuit for clock paths in radiation-tolerant high-speed wireline transmitters / Klekotko, A (Leuven U. ; CERN) ; Baszczyk, M (CERN) ; Biereigel, S (CERN) ; Kulis, S (CERN) ; Martina, F (CERN) ; Moreira, P (CERN) ; Tavernier, F (Leuven U.) ; Prinzie, J (Leuven U.)
Ongoing developments in the field of radiation-toleranthigh-speed transmitters (HSTs)aim at increasing thedata rates above 25 Gb/s while increasingtotal ionizing dose (TID)tolerance above 1 Grad. The use of half-ratearchitectures imposes tight constraints on clock signal quality, in particular itsduty-cycle. [...]
2024 - 7 p. - Published in : JINST 19 (2024) C02030 Fulltext: PDF;
In : Topical Workshop on Electronics for Particle Physics 2023 (TWEPP 2023), Geremeas, Sardinia, Italy, 1 - 6 Oct 2023, pp.C02030
4.
Radiation hard true single-phase-clock logic for high-speed circuits in 28 nm CMOS / Klekotko, A (Leuven U. ; CERN) ; Baszczyk, M (CERN) ; Biereigel, S (Leuven U. ; CERN) ; Kulis, S (CERN) ; Moreira, P (CERN) ; Prinzie, J (Leuven U.) ; Tavernier, F (Leuven U.)
True Single-Phase-Clock (TSPC) dynamic logic is widely used in high-speed circuits such as high-speed SERDES (Serializer/Deserializer) and frequency dividers. TSPC flip-flops (FF) are known for their high operational speed and low power consumption, compared to static FFs. [...]
2023 - 8 p. - Published in : JINST 18 (2023) C02068 Fulltext: PDF;
In : Topical Workshop on Electronics for Particle Physics 2022 (TWEPP 2022), Bergen, Norway, 19 - 23 Sep 2022, pp.C02068
5.
Dual use driver for high speed links transmitters in the future high energy physics experiments / Baszczyk, M (CERN) ; Biereigel, S (CERN) ; Klekotko, A (CERN ; Leuven U.) ; Kulis, S (CERN) ; Martina, F (CERN) ; Moreira, P (CERN)
The paper presents the Dual Use Driver (DUDE) for highspeed links, a circuit designed for the Demonstrator ASIC for Radiation-Tolerant Transmitter in 28 nm CMOS (DART28) developed under the EP-R&D; programme on technologies for future high energyphysics experiments. The driver operates at 25.6 Gbps and it allows driving both 100 Ωtransmission lines and optical Ring Modulators (RMs) integrated in a photonics integrated circuit(PIC). [...]
2024 - 7 p. - Published in : JINST 19 (2024) C03013 Fulltext: PDF;
In : Topical Workshop on Electronics for Particle Physics 2023 (TWEPP 2023), Geremeas, Sardinia, Italy, 1 - 6 Oct 2023, pp.C03013
6.
Single-Event Effect Responses of Integrated Planar Inductors in 65-nm CMOS / Biereigel, Stefan (CERN ; Leuven U. ; Brandenburg Tech. U.) ; Kulis, Szymon (CERN) ; Leroux, Paul (Leuven U.) ; Moreira, Paulo (CERN) ; Kolpin, Alexander (Hamburg, Tech. U.) ; Prinzie, Jeffrey (Leuven U.)
This article describes a previously unreported single-event radiation effect in spiral inductors manufactured in a commercial CMOS technology when subjected to ionizing radiation. Inductors play a major role as the component determining the frequency of LC tank oscillators, which is why any radiation effect in these passive components can have a detrimental impact on the performance of clock generation circuits. [...]
2021 - 11 p. - Published in : IEEE Trans. Nucl. Sci. 68 (2021) 2587-2597 Fulltext: PDF;
7.
The lpGBT PLL and CDR Architecture, Performance and SEE Robustness / Biereigel, Stefan (Brandenburg Tech. U. ; Leuven U. ; CERN) ; Kulis, Szymon (CERN) ; Francisco, Rui (CERN) ; Leitao, Pedro Vicente (CERN) ; Leroux, Paul (Leuven U.) ; Moreira, Paulo (CERN) ; Prinzie, Jeffrey (Leuven U.)
We present the design, architecture and experimental results of the low jitter Clock and Data Recovery (CDR) and Phase Locked Loop (PLL) circuit in the Low-Power Gigabit Transceiver (lpGBT) ASIC. This circuit includes a low noise radiation-tolerant integrated LC-oscillator with a nominal frequency of 5.12 GHz to support a 10.24 Gbps uplink and a 2.56 Gbps downlink CDR. [...]
SISSA, 2020 - 5 p. - Published in : PoS TWEPP2019 (2020) 034 Fulltext: PDF;
In : TWEPP 2019 Topical Workshop on Electronics for Particle Physics, Santiago De Compostela, Spain, 2 - 6 Sep 2019, pp.034
8.
A Radiation-Tolerant 25.6-Gb/s High-Speed Transmitter in 28-nm CMOS With a Tolerance of 1 Grad / Klekotko, A (CERN ; Leuven U.) ; Biereigel, S (CERN) ; Baszczyk, M (CERN) ; Moreira, P (CERN) ; Martina, F (CERN) ; Prinzie, J (Leuven U.) ; Kulis, S (Leuven U.)
This article presents a 25.6-Gbit $\cdot $ s−1 high-speed transmitter (HST) manufactured using 28-nm CMOS technology. The HST macroblock includes an all-digital phase-locked loop (ADPLL), duty cycle corrector (DCC) circuit, data pattern generator, serializer, and a driver capable of driving the differential 100- $\Omega $ line as well as a silicon photonics (SiPh) ring modulator (RM). [...]
2024 - 9 p. - Published in : IEEE Trans. Nucl. Sci. 71 (2024) 2124-2132 Fulltext: PDF;
9.
Source Switched Charge-Pump PLLs for High-Dose Radiation Environments / Prinzie, Jeffrey (Leuven U.) ; Biereigel, Stefan (CERN) ; Kulis, Szymon (CERN) ; Leitao, Pedro (CERN) ; Moreira, Paulo (CERN)
This article presents a radiation tolerant charge-pump phase-locked loop (PLL) with low static phase error variability suitable for high-performance clock systems in high-dose radiation environments. We investigate the use of source switching charge-pump architectures to minimize any voltage- or dose-dependent charge injection and address the limitations of enclosed layout transistors (ELTs) in the conventional drain switched charge-pump. [...]
2023 - 6 p. - Published in : IEEE Trans. Nucl. Sci. 70 (2023) 590-595
In : 2022 IEEE Nuclear and Space Radiation Effects Conference, Provo, Utah, USA, 18 - 23 Jul 2022, pp.590-595
10.
Radiation-Tolerant All-Digital Clock Generators for High Energy Physics / Biereigel, Stefan
The main focus of the presented research is the development and experimental study of radiation-tolerant clock generation circuits intended for applications in high energy physics (HEP) [...]
CERN-THESIS-2022-139 doi:10.26127/BTUOpen-6088. - 215 p.


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