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1.
RD53 pixel chips for the ATLAS and CMS Phase-2 upgrades at HL-LHC / Loddo, F (INFN, Bari) ; Andreazza, A (Milan U. ; INFN, Milan) ; Arteche, F (Sao Paulo, Inst. Tech. Aeronautics) ; Barbero, M B (Marseille, CPPM) ; Barillon, P (Marseille, CPPM) ; Beccherle, R (INFN, Pisa) ; Bilei, G M (INFN, Perugia ; Perugia U.) ; Bjalas, W (CERN) ; Bonaldo, S (INFN, Padua ; Padua U.) ; Bortoletto, D (Oxford U.) et al.
The Phase-2 upgrades at the High-Luminosity LHC of ATLAS and CMS experiments at CERN will require a new tracker with readout electronics operating in extremely harsh radiation environment (1 Grad), high hit rate (3.5 GHz/cm2) and high data rate readout (5 Gb/s). The RD53 collaboration is a joint effort between the ATLAS and CMS to qualify the chosen 65 nm CMOS technology in high radiation environment and develop the pixel readout chips of both experiments. [...]
FERMILAB-PUB-24-0469-PPD.- 2024 - 5 p. - Published in : Nucl. Instrum. Methods Phys. Res., A 1067 (2024) 169682
In : PSD13: The 13th International Conference on Position Sensitive Detectors, Oxford, United Kingdom, 3 - 9 Sep 2023, pp.169682
2.
Digital cells radiation hardness study of TPSCo 65 nm CIS technology by designing a ring oscillator / Barbero, M (Marseille, CPPM) ; Barrillon, P (Marseille, CPPM) ; Fougeron, D (Marseille, CPPM) ; Habib, A (Marseille, CPPM) ; Pangaud, P (Marseille, CPPM)
The CPPM group has long been designing and testing HV-CMOS blocks to complete monolithic chips in various technologies (TJ180, LF150, AMS) in the framework of several collaborations. In 2020, we participated in the MLR1 run in TowerJazz 65 nm technology through CERN’s EP-R&D; WP1.2, by designing a ring oscillator test chip. [...]
2023 - 8 p. - Published in : JINST 18 (2023) C02063
In : Topical Workshop on Electronics for Particle Physics 2022 (TWEPP 2022), Bergen, Norway, 19 - 23 Sep 2022, pp.C02063
3.
Design optimization of a Dual-Interlocked-Cell in 65 nm CMOS tolerant to Single Event Upsets / Márquez, F (U. Sevilla, Dept. Electron. Eng.) ; Palomo, F R (U. Sevilla, Dept. Electron. Eng. ; CERN) ; Muñoz, F (U. Sevilla, Dept. Electron. Eng.) ; Fougeron, D (Marseille, CPPM) ; Menouni, M (Marseille, CPPM)
Dual-Interlocked-Cell (DICE) latches are tolerant to SingleEvent Effects (SEE) by design owing to intrinsic redundancy. Innanometric technologies, as in the 65 nm scale, there are new SEEvulnerabilities associated with charge sharing between nodes. [...]
2023 - 17 p. - Published in : JINST 18 (2023) P10023 Fulltext: PDF;
4.
Optimization of a 65 nm CMOS imaging process for monolithic CMOS sensors for high energy physics / Rinella, G Aglieri (CERN) ; Andronic, A (Munster U., ITP) ; Antonelli, M (INFN, Trieste ; Trieste U.) ; Baccomi, R (INFN, Trieste ; Trieste U.) ; Ballabriga, R (CERN) ; Barbero, M (Marseille, CPPM) ; Barrillon, P (Marseille, CPPM) ; Baudot, J (Strasbourg, IPHC) ; Becht, P (Heidelberg U.) ; Benotto, F (INFN, Turin ; Turin U.) et al.
The long term goal of the CERN Experimental Physics Department R&D; on monolithic sensorsis the development of sub-100nm CMOS sensors for high energy physics. The first technologyselected is the TPSCo 65nm CMOS imaging technology. [...]
2023 - 15 p. - Published in : PoS Pixel2022 (2023) 083 Fulltext: PDF;
In : 10th International Workshop on Semiconductor Pixel Detectors for Tracking and Imaging (PIXEL 2022), Santa Fe, USA, 11 - 16 Dec 2022, pp.083
5.
Single event effects testing of the RD53B chip / Menouni, Mohsine (Marseille, CPPM) ; Barrillon, Pierre (Marseille, CPPM) ; Flores, Leyre (CERN) ; Fougeron, Denis (Marseille, CPPM) ; Hemperek, Tomasz (Bonn U.) ; Joly, Eva (Marseille, CPPM) ; Lalic, Jelena (CERN) ; Strebler, Thomas (Marseille, CPPM)
The RD53 collaboration has been working since 2014 on the development of pixel chips for the CMS and ATLAS Phase 2 tracker upgrade. This work has recently led to the development of the RD53B full-scale readout chip which is using the 65nm CMOS process and containing 153600 pixels of 50 × 50 μm $^{2}$ The RD53B chip is designed to be robust against the Single Event Effects (SEE), allowing such a complex chip to operate reliably in the hostile environment of the HL-LHC. [...]
2022 - 5 p. - Published in : J. Phys. : Conf. Ser. 2374 (2022) 012084 Fulltext: PDF;
In : International Conference on Technology and Instrumentation in Particle Physics (TIPP 2021), Online, Canada, 24 - 29 May 2021, pp.012084
6.
The ATLAS experiment at the CERN Large Hadron Collider: a description of the detector configuration for Run 3 / ATLAS Collaboration
The ATLAS detector is installed in its experimental cavern at Point 1 of the CERN Large Hadron Collider. During Run 2 of the LHC, a luminosity of $\mathcal{L}=2\times 10^{34}\mathrm{cm}^{-2}\mathrm{s}^{-1}$ was routinely achieved at the start of fills, twice the design luminosity. [...]
arXiv:2305.16623; CERN-EP-2022-259.- Geneva : CERN, 2024-05-23 - 233 p. - Published in : JINST 19 (2024) P05063 Fulltext: 2305.16623 - PDF; document - PDF; External link: Previous draft version
In : The Large Hadron Collider and The Experiments for Run 3
7.
Single event effects on the RD53B pixel chip digital logic and on-chip CDR / RD53 Collaboration
The RD53B chip for HL-LHC upgrades of ATLAS and CMS pixel detectors needs to provide reliable operation in a radiation hostile environment with inevitable Single Event Effects (SEE). To answer the challenge, substantial efforts are made to protect and evaluate the critical parts of the digital logic and to characterize the on-chip Clock and Data Recovery (CDR) circuit. [...]
2022 - 7 p. - Published in : JINST 17 (2022) C05001
In : TWEPP 2021 Topical Workshop on Electronics for Particle Physics, Online, Online, 20 - 24 Sep 2021, pp.C05001
8.
Etude et mise en œuvre de cellules résistantes aux radiations dans le cadre de l'évolution du détecteur à pixels d'ATLAS en technologie CMOS 65 nm / Fougeron, Denis
The 65 nm CMOS technology is a promising technology for the pixel readout chips at HL-LHC in terms of high integration density [...]
CERN-THESIS-2020-403 - 129 p.

9.
RD53 analog front-end processors for the ATLAS and CMS experiments at the High-Luminosity LHC / RD53 Collaboration
This work discusses the design and the main results relevant to the characterization of analog front-end processors in view of their operation in the pixel detector readout chips of ATLAS and CMS at the High-Luminosity LHC. The front-end channels presented in this paper are part of RD53A, a large scale demonstrator designed in a 65 nm CMOS technology by the RD53 collaboration.The collaboration is now developing the full-sized readout chips for the actual experiments. [...]
SISSA, 2020 - 9 p. - Published in : PoS Vertex2019 (2020) 021 Fulltext from Publisher: PDF;
In : Vertex 2019: 28th International Workshop on Vertex Detectors, Lopud Island, Croatia, 13 - 18 Oct 2019, pp.021
10.
Measurements of Single Event Upset in ATLAS IBL / Balbi, G. (INFN, Bologna) ; Barbero, M. (Bonn U. ; Marseille, CPPM) ; Beccherle, R. (INFN, Genoa ; INFN, Pisa) ; Bindi, M. (Gottingen U., II. Phys. Inst.) ; Breugnon, P. (Marseille, CPPM) ; Butti, P. (CERN ; SLAC) ; Cinca, D. (Dortmund U.) ; Dickinson, J. (LBL, Berkeley) ; Ferrere, D. (Geneva U.) ; Fougeron, D. (Marseille, CPPM) et al.
Effects of Single Event Upsets (SEU) and Single Event Transients (SET) are studied in the FE-I4B chip of the innermost layer of the ATLAS pixel system. SEU/SET affect the FE-I4B Global Registers as well as the settings for the individual pixels, causing, among other things, occupancy losses, drops in the low voltage currents, noisy pixels, and silent pixels. [...]
arXiv:2004.14116.- 2020-06-17 - 30 p. - Published in : JINST 15 (2020) P06023 Fulltext: PDF; Fulltext from publisher: PDF;

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