Search Results (503)

As CMOS technology continues to scale down, the aging effect—known as negative bias temperature instability (NBTI)—has become increasingly prominent, gradually emerging as a key factor affecting device reliability. Accurate aging-aware static timing analysis (STA) at the early design phase is critical for establishing appropriate timing margins to ensure circuit reliability throughout the chip lifecycle. However, traditional aging-aware timing analysis methods, typically based on Simulation Program with Integrated Circuit Emphasis (SPICE) simulations or aging-aware timing libraries, struggle to balance prediction accuracy with computational cost. In this paper, we propose a multi-view graph learning framework for path-level aging-aware timing prediction, which combines the strengths of the spatial–temporal Transformer network (STTN) and graph attention network (GAT) models to extract the aging timing features of paths from both timing-sensitive and workload-sensitive perspectives. Experimental results demonstrate that our proposed framework achieves an average MAPE score of 3.96% and reduces the average MAPE by 5.8 times compared to FFNN and 2.2 times compared to PNA, while maintaining acceptable increases in processing time. Full article

A direct bidirectional current discharge path between the input/output (I/O) and ground (GND) is essential for the robust protection of charging device models (CDM) in the tightly constrained design parameters of advanced low-voltage (LV) processes. Dual-direction silicon controlled rectifiers (DDSCRs) serve as ESD protection devices with high efficiency unit area discharge, enabling bidirectional electrostatic protection. However, the high trigger voltage of conventional DDSCR makes it unsuitable for ASICs used for the preamplification of biomedical signals, which only operate at low supply voltage. To address this issue, a self-biased triggered DDSCR (STDDSCR) structure is proposed to further reduce the trigger voltage. When the ESD pulse comes, the external RC trigger circuit controls the PMOS turn-on by self-bias, and the current release path is opened in advance to reduce the trigger voltage. As the ESD pulse voltage increases, the SCR loop opens to establish positive feedback and drain the amplified current. Additionally, the junction capacitance is decreased through high-resistance epitaxy and low-concentration P-well injection to further lower the trigger voltage. The simulation results of LTspice and TCAD respectively demonstrate that ESD devices can clamp transient high voltages earlier, with low parasitic capacitance and leakage current suitable for ESD protection of high-speed ports up to 1.5 V under normal operating conditions. Full article

Acid-sensing ion channels (ASICs), which act as proton-gating sodium channels, have garnered attention as pharmacological targets. ASIC1a isoform, notably prevalent in the central nervous system, plays an important role in synaptic plasticity, anxiety, neurodegeneration, etc. In the peripheral nervous system, ASIC1a shares prominence with ASIC3, the latter well established for its involvement in pain signaling, mechanical sensitivity, and inflammatory hyperalgesia. However, the precise contributions of ASIC1a in peripheral functions necessitate thorough investigation. To dissect the specific roles of ASICs, peptide ligands capable of modulating these channels serve as indispensable tools. Employing molecular modeling, we designed the peptide targeting ASIC1a channel from the sea anemone peptide Ugr9-1, originally targeting ASIC3. This peptide (A23K) retained an inhibitory effect on ASIC3 (IC₅₀ 9.39 µM) and exhibited an additional inhibitory effect on ASIC1a (IC₅₀ 6.72 µM) in electrophysiological experiments. A crucial interaction between the Lys23 residue of the A23K peptide and the Asp355 residue in the thumb domain of the ASIC1a channel predicted by molecular modeling was confirmed by site-directed mutagenesis of the channel. However, A23K peptide revealed a significant decrease in or loss of analgesic properties when compared to the wild-type Ugr9-1. In summary, using A23K, we show that negative modulation of the ASIC1a channel in the peripheral nervous system can compromise the efficacy of an analgesic drug. These results provide a compelling illustration of the complex balance required when developing peripheral pain treatments targeting ASICs. Full article

This study applies a forensic examination to six distinct Android fitness applications centered around monitoring running activities. The applications are Adidas Running, MapMyWalk, Nike Run Club, Pumatrac, Runkeeper and Strava. Specifically, we perform a post mortem analysis of each application to find and document artifacts such as timelines and Global Positioning System (GPS) coordinates of running workouts that could prove helpful in digital forensic investigations. First, we focused on the Nike Run Club application and used the gained knowledge to analyze the other applications, taking advantage of their similarity. We began by creating a test environment and using each application during a fixed period. This procedure allowed us to gather testing data, and, to ensure access to all data generated by the apps, we used a rooted Android smartphone. For the forensic analysis, we examined the data stored by the smartphone application and documented the forensic artifacts found. To ease forensic data processing, we created several Python modules for the well-known Android Logs Events And Protobuf Parser (ALEAPP) digital forensic framework. These modules process the data sources, creating reports with the primary digital artifacts, which include the workout activities and related GPS data. Full article

A novel stress suppression design for flexible RF MEMS switches has been presented and demonstrated through theoretical and experimental research to isolate the stress caused by substrate bending. An RF MEMS switch with an S-shaped microspring structure was fabricated by the two-step etching process as a developmental step toward miniaturization and high reliability. The RF MEMS switches with an S-shaped microspring exhibited superior microwave performance and stable driving voltage under different substrate curvatures compared to the conventional non-microspring switches, demonstrating that the bending stress is successfully suppressed by the S-shaped microspring and the island structure. Furthermore, this innovative design could be easily extended to other flexible devices. Full article

Effective Ohmic contact between metals and their conductive channels is a crucial step in developing high-performance Ga₂O₃-based transistors. Distinct from bulk materials, excess thermal energy of the annealing process can destroy the low-dimensional material itself. Given the thermal budget concern, a feasible and moderate solution (i.e., Ar-containing plasma treatment) is proposed to achieve effective Ohmic junctions with (100) β-Ga₂O₃ nanosheets. The impact of four kinds of plasma treatments (i.e., gas mixtures SF₆/Ar, SF₆/O₂/Ar, SF₆/O₂, and Ar) on (100) β-Ga₂O₃ crystals is comparatively studied by X-ray photoemission spectroscopy for the first time. With the optimal plasma pre-treatment (i.e., Ar plasma, 100 W, 60 s), the resulting β-Ga₂O₃ nanosheet field-effect transistors (FETs) show effective Ohmic contact (i.e., contact resistance R_C of 104 Ω·mm) without any post-annealing, which leads to competitive device performance such as a high current on/off ratio (>10⁷), a low subthreshold swing (SS, 249 mV/dec), and acceptable field-effect mobility (μeff, ~21.73 cm² V⁻¹ s⁻¹). By using heavily doped β-Ga₂O₃ crystals (N_e, ~10²⁰ cm⁻³) for Ar plasma treatments, the contact resistance R_C can be further decreased to 5.2 Ω·mm. This work opens up new opportunities to enhance the Ohmic contact performance of low-dimensional Ga₂O₃-based transistors and can further benefit other oxide-based nanodevices. Full article

This two-part work develops a comprehensive toolbox for the statistical characterization of nonlinear distortions of DAC-generated signal constellations to be transmitted over communication links, be they electronic (wireline, wireless) or photonic, Mach–Zehnder modulator (MZM)-based optical interconnects in particular. The all-analytic toolbox developed here delivers closed-form expressions for the second-order statistics (means, variances) of all relevant constellation metrics of the DACs’ building blocks and of DAC-driven MZM-based optical transmitters, all the way to the slicer in the optical receivers over a linear channel with coherent detection. The key impairment targeted by the model is the random current mismatch of the ASIC devices implementing the DAC drivers. In particular the (skew-)centrosymmetry of the DAC metrics is formally derived and explored. A key applicative insight is that the conventional INL/DNL (Integral NonLinearity/Differential NonLinearity) constellation metrics, widely adopted in the electronic devices and circuits community, are not quite useful in the context of communication systems, since these metrics are ill-suited to predict communication link statistical performance. To rectify this deficiency of existing electronic DAC metrics, we introduce modified variants of the INL|DNL, namely the integral error vector (IEV) and the differential error vector (DEV) constellation metrics. The new IEV|DEV represent straightforward predictors of relevant communication-minded metrics: error vector magnitude (EVM) treated here in Part I, and Symbol/Bit Error-Rates (SER, BER) treated in the upcoming Part II of this paper. Full article

With the exponential growth of the Internet of Things (IoT), ensuring robust end-to-end encryption is paramount. Current cryptographic accelerators often struggle with balancing security, area efficiency, and power consumption, which are critical for compact IoT devices and system-on-chips (SoCs). This work presents a novel approach to designing substitution boxes (S-boxes) for Advanced Encryption Standard (AES) encryption, leveraging dual quad-bit structures to enhance cryptographic security and hardware efficiency. By utilizing Algebraic Normal Forms (ANFs) and Walsh–Hadamard Transforms, the proposed Register Transfer Level (RTL) circuitry ensures optimal non-linearity, low differential uniformity, and bijectiveness, making it a robust and efficient solution for ASIC implementations. Implemented on 65 nm CMOS technology, our design undergoes rigorous statistical analysis to validate its security strength, followed by hardware implementation and functional verification on a ZedBoard. Leveraging Cadence EDA tools, the ASIC implementation achieves a central circuit area of approximately 199 μm². The design incurs a hardware cost of roughly 80 gate equivalents and exhibits a maximum path delay of 0.38 ns. Power dissipation is measured at approximately 28.622 μW with a supply voltage of 0.72 V. According to the ASIC implementation on the TSMC 65 nm process, the proposed design achieves the best area efficiency, approximately 66.46% better than state-of-the-art designs. Full article

The combination of high-density, high-time-resolution inorganic scintillation crystals such as Lutetium Yttrium Oxyorthosilicate (LYSO), Yttrium Orthosilicate (YSO) and Bismuth Germanate (BGO) with Silicon Photomultiplier (SiPM) sensors is widely employed in medical imaging, particularly in Positron Emission Tomography (PET), as well as in modern particle physics detectors for precisely timing sub-detectors and calorimeters. During the assembly of each module, following individual component testing, the crystals and SiPMs are bonded together using optical glue and enclosed in a light-tight, temperature-controlled cooling box. After integration with the readout electronics, the bonding is initially tested. The final readout electronics typically comprise Application-Specific Integrated Circuits (ASICs) or low-power Analog-to-Digital Converters (ADCs) and amplifiers, designed not to heat up the temperature-sensitive SiPM sensors. However, these setups are not optimal for testing the optical bonding. Specific setups were developed to test the LYSO + SiPM modules that are already bonded but not enclosed in a box. Through large data collection, small deviations in bonding can be detected if the SiPMs and LYSOs have been thoroughly tested before our measurement. The Monte Carlo simulations we used to study how parameters—which are difficult to measure in the laboratory (LYSO absorption length, refractive index of the coating)—affect the final result. Our setups for particle physics and PET applications are already in use by research institutes and industrial partners. Full article

The proliferation of battery-operated end-user electronic devices due to technological advancements, especially in medical image processing applications, demands low power consumption, high-speed operation, and efficient coding. The design of these devices is centered on the Application-Specific Integrated Circuits (ASIC), General Purpose Processors (GPP), and Field Programmable Gate Array (FPGA) frameworks. The need for low-power functional blocks arises from the growing demand for high-performance computational units that are part of high-speed processors operating at high clock frequencies. The operational speed of the processor is determined by the computational unit, which is the workhorse of high-speed processors. A novel approach to integrating Very Large-Scale Integration (VLSI) ASIC design and the concepts of low-power VLSI compatible with medical image compression was embraced in this research. The focus of this study was the design, development, and implementation of a Power Delay Product (PDP) optimized computational unit targeted for medical image compression using ASIC design flow. This stimulates the research community’s quest to develop an ideal architecture, emphasizing on minimizing power consumption and enhancing device performance for medical image processing applications. The study uses area, delay, power, PDP, and Peak Signal-to-Noise Ratio (PSNR) as performance metrics. The research work takes inspiration from this and aims to enhance the efficiency of the computational unit through minor design modifications that significantly impact performance. This research proposes to explore the trade-off of high-performance adder and multiplier designs to design an ASIC-based computational unit using low-power techniques to enhance the efficiency in power and delay. The computational unit utilized for the digital image compression process was synthesized and implemented using gpdk 45 nm standard libraries with the Genus tool of Cadence. A reduced PDP of 46.87% was observed when the image compression was performed on a medical image, along with an improved PSNR of 5.89% for the reconstructed image. Full article

Microwave annealing, an emerging annealing method known for its efficiency and low thermal budget, has established a foundational research base in the annealing of molybdenum disulfide (MoS₂) devices. Typically, to obtain high-quality MoS₂ devices, mechanical exfoliation is commonly employed. This method’s challenge lies in achieving uniform film thickness, which limits the use of extensive data for studying the effects of microwave annealing on the MoS₂ devices. In this experiment, we utilized a neural network approach based on the HSV (hue, saturation, value) color space to assist in distinguishing film thickness for the fabrication of numerous MoS₂ devices with enhanced uniformity and consistency. This method allowed us to precisely assess the impact of microwave annealing on device performance. We discovered a relationship between the device’s electrical performance and the annealing power. By analyzing the statistical data of these electrical parameters, we identified the optimal annealing power for MoS₂ devices as 700 W, providing insights and guidance for the microwave annealing process of two-dimensional materials. Full article

This paper provides a comparative analysis of AES (Advanced Encryption Standard) and Salsa20 algorithm implementations, focusing on power consumption efficiency in passive RFID (radio-frequency identification) tags and ultra-low-power devices. The main objective of this work is to determine which of these algorithms is more suitable to operate in these types of devices. For this purpose, ASIC (application-specific integrated circuit) implementations of AES and Salsa20 based on low-power approaches were developed and their power consumption was evaluated. The results demonstrate that Salsa20 power consumption is lower than AES (about 17%), indicating that Salsa20 is a much better choice than AES for passive RFID tags. Full article

The paper presents the noise analysis of a MEMS and ASIC readout integrated circuit (ROIC) constituting the accelerometer developed in the frame of the InnoReh project, aiming at the development of methods for monitoring patients with imbalance disorders. Several experiments were performed at different temperatures and in different configurations: ROIC alone, ROIC with emulated parasitic capacitances, MEMS and ROIC in separate packages, and MEMS and ROIC in a single package. Many noise/interference sources were considered. The results obtained experimentally were compared to the results of theoretical investigations and were within the same order of magnitude, although in practice, the observed noise was always greater than the theoretical estimation. The paper also includes an in-depth analysis to explain these differences. Moreover, it is argued that, in terms of noise, the MEMS sensing element, and not the ROIC, is the quality-limiting factor. Full article

The complexity of information processing in the brain requires the development of technologies that can provide spatial and temporal resolution by means of dense electrode arrays paired with high-channel-count signal acquisition electronics. In this work, we present an ultra-low noise modular 512-channel neural recording circuit that is scalable to up to 4096 simultaneously recording channels. The neural readout application-specific integrated circuit (ASIC) uses a dense 8.2 mm × 6.8 mm 2D layout to enable high-channel count, creating an ultra-light 350 mg flexible module. The module can be deployed on headstages for small animals like rodents and songbirds, and it can be integrated with a variety of electrode arrays. The chip was fabricated in a TSMC 0.18 µm 1.8 V CMOS technology and dissipates a total of 125 mW. Each DC-coupled channel features a gain and bandwidth programmable analog front-end along with 14 b analog-to-digital conversion at speeds up to 30 kS/s. Additionally, each front-end includes programmable electrode plating and electrode impedance measurement capability. We present both standalone and in vivo measurements results, demonstrating the readout of spikes and field potentials that are modulated by a sensory input. Full article

Thanks to advancements in silicon photomultiplier sensors (SiPMs) and system-on-chip (SoC) technology, our INFN Roma1 group developed ArduSiPM in 2012, the first all-in-one scintillator particle detector in the literature. It used a custom Arduino Due shield to process fast signals, utilizing the Microchip Sam3X8E SoC’s internal peripherals to control and acquire SiPM signals. The availability of radiation-tolerant SoCs, combined with the goal of reducing system space and weight, led to the development of an innovative second-generation board, a better-performing device called Cosmo ArduSiPM, suitable for space missions. The architecture of the new detector is based on the Microchip SAMV71 300 MHz, 32-bit ARM^® Cortex^®-M7 (Microchip Technology Inc., Chandler, AZ, USA). While the analog front-end is essentially identical to the ArduSiPM, it utilizes components with the smallest possible package. The board fits in a CubeSat module. Thanks to the compact design, the board has two independent channels, with a total weight of only 40 grams within a CubeSat form factor. The ArduSiPM architecture is based on a single microcontroller and fast discrete analog electronics. It benefits from the continued development of SoCs related to the IoT (Internet of Things) market. Compared with a system with a custom ASIC, this architecture based on software and SoC capabilities offers considerable advantages in terms of cost and development time. The ability to incorporate new commercial SoCs, continuously emerging from advancements in the aerospace and automotive industries, provides the system with a robust foundation for sustained growth over the years. A detailed characterization of the hardware and the system’s response to different photon fluxes is presented in this article. Additionally, coupling the device with a scintillator was tested at the end of this article as a preliminary trial for future measurements, showing potential for further enhancement of the detector’s capabilities. Full article