During MMC operation, the SM capacitor parameters are not identical, which constitutes a primary factor in the SM output voltage imbalance. The SM capacitor voltage imbalance is a natural occurrence because of the disparity between the predicted time and the actual on-state time calculated via the modulation.
2.1. SM Capacitor Value Differences
MMC’s basic unit is SM. Its standard structures include the half-bridge type and full-bridge type. In engineering, a half-bridge SM is commonly employed, consisting of two insulated gate bipolar transistors (
IGBTs) and a capacitor, as demonstrated in
Figure 1.
IGBT1 and
IGBT2 determine the SM capacitor
C0 charge or discharge. Assuming that
ism is active from A to B and vice versa, if the potential of A is higher than that of B, then
usm is active and vice versa. The values ‘1’ and ‘0’ indicate
IGBT conduction and shutdown, respectively. Then, the relationship between the on–off of
IGBT1 and
IGBT2, and the state of the SM capacitor
C0 is shown in
Table 1.
From
Figure 1, we can see that if the SM initial voltage is
u0, then the capacitor voltage
uc, instantaneous power
pc, and stored energy
Wc meet the following relationship during a charging cycle:
During operation, we suppose that the voltage and current are
Udc, Idc at the DC side bus. In phase
j(
j =
a,
b,
c), the upper arm current is
ijp; the number of on-state SMs is
npj; and the capacitor value, voltage, and stored energy of the
i-th conducting SM are
Cpi,
ujpi, and
Wjpi, respectively. We draw the circuit diagram of phase
j, as shown in
Figure 2.
From
Figure 2, we can see that the upper bridge
j-phase capacitor voltage
ujp and the stored energy
Wjp are
Similarly, according to Equations (4) and (5), the lower-bridge
j-th phase capacitor voltage
ujn, and capacitor stored energy
Wjn are received. If the SM initial voltages are all the same, at the
ti moment,
SMpi conducts, and the upper-bridge output voltage is
Ui, and its variation is
Ui −
Ui−1 and remains constant. Taking a charge cycle of
SMp1 as an example, the upper bridge
j-phase output voltage
ujp varies, as shown in
Table 2.
Ideally, the SM capacitor values are equal and
SMpi conducts according to
Table 2, making the voltage changes
Ui −
Ui−1 similar. In practice, due to capacitor production error or degradation, the SM capacitor values are not identical [
27]. Suppose
SMpi is turned on according to
Table 2. In that case, the actual value for the
SMpi capacitor voltage deviates from the theoretical value, which causes the difference between the real value of the output voltage
ujp and the theoretical value, resulting in the voltage changes
Ui − Ui−1 being dissimilar to the upper-bridge
j-phase output voltage
ujp, as shown in
Figure 3.
Similarly, if the lower-bridge SM capacitor values are not similar, then they cause discrepancies between the actual and theoretical values for the lower-bridge j-phase output voltage ujn.
Combined with
Figure 2, ideally, according to Kirchhoff’s law:
The circulating current
icirj in phase
j is
Combining Equations (7) and (8),
ijp and
ijn are displayed:
The output voltage
uj in phase
j is
If the SM capacitor values are not the same, then the actual value uj deviates from the theoretical value, exacerbating uj fluctuations.
If
Uj is the
j-th phase output voltage
uj fundamental voltage rms value on the AC side, then the output voltage modulation index
m is
Then, the voltage utilization rate
n is
In operation, assuming
,
, then the output instantaneous power
pout in phase
j is
In phase
j, the interphase circulating current
icirj is
Substituting Equation (12) into (15) yields
When the SM capacitor
Ci is not equal, meaning that the equivalent capacitance decreases in each bridge, causing
Idc to increase, the circulating current
icirj in the
j-th phase is shown in
Figure 4.
From
Figure 4, we can see that the SM capacitor
Ci is not the same, causing the circulating current
icirj in the actual case to be larger than in the ideal case, making the output voltage modulation ratio
m and the DC voltage utilization
n smaller than in the ideal case.
2.2. Modulation Scheme
Currently, there are two main modulation methods for MMC: carrier pulse width and step-wave modulation. The carrier pulse width mainly compares the voltage-modulating waveform generated by the vector control link with the triangular carrier waveform to yield a modulating signal and perform the MMC triggering.
Nearest-level modulation (NLM) is commonly employed as step-wave modulation. According to the MMC’s control target, the voltage-modulated waveform is generated by using the vector control method; the number of SMs to be conducted in the upper and lower bridges is counted in real time so that the output voltage on the AC side comes close to the modulating waveform, which is often applied in flexible DC transmission projects because of its simple design, fast response, and wide range of applications. The NLM modulation diagram is shown in
Figure 5.
From
Figure 5, we can see that the step wave varies with the sinusoidal modulated wave and gradually approaches it. Each arm contains
N SMs. Each SM has a capacitor value and voltage of
C0 and
UC, respectively. For phase
j, the number of conductive SMs in the upper- and lower-bridge arms are
npj and
nnj, separately. According to the modulation strategy, the number of conductive SMs
n in each bridge meets
0 ≤
n ≤
N. Then,
npj,
nnj, satisfy the following relation:
Combined with Equation (6), the ideal value of the SM capacitor voltage
UC is
Whenever the NLM is used, the number of SMs on the upper and lower arms are
denotes the ideal modulating wave in the j-th phase at t time.
The SM capacitor voltage is positively related to its stored energy according to the bridge SM connection. We define the discharge rate
Ki of the
SMi(
i = 1, 2, 3…) as
U1i and
U0i represent the
SMi(
i = 1, 2, 3…) capacitor voltage
Ui after conduction and before the on-time, respectively;
t1i and
t0i indicate the
SMi(
i = 1, 2, 3…) after the on-time and the time before conduction, separately. For example, an MMC requires
SMi(
i = 1, 2, 3…
N) to conduct at
t0 moment, and the SM voltage is
U0 before it is on. According to the modulation principle of the NLM, the on-time is △
t. Then, ideally, the
SMi(
i = 1, 2, 3…
N) discharge diagram is shown in
Figure 6.
As seen in
Figure 6, ideally,
C1 =
C2 =
C3 = …=
CN causes the
SMi(
i = 1, 2, 3…
N) to have a matching discharge rate to
K. After modulation, the
SMi(
i = 1, 2, 3…
N) still maintains equal capacitor voltage, the same discharge power, and balanced stored energy. However, in actual engineering, the SM capacitor values are not exactly alike; for example,
C1 ≠
C2 ≠
C3 = … =
CN. At this time, according to the theoretical on-time△
t, the actual
SMi(
i = 1, 2, 3…
N) discharge schematic is shown in
Figure 7.
Comparing
Figure 6 and
Figure 7,
C1 ≠
C2 ≠
C3 = … =
CN causes the
SMi(
i = 1, 2, 3…
N) discharge rate
K1 < K3 = …
KN <
K2 in practice. If the
SMi(
i = 1, 2, 3…
N) is discharged according to the theoretically figured on-time △
t, making the
SMi(
i = 1, 2, 3…
N) capacitor voltage
U1i(
i = 1, 2, 3…
N), then the discharging power
P1i and the stored energy
W1i are not exactly alike after the on-time, triggering the
SM2 to over-discharge and vibrate. Similarly, if the
SMi(
i = 1, 2, 3…
N) is charged according to the theoretically reckoned on-time, it will induce some SMs to store energy excessively.
In engineering, the SM capacitor values C1 ≠ C2 ≠ C3 ≠ … ≠ CN prompt the SMi(i = 1, 2, 3…N) to charge and discharge at entirely different rates Ki. The SMi(i = 1, 2, 3…N) on-time theoretical time △t1i differs from the conduction △ti calculated by the NLM modulation strategy. After modulation, the SM capacitor voltage deviates from the theoretical value, resulting in unequal energy stored in the different SM capacitors, inducing some SMs to be overcharged and discharged, and reducing the SMs’ service life.