A Low-Power Continuous-Time Delta-Sigma Analogue-to-Digital Converter for the Neural Network Architecture of Battery State Estimation

Abstract

Electric vehicle systems and smart grid systems are setting stringent development targets to respond to global trends in energy saving, carbon reduction, and sustainable environmental development. In the field of batteries, there has been extensive discussion on the estimation of battery charge. In battery management systems (BMSs) and charging/discharging systems, the accuracy of the measurement of battery physical parameters is critical, as it directly affects the system, alongside the algorithm’s estimation and error correction. Therefore, this paper proposes incorporating a low-power continuous-time delta-sigma analogue-to-digital converter into a battery measurement system to support deep learning algorithms for battery state estimation. This approach aims to maintain the accuracy of battery state estimation while reducing latency and overall system power consumption. Implemented using the UMC 0.18 μm CMOS 1P6M process, the proposed design achieves a measured signal-to-noise distortion ratio (SNDR) of 78.42 dB, an effective number of bits (ENOB) of 12.73 bits, and a power consumption of approximately 15.97 μW. The chip layout area is 0.67 mm × 0.56 mm. By applying delta-sigma modulators to energy management systems, this solution aims to increase the total number of battery monitoring units while reducing overall power consumption and construction costs.

1. Introduction

Due to the recent development and evolution of electric vehicles and smart grids, the application of energy management systems has become increasingly important. The widespread adoption of electric vehicles, the expansion of charging stations, the development of renewable energy, and the continuous growth of commercial and residential energy storage systems all contribute to this trend. As the proportion of renewable energy generation in the total energy mix increases, the significance of energy storage systems also rises. Within these systems, the BMS plays a crucial role. Its primary functions are to enhance the overall efficiency of the battery pack, prevent overcharging and over-discharging, extend the overall lifespan of the battery pack, and monitor the status of the battery array.

With the increasing size of battery array systems, the number of batteries that need to be monitored is growing. Alongside this growth, the functions required by BMSs are becoming more complex, increasing the need for battery status information and analysis. Monitoring the voltage, current, and temperature of each battery, and estimating the State-Of-Charge (SOC), State-Of-Health (SOH), and State-Of-Power (SOP) of these batteries, all relatively increase the performance demands and burden on the BMS [1].

In a BMS, there are multiple mechanisms for monitoring, controlling, and protecting battery cells to prevent issues related to battery ageing or degradation, which can cause system–battery mismatch. Additionally, it aims to avoid problems associated with measurement accuracy and errors in estimating battery states.

The architecture of a BMS can be classified into three types: (a) centralised, (b) distributed, and (c) decentralised, as shown in Figure 1. In previous research and practical applications, the most common architectures have been centralised and distributed. In these architectures, the data transmission at each stage involves physical battery signals (voltage, current, temperature), which are integrated through a high-voltage multiplexer that combines the battery’s physical signals at different voltage levels. These signals are then processed by a microcontroller (MCU) to estimate the battery state. The advantage of this architecture is that the overall system hardware cost is relatively low and the communication structure is simple.

In distributed architecture, each battery module has its own monitoring and control unit and communicates with the main controller via a bus. This architecture offers better scalability, reduces the communication load between modules, and lowers the risk of single-point failures. However, with the growing application of battery arrays, especially in electric vehicles and energy storage grids, where the overall battery voltage exceeds 300 V DC, these two battery topologies become limited by their selected components and MCUs. Moreover, they do not easily facilitate the monitoring of individual battery cells.

Decentralised architecture, with its one-to-one monitoring configuration, combines the advantages of both centralised and distributed types. It distributes its monitoring and control functions across multiple modules, with each module capable of independently completing its basic functions without relying on a central controller. This architecture offers higher system stability and scalability while reducing communication bottlenecks inherent in centralised architectures. Since each module can operate independently, if one module fails, the rest of the system can continue functioning normally, thereby enhancing overall system reliability. Decentralised architecture has been proven by numerous studies to be the most effective system topology [2,3,4,5,6,7,8,9]. Therefore, this study uses the high reliability and scalability of decentralised BMS architecture to design a measurement system.

With the advancements in technology in recent years, incorporating deep learning (Deep Neural Network, DNN) algorithms into battery management systems to handle larger data computations has indirectly changed the approach to battery SOC estimation. This is achieved by utilising the features of neural network learning models through pattern recognition and time-series forecasting [10,11,12,13]. Compared to traditional SOC estimation methods based on physical parameters, which involve complex calculations and parameter estimation, machine learning methods can overcome these challenges and provide more reliable and practical solutions in real-time applications [14].

According to the simulation results based on the deep learning architecture in [15,16,17], the precision of the measurement data directly impacts hardware implementation costs and estimation accuracy. Collecting higher-precision data can lead to a more accurate estimation performance. However, collecting higher-precision data will require large amounts of memory for data storage. In addition, using high-precision data to achieve a more accurate estimation of performance will require the use of larger multipliers or adders, which means a higher hardware performance. One paper [15] compares the mean squared error (MSE) of different data precision levels, including precision after the first decimal point and precision after two to four decimal points. Although precision to one decimal place has clear advantages in terms of hardware requirements and computational speed, the difference between precision to one decimal place and two to four decimal places is noticeable. However, the difference is significantly smaller when observing the impact of precision to two or four decimal places on SOC estimation accuracy. Therefore, this paper sets the measurement precision of battery physical quantities to two decimal places.

In order to align with the evolution of energy management systems and the development of deep learning algorithms for battery state estimation, the analogue-to-digital converter (ADC) used in battery measurement has become a crucial mediator between the battery and the algorithm. This paper selects the delta-sigma modulator (DSM) as the ADC used for battery measurement. The primary advantage of the DSM is its ability to enhance the Signal-to-Noise Ratio (SNR) through noise shaping and oversampling techniques. Therefore, this paper defines the chip specifications based on the precision requirements of the deep learning algorithm and implements them through a low-power chip design.

To implement a low-power delta-sigma (ΔΣ) analogue-to-digital converter circuit, this study will design a continuous-time (CT) delta-sigma analogue-to-digital modulator for use in battery measurement systems. A single operational amplifier achieves a second-order integration effect, and the introduction of current-reusing technology can suppress flicker noise, thermal noise, and power consumption. This circuit design uses the UMC 0.18 μm CMOS 1P6M process. The supply voltage for all circuits in the system is set to 1.2 V to reduce overall power consumption. The CTDSM circuit design, with a 10 kHz bandwidth, 128× oversampling rate, and ±0.3 V input amplitude, achieved a signal-to-noise and distortion ratio (SNDR) of 78.42 dB, an effective number of bits (ENOB) of 12.73 bits, and a power consumption of approximately 15.97 μW. The chip area is 0.67 mm × 0.56 mm.

2. Delta-Sigma ADC Architecture

The delta-sigma modulator (DSM)’s architecture consists of three components: an integrator, quantiser, and digital-to-analogue converter (DAC), as shown in Figure 2. The sampling frequency is denoted as Fs. A complete ADC also requires a backend digital decimation filter to filter out high-frequency noise after shaping and to downsample the signal. This allows the analogue signal to be accurately converted into digital data [18].

There are two types of integrator: Continuous Time (CT) and Discrete Time (DT). This study implements CT circuits, which can achieve an effect equivalent to that of an anti-aliasing filter. This reduces the load on the front-end circuits in the measurement system, thereby improving overall performance. In a continuous-time system, only the quantiser requires a clock, effectively preventing the switching noise generated by the toggling of switches. Additionally, during the integration process, the integrator does not produce instantaneous large currents for capacitor charging and discharging. This significantly reduces the bandwidth and slew rate requirements of the operational amplifier (OPA), allowing the system to save considerable power consumption even under typical supply voltages.

Besides this oversampling technique, another significant feature of the delta-sigma modulator (DSM) is its ability to perform noise shaping. This ability is determined by its noise transfer function, which is the most crucial factor affecting its overall performance. A block diagram of the DSM is shown in Figure 3. When analysing at the system level, noise is generated as a quantisation error resulting from the quantiser. This error, denoted as $e_q$, is added to the output of the integrator, which is represented by the transfer function of the integrator $H$. The most important transfer functions are shown in Equations (1) and (2).

Noise Transfer Function, $NTF$:

$$NTF\equiv {\displaystyle \frac{Out}{e_q}}={\displaystyle \frac{1}{1+H}}$$

(1)

Signal Transfer Function, $STF$:

$$STF\equiv {\displaystyle \frac{Out}{In}}={\displaystyle \frac{H}{1+H}}$$

(2)

3. System Simulation and Circuit Implementation of CTDSM

Using simulation data to plan the filter architecture, transfer function, quantiser bits, and DAC architecture is particularly important for the overall stability and non-ideal factor considerations of nonlinear closed-loop DSM systems. For the design specifications of a continuous-time delta-sigma modulator aiming for low power consumption and hardware efficiency, simulation verification based on MATLAB and Simulink can effectively and accurately predict actual circuit behaviour and improve the efficiency of subsequent circuit designs.

3.1. Specification Planning of Delta-Sigma Modulator

Due to the application of the designed delta-sigma modulator in the physical quantity measurement of batteries, and in order to expand the topology of the decentralised BMS, the delta-sigma modulator is designed to be low-power and high-resolution, which can help reduce the overall power consumption of the BMS. However, in battery state estimation based on deep learning chips, the deep learning algorithm requires only two decimal places of precision for the battery’s physical quantity measurement to achieve an estimation error of less than 5% [15,16,17]. Therefore, the ENOB specification is set to 12 bits (>74 dB). According to Equations (3) and (4), to meet the low-power requirements of the modulator, the order is reduced as much as possible to minimise the use of operational amplifiers, and a 1-bit quantiser is chosen for its simplicity and the highest linearity. Hence, a second-order 128× OSR and a 1-bit quantiser are selected for the design.

$$NTF\left(Z\right)={\left(1-z^{-1}\right)}^L$$

(3)

$$SQNR=6.02N+1.76+10·log\left({\displaystyle \frac{2L+1}{{\pi }^{2L}}}\right)+10·\left(2L+1\right)$$

(4)

where $N$ represents the number of bits of the quantiser and $L$ is the order of the integrator. Quantisers with different orders are shown in Figure 4.

Since the chip designed in this paper is intended to measure battery physical quantities, the maximum signal bandwidth is set at 10 kHz. Considering that some non-ideal factors might not have been fully accounted for, the resolution is set at approximately 12 bits. Additionally, to meet the low-power requirements of the system, the supply voltage $\left({\mathrm{V}}_{\mathrm{DD}}\right)$ of the circuits used in this paper operates at 1.2 V.

Table 1. Specifications of the delta-sigma analogue-to-digital modulator.

Delta-Sigma Modulator	Specification
ENOB [bits]	>12 bits
SNDR [dB]	>74 dB
Power Consumption [μW]	<50 μW
VDD [V]	1.2 V
Input Signal [V]	0.6 ÷ 0.3 V
Signal Bandwidth [kHz]	10 kHz
Order	2
OSR	128
Quantiser bit	1
Technology	UMC 0.18 um

shows the specifications of the CTDSM proposed in this paper.

3.2. Simulink Model Development and Simulation

The ideal second-order CTDSM Simulink model is shown in Figure 5a. Figure 5b presents an integrator in the form of a second-order Biquad filter. Using this architecture model to estimate actual circuit implementation, we learn that one Opamp can be eliminated to significantly reduce the power consumption of an actual circuit with a two-stage operational amplifier (OPA).

Figure 6a shows the STF(s) of the second-order Biquad architecture, and Figure 6b shows the NTF(s) of the second-order Biquad architecture. The blue line represents the architecture with the feedforward path excluded, while the red line represents the architecture including the feedforward path for comparison. It can be observed that the architecture without the feedforward path enables the overall STF(s) to have a low-pass filtering effect. Therefore, in the case of a 10 kHz bandwidth application, this architecture can filter out the noise from the front-end input while maintaining its original NTF(s) and not affecting its noise-shaping capability.

To ensure that the integrator output swing remains within its operational range (±1 V), the coefficients are adjusted to $k_1=k_{fb}=1/8, k_2=2$. The following is the ideal second-order Biquad filter used to simulate the stability of the integrator. Figure 7 shows the output waveform of the integrator, simulated using the ideal second-order Biquad filter.

3.3. CTDSM System Circuit

The CTDSM circuit designed in this study is shown in Figure 8. The front-end Biquad filter includes passive components such as capacitors and resistors, as well as an operational amplifier (OPA), quantiser, NRZ-DAC, and D flip-flop circuits. Based on the previously mentioned considerations of non-ideal factors and the Simulink simulation verification, the specifications required for this operational amplifier can be estimated. The noise analysis determines the capacitor and resistor values of the integrator. The dimensions and specifications of the circuit are listed in

Table 2. RC component values at room temperature and standard corner.

$\mathbf{R}[\mathbf{k}\mathbf{\Omega }$]	Value	C [μF]	Value
${\mathrm{R}}_{1p,n}$	1348.22	${\mathrm{C}}_{1p,n}$	3.09
${\mathrm{R}}_{2p,n}$	94.8	${\mathrm{C}}_{2p,n}$	3.09
${\mathrm{R}}_{3p,n}$	674.11

.

3.3.1. Operational Amplifier with Current Reuse

The first stage adopts a current-reused architecture, as shown in Figure 9. The input is processed through a PMOS and an NMOS $\left(M_1,M_2 \mathrm{and} M_3,M_4\right)$, which provide nearly twice the transconductance compared to conventional architectures. These input MOSFETs are operated in the weak inversion region, enabling the achievement of sufficient transconductance $\left(g_m\right)$ to meet the bandwidth requirements of the operational amplifier (OPA) under low power consumption conditions, which are ideal for portable biomedical devices.

3.3.2. First Stage Common-Mode Feedback Circuit $\left({\mathrm{CMFB}}_1\right)$

The circuit architecture of the first stage of the common-mode feedback (CMFB) of the OPA is shown in Figure 10. In this architecture, $M_5$ and $M_6$ form a self-biasing feedback circuit, and the $V_{gs}$ of these two transistors is used to determine the common-mode level at the output. Since the currents flowing through $M_5$ and $M_6$ are known, the common-mode level can be determined by the size of $M_5$ and $M_6$ based on the transistor current formula. In this design, the common-mode level is set slightly below half of the $V_{DD}$. This is to ensure that the transistors responsible for transconductance in the second stage have a lower gate voltage $V_{gs}$, resulting in a lower $V_{gs}$ and hence a smaller $V_{ov}$. This leads to a higher $g_m$ value. This adjustment has a significant effect on shifting the second pole to higher frequencies.

3.3.3. Second Stage Common-Mode Feedback Circuit $\left({\mathrm{CMFB}}_2\right)$

The Resistor-Averaged method is used in this study, as shown in Figure 11. This method uses two resistors of the same size to detect the current’s common-mode level and compares it with an externally provided common-mode voltage using a differential amplifier. The advantage of this detection method is that it can withstand the larger output swing of the OPA. However, care must be taken regarding the loading effect, so the resistance values should not be too small. These resistors, along with the parasitic capacitance of the differential pair, form a pole. Therefore, a larger capacitor needs to be placed in parallel with these resistors to eliminate the effect of this parasitic capacitance, as shown in Equation (5).

$$\begin{gathered} {\mathrm{V}}_{\mathrm{O},\mathrm{CM}}=\left({\mathrm{V}}_{\mathrm{op}}+{\mathrm{V}}_{\mathrm{on}}\right){\displaystyle \frac{1+s{C}_{CM}{R}_{CM}}{2+s\left(2C_{CM}+C_{para}\right)R_{CM}}}, \\ if2C_{CM}\gg C_{para}\Rightarrow {\mathrm{V}}_{\mathrm{O},\mathrm{CM}}={\displaystyle \frac{\left({\mathrm{V}}_{\mathrm{op}}+{\mathrm{V}}_{\mathrm{on}}\right)}{2}} \end{gathered}$$

(5)

3.3.4. Simulation Results of the Operational Amplifier

To fully consider the impact of the system load on the operational amplifier, the system circuit is disconnected from the input end of the OPA, and a differential sine wave is then input. The open-loop small-signal analysis of the operational amplifier is shown in Figure 12. The system’s frequency response (all corners + temperature range 0~100 °C) is shown in Figure 13a,b.

The frequency responses at points A and B in Figure 12 are shown in Figure 13a,b, respectively.

3.3.5. Quantiser and 1-Bit NRZ DAC

The comparator circuit used in this study is shown in Figure 14a. Since the delta-sigma modulator in this circuit employs a one-bit quantiser, non-ideal effects such as resolution and offset have minimal impact. A transient simulation of the comparator circuit is shown in Figure 14b. Therefore, a simple comparator circuit is sufficient here, without the need for a pre-amplifier, which also saves the power consumption of an additional OPA component.

The one-bit digital-to-analogue converter (DAC) is shown in Figure 15. This circuit is implemented using a simple CMOS transmission gate. The values of $Q$ and $Q_b$ determine whether $V_{refp}$ or $V_{refn}$ is fed back to the integrator for addition or subtraction.

4. System Simulation and Layout

4.1. System Simulation

The system simulations of the CTDSM under various conditions, including both pre-simulation and post-simulation analyses, are shown in Figure 16, Figure 17 and Figure 18 for all corners (MOSFET variations, TT), Temp. 0~100 °C, V_DD ± 10%, and over a dynamic range.

4.2. Layout

The circuit layout of the CTDSM system is shown in Figure 19a, and the relative placement of each subsystem circuit is shown in Figure 19b.

4.3. Measurement Results

During measurement, the analogue ground and digital ground are separated and connected using a ferrite bead, effectively filtering out high-frequency coupling noise. Additionally, two sets of LDOs are used to supply the analogue $V_{DD}$ and digital $V_{DD}$ separately, aiming to minimise coupled noise, as shown in Figure 20a. Figure 20b shows the distribution of each component and bias in the chip measurement circuit. The left side represents the analogue section, while the right side represents the digital section. Each bias passes through a filter slot to suppress noise, and there is a circuit in the middle that provides the DC level for the input sine wave signal.

The measurement results are close to the post-simulation results. The overall system measurement of the SNDR is shown in Figure 21a, and the overall system measurement of the dynamic range is shown in Figure 21b, with a measured performance of approximately 12.73 bits. A comparison of the measurement results with the simulation results is shown in

Table 3. Comparison of measurement results with specifications and pre-layout and post-layout simulations.

	Specification.	Pre-Simulation	Post-Simulation	Measurement
Process Technology	UMC 0.18 um
Supply Voltage MI	1.2
Bandwidth [Hz]	10 k
Input Amplitude [V]	0.3
SNDR [dB]	74 @TT-Corner	82.75	81.15	78.42
Resolution [bits]	12 @TT-Corner	13.45	13.18	12.73
Dynamic Range [dB]	As large as possible	86	84	84
Power [μW]	<50 @2.56MHz	22.24	22.76	15.97
FOM 1 [pJ/conv.]	As small as possible	0.0994	0.1226	0.1175
FOM 2 [dB]	As large as possible	172.53	170.43	171.97

.

4.4. Literature Comparison

For decentralised BMSs, enhancing the scalability of the BMS is crucial, and low-power planning is an indispensable aspect of this process. In this study, two figures of merit (FOM) are used for comparison. The reference formulas for the system power consumption comparison are shown in Equations (6) and (7), where $Power\left(W\right)$ represents the power consumption of the circuit, ENOB is the effective number of bits, $f_B\left(Hz\right)$ is the signal bandwidth, and $DR\left(dB\right)$ is the dynamic range. A comparison with previous studies [19,20,21,22,23,24,25,26] is shown in

Table 4. Comparison with DSMs of a similar bandwidth in the literature.

Ref.	[19]	[20]	[21]	[22]	[23]	[24]	[25]	[26]	This Work
Type	DT	SI-DT	CT	DI-DT	CT	DT	CT	ADSM	CT
OSR	100	128	80	64	128	256	256	128	128
SNDR [dB]	84	71.9	64	80.4	95.2	89	80	92	78.42
ENOB [bits]	13.66	11.65	10.34	13.06	15.52	12.73	10	15	12.73
BW [HZ]	20k	10k	2k	10k	25k	10k	1	10k	10k
Power [μW]	860	12,100	96	24.8	800	670	15	290	15.97
VDD	1	3.3	1.6	1.0	1.0	1.8-5	1.2	1	1.2
Process [um]	0.18	0.35	0.15	0.065	0.065	0.18	0.065	0.18	0.18
FOM 1 [pJ/conv.]	1.66	188.26	18.53	0.145	0.34	4.93	1155.26	0.45	0.1175
FOM 2 [dB]	157.67	141.17	137.19	167.56	177.9	165.54	153.24	187	171.97
Publication	IEDE Trans. Circuit sys.	IEEE Trans. On Power Electronics	IEEE Trans. Circuit sys.	IEEE Trans. Instrum. Meas.	IEDE JSSC	IEEE ASSCC	IEEE Access	MDP Sensors	Measurement

. By comparing FOM1 and FOM2, this study demonstrates a superior power consumption performance compared to papers with similar signal bandwidths [20,22,24]. When compared to paper [25], which has similar power consumption, this study shows a wider range in terms of its system operating signal bandwidth and ENOB.

$$FOM1={\displaystyle \frac{Power\left(W\right)\ast {10}^{12}}{2^{\frac{SNR\left(dB\right)-1.76}{6.02}}\ast 2\ast f_B\left(Hz\right)}} pJ/Conv.$$

(6)

$$FOM2=DR\left(dB\right)+10\ast lo{g}_{10}\left({\displaystyle \frac{f_B\left(Hz\right)}{POWER\left(W\right)}}\right)$$

(7)

5. Conclusions

The implemented CTDSM measurement chip achieved an SNDR of 78.42 dB, an ENOB of 12.73, and a power consumption of approximately 15.97 μW, with an overall chip area of 0.67 mm × 0.56 mm. The low-power chip design in this study demonstrates higher energy efficiency in terms of power consumption while also meeting the accuracy requirements of a deep learning algorithm for battery state estimation. When applied to the measurement of battery physical quantities at each node in a decentralised large-battery-array BMS, it can reduce the overall power consumption of the BMS, highlighting the importance of low-power chip designs in decentralised systems. Additionally, this design can alleviate the computational burden of tracking the state estimation of individual batteries in the BMS, effectively enhancing the scalability benefits of decentralised battery management units.