82 TRI = MF->getSubtarget().getRegisterInfo();
83 MRI = &MF->getRegInfo();
84 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
85 TII = MF->getSubtarget().getInstrInfo();
101 : MCID(&TID), NumOperands(0), Flags(0), AsmPrinterFlags(0),
102 DbgLoc(
std::
move(
DL)), DebugInstrNum(0), Opcode(TID.Opcode) {
108 CapOperands = OperandCapacity::get(NumOps);
120 : MCID(&
MI.
getDesc()), NumOperands(0),
Flags(0), AsmPrinterFlags(0),
125 CapOperands = OperandCapacity::get(
MI.getNumOperands());
137 NewMO.TiedTo = OrigMO.TiedTo;
173 MRI.removeRegOperandFromUseList(&MO);
179 MRI.addRegOperandToUseList(&MO);
184 assert(
MBB &&
"Use MachineInstrBuilder to add operands to dangling instrs");
186 assert(MF &&
"Use MachineInstrBuilder to add operands to dangling instrs");
195 return MRI->moveOperands(Dst, Src, NumOps);
197 assert(Dst && Src &&
"Unknown operands");
206 assert(isUInt<LLVM_MI_NUMOPERANDS_BITS>(NumOperands + 1) &&
207 "Cannot add more operands.");
208 assert(MCID &&
"Cannot add operands before providing an instr descriptor");
211 if (&
Op >= Operands && &
Op < Operands + NumOperands) {
227 bool isImpReg =
Op.isReg() &&
Op.isImplicit();
229 while (OpNo && Operands[OpNo-1].
isReg() && Operands[OpNo-1].isImplicit()) {
231 assert(!Operands[OpNo].isTied() &&
"Cannot move tied operands");
242 OperandCapacity OldCap = CapOperands;
245 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
253 if (OpNo != NumOperands)
254 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
259 if (OldOperands != Operands && OldOperands)
264 NewMO->ParentMI =
this;
267 if (NewMO->
isReg()) {
269 NewMO->Contents.Reg.Prev =
nullptr;
274 MRI->addRegOperandToUseList(NewMO);
280 if (NewMO->
isUse()) {
302 if (Operands[i].
isReg())
303 assert(!Operands[i].isTied() &&
"Cannot move tied operands");
308 MRI->removeRegOperandFromUseList(Operands + OpNo);
314 if (
unsigned N = NumOperands - 1 - OpNo)
325 bool HasPreInstrSymbol = PreInstrSymbol !=
nullptr;
326 bool HasPostInstrSymbol = PostInstrSymbol !=
nullptr;
327 bool HasHeapAllocMarker = HeapAllocMarker !=
nullptr;
328 bool HasPCSections = PCSections !=
nullptr;
329 bool HasCFIType = CFIType != 0;
330 bool HasMMRAs = MMRAs !=
nullptr;
331 int NumPointers = MMOs.
size() + HasPreInstrSymbol + HasPostInstrSymbol +
332 HasHeapAllocMarker + HasPCSections + HasCFIType + HasMMRAs;
335 if (NumPointers <= 0) {
344 else if (NumPointers > 1 || HasMMRAs || HasHeapAllocMarker || HasPCSections ||
346 Info.set<EIIK_OutOfLine>(
348 HeapAllocMarker, PCSections, CFIType, MMRAs));
353 if (HasPreInstrSymbol)
354 Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
355 else if (HasPostInstrSymbol)
356 Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
358 Info.set<EIIK_MMO>(MMOs[0]);
396 "Invalid machine functions when cloning memory refrences!");
404 MI.getMMRAMetadata()) {
417 if (
LHS.size() !=
RHS.size())
422 return std::equal(LHSPointees.begin(), LHSPointees.end(),
423 RHSPointees.begin());
433 if (MIs.
size() == 1) {
449 "Invalid machine functions when cloning memory references!");
454 "Invalid machine functions when cloning memory references!");
465 if (
MI.memoperands_empty()) {
471 MergedMMOs.
append(
MI.memoperands_begin(),
MI.memoperands_end());
483 if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
499 if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
553 "Invalid machine functions when cloning instruction symbols!");
572 dyn_cast<OverflowingBinaryOperator>(&
I)) {
573 if (OB->hasNoSignedWrap())
575 if (OB->hasNoUnsignedWrap())
577 }
else if (
const TruncInst *TI = dyn_cast<TruncInst>(&
I)) {
578 if (TI->hasNoSignedWrap())
580 if (TI->hasNoUnsignedWrap())
583 if (
GEP->hasNoUnsignedSignedWrap())
585 if (
GEP->hasNoUnsignedWrap())
591 if (PNI->hasNonNeg())
595 dyn_cast<PossiblyDisjointInst>(&
I)) {
596 if (PD->isDisjoint())
601 if (
const ICmpInst *ICmp = dyn_cast<ICmpInst>(&
I))
602 if (ICmp->hasSameSign())
617 if (Flags.noSignedZeros())
619 if (Flags.allowReciprocal())
621 if (Flags.allowContract())
623 if (Flags.approxFunc())
625 if (Flags.allowReassoc())
629 if (
I.getMetadata(LLVMContext::MD_unpredictable))
639bool MachineInstr::hasPropertyInBundle(
uint64_t Mask, QueryType
Type)
const {
642 if (MII->getDesc().getFlags() & Mask) {
650 if (!MII->isBundledWithSucc())
667 assert(
Other.isBundle() &&
"Expected that both instructions are bundles.");
672 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
675 if (!I1->isIdenticalTo(*I2,
Check))
680 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
748 Other.getDebugExpression(),
Other.isIndirectDebugValue()))
781 case TargetOpcode::PATCHPOINT:
782 case TargetOpcode::STACKMAP:
783 case TargetOpcode::STATEPOINT:
784 case TargetOpcode::FENTRY_CALL:
834 assert(!Pred->isBundledWithSucc() &&
"Inconsistent bundle flags");
843 assert(!Succ->isBundledWithPred() &&
"Inconsistent bundle flags");
852 assert(Pred->isBundledWithSucc() &&
"Inconsistent bundle flags");
861 assert(Succ->isBundledWithPred() &&
"Inconsistent bundle flags");
881 unsigned *GroupNo)
const {
898 NumOps = 1 +
F.getNumOperandRegisters();
899 if (i + NumOps > OpIdx) {
911 return cast<DILabel>(
getOperand(0).getMetadata());
955 assert(
getMF() &&
"Can't have an MF reference here!");
977 if ((
F.isRegUseKind() ||
F.isRegDefKind() ||
F.isRegDefEarlyClobberKind()) &&
978 F.hasRegClassConstraint(RCID))
979 return TRI->getRegClass(RCID);
983 return TRI->getPointerRegClass(MF);
996 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
997 OpndIt.getOperandNo(), Reg, CurRC,
TII,
TRI);
1000 for (
unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
1001 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC,
TII,
TRI);
1008 assert(CurRC &&
"Invalid initial register class");
1023 "Cannot get register constraints for non-register operand");
1024 assert(CurRC &&
"Invalid initial register class");
1027 CurRC =
TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
1029 CurRC =
TRI->getSubClassWithSubReg(CurRC, SubIdx);
1031 CurRC =
TRI->getCommonSubClass(CurRC, OpRC);
1040 while (
I->isBundledWithSucc()) {
1062 bool isKill)
const {
1070 if (MOReg == Reg || (
TRI && Reg && MOReg &&
TRI->regsOverlap(MOReg, Reg)))
1083 bool PartDef =
false;
1084 bool FullDef =
false;
1102 return std::make_pair(
Use || (PartDef && !FullDef), PartDef || FullDef);
1111 bool isDead,
bool Overlap)
const {
1112 bool isPhys = Reg.isPhysical();
1122 bool Found = (MOReg == Reg);
1125 Found =
TRI->regsOverlap(MOReg, Reg);
1127 Found =
TRI->isSubRegister(MOReg, Reg);
1146 if (MCID.
operands()[i].isPredicate())
1171 assert(DefMO.
isDef() &&
"DefIdx must be a def operand");
1172 assert(UseMO.
isUse() &&
"UseIdx must be a use operand");
1173 assert(!DefMO.
isTied() &&
"Def is already tied to another use");
1174 assert(!UseMO.
isTied() &&
"Use is already tied to another def");
1177 UseMO.TiedTo = DefIdx + 1;
1184 "DefIdx out of range");
1189 DefMO.TiedTo = std::min(UseIdx + 1,
TiedMax);
1201 return MO.TiedTo - 1;
1211 if (UseMO.
isReg() && UseMO.
isUse() && UseMO.TiedTo == OpIdx + 1)
1217 if (
getOpcode() == TargetOpcode::STATEPOINT) {
1222 assert(CurUseIdx != -1U &&
"only gc pointer statepoint operands can be tied");
1224 for (
unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {
1227 if (OpIdx == CurDefIdx)
1229 if (OpIdx == CurUseIdx)
1239 unsigned OpIdxGroup = ~0u;
1244 assert(FlagMO.
isImm() &&
"Invalid tied operand on inline asm");
1245 unsigned CurGroup = GroupIdx.
size();
1248 NumOps = 1 +
F.getNumOperandRegisters();
1250 if (OpIdx > i && OpIdx < i + NumOps)
1251 OpIdxGroup = CurGroup;
1253 if (!
F.isUseOperandTiedToDef(TiedGroup))
1257 unsigned Delta = i - GroupIdx[TiedGroup];
1260 if (OpIdxGroup == CurGroup)
1261 return OpIdx - Delta;
1264 if (OpIdxGroup == TiedGroup)
1265 return OpIdx + Delta;
1284 ToReg = RegInfo.
getSubReg(ToReg, SubIdx);
1335 if (
getOpcode() == TargetOpcode::LOCAL_ESCAPE)
1350 bool SawStore =
false;
1361 if (Reg.isPhysical()) {
1410 int64_t MinOffset = std::min(OffsetA, OffsetB);
1414 bool KnownWidthA = WidthA.
hasValue();
1415 bool KnownWidthB = WidthB.
hasValue();
1420 bool SameVal = (ValA && ValB && (ValA == ValB));
1424 if (PSVa && ValB && !PSVa->
mayAlias(&MFI))
1426 if (PSVb && ValA && !PSVb->
mayAlias(&MFI))
1428 if (PSVa && PSVb && (PSVa == PSVb))
1432 if (SameVal && BothMMONonScalable) {
1433 if (!KnownWidthA || !KnownWidthB)
1435 int64_t MaxOffset = std::max(OffsetA, OffsetB);
1436 int64_t LowWidth = (MinOffset == OffsetA)
1439 return (MinOffset + LowWidth > MaxOffset);
1448 assert((OffsetA >= 0) &&
"Negative MachineMemOperand offset");
1449 assert((OffsetB >= 0) &&
"Negative MachineMemOperand offset");
1507 if (NumChecks >
TII->getMemOperandAACheckLimit())
1513 for (
auto *MMOb :
Other.memoperands())
1568 if (!MMO->isUnordered())
1573 if (MMO->isStore())
return false;
1574 if (MMO->isInvariant() && MMO->isDereferenceable())
1579 if (PSV->isConstant(&MFI))
1595 "It's illegal to have a PHI without source operands");
1655 if (MCID.
Opcode == TargetOpcode::STATEPOINT)
1659 if (!Operand.isReg() || Operand.isDef())
1664 if (ExpectedTiedIdx != TiedIdx)
1677 return MRI.getType(
Op.getReg());
1680 if (!OpInfo.isGenericType())
1681 return MRI.getType(
Op.getReg());
1683 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1686 LLT TypeToPrint =
MRI.getType(
Op.getReg());
1690 PrintedTypes.
set(OpInfo.getGenericTypeIndex());
1694#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1703 if (
Depth >= MaxDepth)
1705 if (!AlreadySeenInstrs.
insert(
this).second)
1716 if (Reg.isPhysical())
1719 if (NewMI ==
nullptr)
1721 NewMI->dumprImpl(
MRI,
Depth + 1, MaxDepth, AlreadySeenInstrs);
1726 unsigned MaxDepth)
const {
1728 dumprImpl(
MRI, 0, MaxDepth, AlreadySeenInstrs);
1733 bool SkipDebugLoc,
bool AddNewLine,
1735 const Module *M =
nullptr;
1747 print(
OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine,
TII);
1751 bool IsStandalone,
bool SkipOpers,
bool SkipDebugLoc,
1764 auto getTiedOperandIdx = [&](
unsigned OpIdx) {
1765 if (!ShouldPrintRegisterTies)
1772 unsigned StartOp = 0;
1776 while (StartOp < e) {
1785 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1786 MO.
print(
OS, MST, TypeToPrint, StartOp,
false, IsStandalone,
1787 ShouldPrintRegisterTies, TiedOperandIdx,
TRI, IntrinsicInfo);
1795 OS <<
"frame-setup ";
1797 OS <<
"frame-destroy ";
1819 OS <<
"nofpexcept ";
1839 bool FirstOp =
true;
1840 unsigned AsmDescOp = ~0u;
1841 unsigned AsmOpCount = 0;
1848 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1850 ShouldPrintRegisterTies, TiedOperandIdx,
TRI,
1856 OS <<
" [sideeffect]";
1860 OS <<
" [maystore]";
1862 OS <<
" [isconvergent]";
1864 OS <<
" [alignstack]";
1866 OS <<
" [attdialect]";
1868 OS <<
" [inteldialect]";
1877 if (FirstOp) FirstOp =
false;
else OS <<
",";
1882 auto *DIV = dyn_cast<DILocalVariable>(MO.
getMetadata());
1883 if (DIV && !DIV->getName().empty())
1884 OS <<
"!\"" << DIV->getName() <<
'\"';
1887 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1888 MO.
print(
OS, MST, TypeToPrint, i,
true, IsStandalone,
1889 ShouldPrintRegisterTies, TiedOperandIdx,
TRI, IntrinsicInfo);
1894 if (DIL && !DIL->getName().empty())
1895 OS <<
"\"" << DIL->getName() <<
'\"';
1898 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1899 MO.
print(
OS, MST, TypeToPrint, i,
true, IsStandalone,
1900 ShouldPrintRegisterTies, TiedOperandIdx,
TRI, IntrinsicInfo);
1902 }
else if (i == AsmDescOp && MO.
isImm()) {
1904 OS <<
'$' << AsmOpCount++;
1905 unsigned Flag = MO.
getImm();
1908 OS <<
F.getKindName();
1911 if (!
F.isImmKind() && !
F.isMemKind() &&
F.hasRegClassConstraint(RCID)) {
1913 OS <<
':' <<
TRI->getRegClassName(
TRI->getRegClass(RCID));
1915 OS <<
":RC" << RCID;
1918 if (
F.isMemKind()) {
1924 if (
F.isUseOperandTiedToDef(TiedTo))
1925 OS <<
" tiedto:$" << TiedTo;
1927 if ((
F.isRegDefKind() ||
F.isRegDefEarlyClobberKind() ||
1928 F.isRegUseKind()) &&
1929 F.getRegMayBeFolded()) {
1936 AsmDescOp += 1 +
F.getNumOperandRegisters();
1939 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1943 MO.
print(
OS, MST, TypeToPrint, i,
true, IsStandalone,
1944 ShouldPrintRegisterTies, TiedOperandIdx,
TRI, IntrinsicInfo);
1955 OS <<
" pre-instr-symbol ";
1963 OS <<
" post-instr-symbol ";
1971 OS <<
" heap-alloc-marker ";
1979 OS <<
" pcsections ";
1988 MMRA->printAsOperand(
OS, MST);
1993 OS <<
" cfi-type " << CFIType;
1996 if (DebugInstrNum) {
1999 OS <<
" debug-instr-number " << DebugInstrNum;
2002 if (!SkipDebugLoc) {
2006 OS <<
" debug-location ";
2014 std::unique_ptr<LLVMContext> CtxPtr;
2020 CtxPtr = std::make_unique<LLVMContext>();
2021 Context = CtxPtr.get();
2025 bool NeedComma =
false;
2037 bool HaveSemi =
false;
2059 OS <<
" line no:" << DV->getLine();
2072 bool AddIfNotFound) {
2074 bool hasAliases = isPhysReg &&
2093 if (Reg == IncomingReg) {
2104 }
else if (hasAliases && MO.
isKill() && Reg.isPhysical()) {
2114 while (!DeadOps.
empty()) {
2115 unsigned OpIdx = DeadOps.
back();
2126 if (!Found && AddIfNotFound) {
2138 if (!Reg.isPhysical())
2144 if ((RegInfo && RegInfo->
regsOverlap(Reg, OpReg)) || Reg == OpReg)
2151 bool AddIfNotFound) {
2152 bool isPhysReg = Reg.isPhysical();
2153 bool hasAliases = isPhysReg &&
2178 while (!DeadOps.
empty()) {
2179 unsigned OpIdx = DeadOps.
back();
2190 if (Found || !AddIfNotFound)
2215 if (Reg.isPhysical()) {
2232 bool HasRegMask =
false;
2240 if (!Reg.isPhysical())
2251 for (
const Register &UsedReg : UsedRegs)
2259 HashComponents.
reserve(
MI->getNumOperands() + 1);
2272 const MDNode *LocMD =
nullptr;
2277 if (mdconst::hasa<ConstantInt>(LocMD->
getOperand(0)))
2290 ? mdconst::extract<ConstantInt>(LocMD->
getOperand(0))->getZExtValue()
2306 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
2307 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
2308 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
DL) &&
2309 "Expected inlined-at fields to agree");
2322 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
2323 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
2324 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
DL) &&
2325 "Expected inlined-at fields to agree");
2326 if (MCID.
Opcode == TargetOpcode::DBG_VALUE) {
2328 "DBG_VALUE must contain exactly one debug operand");
2330 if (DebugOp.
isReg())
2343 MIB.addMetadata(Variable).addMetadata(Expr);
2345 if (DebugOp.isReg())
2346 MIB.addReg(DebugOp.getReg());
2371 BuildMI(MF,
DL, MCID, IsIndirect, DebugOps, Variable, Expr);
2381 assert(
MI.getDebugVariable()->isValidLocationForIntrinsic(
MI.getDebugLoc()) &&
2382 "Expected inlined-at fields to agree");
2385 if (
MI.isIndirectDebugValue()) {
2386 assert(
MI.getDebugOffset().getImm() == 0 &&
2387 "DBG_VALUE with nonzero offset");
2389 }
else if (
MI.isDebugValueList()) {
2392 std::array<uint64_t, 1> Ops{{dwarf::DW_OP_deref}};
2394 unsigned OpIdx =
MI.getDebugOperandIndex(
Op);
2402 assert(
MI.hasDebugOperandForReg(SpillReg) &&
"Spill Reg is not used in MI.");
2412 int FrameIndex,
Register SpillReg) {
2414 "DBG_INSTR_REF should not reference a virtual register.");
2425 if (
Op.isReg() &&
Op.getReg() == SpillReg)
2460 Op.ChangeToFrameIndex(FrameIndex);
2467 if (!
MI.getOperand(0).isReg())
2473 if (!DI->isDebugValue())
2475 if (DI->hasDebugOperandForReg(
MI.getOperand(0).getReg()))
2488 auto *
MRI = getRegInfo();
2489 for (
auto &MO :
MRI->use_operands(DefReg)) {
2491 if (!DI->isDebugValue())
2493 if (DI->hasDebugOperandForReg(DefReg)) {
2499 for (
auto *DBI : DbgValues)
2509 for (
const auto *
A : Accesses) {
2511 cast<FixedStackPseudoSourceValue>(
A->getPseudoValue())
2512 ->getFrameIndex())) {
2522std::optional<LocationSize>
2525 if (
TII->isStoreToStackSlotPostFE(*
this, FI)) {
2530 return std::nullopt;
2533std::optional<LocationSize>
2538 return std::nullopt;
2541std::optional<LocationSize>
2544 if (
TII->isLoadFromStackSlotPostFE(*
this, FI)) {
2549 return std::nullopt;
2552std::optional<LocationSize>
2557 return std::nullopt;
2561 if (DebugInstrNum == 0)
2563 return DebugInstrNum;
2567 if (DebugInstrNum == 0)
2569 return DebugInstrNum;
2598std::tuple<Register, LLT, Register, LLT>
2602 return std::tuple(Reg0, getRegInfo()->
getType(Reg0), Reg1,
2606std::tuple<Register, LLT, Register, LLT, Register, LLT>
2611 return std::tuple(Reg0, getRegInfo()->
getType(Reg0), Reg1,
2612 getRegInfo()->
getType(Reg1), Reg2,
2616std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT>
2623 Reg0, getRegInfo()->
getType(Reg0), Reg1, getRegInfo()->
getType(Reg1),
2624 Reg2, getRegInfo()->
getType(Reg2), Reg3, getRegInfo()->
getType(Reg3));
2636 Reg0, getRegInfo()->
getType(Reg0), Reg1, getRegInfo()->
getType(Reg1),
2637 Reg2, getRegInfo()->
getType(Reg2), Reg3, getRegInfo()->
getType(Reg3),
2638 Reg4, getRegInfo()->
getType(Reg4));
2643 assert(InsertBefore !=
nullptr &&
"invalid iterator");
2645 "iterator points to operand of other inst");
2655 TiedOpIndices[OpNo] = TiedTo;
2662 unsigned OpsToMove = NumOperands - OpIdx;
2667 for (
unsigned I = 0;
I < OpsToMove; ++
I) {
2677 for (
auto [Tie1, Tie2] : TiedOpIndices) {
2687 assert(OpId &&
"expected non-zero operand id");
2698 if (
F.isRegUseKind() ||
F.isRegDefKind() ||
F.isRegDefEarlyClobberKind())
2699 return F.getRegMayBeFolded();
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Analysis containing CSE Info
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const HexagonInstrInfo * TII
Module.h This file contains the declarations for the Module class.
Implement a low-level type suitable for MachineInstr level instruction selection.
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
static void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI)
Move NumOps MachineOperands from Src to Dst, with support for overlapping ranges.
static LocationSize getSpillSlotSize(const MMOList &Accesses, const MachineFrameInfo &MFI)
static const DIExpression * computeExprForSpill(const MachineInstr &MI, const SmallVectorImpl< const MachineOperand * > &SpilledOperands)
Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, BatchAAResults *AA, bool UseTBAA, const MachineMemOperand *MMOa, const MachineMemOperand *MMOb)
static void tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetIntrinsicInfo *&IntrinsicInfo, const TargetInstrInfo *&TII)
static const MachineFunction * getMFIfAvailable(const MachineInstr &MI)
static bool hasIdenticalMMOs(ArrayRef< MachineMemOperand * > LHS, ArrayRef< MachineMemOperand * > RHS)
Check to see if the MMOs pointed to by the two MemRefs arrays are identical.
unsigned const TargetRegisterInfo * TRI
This file provides utility analysis objects describing memory locations.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static bool isReg(const MCInst &MI, unsigned OpNo)
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
This file implements the SmallBitVector class.
This file defines the SmallVector class.
static SymbolRef::Type getType(const Symbol *Sym)
static std::optional< unsigned > getOpcode(ArrayRef< VPValue * > Values)
Returns the opcode of Values or ~0 if they do not all agree.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
This class is a wrapper over an AAResults, and it is intended to be used only when there are no IR ch...
bool isNoAlias(const MemoryLocation &LocA, const MemoryLocation &LocB)
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
bool isEntryValue() const
Check if the expression consists of exactly one entry value operand.
static bool isEqualExpression(const DIExpression *FirstExpr, bool FirstIndirect, const DIExpression *SecondExpr, bool SecondIndirect)
Determines whether two debug values should produce equivalent DWARF expressions, using their DIExpres...
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
This class represents an Operation in the Expression.
bool print(raw_ostream &OS, DIDumpOptions DumpOpts, const DWARFExpression *Expr, DWARFUnit *U) const
bool hasTrivialDestructor() const
Check whether this has a trivial destructor.
Diagnostic information for inline asm reporting.
Utility class for floating point operations which can have information about relaxed accuracy require...
Convenience struct for specifying and reasoning about fast-math flags.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
an instruction for type-safe pointer arithmetic to access elements of arrays and structs
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots.
This instruction compares its operands according to the predicate given to the constructor.
static StringRef getMemConstraintName(ConstraintCode C)
constexpr bool isValid() const
This is an important class for using LLVM in a threaded context.
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
A set of physical registers with utility functions to track liveness when walking backward/forward th...
bool available(const MachineRegisterInfo &MRI, MCPhysReg Reg) const
Returns true if register Reg and no aliasing register is in the set.
A set of register units used to track register liveness.
static LocationSize precise(uint64_t Value)
static constexpr LocationSize beforeOrAfterPointer()
Any location before or after the base pointer (but still within the underlying object).
TypeSize getValue() const
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
ArrayRef< MCPhysReg > implicit_defs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
ArrayRef< MCPhysReg > implicit_uses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
MCRegAliasIterator enumerates all registers aliasing Reg.
bool isSubRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA.
bool isSuperRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA.
Wrapper class representing physical registers. Should be passed by value.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
const MDOperand & getOperand(unsigned I) const
unsigned getNumOperands() const
Return number of MDNode operands.
bool isValid() const
isValid - Returns true until all the operands have been visited.
MachineInstr * remove_instr(MachineInstr *I)
Remove the possibly bundled instruction from the instruction list without deleting it.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
instr_iterator erase_instr(MachineInstr *I)
Remove an instruction from the instruction list and delete it.
void printAsOperand(raw_ostream &OS, bool PrintType=true) const
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
void print(raw_ostream &OS, const SlotIndexes *=nullptr, bool IsStandalone=true) const
Instructions::iterator instr_iterator
Instructions::const_iterator const_instr_iterator
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
MachineInstr::ExtraInfo * createMIExtraInfo(ArrayRef< MachineMemOperand * > MMOs, MCSymbol *PreInstrSymbol=nullptr, MCSymbol *PostInstrSymbol=nullptr, MDNode *HeapAllocMarker=nullptr, MDNode *PCSections=nullptr, uint32_t CFIType=0, MDNode *MMRAs=nullptr)
Allocate and construct an extra info structure for a MachineInstr.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
unsigned getNewDebugInstrNum()
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void deallocateOperandArray(OperandCapacity Cap, MachineOperand *Array)
Dellocate an array of MachineOperands and recycle the memory.
MachineOperand * allocateOperandArray(OperandCapacity Cap)
Allocate an array of MachineOperands.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void handleChangeDesc(MachineInstr &MI, const MCInstrDesc &TID)
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForReg(Instruction *MI, Register Reg)
Returns a range of all of the operands that correspond to a debug use of Reg.
bool isDebugValueList() const
void bundleWithPred()
Bundle this instruction with its predecessor.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst5RegLLTs() const
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
void setCFIType(MachineFunction &MF, uint32_t Type)
Set the CFI type for the instruction.
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
iterator_range< mop_iterator > debug_operands()
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
const MachineBasicBlock * getParent() const
MDNode * getMMRAMetadata() const
Helper to extract mmra.op metadata.
void bundleWithSucc()
Bundle this instruction with its successor.
uint32_t getCFIType() const
Helper to extract a CFI type hash if one has been added.
bool isDebugLabel() const
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
bool isDereferenceableInvariantLoad() const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
void setFlags(unsigned flags)
QueryType
API for querying MachineInstr properties.
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
std::tuple< LLT, LLT, LLT, LLT, LLT > getFirst5LLTs() const
bool isCall(QueryType Type=AnyInBundle) const
std::tuple< Register, LLT, Register, LLT, Register, LLT > getFirst3RegLLTs() const
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
uint32_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
const MachineOperand & getDebugExpressionOp() const
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
Register isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
bool allImplicitDefsAreDead() const
Return true if all the implicit defs of this instruction are dead.
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's memory reference descriptor list and replace ours with it.
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
bool isSafeToMove(bool &SawStore) const
Return true if it is safe to move this instruction.
bool mayAlias(BatchAAResults *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction's memory access aliases the memory access of Other.
bool isDebugInstr() const
unsigned getNumDebugOperands() const
Returns the total number of operands which are debug locations.
unsigned getNumOperands() const
Retuns the total number of operands.
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const
Print on dbgs() the current instruction and the instructions defining its operands and so on until we...
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
bool isDebugValueLike() const
bool memoperands_empty() const
Return true if we don't have any memory operands which described the memory access done by this instr...
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)
Scan instructions immediately following MI and collect any matching DBG_VALUEs.
std::optional< LocationSize > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
bool wouldBeTriviallyDead() const
Return true if this instruction would be trivially dead if all of its defined registers were dead.
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
std::tuple< LLT, LLT > getFirst2LLTs() const
std::optional< LocationSize > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
void unbundleFromPred()
Break bundle above this instruction.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
bool isStackAligningInlineAsm() const
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr's memory reference descriptor list.
int findRegisterUseOperandIdx(Register Reg, const TargetRegisterInfo *TRI, bool isKill=false) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
MDNode * getPCSections() const
Helper to extract PCSections metadata target sections.
bool isCFIInstruction() const
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)
Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...
bool isCandidateForAdditionalCallInfo(QueryType Type=IgnoreBundle) const
Return true if this is a call instruction that may have an additional information associated with it.
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst4RegLLTs() const
std::tuple< Register, LLT, Register, LLT > getFirst2RegLLTs() const
unsigned getNumMemOperands() const
Return the number of memory operands.
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
std::optional< LocationSize > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
InlineAsm::AsmDialect getInlineAsmDialect() const
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
bool isEquivalentDbgInstr(const MachineInstr &Other) const
Returns true if this instruction is a debug instruction that represents an identical debug value to O...
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
static uint32_t copyFlagsFromInstruction(const Instruction &I)
void insert(mop_iterator InsertBefore, ArrayRef< MachineOperand > Ops)
Inserts Ops BEFORE It. Can untie/retie tied operands.
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
bool isJumpTableDebugInfo() const
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
void eraseFromBundle()
Unlink 'this' from its basic block and delete it.
iterator_range< mop_iterator > operands()
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can't be determined by the instruction's descr...
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.
bool isLifetimeMarker() const
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
void emitGenericError(const Twine &ErrMsg) const
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
bool isNonListDebugValue() const
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
void setFlag(MIFlag Flag)
Set a MI flag.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
bool isDead(const MachineRegisterInfo &MRI, LiveRegUnits *LivePhysRegs=nullptr) const
Check whether an MI is dead.
std::tuple< LLT, LLT, LLT > getFirst3LLTs() const
const MachineOperand & getDebugVariableOp() const
Return the operand for the debug variable referenced by this DBG_VALUE instruction.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
bool isDebugValue() const
const MachineOperand & getDebugOffset() const
Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...
MachineOperand & getDebugOperand(unsigned Index)
std::optional< LocationSize > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
iterator_range< mop_iterator > implicit_operands()
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
MDNode * getHeapAllocMarker() const
Helper to extract a heap alloc marker if one has been added.
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
std::tuple< LLT, LLT, LLT, LLT > getFirst4LLTs() const
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
const MachineOperand & getOperand(unsigned i) const
void emitInlineAsmError(const Twine &ErrMsg) const
Emit an error referring to the source location of this instruction.
uint32_t getFlags() const
Return the MI flags bitvector.
bool isPseudoProbe() const
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
bool shouldUpdateAdditionalCallInfo() const
Return true if copying, moving, or erasing this instruction requires updating additional call info (s...
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
void unbundleFromSucc()
Break bundle below this instruction.
iterator_range< filtered_mop_iterator > all_defs()
Returns an iterator range over all operands that are (explicit or implicit) register defs.
void clearKillInfo()
Clears kill flags on all operands.
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...
unsigned getNumDefs() const
Returns the total number of definitions.
void setPCSections(MachineFunction &MF, MDNode *MD)
const MDNode * getLocCookieMD() const
For inline asm, get the !srcloc metadata node if we have it, and decode the loc cookie from it.
int findRegisterDefOperandIdx(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
void setMMRAMetadata(MachineFunction &MF, MDNode *MMRAs)
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
void moveBefore(MachineInstr *MovePos)
Move the instruction before MovePos.
MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
bool mayFoldInlineAsmRegOp(unsigned OpId) const
Returns true if the register operand can be folded with a load or store into a frame index.
A description of a memory reference used in the backend.
LocationSize getSize() const
Return the size in bytes of the memory reference.
const PseudoSourceValue * getPseudoValue() const
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
const Value * getValue() const
Return the base address of the memory access.
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const MDNode * getMetadata() const
void setIsDead(bool Val=true)
void setMetadata(const MDNode *MD)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
void setIsKill(bool Val=true)
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
void setIsEarlyClobber(bool Val=true)
void setIsUndef(bool Val=true)
void setIsDebug(bool Val=true)
Register getReg() const
getReg - Returns the register number.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Representation for a specific memory location.
Manage lifetime of a slot tracker for printing IR.
void incorporateFunction(const Function &F)
Incorporate the given function.
A Module instance is used to store all the information related to an LLVM module.
Utility class for integer operators which may exhibit overflow - Add, Sub, Mul, and Shl.
An or instruction, which can be marked as "disjoint", indicating that the inputs don't have a 1 in th...
A udiv or sdiv instruction, which can be marked as "exact", indicating that no bits are destroyed.
Instruction that can have a nneg flag (zext/uitofp).
Special value supplied for machine level alias analysis.
virtual bool mayAlias(const MachineFrameInfo *) const
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
reference emplace_back(ArgTypes &&... Args)
void reserve(size_type N)
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
static unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)
Get index of next meta operand.
MI-level Statepoint operands.
int getFirstGCPtrIdx()
Get index of first GC pointer operand of -1 if there are none.
TargetInstrInfo - Interface to description of machine instruction set.
TargetIntrinsicInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
virtual const TargetInstrInfo * getInstrInfo() const
This class represents a truncation of integer types.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
A Use represents the edge between a Value definition and its users.
LLVM Value Representation.
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
self_iterator getIterator()
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
hash_code hash_value(const FixedPointSemantics &Val)
formatted_raw_ostream & fdbgs()
fdbgs() - This returns a reference to a formatted_raw_ostream for debug output.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
iterator_range< pointee_iterator< WrappedIteratorT > > make_pointee_range(RangeT &&Range)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex, Register SpillReg)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
Implement std::hash so that hash_code can be used in STL containers.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
static unsigned getHashValue(const MachineInstr *const &MI)