Code Generation

PowerPC Discuss the PowerPC backend. Mips Ask questions about the Mips backend. ARM For questions about the Arm backend. WebAssembly For questions about the WebAssembly backend. X86 For questions about the X86 backend. AArch64 For questions about the AArch64 backend. AMDGPU This category is for discussions specific to both the development of the AMDGPU target in upstream LLVM and its use inside the LLVM project and by outside compiler frontends (e.g. LLPC, Mesa). RISCV For discussing RISCV code generation in LLVM. Common CodeGen Infrastructure This category is for common code generation infrastructure related to all backends.

Topic	Replies	Views	Activity
About the Code Generation category Code Generation	4	808	January 11, 2022
[RFC][tblgen] Generate linker code with TableGen Common CodeGen Infrastructure	11	321	June 26, 2025
[RFC] Assembly Super Optimiser Code Generation	22	2604	June 24, 2025
X86 isel bug X86 core , x86 , clang , llvm , llvm-ir	1	112	June 20, 2025
RISC-V LLVM sync-up call June 19th 2025 RISCV	0	29	June 18, 2025
Add a field to Coverage Mapping to track instrumentation level Code Generation llvm	4	99	June 18, 2025
PBQP codegen acceleration? Common CodeGen Infrastructure	5	130	June 18, 2025
Size of ISelLowering.cpp files Code Generation	8	314	June 18, 2025
[RFC] Adding SFrame support to llvm Code Generation	2	224	June 17, 2025
LOH conflicting with MachineOutliner AArch64	16	483	June 11, 2025
Linking errors when using Sleef_expfx_u10rvvm2 RISCV riscv , clang	3	36	June 9, 2025
The bug for BinaryUIOpConversion of ArithToEmitC Common CodeGen Infrastructure mlir	0	29	June 9, 2025
Best way to implement a fully custom optimization + codegen pipeline using NPM Code Generation llvm	6	125	June 5, 2025
Including location information when calling `reportFatalUsageError` Common CodeGen Infrastructure llvm	2	35	June 4, 2025
[RFC] Dynamic sizes and field offsets in DWARF Code Generation debuginfo	10	257	June 4, 2025
CANCELLED RISC-V LLVM sync-up call June 5th 2025 RISCV	0	11	June 4, 2025
[RFC] Improving MachineSink sinking into Cycles Common CodeGen Infrastructure llvm	0	106	June 3, 2025
TPDE-LLVM: 10-20x Faster LLVM -O0 Back-End Code Generation llvm	5	2061	June 3, 2025
Question on rvv builtin and policies RISCV	11	142	May 25, 2025
[RFC][DwarfDebug] Fix and improve handling imported entities, types and static local in subprogram and lexical block scopes Common CodeGen Infrastructure debuginfo	11	980	May 28, 2025
Compiler crash on variadic functions on mips3 Mips	1	121	May 28, 2025
Recommended open-source 32-bit RISC-V core for validating custom LLVM backend extensions? RISCV riscv , llvm	1	65	May 26, 2025
RISC-V LLVM sync-up call May 22nd 2025 RISCV	0	25	May 22, 2025
Possible problem related to Subtarget usage RISCV	4	363	May 22, 2025
Are the latencies of vextractf128 correct for Zen2/3 in MCA? X86	3	66	May 21, 2025
Match DAG node with 2 results Common CodeGen Infrastructure	1	72	May 20, 2025
Inter-procedural register allocation RISCV llvm-weekly	1	134	May 14, 2025
Help with Segmentation Fault from Custom Pseudo-Instruction Optimization on RISC-V(Xalancbmk)) RISCV riscv , clang , llvm	6	93	May 9, 2025
[llvm-exegesis][AArch64] Load and Store Instruction Benchmarking Support AArch64 llvm	1	59	May 8, 2025
CANCELLED RISC-V LLVM sync-up call May 8th 2025 RISCV	0	35	May 7, 2025