Recommended open-source 32-bit RISC-V core for validating custom LLVM backend extensions?

Code Generation RISCV
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Hi all,

I’m currently working on a modified LLVM backend (cloned from llvm-project mainline) targeting a 32-bit RISC-V architecture (RV32IM), where I’ve added support for a custom instruction intended to accelerate.

I’m looking for an open-source RISC-V core that is suitable for functional and performance validation of this backend. Ideally, the core:

  • Can be deployed on an FPGA (e.g., Vivado-based flow),

  • Allows for architectural modifications to support custom opcodes,

  • Works well with LLVM/Clang output instead of relying solely on the riscv-gnu-toolchain.

While adapting cores like PicoRV32 and NEORV32, I noticed most of their toolchains and Makefiles are tightly coupled with GCC and newlib, and integrating Clang-generated binaries despite building correctly results in undefined behavior or incomplete execution on hardware.

I’d appreciate feedback on:

  1. Open-source RISC-V cores (32-bit) that are known to integrate well with LLVM, especially for testing custom instructions end-to-end (from IR to FPGA),

  2. Known issues or patterns in adapting linker scripts, startup code, or libc stubs when switching from GCC to LLVM,

  3. Experiences with running Clang-generated firmware in simulation (e.g., Verilator, GHDL) or synthesis (Vivado, etc.) environments.

If anyone has been through a similar flow or published a minimal LLVM-friendly firmware runtime setup for RISC-V soft cores, I’d love to hear about it.

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Never used it myself and I’m certainly not hardware engineer, but have you tried Rocket? It’s the (spiritual) successor to the original RISC-V core. And it has a pretty active community AFAIK. Not sure if it has infrastructure to run end-to-end tests as you described though.