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2020 – today
- 2024
[j34]Ryuichi Nakajima
, Takafumi Ito, Shotaro Sugitani, Tomoya Kii, Mitsunori Ebara, Jun Furuta, Kazutoshi Kobayashi, Mathieu Louvat, Francois Jacquet, Jean-Christophe Eloy, Olivier Montfort, Lionel Jure, Vincent Huard:
Soft-Error Tolerance by Guard-Gate Structures on Flip-Flops in 22 and 65 nm FD-SOI Technologies. IEICE Trans. Electron. 107(7): 191-200 (2024)- [j33]Jun Furuta, Shotaro Sugitani, Ryuichi Nakajima, Takafumi Ito, Kazutoshi Kobayashi:
Measuring SET Pulse Widths in pMOSFETs and nMOSFETs Separately by Heavy Ion and Neutron Irradiation. IEICE Trans. Electron. 107(9): 255-262 (2024) - [c56]Jun Furuta, Shotaro Sugitani, Ryuichi Nakajima, Kazutoshi Kobayashi:
A Partially-redundant Flip-flip Suitable for Mitigating Single Event Upsets in a FD-SOI Process with Low Performance Overhead. IRPS 2024: 1-4 - [c55]Ryuichi Nakajima, Shotaro Sugitani, Haruto Sugisaki, Takafumi Ito, Jun Furuta, Kazutoshi Kobayashi, Makoto Sakai:
An Approach to Neutron-Induced SER Evaluation Using a Clinical 290 MeV/ u Carbon Beam and Particle Transport Simulations. IRPS 2024: 1-4 - 2023
- [j32]Yuki Abe, Kazutoshi Kobayashi, Jun Shiomi, Hiroyuki Ochi:
Nonvolatile Storage Cells Using FiCC for IoT Processors with Intermittent Operations. IEICE Trans. Electron. 106(10): 546-555 (2023) - [j31]Yoshisato Yokoyama, Koji Nii, Yuichiro Ishii, Shinji Tanaka, Kazutoshi Kobayashi:
Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing. IEEE J. Solid State Circuits 58(7): 2098-2108 (2023) - [c54]Daisuke Kikuta, Ryo Kishida, Kazutoshi Kobayashi:
Ring Oscillators with identical Circuit Structure to Measure Bias Temperature Instability. ASICON 2023: 1-4 - [c53]Kazutoshi Kobayashi:
Scalable Highly Integrated Quantum Bit Error Correction System by Classical Electronics. ASICON 2023: 1 - [c52]Haruto Sugisaki, Ryuichi Nakajima, Shotaro Sugitani, Jun Furuta, Kazutoshi Kobayashi:
Frequency Dependency of Soft Error Rates Based on Dynamic Soft Error Measurements. ICICDT 2023: 68-71 - [c51]Keita Yoshida, Ryuichi Nakajima, Shotaro Sugitani, Takafumi Ito, Jun Furuta, Kazutoshi Kobayashi:
SEU Sensitivity of PMOS and NMOS Transistors in a 65 nm Bulk Process by α-Particle Irradiation. ICICDT 2023: 72-75 - [c50]Shotaro Sugitani, Ryuichi Nakajima, Takafumi Ito, Jun Furuta, Kazutoshi Kobayashi, Mathieu Louvat, Francois Jacquet, Jean-Christophe Eloy, Olivier Montfort, Lionel Jure, Vincent Huard:
Radiation Hardness Evaluations of a Stacked Flip Flop in a 22 nm FD-SOI Process by Heavy-Ion Irradiation. IOLTS 2023: 1-5 - [c49]Yuya Aoki, Tatsuya Iwata, Takuji Miki, Kazutoshi Kobayashi, Takefumi Yoshikawa:
A 13-bit Radiation-Hardened SAR-ADC with Error Correction by Adaptive Topology Transformation. IRPS 2023: 1-8 - [c48]Kazutoshi Kobayashi, Tomoharu Kishita, Hiroki Nakano, Jun Furuta, Mitsuhiko Igarashi, Shigetaka Kumashiro, Michitarou Yabuuchi, Hironori Sakamoto:
Ultra Long-term Measurement Results of BTI-induced Aging Degradation on 7-nm Ring Oscillators. IRPS 2023: 1-7 - [c47]Shotaro Sugitani, Ryuichi Nakajima, Keita Yoshida, Jun Furuta, Kazutoshi Kobayashi:
Radiation Hardened Flip-Flops with low Area, Delay and Power Overheads in a 65 nm bulk process. IRPS 2023: 1-5 - 2022
- [c46]Yuki Abe, Kazutoshi Kobayashi, Jun Shiomi, Hiroyuki Ochi:
Zero-standby-power Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent Operations. COOL CHIPS 2022: 1-6 - [c45]Ryuichi Nakajima, Kazuya Ioki, Jun Furuta, Kazutoshi Kobayashi:
Radiation Hardened Flip-Flops Minimizing Area, Power, and Delay Overheads with 1/100 Lower α-SER in a 130 nm Bulk Process. IOLTS 2022: 1-5 - [c44]Ikuo Suda, Ryo Kishida, Kazutoshi Kobayashi:
An Aging Degradation Suppression Scheme at Constant Performance by Controlling Supply Voltage and Body Bias in a 65 nm Fully-Depleted Silicon-On-Insulator Process. IRPS 2022: 4-1 - [c43]Yuki Abe, Kazutoshi Kobayashi, Hiroyuki Ochi:
Nonvolatile Flip-Flops Using FiCC for IoT Processors with Intermittent Operations. MWSCAS 2022: 1-4 - 2021
- [j30]Takefumi Yoshikawa, Masahiro Ishimaru, Tatsuya Iwata, Fuma Mori, Kazutoshi Kobayashi:
A Bit-Error Rate Measurement and Error Analysis of Wireline Data Transmission using Current Source Model for Single Event Effect under Irradiation Environment. J. Electron. Test. 37(5): 675-684 (2021) - [j29]Junichiro Nagao, Urmimala Chatterjee, Xiangdong Li, Jun Furuta, Stefaan Decoutere, Kazutoshi Kobayashi:
An E-mode p-GaN HEMT monolithically-integrated three-level gate driver operating with a single voltage supply. IEICE Electron. Express 18(6): 20210059 (2021) - [j28]Mitsuhiko Igarashi, Yuuki Uchida, Yoshio Takazawa, Makoto Yabuuchi, Yasumasa Tsukamoto, Koji Shibutani, Kazutoshi Kobayashi:
An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(11): 1536-1545 (2021) - [j27]Yoshisato Yokoyama, Yuichiro Ishii, Koji Nii, Kazutoshi Kobayashi:
Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs. IEEE Trans. Very Large Scale Integr. Syst. 29(7): 1495-1499 (2021) - [c42]Takaki Urabe, Hiroyuki Ochi, Kazutoshi Kobayashi:
Nonvolatile SRAM Using Fishbone-in-Cage Capacitor in a 180 nm Standard CMOS Process for Zero-Standby and Instant-Powerup Embedded Memory on IoT. COOL CHIPS 2021: 1-3 - [c41]Ryo Kishida, Ikuo Suda, Kazutoshi Kobayashi:
Bias Temperature Instability Depending on Body Bias through Buried Oxide (BOX) Layer in a 65 nm Fully-Depleted Silicon-On-Insulator Process. IRPS 2021: 1-6 - 2020
- [j26]Kentaro Kojima, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi:
Evaluation of Heavy-Ion-Induced Single Event Upset Cross Sections of a 65-nm Thin BOX FD-SOI Flip-Flops Composed of Stacked Inverters. IEICE Trans. Electron. 103-C(4): 144-152 (2020) - [j25]Takumi Hosaka, Shinichi Nishizawa, Ryo Kishida, Takashi Matsumoto, Kazutoshi Kobayashi:
Universal NBTI Compact Model Replicating AC Stress/Recovery from a Single-shot Long-term DC Measurement. IPSJ Trans. Syst. LSI Des. Methodol. 13: 56-64 (2020) - [j24]Shigetaka Kumashiro, Tatsuya Kamei, Akira Hiroki, Kazutoshi Kobayashi:
An Efficient and Accurate Time Step Control Method for Power Device Transient Simulation Utilizing Dominant Time Constant Approximation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 451-463 (2020)
2010 – 2019
- 2019
- [j23]Yuki Yamashita, Steve Stoffels, Niels Posthuma, Karen Geens, Xiangdong Li, Jun Furuta, Stefaan Decoutere, Kazutoshi Kobayashi:
Monolithic integration of gate driver and p-GaN power HEMT for MHz-switching implemented by e-mode GaN-on-SOI process. IEICE Electron. Express 16(22): 20190516 (2019) - [j22]Masanori Hashimoto, Kazutoshi Kobayashi, Jun Furuta, Shin-ichiro Abe, Yukinobu Watanabe:
Characterizing SRAM and FF soft error rates with measurement and simulation. Integr. 69: 161-179 (2019) - [c40]Takuya Asuke, Ryo Kishida, Jun Furuta, Kazutoshi Kobayashi:
Temperature Dependence of Bias Temperature Instability (BTI) in Long-term Measurement by BTI-sensitive and -insensitive Ring Oscillators Removing Environmental Fluctuation. ASICON 2019: 1-4 - [c39]Yuto Tsukita, Mitsunori Ebara, Jun Furuta, Kazutoshi Kobayashi:
Soft-Error Tolerance Depending on Supply Voltage by Heavy Ions on Radiation-Hardened Flip Flops in a 65 nm Bulk Process. ASICON 2019: 1-4 - [c38]Shuzhen You, Xiangdong Li, Stefaan Decoutere, Guido Groeseneken, Zhanfei Chen, Jun Liu, Yuki Yamashita, Kazutoshi Kobayashi:
Monolithically integrated GaN power ICs designed using the MIT virtual source GaNFET (MVSG) compact model for enhancement-mode p-GaN gate power HEMTs, logic transistors and resistors. ESSDERC 2019: 158-161 - [c37]Mitsunori Ebara, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi:
Comparison of Radiation Hardness of Stacked Transmission-Gate Flip Flop and Stacked Tristate-Inverter Flip Flop in a 65 nm Thin BOX FDSOI Process. IOLTS 2019: 1-6 - [c36]Takashi Yoshida, Kazutoshi Kobayashi, Jun Furuta:
Total Ionizing Dose Effects by alpha irradiation on circuit performance and SEU tolerance in thin BOX FDSOI process. IOLTS 2019: 236-238 - [c35]Takumi Hosaka, Shinichi Nishizawa, Ryo Kishida, Takashi Matsumoto, Kazutoshi Kobayashi:
Compact Modeling of NBTI Replicating AC Stress / Recovery from a Single-shot Long-term DC Measurement. IOLTS 2019: 305-309 - [c34]Jun Furuta, Yuto Tsukita, Kodai Yamada, Mitsunori Ebara, Kentaro Kojima, Kazutoshi Kobayashi:
Impact of Combinational Logic Delay for Single Event Upset on Flip Flops in a 65 nm FDSOI Process. IRPS 2019: 1-4 - [c33]Kentaro Kojima, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi:
An Accurate Device-Level Simulation Method to Estimate Cross Sections of Single Event Upsets by Silicon Thickness in Raised Layer. IRPS 2019: 1-5 - 2018
- [j21]Haruki Maruoka, Masashi Hifumi, Jun Furuta, Kazutoshi Kobayashi:
A Low-Power Radiation-Hardened Flip-Flop with Stacked Transistors in a 65 nm FDSOI Process. IEICE Trans. Electron. 101-C(4): 273-280 (2018) - [c32]Kodai Yamada, Haruki Maruoka, Jun Furuta, Kazutoshi Kobayashi:
Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process. IRPS 2018: 3-1 - 2017
- [j20]Takuya Komawaki, Michitarou Yabuuchi, Ryo Kishida, Jun Furuta, Takashi Matsumoto, Kazutoshi Kobayashi:
Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2758-2763 (2017) - [c31]Kazutoshi Kobayashi:
Highly-reliable integrated circuits for Gro. ASICON 2017: 647-650 - [c30]Takuya Komawaki, Michitarou Yabuuchi, Ryo Kishida, Jun Furuta, Takashi Matsumoto, Kazutoshi Kobayashi:
Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS. ICICDT 2017: 1-4 - 2016
- [j19]Michitarou Yabuuchi, Kazutoshi Kobayashi:
Size Optimization Technique for Logic Circuits that Considers BTI and Process Variations. IPSJ Trans. Syst. LSI Des. Methodol. 9: 72-78 (2016) - 2015
- [j18]Jun Furuta, Kazutoshi Kobayashi, Hidetoshi Onodera:
Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets. IEICE Trans. Electron. 98-C(4): 298-303 (2015) - [j17]Koichiro Ishibashi, Nobuyuki Sugii, Shiro Kamohara, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham:
A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode. IEICE Trans. Electron. 98-C(7): 536-543 (2015) - [c29]Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera:
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. ASP-DAC 2015: 14-15 - [c28]Azusa Oshima, Pieter Weckx, Ben Kaczer, Kazutoshi Kobayashi, Takashi Matsumoto:
Impact of random telegraph noise on ring oscillators evaluated by circuit-level simulations. ICICDT 2015: 1-4 - [c27]Ryo Kishida, Azusa Oshima, Kazutoshi Kobayashi:
Negative bias temperature instability caused by plasma induced damage in 65 nm bulk and Silicon on thin BOX (SOTB) processes. IRPS 2015: 2 - 2014
- [j16]Kazutoshi Kobayashi:
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(7): 1443 (2014) - [j15]Michitarou Yabuuchi, Ryo Kishida, Kazutoshi Kobayashi:
Correlations between BTI-Induced Degradations and Process Variations on ASICs and FPGAs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2367-2372 (2014) - [j14]Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera:
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2518-2529 (2014) - [c26]Takashi Matsumoto, Kazutoshi Kobayashi, Hidetoshi Onodera:
Impact of random telegraph noise on CMOS logic circuit reliability. CICC 2014: 1-8 - [c25]Koichiro Ishibashi, Nobuyuki Sugii, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham, Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Hidekazu Oda, Takumi Hasegawa, Shinobu Okanishi, Hiroshi Yanagita, Shiro Kamohara, Masaru Kadoshima, Keiichi Maekawa, Tomohiro Yamashita, Duc-Hung Le, Takumu Yomogita, Masaru Kudo, Kuniaki Kitamori, Shuya Kondo, Yuuki Manzawa:
A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. COOL Chips 2014: 1-3 - [c24]Shiro Kamohara, Nobuyuki Sugii, Koichiro Ishibashi, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham:
A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode. Hot Chips Symposium 2014: 1 - 2013
- [j13]Kuiyuan Zhang, Jun Furuta, Ryosuke Yamamoto, Kazutoshi Kobayashi, Hidetoshi Onodera:
A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect. IEICE Trans. Electron. 96-C(4): 511-517 (2013) - 2012
- [j12]Michitarou Yabuuchi, Kazutoshi Kobayashi:
NBTI-Induced Delay Degradation Analysis of FPGA Routing Structures. Inf. Media Technol. 7(4): 1346-1352 (2012) - [j11]Michitarou Yabuuchi, Kazutoshi Kobayashi:
NBTI-Induced Delay Degradation Analysis of FPGA Routing Structures. IPSJ Trans. Syst. LSI Des. Methodol. 5: 143-149 (2012) - 2011
- [j10]Chikara Hamanaka, Ryosuke Yamamoto, Jun Furuta, Kanto Kubota, Kazutoshi Kobayashi, Hidetoshi Onodera:
Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2669-2675 (2011) - [c23]Jun Furuta, Chikara Hamanaka, Kazutoshi Kobayashi, Hidetoshi Onodera:
A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles. ASP-DAC 2011: 83-84 - [c22]Jun Furuta, Ryosuke Yamamoto, Kazutoshi Kobayashi, Hidetoshi Onodera:
Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65nm. A-SSCC 2011: 209-212 - [c21]Kyosuke Ito, Takashi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi, Hidetoshi Onodera:
Modeling of Random Telegraph Noise under circuit operation - Simulation and measurement of RTN-induced delay fluctuation. ISQED 2011: 22-27 - 2010
- [j9]Jun Furuta, Kazutoshi Kobayashi, Hidetoshi Onodera:
An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity. IEICE Trans. Electron. 93-C(3): 340-346 (2010) - [j8]Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera:
Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells. Inf. Media Technol. 5(2): 424-433 (2010) - [j7]Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera:
Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells. IPSJ Trans. Syst. LSI Des. Methodol. 3: 130-139 (2010) - [c20]Michitarou Yabuuchi, Kazutoshi Kobayashi:
Evaluation of FPGA design guardband caused by inhomogeneous NBTI degradation considering process variations. FPT 2010: 417-420 - [c19]Jun Yao, Hajime Shimada, Kazutoshi Kobayashi:
A Stage-Level Recovery Scheme in Scalable Pipeline Modules for High Dependability. IWIA 2010: 21-29 - [c18]Jun Yao, Ryoji Watanabe, Takashi Nakada, Hajime Shimada, Yasuhiko Nakashima, Kazutoshi Kobayashi:
A Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors. PRDC 2010: 237-238
2000 – 2009
- 2009
- [c17]Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera:
Erect of regularity-enhanced layout on printability and circuit performance of standard cells. ISQED 2009: 195-200 - 2008
- [c16]Kazutoshi Kobayashi, Hidetoshi Onodera:
Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs. ASP-DAC 2008: 811-812 - [c15]Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera:
Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs. FPGA 2008: 257 - [c14]Kazutoshi Kobayashi, Yohei Kume, Cam Lai Ngo, Yuuri Sugihara, Hidetoshi Onodera:
A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS. FPL 2008: 107-112 - [c13]Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera:
Performance optimization by track swapping on critical paths utilizing random variations for FPGAS. FPL 2008: 503-506 - 2007
- [j6]Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera:
A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations. IEICE Trans. Electron. 90-C(4): 699-707 (2007) - [j5]Kazutoshi Kobayashi, Kazuya Katsuki, Manabu Kotani, Yuuri Sugihara, Yohei Kume, Hidetoshi Onodera:
A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations. IEICE Trans. Electron. 90-C(10): 1919-1926 (2007) - [c12]Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera:
A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations. ASP-DAC 2007: 122-123 - 2006
- [j4]Yoichi Yuyama, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera:
Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect. IEICE Trans. Electron. 89-C(3): 327-333 (2006) - [j3]Kazutoshi Kobayashi, Akihiko Higuchi, Hidetoshi Onodera:
A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era. IEICE Trans. Electron. 89-C(6): 838-843 (2006) - [c11]Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera:
Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices. ASP-DAC 2006: 110-111 - [c10]Kazutoshi Kobayashi, Manabu Kotani, Kazuya Katsuki, Y. Takatsukasa, K. Ogata, Yuuri Sugihara, Hidetoshi Onodera:
A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime. FPL 2006: 1-4 - 2005
- [j2]Kazutoshi Kobayashi, Masao Aramoto, Hidetoshi Onodera:
A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era. IEICE Trans. Electron. 88-C(4): 552-558 (2005) - [c9]Kazutoshi Kobayashi, Masao Aramoto, Yoichi Yuyama, Akihiko Higuchi, Hidetoshi Onodera:
A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing. ASP-DAC 2005: 619-622 - [c8]Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera:
A yield and speed enhancement scheme under within-die variations on 90nm LUT array. CICC 2005: 601-604 - 2004
- [j1]Kazutoshi Kobayashi, Hidetoshi Onodera:
A Comprehensive Simulation and Test Environment for Prototype VLSI Verification. IEICE Trans. Inf. Syst. 87-D(3): 630-636 (2004) - [c7]Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera:
An SoC architecture and its design methodology using unifunctional heterogeneous processor array. ASP-DAC 2004: 737-742 - [c6]Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera:
RTL/ISS co-modeling methodology for embedded processor using SystemC. ISCAS (5) 2004: 305-308 - 2002
- [c5]Kazutoshi Kobayashi, Junji Yamaguchi, Hidetoshi Onodera:
Measurement results of on-chip IR-drop. CICC 2002: 521-524 - 2001
- [c4]Kazutoshi Kobayashi, Makoto Eguchi, Takuya Iwahashi, Takehide Shibayama, Xiang Li, Kousuke Takai, Hidetoshi Onodera:
A vector-pipeline DSP for low-rate videophones. ASP-DAC 2001: 1-2 - [c3]Kazutoshi Kobayashi, Hidetoshi Onodera:
ST: PERL package for simulation and test environment. ISCAS (5) 2001: 89-92
1990 – 1999
- 1998
- [c2]Kazuhiko Terada, Masahiro Takeuchi, Kazutoshi Kobayashi, Keikichi Tamaru:
Real time low bit-rate video coding algorithm using multi-stage hierarchical vector quantization. ICASSP 1998: 2673-2676 - 1997
- [c1]Kazutoshi Kobayashi, Masayoshi Kinoshita, Masahiro Takeuchi, Hidetoshi Onodera, Keikichi Tamaru:
A functional memory type parallel processor for vector quantization. ASP-DAC 1997: 665-666
Coauthor Index
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