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ORCIDShuichi Sakai
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- affiliation: University of Tokyo, Graduate School of Information Science & Technology, Japan
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2020 – today
- 2024
[c89]Shun Nagasaki
, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Multi-Tree Network Protocol Enabling System Partitioning for Shape-Changeable Computer System. CF 2024- [c88]Masato Goto, Ibuki Sugiyama, Kenta Higuchi, Toshiki Goto, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
CommuTiles: Shape-Changeable Modular Computer System Using Proximity Wireless Communication. CHI Extended Abstracts 2024: 395:1-395:5 - [c87]Reoma Matsuo, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya:
Branch Divergence-Aware Flexible Approximating Technique on GPUs. COOL CHIPS 2024: 1-6 - [c86]Shoi To, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
DataPipettor: Touch-Based Information Transfer Interface Using Proximity Wireless Communication. UIST (Adjunct Volume) 2024: 94:1-94:3 - 2023
- [j26]Shun Nagasaki, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Dynamically Reconfigurable Network Protocol for Shape-Changeable Computer System. IEEE Des. Test 40(6): 18-29 (2023) - [j25]Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
A Principal Factor of Performance in Decoupled Front-End. IEICE Trans. Inf. Syst. 106(12): 1960-1968 (2023) - [j24]Rin Oishi, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
FPGA-based Garbling Accelerator with Parallel Pipeline Processing. IEICE Trans. Inf. Syst. 106(12): 1988-1996 (2023) - [c85]Shu Sugita, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai:
A Sound and Complete Algorithm for Code Generation in Distance-Based ISA. CC 2023: 73-84 - [c84]Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya:
TURBULENCE: Complexity-effective Out-of-order Execution on GPU with Distance-based ISA. DATE 2023: 1-2 - [c83]Taichi Amano, Junichiro Kadomoto, Satoshi Mitsuno, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai:
An Out-of-Order Superscalar Processor Using STRAIGHT Architecture in 28 nm CMOS. ISCAS 2023: 1-5 - [c82]Toru Koizumi, Ryota Shioya, Shu Sugita, Taichi Amano, Yuya Degawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors. MICRO 2023: 1-16 - [c81]Kenta Higuchi, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Poster Abstract: Investigation of Distance Sensing Method Using Magnetic Resonant Coupled Coils for Deformable User Interfaces. SenSys 2023: 502-503 - [c80]Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Poster Abstract: Towards a Tiny Digital Displacement Sensor Utilizing Bit-Error Characteristics of Inter-Chip Wireless Bus. SenSys 2023: 554-555 - [c79]Yusuke Izawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
A Functional Reactive Programming Language for Wirelessly Connected Shape-Changeable Chiplet-Based Computers. SPLASH Companion 2023: 61-62 - [c78]Takashi Murayama, Shu Sugita, Hiroyuki Saegusa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
iKnowde: Interactive Learning Path Generation System Based on Knowledge Dependency Graphs. UIST (Adjunct Volume) 2023: 25:1-25:3 - 2022
- [c77]Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Deformable Chiplet-Based Computer Using Inductively Coupled Wireless Communication. ASP-DAC 2022: 98-99 - [c76]Toru Koizumi, Tomoki Nakamura, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya:
T-SKID: Predicting When to Prefetch Separately from Address Prediction. DATE 2022: 1389-1394 - [c75]Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Evaluation of Different Microarchitectures for Energy-Efficient RISC-V Cores. MCSoC 2022: 78-84 - 2021
- [j23]Junichiro Kadomoto, Takuya Sasatani, Koya Narumi, Naoto Usami, Hidetsugu Irie, Shuichi Sakai, Yoshihiro Kawahara:
Toward Wirelessly Cooperated Shape-Changing Computing Particles. IEEE Pervasive Comput. 20(3): 9-17 (2021) - [c74]Tomoki Nakamura, Kazutaka Tomida, Shouta Kouno, Hidetsugu Irie, Shuichi Sakai:
Stochastic Iterative Approximation: Software/hardware techniques for adjusting aggressiveness of approximation. ICCD 2021: 74-82 - [c73]Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Accurate and Fast Performance Modeling of Processors with Decoupled Front-end. ICCD 2021: 88-92 - [c72]Toru Koizumi, Shu Sugita, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Compiling and Optimizing Real-world Programs for STRAIGHT ISA. ICCD 2021: 400-408 - [c71]Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Multiport Register File Design for High-Performance Embedded Cores. MCSoC 2021: 281-286 - 2020
- [c70]Junichiro Kadomoto, Satoshi Mitsuno, Hidetsugu Irie, Shuichi Sakai:
An Inductively Coupled Wireless Bus for Chiplet-Based Systems. ASP-DAC 2020: 9-10 - [c69]Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
A Self-Sensing Technique Using Inductively-Coupled Coils for Deformable User Interfaces. AsianCHI@CHI 2020: 7 - [c68]Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
A RISC-V Processor with an Inter-Chiplet Wireless Communication Interface for Shape-Changeable Computers. COOL CHIPS 2020: 1-3 - [c67]Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai:
A High-Performance Out-of-Order Soft Processor Without Register Renaming. FPL 2020: 73-78 - [c66]Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Design of Shape-Changeable Chiplet-Based Computers Using an Inductively Coupled Wireless Bus Interface. ICCD 2020: 589-596
2010 – 2019
- 2019
- [c65]Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
WiXI: An Inter-Chip Wireless Bus Interface for Shape-Changeable Chiplet-Based Computers. ICCD 2019: 100-108 - 2018
- [j22]Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai:
Bank-Aware Instruction Scheduler for a Multibanked Register File. J. Inf. Process. 26: 696-705 (2018) - [c64]Junichiro Kadomoto, Toru Koizumi, Akifumi Fukuda, Reoma Matsuo, Susumu Mashimo, Akifumi Fujita, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai:
An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming. FPT 2018: 374-377 - [c63]Toru Koizumi, Satoshi Nakae, Akifumi Fukuda, Hidetsugu Irie, Shuichi Sakai:
Reduction of Instruction Increase Overhead by STRAIGHT Compiler. CANDAR Workshops 2018: 92-98 - [c62]Takahiro Yamada, Hidetsugu Irie, Masahiro Kunitake, Eiji Nagano, Shuichi Sakai:
Estimating driver's readiness by understanding driving posture. ICCE 2018: 1-4 - [c61]Hidetsugu Irie, Toru Koizumi, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Ryota Shioya, Takahiro Notsu, Katsuhiro Yoda, Teruo Ishihara, Shuichi Sakai:
STRAIGHT: Hazardless Processor Architecture Without Register Renaming. MICRO 2018: 121-133 - 2017
- [j21]Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai:
Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology. IEICE Trans. Electron. 100-C(3): 232-244 (2017) - [j20]Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai:
Skewed Multistaged Multibanked Register File for Area and Energy Efficiency. IEICE Trans. Inf. Syst. 100-D(4): 822-837 (2017) - [c60]Mizuki Miyanaga, Hidetsugu Irie, Shuichi Sakai:
Accelerating Integrity Verification on Secure Processors by Promissory Hash. PRDC 2017: 20-29 - 2016
- [j19]Minseong Choi, Takashi Fukuda, Masahiro Goshima, Shuichi Sakai:
An Inductive Method to Select Simulation Points. IEICE Trans. Inf. Syst. 99-D(12): 2891-2900 (2016) - [c59]Hayato Nomura, Hiroyuki Katchi, Hidetsugu Irie, Shuichi Sakai:
"Stubborn" strategy to mitigate remaining cache misses. ICCD 2016: 388-391 - [c58]Takahiro Yamada, Hidetsugu Irie, Shuichi Sakai:
High-Accuracy Joint Position Estimation and Posture Detection System for Driving. MobiQuitous (Adjunct Proceedings) 2016: 219-224 - 2015
- [j18]Naruki Kurata, Ryota Shioya, Masahiro Goshima, Shuichi Sakai:
Address Order Violation Detection with Parallel Counting Bloom Filters. IEICE Trans. Electron. 98-C(7): 580-593 (2015) - [c57]Minseong Choi, Takashi Fukuda, Masahiro Goshima, Shuichi Sakai:
An Inductive Method to Select Simulation Points. CANDAR 2015: 392-395 - 2014
- [c56]Koki Murakami, Tsuyoshi Yamada, Rie Shigetomi Yamaguchi, Masahiro Goshima, Shuichi Sakai:
A cloud architecture for protecting guest's information from malicious operators with memory management. CODASPY 2014: 155-158 - 2013
- [j17]Ryota Shioya, Naruki Kurata, Takashi Toyoshima, Masahiro Goshima, Shuichi Sakai:
Register Indirect Jump Target Forwarding. IEICE Trans. Inf. Syst. 96-D(2): 278-288 (2013) - 2011
- [j16]Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, Shuichi Sakai:
Low-Overhead Architecture for Security Tag. IEICE Trans. Inf. Syst. 94-D(1): 69-78 (2011) - 2010
- [c55]Ryota Shioya, Kazuo Horio, Masahiro Goshima, Shuichi Sakai:
Register Cache System Not for Latency Reduction Purpose. MICRO 2010: 301-312
2000 – 2009
- 2009
- [c54]Shuichi Sakai, Hidetoshi Onodera, Hiroto Yasuura, James C. Hoe:
Dependable VLSI: device, design and architecture: how should they cooperate? ASP-DAC 2009: 859-860 - [c53]Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, Shuichi Sakai:
Low-Overhead Architecture for Security Tag. PRDC 2009: 135-142 - [c52]Kunbo Li, Ryota Shioya, Masahiro Goshima, Shuichi Sakai:
String-Wise Information Flow Tracking against Script Injection Attacks. PRDC 2009: 169-176 - 2008
- [j15]Shuichi Sakai, Masahiro Goshima, Hidetsugu Irie:
Ultra Dependable Processor. IEICE Trans. Electron. 91-C(9): 1386-1393 (2008) - 2007
- [j14]Tomoyoshi Kinoshita, Ibuki Handa, Makoto Muto, Shuichi Sakai, Hidehiko Tanaka:
Musical part separation based on perceptual hierarchy. Syst. Comput. Jpn. 38(2): 91-100 (2007) - [j13]Hidetsugu Irie, Ken Sugimoto, Masahiro Goshima, Shuichi Sakai:
Preventing timing errors on register writes: mechanisms of detections and recoveries. SIGARCH Comput. Archit. News 35(5): 25-31 (2007) - [c51]Luong Dinh Hung, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai:
Utilization of SECDED for soft error and variation-induced defect tolerance in caches. DATE 2007: 1134-1139 - 2006
- [j12]Naoya Hatta, Niko Demus Barli, Chitaka Iwama, Luong Dinh Hung, Daisuke Tashiro, Shuichi Sakai, Hidehiko Tanaka:
Bus Serialization for Reducing Power Consumption. Inf. Media Technol. 1(2): 686-694 (2006) - [j11]Luong Dinh Hung, Shuichi Sakai:
Dynamic Estimation of Task Level Parallelism with Operating System Support. Inf. Media Technol. 1(2): 860-868 (2006) - [c50]Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai:
SEVA: A Soft-Error- and Variation-Aware Cache Architecture. PRDC 2006: 47-54 - [c49]Satoshi Katsunuma, Hiroyuki Kurita, Ryota Shioya, Kazuto Shimizu, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai:
Base Address Recognition with Data Flow Tracking for Injection Attack Detection. PRDC 2006: 165-172 - 2005
- [j10]Koichi Miura, Motomu Takano, Reiko Hamada, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka:
Associating semantically structured cooking videos with their preparation steps. Syst. Comput. Jpn. 36(2): 51-62 (2005) - [c48]Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai:
Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag. ICCD 2005: 342-350 - [c47]Luong Dinh Hung, Shuichi Sakai:
Dynamic Estimation of Task Level Parallelism with Operating System Support. ISPAN 2005: 358-363 - [c46]Reiko Hamada, Jun Okabe, Ichiro Ide, Shin'ichi Satoh, Shuichi Sakai, Hidehiko Tanaka:
Cooking navi: assistant for daily cooking in kitchen. ACM Multimedia 2005: 371-374 - 2004
- [c45]Reiko Hamada, Koichi Miura, Ichiro Ide, Shin'ichi Satoh, Shuichi Sakai, Hidehiko Tanaka:
Multimedia Integration for Cooking Video Indexing. PCM (2) 2004: 657-664 - 2003
- [j9]Shuichi Sakai, Mitsunori Togasaki, Koichi Yamazaki:
A note on greedy algorithms for the maximum weighted independent set problem. Discret. Appl. Math. 126(2-3): 313-322 (2003) - [j8]Ichiro Ide, Reiko Hamada, Shuichi Sakai, Hidehiko Tanaka:
Compilation of dictionaries for semantic attribute analysis of television news captions. Syst. Comput. Jpn. 34(12): 32-44 (2003) - [c44]Koichi Miura, Reiko Hamada, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka:
Associating Cooking Video Segments with Preparation Steps. CIVR 2003: 174-183 - [c43]Hideyuki Miura, Luong Dinh Hung, Chitaka Iwama, Daisuke Tashiro, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka:
Compiler-Assisted Thread Level Control Speculation. Euro-Par 2003: 603-608 - [c42]Yoshimitsu Yanagawa, Luong Dinh Hung, Chitaka Iwama, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka:
Complexity Analysis of a Cache Controller for Speculative Multithreading Chip Multiprocessors. HiPC 2003: 393-404 - 2002
- [c41]Okihisa Utsumi, Koichi Miura, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka:
An object detection method for describing soccer games from video. ICME (1) 2002: 45-48 - [c40]Shuichi Sakai:
CMP on SoC: Architect's View. ISSS 2002: 101-102 - 2001
- [c39]Chitaka Iwama, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka:
Improving Conditional Branch Prediction on Speculative Multithreading Architectures. Euro-Par 2001: 413-417 - [c38]Ichiro Ide, Reiko Hamada, Shuichi Sakai, Hidehiko Tanaka:
An attribute based news video indexing. ACM Multimedia Workshops 2001: 70-73 - 2000
- [c37]Reiko Hamada, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka:
Structural analysis of cooking preparation steps in Japanese. IRAL 2000: 157-164 - [c36]Ichiro Ide, Reiko Hamada, Shuichi Sakai, Hidehiko Tanaka:
Scene identification in news video by character region segmentation. ACM Multimedia Workshops 2000: 195-200 - [c35]Reiko Hamada, Ichiro Ide, Shuichi Sakai:
Associating cooking video with related textbook. ACM Multimedia Workshops 2000: 237-241
1990 – 1999
- 1999
- [c34]Antonio Magnaghi, Shuichi Sakai, Hidehiko Tanaka:
Inter-procedural Analysis for Parallelization of Java Programs. ACPC 1999: 594-595 - [c33]Ichiro Ide, Reiko Hamada, Shuichi Sakai, Hidehiko Tanaka:
Relating Graphical Features with Concept Classes for Automatic News Video Indexing. Intelligent Information Integration 1999 - [c32]Reiko Hamada, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka:
Associating video with related documents. ACM Multimedia (2) 1999: 17-20 - [c31]Masaaki Honda, Takeo Igarashi, Hidehiko Tanaka, Shuichi Sakai:
Integrated Manipulation: Context-Aware Manipulation of 2D Diagrams. ACM Symposium on User Interface Software and Technology 1999: 159-160 - 1997
- [c30]Yuetsu Kodama, Hirofumi Sakane, Hanpei Koike, Mitsuhisa Sato, Shuichi Sakai, Yoshinori Yamaguchi:
Parallel Execution of Radix Sort Program Using Fine-Grain Communication. IEEE PACT 1997: 136-145 - [c29]Takashi Yokota, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono, Shuichi Sakai:
Virtual control channel and its application to the massively parallel computer RWC-1. HiPC 1997: 443-448 - [c28]Mitsuhisa Sato, Yuetsu Kodama, Hirofumi Sakane, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi:
Experience with Fine-Grain Communication in EM-X Multiprocessor for Parallel Sparse Matrix Computation. IPPS 1997: 242-248 - [c27]Andrew Sohn, Yuetsu Kodama, Jui Ku, Mitsuhisa Sato, Hirofumi Sakane, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi:
Fine-Grain Multithreading with the EM-X Multiprocessor. SPAA 1997: 189-198 - 1996
- [c26]Kazuaki Okamoto, Shuichi Sakai, Hiroshi Matsuoka, Takashi Yokota, Hideo Hirono:
Multithread execution mechanisms on RICA-1 for massively parallel computation. IEEE PACT 1996: 116-121 - [c25]Andrew Sohn, Jui Ku, Yuetsu Kodama, Mitsuhisa Sato, Hirofumi Sakane, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi:
Identifying the capability of overlapping computation with communication. IEEE PACT 1996: 133-138 - 1995
- [j7]Shuichi Sakai, Yuetsu Kodama, Mitsuhisa Sato, Andrew Shaw, Hiroshi Matsuoka, Hideo Hirono, Kazuaki Okamoto, Takashi Yokota:
Reduced Interprocessor-Communication Architecture and its Implementation on EM-4. Parallel Comput. 21(5): 753-769 (1995) - [c24]Takashi Yokota, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono, Atsushi Hori, Shuichi Sakai:
A prototype router for the massively parallel computer RWC-1. ICCD 1995: 279-284 - [c23]Hayato Yamana, Mitsuhisa Sato, Yuetsu Kodama, Hirofumi Sakane, Shuichi Sakai, Yoshinori Yamaguchi:
A Macrotask-level Unlimited Speculative Execution on Multiprocessors. International Conference on Supercomputing 1995: 328-337 - [c22]Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi:
The EM-X Parallel Computer: Architecture and Basic Performance. ISCA 1995: 14-23 - [c21]Atsushi Hori, Takashi Yokota, Yutaka Ishikawa, Shuichi Sakai, Hiroki Konaka, Munenori Maeda, Takashi Tomokiyo, Jörg Nolte, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono:
Time Space Sharing Scheduling and Architectural Support. JSSPP 1995: 92-105 - 1994
- [c20]Shuichi Sakai:
Overview of RWC Massively Parallel Computer Project. HPDC 1994: 5 - [c19]Mitsuhisa Sato, Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi:
EM-C: Programming with Explicit Parallelism and Locality for EM-4 Multiprocessor. IFIP PACT 1994: 3-14 - [c18]Mitsuhisa Sato, Yuetsu Kodama, Yoshinori Yamaguchi, Shuichi Sakai:
Experience with Executing Shared Memory Programs using Fine-Grain Communication and Multithreading in EM-4. IPPS 1994: 630-636 - [c17]Yuetsu Kodama, Hirofumi Sakane, Mitsuhisa Sato, Shuichi Sakai, Yoshinori Yamaguchi:
Message-based efficient remote memory access on a highly parallel computer EM-X. ISPAN 1994: 135-142 - [c16]Andrew Sohn, Mitsuhisa Sato, Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi:
Nonnumeric search results on the EM-4 distributed-memory multiprocessor. SC 1994: 301-310 - [c15]Andrew Sohn, Mitsuhisa Sato, Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi:
Parallel bidirectional heuristic search on the EM-4 multiprocessor. SPDP 1994: 100-107 - [c14]Mitsuhisa Sato, Yuetsu Kodama, Hirofumi Sakane, Yoshinori Yamaguchi, Shuichi Sakai:
Programming with Distributed Data Structure for EM-X Multiprocessor. Theory and Practice of Parallel Programming 1994: 472-483 - 1993
- [j6]Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi:
Design and Implementation of a Circular Omega Network in the EM-4. Parallel Comput. 19(2): 125-142 (1993) - [j5]Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi:
Evaluation of parallel execution performance by highly parallel computer EM-4. Syst. Comput. Jpn. 24(9): 32-41 (1993) - [c13]Yuetsu Kodama, Yasuhito Koumura, Mitsuhisa Sato, Hirohumi Sakane, Shuichi Sakai, Yoshinori Yamaguchi:
EMC-Y: Parallel Processing Element Optimizing Communication and Computation. International Conference on Supercomputing 1993: 167-174 - [c12]Shuichi Sakai, Kazuaki Okamoto, Hiroshi Matsuoka, Hideo Hirono, Yuetsu Kodama, Mitsuhisa Sato:
Super-Threading: Architectural and Software Mechanisms for Optimizing Parallel Computation. International Conference on Supercomputing 1993: 251-260 - [c11]Shuichi Sakai, Hiroshi Matsuoka, Yuetsu Kodama, Mitsuhisa Sato, Andrew Shaw, Hideo Hirono, Kazuaki Okamoto, Takashi Yokota:
RICA: Reduced Interprocessor-Communication Architecture - Concept and Mechanisms. SPDP 1993: 122-127 - 1992
- [j4]Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi:
A prototype of a highly parallel dataflow machine EM-4 and its preliminary evaluation. Future Gener. Comput. Syst. 7(2-3): 199-209 (1992) - [j3]Kazuaki Okamoto, Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi:
Methodologies in development and testing of the dataflow machine EM-4. Parallel Comput. 18(8): 901-912 (1992) - [c10]Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi:
Evaluation of the EM-4 Highly Parallel Computer using a Game Tree Searching Problem. FGCS 1992: 731-738 - [c9]Mitsuhisa Sato, Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi, Yasuhito Koumura:
Thread-based Programming for the EM-4 Hybrid Dataflow Machine. ISCA 1992: 146-155 - [c8]Kenji Toda, Kenji Nishida, Shuichi Sakai, Toshio Shimada:
A priority forwarding scheme for real-time multistage interconnection networks. RTSS 1992: 208-217 - 1991
- [c7]Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi:
Design and Implementation of a Versatile Interconnection Network in the EM-4. ICPP (1) 1991: 426-430 - [c6]Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi:
Prototype Implementation of a Highly Parallel Dataflow Machine EM-4. IPPS 1991: 278-286 - [c5]Kenji Toda, Kenji Nishida, Yoshinobu Uchibori, Shuichi Sakai, Toshio Shimada:
Parallel Multi-Context Architecture with High-Speed Synchronization Mechanism. IPPS 1991: 336-343 - [c4]Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi:
Load balancing by function distribution on the EM-4 prototype. SC 1991: 522-531 - 1990
- [c3]Toshitsugu Yuba, Toshio Shimada, Yoshinori Yamaguchi, Kei Hiraki, Shuichi Sakai:
Dataflow computer development in Japan. ICS 1990: 140-147
1980 – 1989
- 1989
- [c2]Yoshinori Yamaguchi, Shuichi Sakai, Kei Hiraki, Yuetsu Kodama:
An Architectural Disgn of a Highly Parallel Dataflow Machine. IFIP Congress 1989: 1155-1160 - [c1]Shuichi Sakai, Yoshinori Yamaguchi, Kei Hiraki, Yuetsu Kodama, Toshitsugu Yuba:
An Architecture of a Dataflow Single Chip Processor. ISCA 1989: 46-53 - 1986
- [j2]Shuichi Sakai, Masaru Kitsuregawa, Hidehiko Tanaka, Tohru Moto-Oka:
Interconnection networks for bucket distribution on relational algebra machine GRACE. Syst. Comput. Jpn. 17(5): 45-53 (1986) - 1985
- [j1]Shuichi Sakai, Masaru Kitsuregawa, Hidehiko Tanaka, Tohru Moto-Oka:
Interconnection network for bucket collection on relational algebra machine GRACE. Syst. Comput. Jpn. 16(5): 79-87 (1985)
Coauthor Index
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