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2020 – today
- 2023
[j13]Hiroshi Fuketa
, Ippei Akita, Tomohiro Ishikawa, Hanpei Koike, Takahiro Mori:
A Cryogenic CMOS Current Integrator and Correlation Double Sampling Circuit for Spin Qubit Readout. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 5220-5228 (2023)- 2022
- [c32]Hiroshi Fuketa, Ippei Akita, Tomohiro Ishikawa, Hanpei Koike, Takahiro Mori:
A Cryogenic CMOS Current Comparator for Spin Qubit Readout Achieving Fast Readout Time and High Current Resolution. VLSI Technology and Circuits 2022: 234-235 - 2020
- [j12]Yasuhiro Ogasahara, Yohei Hori, Toshihiro Katashita, Tomoki Iizuka, Hiromitsu Awano, Makoto Ikeda, Hanpei Koike:
Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shipping. Integr. 71: 144-153 (2020)
2010 – 2019
- 2018
- [j11]Toshihiro Katashita, Masakazu Hioki, Yohei Hori, Hanpei Koike:
Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device. IEICE Trans. Inf. Syst. 101-D(2): 303-313 (2018) - 2016
- [j10]Masakazu Hioki, Hanpei Koike:
Low Overhead Design of Power Reconfigurable FPGA with Fine-Grained Body Biasing on 65-nm SOTB CMOS Technology. IEICE Trans. Inf. Syst. 99-D(12): 3082-3089 (2016) - [c31]Yasuhiro Ogasahara, Yohei Hori, Hanpei Koike:
Implementation of pseudo linear feedback shift register physical unclonable function on silicon. ISCAS 2016: 758-761 - 2015
- [j9]Yasuhiro Ogasahara, Tadashi Nakagawa, Toshihiro Sekigawa, Toshiyuki Tsutsumi, Hanpei Koike:
Impacts of flexible Vth control, low process variability, and steep SS with low on-current of new structure transistors to ultra-low voltage designs. IEICE Electron. Express 12(15): 20150460 (2015) - [c30]Yasuhiro Ogasahara, Yohei Hori, Hanpei Koike:
Standard cell implementation of buskeeper PUF with symmetric inverters and neighboring cells for passing randomness tests. GCCE 2015: 550-551 - 2013
- [c29]Masakazu Hioki, Toshihiro Sekigawa, Tadashi Nakagawa, Hanpei Koike, Yohei Matsumoto, Takashi Kawanami, Toshiyuki Tsutsumi:
Fully-functional FPGA prototype with fine-grain programmable body biasing. FPGA 2013: 73-80 - 2012
- [j8]Shin-ichi O'Uchi, Kazuhiko Endo, Takashi Matsukawa, Yongxun Liu, Tadashi Nakagawa, Yuki Ishikawa, Junichi Tsukada, Hiromi Yamauchi, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara:
A 0.7-V Opamp in Scaled Low-Standby-Power FinFET Technology. IEICE Trans. Electron. 95-C(4): 686-695 (2012) - [j7]Hideo Sakai, Shin-ichi O'Uchi, Takashi Matsukawa, Kazuhiko Endo, Yongxun Liu, Junichi Tsukada, Yuki Ishikawa, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara, Hiroki Ishikuro:
High-Frequency Precise Characterization of Intrinsic FinFET Channel. IEICE Trans. Electron. 95-C(4): 752-760 (2012) - 2010
- [c28]Naoto Miyamoto, Yohei Matsumoto, Hanpei Koike, Tadayuki Matsumura, Kenichi Osada, Yaoko Nakagawa, Tadahiro Ohmi:
Development of a CAD tool for 3D-FPGAs. 3DIC 2010: 1-6 - [c27]Shin-ichi O'Uchi, Kazuhiko Endo, Yongxun Liu, Tadashi Nakagawa, Takashi Matsukawa, Yuki Ishikawa, Junichi Tsukada, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara:
Realization of 0.7-V analog circuits by adaptive-Vt operation of FinFET. CICC 2010: 1-4 - [c26]Shin-ichi O'Uchi, Kazuhiko Endo, Yongxun Liu, Tadashi Nakagawa, Takashi Matsukawa, Yuki Ishikawa, Junichi Tsukada, Hiromi Yamauchi, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara:
0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging malfunctioned bits. ESSCIRC 2010: 474-477
2000 – 2009
- 2009
- [c25]Seid Hadi Rasouli, Hanpei Koike, Kaustav Banerjee:
High-speed low-power FinFET based domino logic. ASP-DAC 2009: 829-834 - 2008
- [j6]Shin-ichi O'Uchi, Meishoku Masahara, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Kunihiro Sakamoto, Toshihiro Sekigawa, Hanpei Koike, Eiichi Suzuki:
FinFET-Based Flex-Vth SRAM Design for Drastic Standby-Leakage-Current Reduction. IEICE Trans. Electron. 91-C(4): 534-542 (2008) - [j5]Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Hanpei Koike, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa:
Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations. ACM Trans. Reconfigurable Technol. Syst. 1(1): 3:1-3:31 (2008) - 2007
- [j4]Takashi Kawanami, Masakazu Hioki, Yohei Matsumoto, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA. IEICE Trans. Inf. Syst. 90-D(12): 1947-1955 (2007) - [c24]Shin-ichi O'Uchi, Meishoku Masahara, Kunihiro Sakamoto, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Toshihiro Sekigawa, Hanpei Koike, Eiichi Suzuki:
Flex-Pass-Gate SRAM Design for Static Noise Margin Enhancement Using FinFET-Based Technology. CICC 2007: 33-36 - [c23]Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Performance and yield enhancement of FPGAs with within-die variation using multiple configurations. FPGA 2007: 169-177 - [c22]Masakazu Hioki, Takashi Kawanami, Yohei Matsumoto, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Toshiyuki Tsutsumi:
A Power Configurable Block Array Connected in Series as First Prototype Flex Power FPGA Chip. FPT 2007: 285-288 - 2006
- [c21]Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Evaluation of granularity on threshold voltage control in flex power FPGA. FPGA 2006: 223 - [c20]Yohei Matsumoto, Hanpei Koike, Akira Masaki:
FPGAs with multidimensional mesh topology. FPGA 2006: 223 - [c19]Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Evaluation of granularity on threshold voltage control in flex power FPGA. FPT 2006: 17-24 - [c18]Takashi Kawanami, Masakazu Hioki, Yohei Matsumoto, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Optimal set of body bias voltages for an FPGA with field-programmable Vth components. FPT 2006: 329-332 - 2005
- [c17]Hanpei Koike, Toshihiro Sekigawa:
XDXMOS: a novel technique for the double-gate MOSFETs logic circuits - to achieve high drive current and small input capacitance together. CICC 2005: 247-250 - 2004
- [j3]Takashi Kawanami, Masakazu Hioki, Hiroshi Nagase, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity. IEICE Trans. Inf. Syst. 87-D(8): 2004-2010 (2004) - [c16]Takashi Kawanami, Masakazu Hioki, Hiroshi Nagase, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity. FPGA 2004: 257
1990 – 1999
- 1998
- [c15]Hayato Yamana, Hanpei Koike, Yuetsu Kodama, Hirofumi Sakane, Yoshinori Yamaguchi:
Fast Speculative Search Engine on the Highly Parallel Computer EM-X. SIGIR 1998: 390 - 1997
- [c14]Yuetsu Kodama, Hirofumi Sakane, Hanpei Koike, Mitsuhisa Sato, Shuichi Sakai, Yoshinori Yamaguchi:
Parallel Execution of Radix Sort Program Using Fine-Grain Communication. IEEE PACT 1997: 136-145 - 1994
- [j2]Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka:
Architecture of parallel management kernel for PIE64. Future Gener. Comput. Syst. 10(1): 29-43 (1994) - [c13]Hidemoto Nakada, Takuya Araki, Hanpei Koike, Hidehiko Tanaka:
A Fleng Compiler for PIE64. IFIP PACT 1994: 257-266 - [c12]Jun'ichi Tatemura, Hanpei Koike, Hidehiko Tanaka:
A Performance Debugger for a Parallel Logic Programming Language Fleng. Theory and Practice of Parallel Programming 1994: 284-299 - 1993
- [j1]Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka:
UNIRED II: The High Performance Inference Processor for the Parallel Inference Machine PIE64. New Gener. Comput. 11(3): 251-269 (1993) - [c11]Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka:
The Instruction Set Architecture of the Inference Processor UNIRED II. Architectures and Compilation Techniques for Fine and Medium Grain Parallelism 1993: 117-128 - [c10]Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka:
Multiple Threads in Cyclic Register Windows. ISCA 1993: 131-142 - [c9]Jun'ichi Tatemura, Hanpei Koike, Hidehiko Tanaka:
Control and Data Flow Visualization for Parallel Logic Programs on a Multi-window Debugger HyperDEBU. PARLE 1993: 414-425 - 1992
- [c8]Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka:
UNIRED II: The High Performance Inference Processor for the Parallel Inference Machine PIE64. FGCS 1992: 715-722 - [c7]Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka:
Architecture of Parallel Management Kernel for PIE64. PARLE 1992: 685-700 - [c6]Jun'ichi Tatemura, Hanpei Koike, Hidehiko Tanaka:
HyperDEBU: A Multiwindow Debugger for Parallel Logic Programs. Programming Environments for Parallel Computing 1992: 87-105 - 1991
- [c5]Yasuo Hidaka, Hanpei Koike, Jun'ichi Tatemura, Hidehiko Tanaka:
A Static Load Partitioning Method based on Execution Profile for Committed Choice Languages. ISLP 1991: 470-484
1980 – 1989
- 1989
- [c4]Lu Xu, Hanpei Koike, Hidehiko Tanaka:
Distributed Garbage Collection for the Parallel Inference Machine PIE64. IFIP Congress 1989: 1161-1166 - [c3]Lu Xu, Hanpei Koike, Hidehiko Tanaka:
Distributed Garbage Collection for the Parallel Inference Engine PIE64. NACLP 1989: 922-941 - 1988
- [c2]Hanpei Koike, Hidehiko Tanaka:
Multi-Context Processing and Data Balancing Mechanism of the Parallel Inference Machine PIE64. FGCS 1988: 970-977 - 1986
- [c1]Hanpei Koike, Hidehiko Tanaka:
Fast Execution Mechanisms of Parallel Inference Engine PIE: PIEpelined Goal Rewriting and Goal Multicasting. LP 1986: 159-169
Coauthor Index
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