default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID43rd MICRO 2010: Atlanta, Georgia, USA
- 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2010, 4-8 December 2010, Atlanta, Georgia, USA. IEEE Computer Society 2010, ISBN 978-0-7695-4299-7
Transactional Systems
- Hanjun Kim
, Arun Raman, Feng Liu, Jae W. Lee, David I. August:
Scalable Speculative Parallelization on Commodity Clusters. 3-14 - Utku Aydonat, Tarek S. Abdelrahman:
Hardware Support for Relaxed Concurrency Control in Transactional Memory. 15-26 - Marc Lupon, Grigorios Magklis, Antonio González:
A Dynamically Adaptable Hardware Transactional Memory. 27-38 - Jae-Woong Chung, Luke Yen, Stephan Diestelhorst, Martin Pohlack, Michael Hohmuth, David Christie, Dan Grossman:
ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory. 39-50
Scheduling
- Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang:
Memory Latency Reduction via Thread Throttling. 53-64 - Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor Harchol-Balter:
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior. 65-76 - Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David M. Brooks:
Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling. 77-88 - Yoav Etsion, Felipe Cabarcas, Alejandro Rico, Alex Ramírez, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Task Superscalar: An Out-of-Order Task Pipeline. 89-100
Reliability/Scheduling
- Erika Gunadi, Abhishek A. Sinkar, Nam Sung Kim, Mikko H. Lipasti:
Combating Aging with the Colt Duty Cycle Equalizer. 103-114 - Nak Hee Seong, Dong Hyuk Woo, Vijayalakshmi Srinivasan, Jude A. Rivers, Hsien-Hsin S. Lee:
SAFER: Stuck-At-Fault Error Recovery for Memories. 115-124 - Arun A. Nair, Lizy Kurian John, Lieven Eeckhout:
AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-Case Vulnerability to Soft Errors. 125-136 - Daniel Y. Deng, Daniel Lo, Greg Malysa, Skyler Schneider, G. Edward Suh:
Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric. 137-148
Caching
- Aamer Jaleel, Eric Borch, Malini Bhandaru, Simon C. Steely Jr., Joel S. Emer:
Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management Policies. 151-162 - Dongyuan Zhan, Hong Jiang, Sharad C. Seth:
STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches. 163-174 - Samira Manabi Khan, Yingying Tian, Daniel A. Jiménez:
Sampling Dead Block Prediction for Last-Level Caches. 175-186 - Daniel Sánchez, Christos Kozyrakis:
The ZCache: Decoupling Ways and Associativity. 187-198
Data Parallelism
- Rajkishore Barik, Jisheng Zhao, Vivek Sarkar:
Efficient Selection of Vector Instructions Using Dynamic Programming. 201-212 - Jaekyu Lee, Nagesh B. Lakshminarayana, Hyesoon Kim, Richard W. Vuduc:
Many-Thread Aware Prefetching Mechanisms for GPGPU Applications. 213-224 - Eric S. Chung, Peter A. Milder, James C. Hoe, Ken Mai:
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs? 225-236 - Michael Steffen, Joseph Zambreno:
Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels. 237-248
Concurrency
- Adrian Nistor, Darko Marinov, Josep Torrellas:
InstantCheck: Checking the Determinism of Parallel Programs Using On-the-Fly Incremental Hashing. 251-262 - Jie Yu, Satish Narayanasamy:
Tolerating Concurrency Bugs Using Transactions as Lifeguards. 263-274 - Enrique Vallejo, Ramón Beivide, Adrián Cristal, Tim Harris, Fernando Vallejo, Osman S. Unsal, Mateo Valero:
Architectural Support for Fair Reader-Writer Locking. 275-286 - Abdullah Muzahid, Norimasa Otsuki, Josep Torrellas:
AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection. 287-297
Microarchitecture I
- Ryota Shioya, Kazuo Horio, Masahiro Goshima, Shuichi Sakai:
Register Cache System Not for Latency Reduction Purpose. 301-312 - Shekhar Srikantaiah, Mahmut T. Kandemir:
Synergistic TLBs for High Performance Address Translation in Chip Multiprocessors. 313-324 - Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott A. Mahlke:
Erasing Core Boundaries for Robust and Configurable Performance. 325-336 - Guoping Long, Diana Franklin, Susmit Biswas, Pablo J. Ortiz, Jason Oberg, Dongrui Fan, Frederic T. Chong:
Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors. 337-348
Memories
- Timothy N. Miller, Renji Thomas, James Dinan, Bruce M. Adcock, Radu Teodorescu:
Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches. 351-362 - Thomas Vogelsang:
Understanding the Energy Consumption of Dynamic Random Access Memories. 363-374 - Jeffrey Stuecheli, Dimitris Kaseridis, Hillery C. Hunter, Lizy K. John:
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory. 375-384 - Adrian M. Caulfield, Arup De, Joel Coburn, Todor I. Mollow, Rajesh K. Gupta, Steven Swanson:
Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories. 385-395
NoCs
- Minseon Ahn, Eun Jung Kim:
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks. 399-408 - Jin Ouyang, Yuan Xie:
LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support. 409-420 - Ali Bakhoda, John Kim, Tor M. Aamodt:
Throughput-Effective On-Chip Networks for Manycore Accelerators. 421-432 - Syed Ali Raza Jafri, Yu-Ju Hong, Mithuna Thottethodi, T. N. Vijaykumar:
Adaptive Flow Control for Robust Performance and Energy. 433-444
Coherence
- Xuehai Qian, Wonsun Ahn, Josep Torrellas:
ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment. 447-458 - Daehoon Kim, Hwanju Kim, Jaehyuk Huh:
Virtual Snooping: Filtering Snoops in Virtualized Multi-cores. 459-470 - Meng Zhang, Alvin R. Lebeck, Daniel J. Sorin:
Fractal Coherence: Scalably Verifiable Cache Coherence. 471-482
Microarchitecture II
- Christophe Dubach, Timothy M. Jones, Edwin V. Bonilla, Michael F. P. O'Boyle:
A Predictive Model for Dynamic Microarchitectural Adaptivity Control. 485-496 - Matthew A. Watkins, David H. Albonesi:
ReMAP: A Reconfigurable Heterogeneous Multicore Architecture. 497-508 - Michael Mihn-Jong Lee, John Kim, Dennis Abts, Michael R. Marty, Jae W. Lee:
Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs. 509-519
Tools
- Jianwei Chen, Lakshmi Kumar Dabbiru, Daniel Wong, Murali Annavaram, Michel Dubois:
Adaptive and Speculative Slack Simulations of CMPs on CMPs. 523-534 - Minjang Kim, Hyesoon Kim, Chi-Keung Luk:
SD3: A Scalable Approach to Dynamic Data-Dependence Profiling. 535-546 - Aparna Kotha, Kapil Anand, Matthew Smithson, Greeshma Yellareddy, Rajeev Barua:
Automatic Parallelization in a Binary Rewriter. 547-557
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-01-26 23:33 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
