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A Real-Time Demonstrator for Track Reconstruction in the CMS L1 Track-Trigger System Based on Custom Associative Memories and High-Performance FPGAs
/ Fedi, Giacomo (INFN, Pisa ; Pisa U.) ; Palla, Fabrizio (INFN, Pisa ; Pisa U.) ; Gentsos, Christos (INFN, Perugia ; Perugia U.) ; Magalotti, Daniel (INFN, Perugia ; Perugia U.) ; Modak, Atanu (INFN, Perugia ; Perugia U.) ; Bilei, Gian Mario (INFN, Perugia ; Perugia U.) ; Roy Chowdhury, Suvankar (Saha Inst.) ; Checcucci, Bruno (INFN, Perugia ; Perugia U.) ; Tcherniakhovski, Denis (KIT, Karlsruhe) ; Galbit, Geoffrey Christian (Lyon, IPN) et al.
A Real-Time demonstrator based on the ATCA Pulsar-IIB custom board and on the Pattern Recognition Mezzanine (PRM) board has been developed as a flexible platform to test and characterize low-latency algorithms for track reconstruction and L1 Trigger generation in future High Energy Physics experiments. The demonstrator has been extensively used to test and characterize the Track-Trigger algorithms and architecture based on the use of the Associative Memory ASICs and of the PRM cards. [...]
SISSA, 2018 - 5 p.
- Published in : PoS TWEPP-17 (2018) 138
Fulltext: PDF; External link: PoS server
In : Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017, pp.138
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Results from CHIPIX-FE0, a small-scale prototype of a new generation pixel readout ASIC in 65 nm CMOS for HL-LHC
/ Pacher, Luca (INFN, Turin) ; Monteil, Ennio (INFN, Turin) ; Paternò, Andrea (INFN, Turin ; Polytech. Turin) ; Panati, Serena (INFN, Turin ; Polytech. Turin) ; Demaria, Natale (INFN, Turin) ; Rivetti, Angelo (INFN, Turin) ; Da Rocha Rolo, Manuel Dionisio (INFN, Turin) ; Dellacasa, Giulio (INFN, Turin) ; Mazza, Giovanni (INFN, Turin) ; Rotondo, Francesco (INFN, Turin) et al.
A prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to as CHIPIX-FE0, is composed of a matrix of 64 x 64 pixels with 50 $\mu$m x 50 $\mu$m pixel size embedding two different architectures of analog front-ends working in parallel. [...]
SISSA, 2017 - 5 p.
- Published in : PoS TWEPP-17 (2017) 024
Fulltext: PDF; External link: PoS server
In : Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017, pp.024
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Development of a large pixel chip demonstrator in RD53 for ATLAS and CMS upgrades
/ Conti, Elia (CERN) ; Barbero, Marlon (Marseille, CPPM) ; Fougeron, Denis (Marseille, CPPM) ; Godiot, Stephanie (Marseille, CPPM) ; Menouni, Mohsine (Marseille, CPPM) ; Pangaud, Patrick (Marseille, CPPM) ; Rozanov, Alexandre (Marseille, CPPM) ; Breugnon, Patrick (Marseille, CPPM) ; Bomben, Marco (Paris U., VI-VII) ; Calderini, Giovanni (Paris U., VI-VII) et al.
/RD53
RD53A is a large scale 65 nm CMOS pixel demonstrator chip that has been developed by the RD53 collaboration for very high rate (3 GHz/cm$^2$) and very high radiation levels (500 Mrad, possibly 1 Grad) for ATLAS and CMS phase 2 upgrades. It features serial powering operation and design variations in the analog and digital pixel matrix for different testing purposes. [...]
SISSA, 2017 - 5 p.
- Published in : PoS TWEPP-17 (2017) 005
Fulltext: PDF; External link: PoS server
In : Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017, pp.005
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Track finding mezzanine for Level-1 triggering in HL-LHC experiments
/ Gentsos, Christos (INFN, Perugia ; Perugia U.) ; Fedi, Giacomo (INFN, Pisa ; Pisa U.) ; Magazzù, Guido (INFN, Pisa ; Pisa U.) ; Magalotti, Daniel (INFN, Perugia ; Perugia U.) ; Modak, Atanu (INFN, Perugia ; Perugia U.) ; Storchi, Loriano (INFN, Perugia ; Perugia U.) ; Palla, Fabrizio (INFN, Pisa ; Pisa U.) ; Bilei, Gian Mario (INFN, Perugia ; Perugia U.) ; Biesuz, Nicolò (INFN, Pisa ; Pisa U.) ; Roy Chowdhury, Suvankar (Saha Inst.) et al.
The increase of the luminosity in the High Luminosity upgrade of the CERN Large Hadron Collider (HL-LHC) will require the use of Tracker information in the evaluation of the Level-1 trigger in order to keep the trigger rate acceptable (i.e.: <;1MHz). In order to extract the track information within the latency constraints (<;5μs), a custom real-time system is necessary. [...]
2017 - 4 p.
- Published in : 10.1109/MOCAST.2017.7937676
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A simulation framework for the CMS Track Trigger electronics
/ Amstutz, Christian (Karlsruhe U., EKP) ; Magazzu, Guido (INFN, Pisa) ; Weber, Marc (Karlsruhe U., EKP) ; Palla, Fabrizio (INFN, Pisa)
A simulation framework has been developed to test and characterize algorithms, architectures and hardware implementations of the vastly complex CMS Track Trigger for the high luminosity upgrade of the CMS experiment at the Large Hadron Collider in Geneva. High-level SystemC models of all system components have been developed to simulate a portion of the track trigger. [...]
CMS-CR-2014-360.-
Geneva : CERN, 2014 - 10 p.
- Published in : JINST 10 (2015) P03029
Fulltext: PDF;
In : Topical Workshop on Electronics for Particle Physics 2014, Aix En Provence, France, 22 - 26 Sep 2014, pp.P03029
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A high-resolution TDC-based board for a fully digital trigger and data acquisition system in the NA62 experiment at CERN
/ Pedreschi, Elena (Pisa U. ; INFN, Pisa) ; Angelucci, Bruno (Pisa U. ; INFN, Pisa) ; Avanzini, Carlo (Pisa U. ; INFN, Pisa) ; Galeotti, Stefano (INFN, Pisa) ; Lamanna, Gianluca (Pisa U. ; INFN, Pisa) ; Magazzù, Guido (INFN, Pisa) ; Pinzino, Jacopo (INFN, Pisa) ; Piandani, Roberto (INFN, Pisa) ; Sozzi, Marco (Pisa U. ; INFN, Pisa) ; Spinella, Franco (INFN, Pisa) et al.
A Time to Digital Converter (TDC) based system, to be used for most sub-detectors in the high-flux rare-decay experiment NA62 at CERN SPS, was built as part of the NA62 fully digital Trigger and Data AcQuisition system (TDAQ), in which the TDC Board (TDCB) and a general-purpose motherboard (TEL62) will play a fundamental role. While TDCBs, housing four High Performance Time to Digital Converters (HPTDC), measure hit times from sub-detectors, the motherboard processes and stores them in a buffer, produces trigger primitives from different detectors and extracts only data related to the lowest trigger level decision, once this is taken on the basis of the trigger primitives themselves. [...]
arXiv:1407.2456.-
2015 - 6 p.
- Published in : IEEE Trans.Nucl.Sci.: 62 (2015) , no. 3, pp. 1050-1055
Fulltext: arXiv:1407.2456 - PDF; 1407.2456 - PDF; External link: Preprint
In : 19th IEEE-NPSS Real-Time conference 2014, Nara, Japan, 26 - 30 May 2014, pp.7097526
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