2011 20th European Conference on Circuit Theory and Design (ECCTD)

Low-Voltage Low-Power CMOS Rail-to-Rail

V-I Converters
C. Azcona, B. Calvo, S. Celma, N. Medrano
Group of Electronic Design
University of Zaragoza
Zaragoza, Spain
{cris.azcona, becalvo, scelma, nmedrano}@unizar.es

Abstract—This paper presents three compact and simple CMOS

voltage-to-current (V-I) converter schemes attaining rail-to-rail VDD
VDD
operation with a highly linear V-I relationship over a (-40, T2 K:1 T3
K :1
+140 ºC) temperature range. Based on an OTA/common source Vin T1 T2
amplifier configuration, the key idea to reach rail-to-rail Vin
operation is reducing the voltage across the linear resistor that
T1 I out
performs the V-I conversion to keep the output current A V =V
A in Iout
mirroring transistor working in the saturation region over the V in
V in RS
complete input range. Results for 1.2 V – 0.18 µm CMOS RS
RS
RS
implementations show that all the proposed converters operate
over the entirely input range with GM errors below 2.5 %,
(a) (b)
linearity errors below 0.011 % and power consumptions below
70 µW, which makes them suitable for portable applications. Figure 1. V-I schemes: (a) conventional stage, (b) wide-swing approach

Keywords: V-I converter, low-voltage low-power, rail-to-rail, be reconsidered if achievement of rail-to-rail operation is a key
temperature compensation. issue for the circuit, as occurs in our application, where not
I. INTRODUCTION making use of the full supply voltage restricts the maximum
allowable resolution for the VFC output frequency.
Voltage-to-current (V-I) converters are key cells in many
analog and mixed applications: multipliers, continuous-time To address this problem, this paper proposes three new
filters, variable gain amplifiers, data converters and other CMOS rail-to rail V-I converters, achieving high linearity and
interface circuits can be built based on the V-I converter. In moderate power consumption. In addition, they are temperature
particular, the motivation of this study is the design of a V-I compensated. The paper is organized as follows. Section II
converter constituting the input stage of a CMOS voltage-to- presents the different approaches proposed to attain rail-to-rail
frequency converter (VFC) to be used in low power embedded V-I converters. Section III summarizes and compares the main
applications [1]. performance results obtained for 1.2 V − 0.18 µm CMOS
designs. Finally, preliminary conclusions are drawn in Section
The conventional V-I converter (Fig. 1a) is based on an IV.
operational amplifier (OA) or a transconductance amplifier
(OTA) driving an NMOS T1 and a grounded resistance RS in a II. PROPOSED RAIL-TO-RAIL V-I CONVERTERS
negative feedback loop. This structure is highly linear, but Based on the OTA/common source amplifier V-I
presents an important shortcoming: the minimum voltage architecture shown in Fig. 1b, the idea to reach rail-to-rail
headroom across the current mirror T2-T3 stacked to convey the operation is to reduce the voltage across the resistor RS which
current signal (Vin/RS) significantly reduces the voltage performs the V-I conversion from Vin to αVin, being α < 1, in
operating range down to VDD-(VTH2+Vds,sat2), where VTH2 and order to keep the transistor T1 working in the saturation region
Vds,sat2 are respectively the threshold voltage and the saturation over the complete input voltage range. In this way, assuming a
voltage of transistor T2. This limitation is critical in low- rail-to-rail input, the output current mirroring will not cause a
voltage modern CMOS processes. To extend the voltage reduction in the V-I operating range. So, three new approaches
operating range close to the supply voltage, the V-I converter that extend to rail-to-rail the operating range are next
of Fig. 1b was proposed by authors [1]. This structure, based introduced and analyzed, denoted as feedforward voltage
on an OTA/common source amplifier configuration, is used in attenuation (FFVA), feedback voltage attenuation (FBVA) and
voltage regulator design since the output VS = Vin can swing all current attenuation (CA) V-I converters.
the way up to the supply voltage. However, the transistor that
makes the current copy (T1) does not work in saturation over A. Feedforward Voltage Attenuation V-I converter
all the input voltage. As a result, the input voltage is The simplest proposal to obtain a rail-to-rail V-I converter
considerably extended, but the operation range is still limited to makes use of a rail-to-rail input voltage divider before the
VDD-Vds,sat1. Therefore, the design of this V-I converter needs to OTA/common source amplifier V-I converter. For attenuating

This work has been partially supported by MICINN (RYC-2008-03185,

PET2007-00336 PET2008-0021, TEC2009-09175), DGA (PI113/2009) and
DGA-La Caixa (GA-LC-039/2008).

978-1-4577-0618-9/11/$26.00 ©2011 IEEE 182

 VDD VDD
VDD
K :1
α Vin K :1
Vin T1 T2 T3
Vin T2 T3
OTA1
OTA1 OTA2

R2 T2C T3C
R1 T3C
Vin VB
T2C R1
Vin VB
R2 OTA2 Iout
A A
V A = α V in T1 V A = α V in
I out VDD
αVin RS
αVin
RS I1= I1=
RS
RS

Figure 2. Schematic scheme of the FFVA V-I converter Figure 3. Schematic scheme of the FBVA V-I converter

the input voltage, as shown in Fig. 2, an OTA/common source V

I (4)
amplifier voltage regulator loaded with a resistive voltage R
divider formed by linear resistors R1 and R2 is used. Thus, the B. Feedback Voltage Attenuation V-I Converter
voltage Vin is buffered by the OTA1-T1 voltage regulator with The FBVA V-I converter’s approach is showed in Fig. 3.
rail-to-rail input-output operation and attenuated to αVin The voltage reduction across resistor RS is made introducing
through R1-R2, where α=R2/(R1+R2). This new voltage is the between the main OTA (OTA1) non-inverting input – at a
input to the main V-I converter formed by OTA2 and voltage Vin due to negative feedback- and node A, a floating
transistors T2 and T2C. Output cascode transistors are used in dynamic battery. This dynamic battery is implemented using a
order to improve the current copy, so that the generated current non-inverting amplifier stage formed by the OTA/common
I1= αVin/RS is driven by T2-T2C and replicated through T3-T3C source amplifier OTA2-T1 and linear feedback resistors R1 and
with a scaling factor K. Therefore, the output current Iout is R2. Analyzing this stage, as the output voltage has to be Vin, the
given by non-inverting input of the OTA2 is v- = αVin, where
I
V
(1) α=R1/(R1+R2). Because of negative feedback, v- = v+ = αVin,
KRS and thus the voltage at node A is reduced to V0 = αVin.
The circuit temperature dependence is mainly due to the Therefore, a current I1 given by (5) is generated, and it is
resistor RS which performs the V-I conversion. Therefore, if RS replicated through transistors T3-T3C with an scaling factor K,
is implemented with a single resistive layer among those obtaining an output current Iout given by (6).
provided by the integrating technology –for example, with a I
V
(5)
HRP (High Resistance Polysilicon) to optimize area– high RS
temperature drifts can be introduced due to the resistance V
variation with temperature, given by I (6)
KRS

RS T R 1 TC T 25 TC T 25 (2) Again, circuit temperature dependence is mainly due to

resistor RS, it is done by implementing RS as a serial
where R0 is the resistor value at room temperature and TC1 -
connection of two resistors RN and RP with opposite T-
TC2 are the first and second order temperature coefficients.
coefficients. As in FFVA, resistors in the non inverting stage
Hence, resistor RS must be temperature independent to achieve do not need to be temperature compensated and do not need to
a temperature independent V-I characteristic. This is done by have accurate specified values: if they are well matched the
implementing RS as the serial connection of two resistors RN ratio will remain constant.
and RP with opposite T-coefficients TCN and TCP which
provide the suitable thermal coefficient given by In order to achieve a good resistance matching, resistances
are set to R1 = 4R, R2 = R and are implemented using a HRP
TC TC N β⁄ 1 β TC P 1⁄ 1 β (3) layer to optimize area. Temperature compensated resistance is
where β=R0N/R0P is the relative size of resistances at room set to be RS = 4R and the scaling factor to K = 10, so that the
temperature, in order to achieve an overall temperature- voltage across resistor RS is also reduced to αVin = 0.8Vin, and
independent V-I conversion [2]. As for the resistors in the the output current Iout is given by
voltage divider, they do not need to be temperature V
compensated and do not need to have accurate specified I (7)
R
values: if they are well matched their ratio will remain
C. Current Attenuation V-I Converter
constant.
In this approach, illustrated in Fig. 4, the reduction of the
In order to achieve a good resistance matching, resistances voltage across resistor RS is attained introducing, between the
are selected to be R1 = R and R2 = 4R and are implemented main OTA (OTA2) non-inverting input –at a voltage Vin due to
using a HRP layer to optimize area. Temperature compensated negative feedback– and node A, a floating dynamic battery
resistance is set to be RS = 4R and the scaling factor to K = 10, implemented using a linear resistor R2 driven by a current
so that the voltage across resistor RS is reduced to source proportional to Vin, so that there is a voltage reduction at
αVin = 0.8Vin, and the output current Iout is given by node A. To generate the required current, a second

183
 VDD VDD VDD

K1 : 1 K2 : 1 IB M4 M 4 M4 M4
Vin T1 T2 Vin T3 T4
OTA1 OTA2
I3 M2 M2

T1C T 2C T 3C T4C - M1 M1 Vout

VB VB Vin
+
Vin
R1K1 R2 M3
Vin A
V A = αV i n IB
Vin
Iout M3 M3 M3
R1 I1= RS α Vin
R1 I2=
RS

Figure 5. Schematic scheme of the OTA

Figure 4. Schematic scheme of the CA V-I converter
achieve a rail to rail input. It is biased with IB = 0.5 µA, and it
OTA/common source amplifier V-I converter formed by has a power consumption of 2.35 µW. It has a gain of 41.9 dB
OTA1, T1-T1C and R1 is used: Vin is converted to a current and a frequency at unity gain of fT = 2.66 MHz.
I1 = Vin/R1, which is replicated with a scaling factor K1 to drive
resistor R2, so that the voltage across R2 results The integrating technology used for the designs in this
VR2 = VinR2/K1R1 and the voltage at node A is reduced to paper, UMC 0.18 µm, provides negative and positive
V0 = αVin, with α = (K1R1-R2)/K1R1. Therefore, the current I2 temperature coefficient resistors, thus, using as RN the high-
through resistor RS is given by resistance (HRP) resistor (TC1 = -8.34 . 10-4 ºC-1,
TC2 = 1.3 . 10-6 ºC-2) and as RP the P+ nonsalicide diffusion
V V
I (8) (PND) resistor (TC1 = 1.184 . 10-3 ºC-1, TC2 = 3.197 . 10-7 ºC-2)
RS RS
given by technology, values that immunize the resistor against
and the current through output transistors T3 and T3C, I2, is temperature variation are R0N/R0P = 1.5; therefore, final first
given by and second order temperature coefficients for compensated
I
resistors are TC1 = -2.68 . 10-5 ºC-1 and TC2 = 9.08-7 ºC-2.
I I αV (9)
K RS K R R As said, in order to minimize the area, resistors of the
This current is then replicated with a scaling factor K2 to voltage divider in FFVA V-I converter (R1 = R = 10kΩ,
generate an output current given by (10). R2 = 4R) and resistors of the non-inverting stage of the FBVA
V-I converter (R1 = 4R, R2 = R =10kΩ) do not need to be
I V
I (10) temperature compensated, therefore, they are HRP resistors,
K K RS K R R
with a sheet resistance of 1039 Ω/sq.
Note that for this approach, in the auxiliary V-I converter Fig. 6 shows the normalized generated current versus the
the current copy across transistors T1-T2 is not seriously input voltage for the three presented V-I converters, compared
degraded when they enter the triode region, since T1-T2 with the results obtained for the conventional V-I converter in
maintain the same gate and drain voltage values. In this case, to Fig. 1a using a high swing cascode mirror in order to improve
achieve a temperature independent transfer function, it is the current copy with a scaling factor K = 10, and the resistor
necessary to have all resistances R1, R2 and RS temperature RS that makes the V-I conversion is set to RS = 40 kΩ, and the
compensated. V-I in Fig.1b with cascode transistors to improve the current
In order to achieve a good resistance matching, resistances copy, a scaling factor of K = 10 and RS = 40 kΩ. It can be seen
are set to R1 = 2R, R2 = 3R and RS = 2R, and the scaling factors that classic proposal has a rather limited input range 0 - 0.75 V,
are set to K1 = 7.5 and K2 = 10, so that that the voltage across which is significantly extended with the wide-swing approach,
resistor RS is also reduced to αVin = 0.8Vin and the output but it is still limited to 0 - 1.08V, while rail-to-rail operation is
current Iout is given by achieved with the new configurations. The FFVA V-I
V
converter can swing from 0 to 1.2 V, with a GM = 2.012 µS/V
I (11) (0.6% error), a linearity error defined as the deviation of a
R
straight line passing through the experimental points below
III. SIMULATION RESULTS 2
2

The structures presented above have been designed in 1.75

wide swing
CA

0.18 µm CMOS technology with a single 1.2 V supply. There FFVAh

Normalized I out

1.5 FBA

are some criterions followed in all circuits: the final scaling 1.5
Nomalized I out

factor K or K2 is set to 10 to optimize power consumption; the 1.25

1
resistor that realizes the main V-I conversion is set to 1
1 1.05 1.1 1.15 1.2

RS = 40 kΩ as a trade-off between power consumption and Vin (V)

classical
area; and the attenuation factor α is set to 0.8. The ongoing 0.5
wide swing

results have been obtained with same load conditions: CA

FFVA
RL = 10kΩ and CL = 0.5 pF. All V-I approaches are designed 0
FBVA
0 0.2 0.4 0.6 0.8 1 1.2 1.4
using the same core OTA, shown in Fig. 5. It includes two Vin (V)

complementary differential amplifier stages in parallel [3] to Figure 6. Normalized Iout vs. VIN for different V-I converters

184
 0.012

0.001% and a power consumption of 52.73 µW. In the FBVA 0.01

VD
CA
V-I converter, for an input range of (0 – 1.19 V), it has a VA

GM = 2.003 µS/V (0.15% error), a linearity below 0.001% and 0.008

linearity error (%)

the power consumption is 52.86 µW. For the CA V-I converter, 0.006

an input range of (0 - 1.18 V) is achieved, with a 0.004

GM = 1.681 µS/V (0.86% error), a linearity error below 0.001

0.002
% and a power consumption of 69.08 µW.
0
-50 0 50 100 150
The three circuits have been tested for a temperature range temp (ºC)

of (-40, +140 ºC), giving successful results in terms of Figure 7. Linearity error vs. temperature
temperature sensitivity: linearity error remains below 0.003 % -40
VD
for the FFVA V-I converter and GM varies up to 2.5 %, for the -45
CA

FBVA V-I converter linearity error remains below 0.011 % VA

while there is a GM variation of 2.15 % and for the CA the error -50

THD (dB)
is below 0.007 % and there is a GM variation of 1.13 %. In Fig. -55
7 the variation of linearity error with temperature is shown.
-60
The FFVA V-I converter has a bandwidth of 3.82 MHz,
FBVA V-I converter has a bandwidth of 5.23 MHz and the CA -65
10
2
10
3 4
10

V-I converter has a bandwidth of 6.64 MHz with the freq (Hz)

considered load RL = 10 kΩ and CL = 0.5 pF. FBVA V-I Figure 8. THD variation for 1Vpp
converter shows greater bandwidth than FFVA V-I converter
specification, as well as for other low voltage analog circuits
because there is a compensation pole-zero in its frequency
that loose a significant amount of operating range with the
response. Fig. 8 shows the total harmonic distortion (THD) for
increasing reduction of power supply voltages. In voltage
the V-I converters, for an input of 1Vpp. The THD is better in
attenuation V-I converters, a single differential pair could be
FBVA V-I converter, being above -50 dB for frequencies
used as the main OTA, as its input voltage is reduced to αVin.
below 10 kHz. However, all these V-I converters are good in
However, in these voltage attenuation V-I converters an OTA
terms of THD, since the application of these V-I converters is
that includes two complementary differential amplifier stages
VFCs, where the input signal is slowly varying. Finally, the V-
in parallel is used in order to have more compact architectures.
I converters are nominally biased at 1.2 V, and the output
current has been measured for supply voltage drops up to REFERENCES
0.2 V. Obviously, as VDD scales, the input voltage range is
[1] C.Azcona, B. Calvo, N. Medrano, A. Bayo, S. Celma, “12-b enhanced
scaled; however, linearity errors remains constant, and so do input range on-chip quasi-digital converter with temperature
each GM. compensation,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no. 3,
pp. 164-168, March 2011.
The proposed V-I main performances are summarized in
[2] K. Ueno, T. Asai, Y. Amemilla, “A 30-MHz, 90-ppm/ºC Fully-
Table I and compared with previously published rail to rail V-I integrated Clock Reference Generator with Frequency-locked Clock,” in
converters [4-5]. Proc. of the 35th European Solid-State Circuits Conference, pp. 392-395,
2009
IV. CONCLUSIONS [3] J R. J. Baker, H. W. Li, D. E. Boyce, CMOS, Circuit design, layout and
simulation, IEEE Press, USA, 1998
Three novel 1.2 V − 0.18 µm CMOS voltage-to-current
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CMOS V-I converter,” IEEE Trans. Circuits Syst. II, Analog and digital
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TABLE I. COMPARISON OF VFC PERFORMANCES

Parameter [4], 1999 [5], 2009 FFVA, 2011 FBVA, 2011 CA, 2011
Technology 1.2 µm CMOS 0.18 µm CMOS 0.18 µm CMOS 0.18 µm CMOS 0.18 µm CMOS
Supply Voltage 3V 1V 1.2 V 1.2 V 1.2 V
GM 20 µS/V 100 µS/V 2.012 µS/V 2.003 µS/V 1.681 µS/V
13 % 3% 12.8 % 1.25 % 3.2 %
GM deviation
(full range) (Vin > 0.1 V) (full range) (full range) (full range)
Input Voltage Range 0 – 2.8 V 0-1V 0-1.2 V 0-1.19 V 0-1.18 V
Bandwidth -- 39.22 MHz 3.82 MHz 5.23 MHz 6.64 MHz
THD @ 1Vpp -37.4 dB (1kHz) -44.4 dB (1MHz) -41.2 dB (10kHz) -53.5 dB (10kHz) -48.3 dB (10kHz)
Power Consumption 310 µW 730 µW 52.873 µW 52.86 µW 69.08 µW
Area 0.129 mm2 -- 0.0102 mm2 0.0112 mm2 0.0144 mm2

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